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authorTariq Toukan <tariqt@mellanox.com>2017-10-09 16:59:48 +0300
committerDavid S. Miller <davem@davemloft.net>2017-10-09 10:33:05 -0700
commitbb428a5c4df5f50acdce89449e476faa0b295e95 (patch)
tree692a2a2e599a46e0265dac77c93a5df4768a5b89 /drivers/net/ethernet/mellanox/mlx4/en_resources.c
parentacb40d8412572b2a79216a98acdbac10e620da1b (diff)
net/mlx4: Fix endianness issue in qp context params
Should take care of the endianness before assigning to params2 field. Fixes: 53f33ae295a5 ("net/mlx4_core: Port aggregation upper layer interface") Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx4/en_resources.c')
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/en_resources.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_resources.c b/drivers/net/ethernet/mellanox/mlx4/en_resources.c
index 5a47f9669621..6883ac75d37f 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_resources.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_resources.c
@@ -53,7 +53,7 @@ void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
if (is_tx) {
context->sq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4);
if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)
- context->params2 |= MLX4_QP_BIT_FPP;
+ context->params2 |= cpu_to_be32(MLX4_QP_BIT_FPP);
} else {
context->sq_size_stride = ilog2(TXBB_SIZE) - 4;