diff options
| author | Auke Kok <auke-jan.h.kok@intel.com> | 2006-06-27 09:08:03 -0700 |
|---|---|---|
| committer | Auke Kok <juke-jan.h.kok@intel.com> | 2006-06-27 09:08:03 -0700 |
| commit | ee04022a21764a12e29eee144b72344ebfe0a55c (patch) | |
| tree | 88744e14d2df93fe287abc39b0d4446ae159a7ae /drivers/net/e1000/e1000_hw.h | |
| parent | f1b3a85354d3877fae45ef448e7e49c2efd692d5 (diff) | |
e1000: M88 PHY workaround
M88 rev 2 PHY needs a longer downshift to function properly. This adds
a much longer downshift counter for this specific device.
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Diffstat (limited to 'drivers/net/e1000/e1000_hw.h')
| -rw-r--r-- | drivers/net/e1000/e1000_hw.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h index 941b47d61674..1908e0d3110c 100644 --- a/drivers/net/e1000/e1000_hw.h +++ b/drivers/net/e1000/e1000_hw.h @@ -2765,6 +2765,17 @@ struct e1000_host_command_info { #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ +/* M88EC018 Rev 2 specific DownShift settings */ +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 + /* IGP01E1000 Specific Port Config Register - R/W */ #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 #define IGP01E1000_PSCFR_PRE_EN 0x0020 |