diff options
| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2020-09-18 13:57:48 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-09-18 17:52:40 -0700 |
| commit | 123d231a166369b31b212ef3106fad9c4104f126 (patch) | |
| tree | fd08e2c7ea39c21ccace03c60e9edee9ef02fe39 /drivers/net/dsa/ocelot | |
| parent | 9ef9e0d28240a3bb2bee838afe322401e79fd572 (diff) | |
net: dsa: seville: reindent defines for MDIO controller
Reindent these definitions to be in line with the rest of the driver.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/ocelot')
| -rw-r--r-- | drivers/net/dsa/ocelot/seville_vsc9953.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index a7e059b554d7..50a7dada8989 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -16,12 +16,12 @@ #define VSC9953_VCAP_IS2_ENTRY_WIDTH 376 #define VSC9953_VCAP_PORT_CNT 10 -#define MSCC_MIIM_CMD_OPR_WRITE BIT(1) -#define MSCC_MIIM_CMD_OPR_READ BIT(2) -#define MSCC_MIIM_CMD_WRDATA_SHIFT 4 -#define MSCC_MIIM_CMD_REGAD_SHIFT 20 -#define MSCC_MIIM_CMD_PHYAD_SHIFT 25 -#define MSCC_MIIM_CMD_VLD BIT(31) +#define MSCC_MIIM_CMD_OPR_WRITE BIT(1) +#define MSCC_MIIM_CMD_OPR_READ BIT(2) +#define MSCC_MIIM_CMD_WRDATA_SHIFT 4 +#define MSCC_MIIM_CMD_REGAD_SHIFT 20 +#define MSCC_MIIM_CMD_PHYAD_SHIFT 25 +#define MSCC_MIIM_CMD_VLD BIT(31) static const u32 vsc9953_ana_regmap[] = { REG(ANA_ADVLEARN, 0x00b500), |