diff options
| author | Ezequiel Garcia <ezequiel.garcia@free-electrons.com> | 2013-11-14 18:25:33 -0300 |
|---|---|---|
| committer | Brian Norris <computersforpeace@gmail.com> | 2014-01-03 11:22:13 -0800 |
| commit | c39ff03a402e354eb73c61cb732f9bc881d76879 (patch) | |
| tree | d3bb1608a51e0b4c7a7ce471913fc9b0318cde9b /drivers/mtd | |
| parent | 01d9947e04fe16ab5891c932f47a171db5607bb5 (diff) | |
mtd: nand: pxa3xx: Split prepare_command_pool() in two stages
This commit splits the prepare_command_pool() function into two
stages: prepare_start_command() / prepare_set_command().
This is a preparation patch without any functionality changes,
and is meant to allow support for multiple page reading/writing
operations.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/pxa3xx_nand.c | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 0fdcc91af1e2..db96a7fe04a1 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -603,18 +603,8 @@ static void set_command_address(struct pxa3xx_nand_info *info, } } -static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, - uint16_t column, int page_addr) +static void prepare_start_command(struct pxa3xx_nand_info *info, int command) { - int addr_cycle, exec_cmd; - struct pxa3xx_nand_host *host; - struct mtd_info *mtd; - - host = info->host[info->cs]; - mtd = host->mtd; - addr_cycle = 0; - exec_cmd = 1; - /* reset data and oob column point to handle data */ info->buf_start = 0; info->buf_count = 0; @@ -623,10 +613,6 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, info->use_spare = 1; info->retcode = ERR_NONE; info->ndcb3 = 0; - if (info->cs != 0) - info->ndcb0 = NDCB0_CSEL; - else - info->ndcb0 = 0; switch (command) { case NAND_CMD_READ0: @@ -638,14 +624,32 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, case NAND_CMD_PARAM: info->use_spare = 0; break; - case NAND_CMD_SEQIN: - exec_cmd = 0; - break; default: info->ndcb1 = 0; info->ndcb2 = 0; break; } +} + +static int prepare_set_command(struct pxa3xx_nand_info *info, int command, + uint16_t column, int page_addr) +{ + int addr_cycle, exec_cmd; + struct pxa3xx_nand_host *host; + struct mtd_info *mtd; + + host = info->host[info->cs]; + mtd = host->mtd; + addr_cycle = 0; + exec_cmd = 1; + + if (info->cs != 0) + info->ndcb0 = NDCB0_CSEL; + else + info->ndcb0 = 0; + + if (command == NAND_CMD_SEQIN) + exec_cmd = 0; addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles + host->col_addr_cycles); @@ -780,8 +784,10 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, nand_writel(info, NDTR1CS0, info->ndtr1cs0); } + prepare_start_command(info, command); + info->state = STATE_PREPARED; - exec_cmd = prepare_command_pool(info, command, column, page_addr); + exec_cmd = prepare_set_command(info, command, column, page_addr); if (exec_cmd) { init_completion(&info->cmd_complete); init_completion(&info->dev_ready); |