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authorHuang Shijie <b32955@freescale.com>2013-09-25 14:58:12 +0800
committerBrian Norris <computersforpeace@gmail.com>2013-10-27 16:27:05 -0700
commit1c195e909cbe335b02a5dd01075ba65448927ae6 (patch)
tree8dbde209d13ca18ac02f028a9b78bba684230008 /drivers/mtd
parent7db906b79f69b6ed936a1ef1d788f02e3ad42462 (diff)
mtd: nand: add the "bits per cell" info for legacy ID NAND
The legacy ID NAND are all SLC. This patch sets 1 to the @bits_per_cell for the legacy ID NAND, which means they are all SLC. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/nand_base.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 5fb00957fd25..aebc7ea9f379 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3238,6 +3238,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
mtd->oobsize = mtd->writesize / 32;
*busw = type->options & NAND_BUSWIDTH_16;
+ /* All legacy ID NAND are small-page, SLC */
+ chip->bits_per_cell = 1;
+
/*
* Check for Spansion/AMD ID + repeating 5th, 6th byte since
* some Spansion chips have erasesize that conflicts with size