diff options
| author | Michael Walle <michael@walle.cc> | 2020-01-16 16:42:09 +0100 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2020-01-19 08:33:02 +0200 |
| commit | f3418718c0ec934013a36d717a00554d5fbcffc5 (patch) | |
| tree | 94de54dd974e166a61c434d11c7998bc56784dc2 /drivers/mtd/spi-nor | |
| parent | 52bbd2dcb42c21f183a2f59ad843a8d38fb68250 (diff) | |
mtd: spi-nor: Add support for w25q32jwm
Add support for the Winbond W25Q32JW-xM flashes. These have a
programmable QE bit. There is also the W25Q32JW-xQ variant which shares
the ID with the W25Q32DW and W25Q32FW parts. The W25Q32JW-xQ has the QE
bit hard strapped to 1, thus don't support the /HOLD and /WP pins.
This was tested in single, dual and quad mode on a custom board with the
NXP FlexSPI controller. Also the BP bits as well as the TB bit were
tested.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 9325c6f4c1eb..a482c9ca74dd 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2649,6 +2649,11 @@ static const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, { |