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authorSowjanya Komatineni <skomatineni@nvidia.com>2019-03-23 21:45:25 -0700
committerUlf Hansson <ulf.hansson@linaro.org>2019-04-15 11:55:54 +0200
commit688956440e80946e164289b23e54309bcbca7144 (patch)
tree17c4bb1bc1af4b540e6e3d4bf880413c0ead5226 /drivers/mmc
parentc6e7ab909262f3c9a1f35c1a9cc9f59200531b16 (diff)
mmc: cqhci: add CQHCI_SSC1 register CBC field mask
This patch adds define for CBC field mask of the register CQHCI_SSC1. Tested-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/cqhci.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
index 928ec491eecf..1e8e01d81015 100644
--- a/drivers/mmc/host/cqhci.h
+++ b/drivers/mmc/host/cqhci.h
@@ -88,6 +88,7 @@
/* send status config 1 */
#define CQHCI_SSC1 0x40
+#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
/* send status config 2 */
#define CQHCI_SSC2 0x44