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authoryong mao <yong.mao@mediatek.com>2019-08-28 17:45:24 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2019-09-11 15:58:39 +0200
commit26c71a13a8f9db0c5f24f5c0ec6a9f7e1da0dd5a (patch)
tree2805fb20951fe8112b76a17bc4ad8f59761ddc20 /drivers/mmc
parent7353788c6a63ddfd0f0dec10049b0bef3da8d0bd (diff)
mmc: mediatek: enable SDIO IRQ low level trigger function
SDIO IRQ is not defaultly triggered by low level, but by falling edge. It needs to set related register to enable SDIO IRQ low level trigger function. Otherwise the SDIO IRQ may be lost in some specail condition. Signed-off-by: Yong Mao <yong.mao@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/mtk-sd.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 4c72c5b73e87..6946bb040a28 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -192,6 +192,7 @@
#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
+#define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */
/* SDC_ADV_CFG0 mask */
#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
@@ -1577,6 +1578,7 @@ static void msdc_init_hw(struct msdc_host *host)
/* Config SDIO device detect interrupt function */
sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
+ sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
/* Configure to default data timeout */
sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);