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authorSeungwon Jeon <tgih.jun@samsung.com>2014-03-14 21:12:13 +0900
committerChris Ball <chris@printf.net>2014-04-20 16:59:41 -0400
commit6dad6c9594577969f6d74ca1b344e00314bb3b64 (patch)
tree8978ad284412ac7082255c6cedaef3d194f7bde5 /drivers/mmc/host
parent79f7ae7c45a6ccf04e2908337461dee615f6afb0 (diff)
mmc: mmci: clarify DDR timing mode between SD-UHS and eMMC
Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS. CC: Russell King <linux@arm.linux.org.uk> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/mmci.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 771c60ab4a32..7e853932393b 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -299,7 +299,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
clk |= MCI_ST_8BIT_BUS;
- if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
+ if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
+ host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
clk |= MCI_ST_UX500_NEG_EDGE;
mmci_write_clkreg(host, clk);
@@ -784,7 +785,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
mmci_write_clkreg(host, clk);
}
- if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
+ if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
+ host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
datactrl |= MCI_ST_DPSM_DDRMODE;
/*