diff options
| author | Matthew Fleming <matthew.fleming@imgtec.com> | 2008-10-02 12:24:05 +0100 |
|---|---|---|
| committer | Pierre Ossman <drzeus@drzeus.cx> | 2008-10-12 11:04:37 +0200 |
| commit | 0d3e0460f307e84904968aad6cff97bd688583d8 (patch) | |
| tree | ea939e4e6b8a5b24b294932974fbe42ca7d427be /drivers/mmc/core | |
| parent | 7244b85bd17313d7d300ee93ec7bfbca1f4ccf3d (diff) | |
MMC: CSD and CID timeout values
The MMC spec states that the timeout for accessing the CSD and CID
registers is 64 clock cycles.
Signed-off-by: Matthew Fleming <matthew.fleming@imgtec.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Diffstat (limited to 'drivers/mmc/core')
| -rw-r--r-- | drivers/mmc/core/mmc_ops.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index 64b05c6270f2..9c50e6f1c236 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c @@ -248,8 +248,12 @@ mmc_send_cxd_data(struct mmc_card *card, struct mmc_host *host, sg_init_one(&sg, data_buf, len); - if (card) - mmc_set_data_timeout(&data, card); + /* + * The spec states that CSR and CID accesses have a timeout + * of 64 clock cycles. + */ + data.timeout_ns = 0; + data.timeout_clks = 64; mmc_wait_for_req(host, &mrq); |