diff options
| author | Oded Gabbay <ogabbay@kernel.org> | 2021-01-26 22:59:35 +0200 |
|---|---|---|
| committer | Oded Gabbay <ogabbay@kernel.org> | 2021-01-27 21:03:51 +0200 |
| commit | f1aebf5e3d606a2a910eed54bc8d17655f12b606 (patch) | |
| tree | eac24a558c8a72edd4e7d1bd68dc9348a7a7157a /drivers/misc/habanalabs | |
| parent | 230cd89480d322ff76ed241973158059a170fc5c (diff) | |
habanalabs: update to latest hl_boot_if.h spec from F/W
It adds the definition for indication that the F/W handles HBM ECC
events.
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs')
| -rw-r--r-- | drivers/misc/habanalabs/include/common/hl_boot_if.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h index e29c77bdea07..57785478a4ef 100644 --- a/drivers/misc/habanalabs/include/common/hl_boot_if.h +++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h @@ -69,8 +69,9 @@ * image has failed to match expected * checksum. Trying to program image again * might solve this. + * * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one - * of the PLLs remained in REF_CLK + * of the PLLs remains in REF_CLK * * CPU_BOOT_ERR0_ENABLED Error registers enabled. * This is a main indication that the @@ -161,6 +162,10 @@ * FW initialized Clock Gating. * Initialized in: preboot * + * CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled. + * FW handles HBM ECC indications. + * Initialized in: linux + * * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. * This is a main indication that the * running FW populates the device status @@ -184,6 +189,7 @@ #define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << 11) #define CPU_BOOT_DEV_STS0_SP_SRAM_EN (1 << 12) #define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << 13) +#define CPU_BOOT_DEV_STS0_HBM_ECC_EN (1 << 14) #define CPU_BOOT_DEV_STS0_ENABLED (1 << 31) enum cpu_boot_status { |