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author | gexueyuan <gexueyuan@gmail.com> | 2021-03-31 11:10:56 +0800 |
---|---|---|
committer | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-04-05 16:15:58 +0200 |
commit | 25dcca7fedcd4e31cb368ad846bfd738c0c6307c (patch) | |
tree | 634d9b979ad0ed8717332b9cff72768ed4ef172f /drivers/memory | |
parent | b11a188aef6d19fe3ca505831d9c627ef683476f (diff) |
memory: pl353: fix mask of ECC page_size config register
The mask for page size of ECC Configuration Register should be 0x3,
according to the datasheet of PL353 smc.
Fixes: fee10bd22678 ("memory: pl353: Add driver for arm pl353 static memory controller")
Signed-off-by: gexueyuan <gexueyuan@gmail.com>
Link: https://lore.kernel.org/r/20210331031056.5326-1-gexueyuan@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r-- | drivers/memory/pl353-smc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c index 3b5b1045edd9..9c0a28416777 100644 --- a/drivers/memory/pl353-smc.c +++ b/drivers/memory/pl353-smc.c @@ -63,7 +63,7 @@ /* ECC memory config register specific constants */ #define PL353_SMC_ECC_MEMCFG_MODE_MASK 0xC #define PL353_SMC_ECC_MEMCFG_MODE_SHIFT 2 -#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0xC +#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0x3 #define PL353_SMC_DC_UPT_NAND_REGS ((4 << 23) | /* CS: NAND chip */ \ (2 << 21)) /* UpdateRegs operation */ |