diff options
| author | Peter Collingbourne <pcc@google.com> | 2021-05-07 11:59:05 -0700 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2021-05-10 18:56:25 +0100 |
| commit | 37a8024d265564eba680575df6421f19db21dfce (patch) | |
| tree | dd261c684b25c33c1ee9c748ed16c0d83367c8ea /drivers/memory/ti-emif-sram-pm.S | |
| parent | a1bed090fc56e6e24517d96bc076595544fb5317 (diff) | |
arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup
A valid implementation choice for the ChooseRandomNonExcludedTag()
pseudocode function used by IRG is to behave in the same way as with
GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR
which must have a non-zero value in order for IRG to properly produce
pseudorandom numbers. However, RGSR_EL1 is reset to an UNKNOWN value
on soft reset and thus may reset to 0. Therefore we must initialize
RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves
as expected.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Fixes: 3b714d24ef17 ("arm64: mte: CPU feature detection and initial sysreg configuration")
Cc: <stable@vger.kernel.org> # 5.10
Link: https://linux-review.googlesource.com/id/I2b089b6c7d6f17ee37e2f0db7df5ad5bcc04526c
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210507185905.1745402-1-pcc@google.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'drivers/memory/ti-emif-sram-pm.S')
0 files changed, 0 insertions, 0 deletions