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authorKeith Busch <keith.busch@intel.com>2017-02-03 16:46:13 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-02-10 14:36:14 -0600
commitabdbf4d635a9a8c956bb9757a9d4f08c2abe1f97 (patch)
tree505f28df23e7cf1413c3537f258f722f2627492d /drivers/memory/tegra/tegra114.c
parent87b336d003d47876e376d943be3c9d35152f3b86 (diff)
PCI/DPC: Wait for Root Port busy to clear
Per PCIe r3.1, sec 6.2.10 and sec 7.13.4, on Root Ports that support "RP Extensions for DPC", When the DPC Trigger Status bit is Set and the DPC RP Busy bit is Set, software must leave the Root Port in DPC until the DPC RP Busy bit reads 0b. Wait up to 1 second for the Root Port to become non-busy. [bhelgaas: changelog, spec references] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/memory/tegra/tegra114.c')
0 files changed, 0 insertions, 0 deletions