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| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-06-22 12:16:24 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:52:09 +0100 |
| commit | cac8f5d28e56c405befd1613fc38c962aaf69f30 (patch) | |
| tree | db75fe3b01234730fee1d89847e102a49c5ebc3a /drivers/media/i2c/ccs/ccs-data.h | |
| parent | e583e654565fd12e45d8cef64dcdd80e2902ac13 (diff) | |
media: ccs-pll: Add support for lane speed model
CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.
Move calculation of the pixel rate on the CSI-2 bus early in the function
as everything needed to calculate it is already available.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs/ccs-data.h')
0 files changed, 0 insertions, 0 deletions