diff options
| author | Fabrice Gasnier <fabrice.gasnier@st.com> | 2020-11-06 17:57:26 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2020-11-14 15:51:13 +0000 |
| commit | 89d1f72570027aa9724f00454f51885e27221413 (patch) | |
| tree | e08c6b1f48848753d18b2adc3b398933371d0699 /drivers/irqchip/irq-mips-gic.c | |
| parent | 8dedcc3eee3aceb37832176f0a1b03d5687acda3 (diff) | |
iio: adc: stm32-adc: adapt clock duty cycle for proper operation
For proper operation, STM32 ADC should be used with a clock duty cycle
of 50%, in the range of 49% to 51%. Depending on the clock tree, divider
can be used in case clock duty cycle is out of this range.
In case clk_get_scaled_duty_cycle() returns an error, kindly apply a
divider by default (don't make the probe fail).
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Link: https://lore.kernel.org/r/1604681846-31234-1-git-send-email-fabrice.gasnier@st.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/irqchip/irq-mips-gic.c')
0 files changed, 0 insertions, 0 deletions