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authorPetr Machata <petrm@mellanox.com>2018-09-20 09:21:25 +0300
committerDavid S. Miller <davem@davemloft.net>2018-09-20 07:46:01 -0700
commit3a4dbfb044ea37e9cabb1e2499859e423a96ab15 (patch)
tree1b8d0698b2da0741d4e792174be2f195112e2a37 /drivers/irqchip/irq-goldfish-pic.c
parenta9f36656b519a9a21309793c306941a3cd0eeb8f (diff)
mlxsw: spectrum_buffers: Use devlink pool indices throughout
Currently, mlxsw assumes that each ingress pool has its egress counterpart, and that pool index for purposes of caching matches the index with which the hardware should be configured. As we want to expose the MC pool, both of these assumptions break. Instead, maintain the pool index as long as possible. Unify ingress and egress caches and use the pool index as cache index as well. Only translate to FW pool numbering when actually packing the registers. This simplifies things considerably, as the pool index is the only quantity necessary to uniquely identify a pool, and the pool/direction split is not necessary until firmware is talked to. To support the mapping between pool indices and pool numbers and directions, which is not neatly mathematical anymore, introduce a pool descriptor table, indexed by pool index, to facilitate the translation. Include the MC pool in the descriptor table as well, so that it can be referenced from mlxsw_sp_sb_cms_egress. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/irqchip/irq-goldfish-pic.c')
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