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authorDave Airlie <airlied@redhat.com>2020-11-06 14:37:56 +1000
committerDave Airlie <airlied@redhat.com>2020-11-06 15:00:01 +1000
commitc0f98d2f8b076bf3e3183aa547395f919c943a14 (patch)
tree943ca640139742367c9b22aaec0c9f7b67ab631e /drivers/iommu
parente047c7be173caab95f3876ab30c03ebcf654c300 (diff)
parent24e146cdf9f5a8fb464dd98ba8357d662d37d22f (diff)
Merge tag 'drm-misc-next-2020-11-05' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.11: UAPI Changes: Cross-subsystem Changes: - arch/arm64: Describe G12b GPU as coherent - iommu: Support coherency for Mali LPAE Core Changes: - atomic: Pass full state to CRTC atomic_{check, begin, flush}(); Use atomic-state pointers - drm: Remove SCATTER_LIST_MAX_SEGMENT; Cleanups - doc: Document legacy_cursor_update better; cleanups - edid: Don't warn n EDIDs of zero - ttm: New backend allocation pool; Remove old page allocator; Rework no_retry handling; Replace flags with booleans in struct ttm_operation_ctx - vram-helper: Cleanups - fbdev: Cleanups - console: Store font size as unsigned value Driver Changes: - ast: Support new display mode - amdgpu: Switch to new TTM allocator - hisilicon: Cleanups - nouveau: Switch to new TTM allocator; Fix include of swiotbl.h and limits.h; Use state helper instead of CRTC state pointer - panfrost: Support cache-coherent integrations; Fix mutex corruption on open/close; Cleanupse - qxl: Cleanups - radeon: Switch to new TTM allocator - ticdc: Fix build failure - vmwgfx: Switch to new TTM allocator - xlnx: Use dma_request_chan - fbdev/sh_mobile: Cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20201105101641.GA13099@linux-uq9g
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/io-pgtable-arm.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index a7a9bc08dcd1..bcfbd0e44a4a 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -417,7 +417,13 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
}
- if (prot & IOMMU_CACHE)
+ /*
+ * Also Mali has its own notions of shareability wherein its Inner
+ * domain covers the cores within the GPU, and its Outer domain is
+ * "outside the GPU" (i.e. either the Inner or System domain in CPU
+ * terms, depending on coherency).
+ */
+ if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
pte |= ARM_LPAE_PTE_SH_IS;
else
pte |= ARM_LPAE_PTE_SH_OS;
@@ -1021,6 +1027,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
ARM_MALI_LPAE_TTBR_READ_INNER |
ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
+ if (cfg->coherent_walk)
+ cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
+
return &data->iop;
out_free_data: