diff options
| author | Will Deacon <will@kernel.org> | 2020-11-25 13:10:41 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-11-25 13:10:41 +0000 |
| commit | 9c00c6400f8008971069fce290d404212b5f35ca (patch) | |
| tree | 5c447e7a68da8fd646a5c7a811e5e06115b78df5 /drivers/iommu | |
| parent | a29bbb0861f487a5e144dc997a9f71a36c7a2404 (diff) | |
| parent | e67890c97944b9962cf8c140a7f8077ed643b7d7 (diff) | |
Merge branch 'for-next/iommu/io-pgtable-domain-attr' into for-next/iommu/arm-smmu
Merge in support for the new DOMAIN_ATTR_IO_PGTABLE_CFG domain attribute
and its associated IO_PGTABLE_QUIRK_ARM_OUTER_WBWA io-pgtable quirk,
as these are needed to enable support for Qualcomm's System Cache in
conjunction with their GPU SMMU.
* for-next/iommu/io-pgtable-domain-attr:
iommu/io-pgtable-arm: Add support to use system cache
iommu/io-pgtable: Add a domain attribute for pagetable configuration
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/io-pgtable-arm.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index a7a9bc08dcd1..7c9ea9d7874a 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -761,7 +761,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NON_STRICT | - IO_PGTABLE_QUIRK_ARM_TTBR1)) + IO_PGTABLE_QUIRK_ARM_TTBR1 | + IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)) return NULL; data = arm_lpae_alloc_pgtable(cfg); @@ -773,10 +774,15 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) tcr->sh = ARM_LPAE_TCR_SH_IS; tcr->irgn = ARM_LPAE_TCR_RGN_WBWA; tcr->orgn = ARM_LPAE_TCR_RGN_WBWA; + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA) + goto out_free_data; } else { tcr->sh = ARM_LPAE_TCR_SH_OS; tcr->irgn = ARM_LPAE_TCR_RGN_NC; - tcr->orgn = ARM_LPAE_TCR_RGN_NC; + if (!(cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)) + tcr->orgn = ARM_LPAE_TCR_RGN_NC; + else + tcr->orgn = ARM_LPAE_TCR_RGN_WBWA; } tg1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1; |