iommu: add ARM LPAE page table allocator

A number of IOMMUs found in ARM SoCs can walk architecture-compatible
page tables.

This patch adds a generic allocator for Stage-1 and Stage-2 v7/v8
long-descriptor page tables. 4k, 16k and 64k pages are supported, with
up to 4-levels of walk to cover a 48-bit address space.

Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
index fdd792c37698..05c4e593a25f 100644
--- a/drivers/iommu/io-pgtable.h
+++ b/drivers/iommu/io-pgtable.h
@@ -5,6 +5,10 @@
  * Public API for use by IOMMU drivers
  */
 enum io_pgtable_fmt {
+	ARM_32_LPAE_S1,
+	ARM_32_LPAE_S2,
+	ARM_64_LPAE_S1,
+	ARM_64_LPAE_S2,
 	IO_PGTABLE_NUM_FMTS,
 };
 
@@ -47,6 +51,16 @@ struct io_pgtable_cfg {
 
 	/* Low-level data specific to the table format */
 	union {
+		struct {
+			u64	ttbr[2];
+			u64	tcr;
+			u64	mair[2];
+		} arm_lpae_s1_cfg;
+
+		struct {
+			u64	vttbr;
+			u64	vtcr;
+		} arm_lpae_s2_cfg;
 	};
 };