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authorThomas Gleixner <tglx@linutronix.de>2020-10-24 22:35:20 +0100
committerThomas Gleixner <tglx@linutronix.de>2020-10-28 20:26:27 +0100
commit341b4a7211b6ba3a7089e1dc09ac4bd576dfb05f (patch)
treeb426a1bb19d527d4ea4da146a4d38789507a2d65 /drivers/iommu/amd/iommu.c
parenta27dca645d2c0f31abb7858aa0e10b2fa0f2f659 (diff)
x86/ioapic: Cleanup IO/APIC route entry structs
Having two seperate structs for the I/O-APIC RTE entries (non-remapped and DMAR remapped) requires type casts and makes it hard to map. Combine them in IO_APIC_routing_entry by defining a union of two 64bit bitfields. Use naming which reflects which bits are shared and which bits are actually different for the operating modes. [dwmw2: Fix it up and finish the job, pulling the 32-bit w1,w2 words for register access into the same union and eliminating a few more places where bits were accessed through masks and shifts.] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20201024213535.443185-21-dwmw2@infradead.org
Diffstat (limited to 'drivers/iommu/amd/iommu.c')
-rw-r--r--drivers/iommu/amd/iommu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index b0e5210e53b2..3d72ec7bbbf8 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -3687,11 +3687,11 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data,
entry = info->ioapic.entry;
info->ioapic.entry = NULL;
memset(entry, 0, sizeof(*entry));
- entry->vector = index;
- entry->trigger = info->ioapic.is_level;
- entry->polarity = info->ioapic.active_low;
+ entry->vector = index;
+ entry->is_level = info->ioapic.is_level;
+ entry->active_low = info->ioapic.active_low;
/* Mask level triggered irqs. */
- entry->mask = info->ioapic.is_level;
+ entry->masked = info->ioapic.is_level;
break;
case X86_IRQ_ALLOC_TYPE_HPET: