diff options
| author | oulijun <oulijun@huawei.com> | 2017-11-10 16:55:50 +0800 |
|---|---|---|
| committer | Doug Ledford <dledford@redhat.com> | 2017-11-10 12:31:52 -0500 |
| commit | b5fddb7ce768a2e97dcf90614c5da4a7824bdc81 (patch) | |
| tree | 03374c820f8b80166d0c37cf53383262c82cd540 /drivers/infiniband/hw | |
| parent | 2872646134aa5cb99f674d81c1fdb0d595243499 (diff) | |
RDMA/hns: Add sq_invld_flg field in QP context
In hip08 RoCE, it need to add the sq_invld_flg field
in QP context for RoCE hardware.
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Shaobo Xu <xushaobo2@huawei.com>
Signed-off-by: Yixian Liu <liuyixian@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Diffstat (limited to 'drivers/infiniband/hw')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 2 | ||||
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 6 |
2 files changed, 6 insertions, 2 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index d74a5220d826..c1f33251a73c 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -2042,6 +2042,8 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, roce_set_bit(qpc_mask->byte_168_irrl_idx, V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0); + roce_set_bit(qpc_mask->byte_168_irrl_idx, + V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0); roce_set_field(qpc_mask->byte_168_irrl_idx, V2_QPC_BYTE_168_IRRL_IDX_LSB_M, V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0); diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 3d9114ee0154..04b7a51b8efb 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -606,8 +606,10 @@ struct hns_roce_v2_qp_context { #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20 -#define V2_QPC_BYTE_168_LP_SGEN_INI_S 21 -#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 21) +#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21 + +#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22 +#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22) #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24 #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24) |