diff options
author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2017-10-10 14:32:12 -0600 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-10-20 15:03:06 +0200 |
commit | 0bbb194c0c33c251ac3d33f46c8fd045d82350e5 (patch) | |
tree | 4bcde932e0f28bc9efbd2345eb6e82c1e5972c47 /drivers/hwtracing/coresight/coresight-etm3x.c | |
parent | 58f2c391cc0560231d7636c39d31b1b26c9396b7 (diff) |
coresight: Extend the PIDR mask to cover relevant bits in PIDR2
As per coresight standards, PIDR2 register has the following format :
[2-0] - JEP106_bits6to4
[3] - JEDEC, designer ID is specified by JEDEC.
However some of the drivers only use mask of 0x3 for the PIDR2 leaving
bits [3-2] unchecked, which could potentially match the component for
a different device altogether. This patch fixes the mask and the
corresponding id bits for the existing devices.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-etm3x.c')
-rw-r--r-- | drivers/hwtracing/coresight/coresight-etm3x.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index e5b1ec57dbde..39f42fdd503d 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -901,33 +901,33 @@ static const struct dev_pm_ops etm_dev_pm_ops = { static const struct amba_id etm_ids[] = { { /* ETM 3.3 */ - .id = 0x0003b921, - .mask = 0x0003ffff, + .id = 0x000bb921, + .mask = 0x000fffff, .data = "ETM 3.3", }, { /* ETM 3.5 - Cortex-A5 */ - .id = 0x0003b955, - .mask = 0x0003ffff, + .id = 0x000bb955, + .mask = 0x000fffff, .data = "ETM 3.5", }, { /* ETM 3.5 */ - .id = 0x0003b956, - .mask = 0x0003ffff, + .id = 0x000bb956, + .mask = 0x000fffff, .data = "ETM 3.5", }, { /* PTM 1.0 */ - .id = 0x0003b950, - .mask = 0x0003ffff, + .id = 0x000bb950, + .mask = 0x000fffff, .data = "PTM 1.0", }, { /* PTM 1.1 */ - .id = 0x0003b95f, - .mask = 0x0003ffff, + .id = 0x000bb95f, + .mask = 0x000fffff, .data = "PTM 1.1", }, { /* PTM 1.1 Qualcomm */ - .id = 0x0003006f, - .mask = 0x0003ffff, + .id = 0x000b006f, + .mask = 0x000fffff, .data = "PTM 1.1", }, { 0, 0}, |