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authorStefan Roese <sr@denx.de>2015-10-19 08:40:13 +0200
committerBrian Norris <computersforpeace@gmail.com>2015-10-26 13:19:40 -0700
commite278fc71b2c63905d3631b8d7b12ab7bcba9d2be (patch)
tree5560d7283e2ae7f9824d3b9ef725a803d9263f38 /drivers/hwmon
parent48c25cf441182e629e52e7f9fa56c2019e75fb00 (diff)
mtd: fsmc_nand: Add BCH4 SW ECC support for SPEAr600
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your nand controller DT node: nand-ecc-mode = "soft_bch"; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; Tested on a custom SPEAr600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> [Brian: tweaked the comments a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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