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authorPrike.Liang <Prike.Liang@amd.com>2020-06-08 15:20:56 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 01:59:18 -0400
commit207f0f13574825a700a4ea52d3ac4821cea627c8 (patch)
tree799ba6266e61fa9519cab7435ab30608de0cb2b9 /drivers/gpu
parentd00c3d045cd91b8d45e0a9cdfd91d4ace4e0bbc9 (diff)
drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base accessing
The failed case is no SDMA1 IP for Renoir discovery table while in accessing SDMA1 reg base, thus need have nullptr test for soc15_read_register invoked in MMR addres space inquire opt. Signed-off-by: Prike.Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 623745b2d8b3..3e406eeeaff6 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -415,7 +415,8 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
*value = 0;
for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
en = &soc15_allowed_read_registers[i];
- if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
+ if (adev->reg_offset[en->hwip][en->inst] &&
+ reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
+ en->reg_offset))
continue;