diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2018-05-23 13:00:02 +0200 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2018-05-24 10:21:15 +0900 |
| commit | cb5fba715babc599e82f40d53b6b956efcc8fc25 (patch) | |
| tree | d56cf7f81d2e39d826365808d89a41125f56e746 /drivers/gpu/drm | |
| parent | e05f3ea260d6db1fb9aede6af29d7cf8f491f0ed (diff) | |
drm/exynos: decon: Add support for hardware windows no 4 and 5
Enable support for 2 more hardware windows. This require enabling a few
more clocks and set proper plane type for all windows. In the new
configuration primary plane uses hardware window no 3 and cursor uses
window no 5. The remaining hardware windows are used for overlays. This
gives us an overlay plane both below and above primary plane for both
Decon and DeconTV (which uses hardware window nr 0 for background).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 1c330f2a7a5d..82c95c34447f 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -31,7 +31,10 @@ #define DSD_CFG_MUX 0x1004 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13) -#define WINDOWS_NR 3 +#define WINDOWS_NR 5 +#define PRIMARY_WIN 2 +#define CURSON_WIN 4 + #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 #define I80_HW_TRG (1 << 0) @@ -43,6 +46,9 @@ static const char * const decon_clks_name[] = { "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", + "aclk_smmu_decon1x", + "aclk_xiu_decon1x", + "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk", }; @@ -74,9 +80,8 @@ static const uint32_t decon_formats[] = { }; static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { - DRM_PLANE_TYPE_PRIMARY, - DRM_PLANE_TYPE_OVERLAY, - DRM_PLANE_TYPE_CURSOR, + [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY, + [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, }; static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, @@ -552,12 +557,10 @@ static int decon_bind(struct device *dev, struct device *master, void *data) drm_dev->max_vblank_count = 0xffffffff; for (win = ctx->first_win; win < WINDOWS_NR; win++) { - int tmp = (win == ctx->first_win) ? 0 : win; - ctx->configs[win].pixel_formats = decon_formats; ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); - ctx->configs[win].zpos = win; - ctx->configs[win].type = decon_win_types[tmp]; + ctx->configs[win].zpos = win - ctx->first_win; + ctx->configs[win].type = decon_win_types[win]; ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, &ctx->configs[win]); @@ -565,7 +568,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) return ret; } - exynos_plane = &ctx->planes[ctx->first_win]; + exynos_plane = &ctx->planes[PRIMARY_WIN]; out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI : EXYNOS_DISPLAY_TYPE_LCD; ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |