diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-10-03 11:09:16 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-10-03 11:09:16 +0200 |
| commit | 0d3c24e936feefeca854073ccb40613cd6eba9a9 (patch) | |
| tree | 1f675397b924846740b0931b066ddce6f3d7eb3d /drivers/gpu/drm | |
| parent | 1af0838de60e723cb02253ecc9b555c30f8f6a6f (diff) | |
| parent | ebec44a2456fbe5fe18aae88f6010f6878f0cb4a (diff) | |
Merge airlied/drm-next into drm-misc-next
Just catching up with upstream.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
504 files changed, 21693 insertions, 45124 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c9f09fc298bb..4d9f21831741 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -184,6 +184,7 @@ config DRM_AMDGPU select BACKLIGHT_CLASS_DEVICE select BACKLIGHT_LCD_SUPPORT select INTERVAL_TREE + select CHASH help Choose this option if you have a recent AMD Radeon graphics card. @@ -191,6 +192,8 @@ config DRM_AMDGPU source "drivers/gpu/drm/amd/amdgpu/Kconfig" +source "drivers/gpu/drm/amd/lib/Kconfig" + source "drivers/gpu/drm/nouveau/Kconfig" source "drivers/gpu/drm/i915/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 0ee184f56a60..a3fdc5a68dff 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_DRM_ARM) += arm/ obj-$(CONFIG_DRM_TTM) += ttm/ obj-$(CONFIG_DRM_TDFX) += tdfx/ obj-$(CONFIG_DRM_R128) += r128/ +obj-y += amd/lib/ obj-$(CONFIG_HSA_AMD) += amd/amdkfd/ obj-$(CONFIG_DRM_RADEON)+= radeon/ obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/ diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 658bac0cdc5e..25a95c95df14 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -133,5 +133,3 @@ include $(FULL_AMD_PATH)/powerplay/Makefile amdgpu-y += $(AMD_POWERPLAY_FILES) obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o - -CFLAGS_amdgpu_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a5427cf4b19d..ebfc267467ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -65,6 +65,7 @@ #include "amdgpu_uvd.h" #include "amdgpu_vce.h" #include "amdgpu_vcn.h" +#include "amdgpu_mn.h" #include "gpu_scheduler.h" #include "amdgpu_virt.h" @@ -76,7 +77,7 @@ extern int amdgpu_modeset; extern int amdgpu_vram_limit; extern int amdgpu_vis_vram_limit; -extern unsigned amdgpu_gart_size; +extern int amdgpu_gart_size; extern int amdgpu_gtt_size; extern int amdgpu_moverate; extern int amdgpu_benchmarking; @@ -91,11 +92,12 @@ extern int amdgpu_dpm; extern int amdgpu_fw_load_type; extern int amdgpu_aspm; extern int amdgpu_runtime_pm; -extern unsigned amdgpu_ip_block_mask; +extern uint amdgpu_ip_block_mask; extern int amdgpu_bapm; extern int amdgpu_deep_color; extern int amdgpu_vm_size; extern int amdgpu_vm_block_size; +extern int amdgpu_vm_fragment_size; extern int amdgpu_vm_fault_stop; extern int amdgpu_vm_debug; extern int amdgpu_vm_update_mode; @@ -103,14 +105,14 @@ extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_no_evict; extern int amdgpu_direct_gma_size; -extern unsigned amdgpu_pcie_gen_cap; -extern unsigned amdgpu_pcie_lane_cap; -extern unsigned amdgpu_cg_mask; -extern unsigned amdgpu_pg_mask; -extern unsigned amdgpu_sdma_phase_quantum; +extern uint amdgpu_pcie_gen_cap; +extern uint amdgpu_pcie_lane_cap; +extern uint amdgpu_cg_mask; +extern uint amdgpu_pg_mask; +extern uint amdgpu_sdma_phase_quantum; extern char *amdgpu_disable_cu; extern char *amdgpu_virtual_display; -extern unsigned amdgpu_pp_feature_mask; +extern uint amdgpu_pp_feature_mask; extern int amdgpu_vram_page_split; extern int amdgpu_ngg; extern int amdgpu_prim_buf_per_se; @@ -177,6 +179,7 @@ struct amdgpu_cs_parser; struct amdgpu_job; struct amdgpu_irq_src; struct amdgpu_fpriv; +struct amdgpu_bo_va_mapping; enum amdgpu_cp_irq { AMDGPU_CP_IRQ_GFX_EOP = 0, @@ -291,14 +294,25 @@ struct amdgpu_buffer_funcs { /* provided by hw blocks that can write ptes, e.g., sdma */ struct amdgpu_vm_pte_funcs { + /* number of dw to reserve per operation */ + unsigned copy_pte_num_dw; + /* copy pte entries from GART */ void (*copy_pte)(struct amdgpu_ib *ib, uint64_t pe, uint64_t src, unsigned count); + /* write pte one entry at a time with addr mapping */ void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, uint64_t value, unsigned count, uint32_t incr); + + /* maximum nums of PTEs/PDEs in a single operation */ + uint32_t set_max_nums_pte_pde; + + /* number of dw to reserve per operation */ + unsigned set_pte_pde_num_dw; + /* for linear pte/pde updates without addr mapping */ void (*set_pte_pde)(struct amdgpu_ib *ib, uint64_t pe, @@ -331,6 +345,7 @@ struct amdgpu_gart_funcs { struct amdgpu_ih_funcs { /* ring read/write ptr handling, called from interrupt context */ u32 (*get_wptr)(struct amdgpu_device *adev); + bool (*prescreen_iv)(struct amdgpu_device *adev); void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); void (*set_rptr)(struct amdgpu_device *adev); @@ -398,6 +413,7 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); /* sub-allocation manager, it has to be protected by another lock. @@ -454,9 +470,10 @@ struct amdgpu_sa_bo { */ void amdgpu_gem_force_release(struct amdgpu_device *adev); int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, - int alignment, u32 initial_domain, - u64 flags, bool kernel, - struct drm_gem_object **obj); + int alignment, u32 initial_domain, + u64 flags, bool kernel, + struct reservation_object *resv, + struct drm_gem_object **obj); int amdgpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, @@ -730,8 +747,8 @@ struct amdgpu_ctx_mgr { struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); int amdgpu_ctx_put(struct amdgpu_ctx *ctx); -uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, - struct dma_fence *fence); +int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, + struct dma_fence *fence, uint64_t *seq); struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, uint64_t seq); @@ -748,6 +765,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); struct amdgpu_fpriv { struct amdgpu_vm vm; struct amdgpu_bo_va *prt_va; + struct amdgpu_bo_va *csa_va; struct mutex bo_list_lock; struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; @@ -1012,7 +1030,6 @@ struct amdgpu_gfx { /* reset mask */ uint32_t grbm_soft_reset; uint32_t srbm_soft_reset; - bool in_reset; /* s3/s4 mask */ bool in_suspend; /* NGG */ @@ -1054,6 +1071,7 @@ struct amdgpu_cs_parser { /* buffer objects */ struct ww_acquire_ctx ticket; struct amdgpu_bo_list *bo_list; + struct amdgpu_mn *mn; struct amdgpu_bo_list_entry vm_pd; struct list_head validated; struct dma_fence *fence; @@ -1181,6 +1199,9 @@ struct amdgpu_firmware { /* gpu info firmware data pointer */ const struct firmware *gpu_info_fw; + + void *fw_buf_ptr; + uint64_t fw_buf_mc; }; /* @@ -1195,20 +1216,6 @@ void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); void amdgpu_test_moves(struct amdgpu_device *adev); /* - * MMU Notifier - */ -#if defined(CONFIG_MMU_NOTIFIER) -int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); -void amdgpu_mn_unregister(struct amdgpu_bo *bo); -#else -static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) -{ - return -ENODEV; -} -static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} -#endif - -/* * Debugfs */ struct amdgpu_debugfs { @@ -1482,9 +1489,6 @@ struct amdgpu_device { struct amdgpu_mman mman; struct amdgpu_vram_scratch vram_scratch; struct amdgpu_wb wb; - atomic64_t vram_usage; - atomic64_t vram_vis_usage; - atomic64_t gtt_usage; atomic64_t num_bytes_moved; atomic64_t num_evictions; atomic64_t num_vram_cpu_page_faults; @@ -1593,6 +1597,7 @@ struct amdgpu_device { /* record last mm index being written through WREG32*/ unsigned long last_mm_index; + bool in_sriov_reset; }; static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) @@ -1760,6 +1765,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) +#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) @@ -1792,18 +1798,6 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, u64 num_vis_bytes); void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); -int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); -int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, - uint32_t flags); -bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); -struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); -bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, - unsigned long end); -bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, - int *last_invalidated); -bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); -uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, - struct ttm_mem_reg *mem); void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); @@ -1886,10 +1880,9 @@ static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } #endif -struct amdgpu_bo_va_mapping * -amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, - uint64_t addr, struct amdgpu_bo **bo); -int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); +int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, + uint64_t addr, struct amdgpu_bo **bo, + struct amdgpu_bo_va_mapping **mapping); #include "amdgpu_object.h" #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index c7bcf5207d79..5432af39a674 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -28,14 +28,14 @@ #include <linux/module.h> const struct kgd2kfd_calls *kgd2kfd; -bool (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**); +bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**); int amdgpu_amdkfd_init(void) { int ret; #if defined(CONFIG_HSA_AMD_MODULE) - int (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**); + int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**); kgd2kfd_init_p = symbol_request(kgd2kfd_init); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index b8802a561cbd..8d689ab7e429 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -26,6 +26,7 @@ #define AMDGPU_AMDKFD_H_INCLUDED #include <linux/types.h> +#include <linux/mmu_context.h> #include <kgd_kfd_interface.h> struct amdgpu_device; @@ -60,4 +61,19 @@ uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd); +#define read_user_wptr(mmptr, wptr, dst) \ + ({ \ + bool valid = false; \ + if ((mmptr) && (wptr)) { \ + if ((mmptr) == current->mm) { \ + valid = !get_user((dst), (wptr)); \ + } else if (current->mm == NULL) { \ + use_mm(mmptr); \ + valid = !get_user((dst), (wptr)); \ + unuse_mm(mmptr); \ + } \ + } \ + valid; \ + }) + #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 5254562fd0f9..dc7e25cce741 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -39,6 +39,12 @@ #include "gmc/gmc_7_1_sh_mask.h" #include "cik_structs.h" +enum hqd_dequeue_request_type { + NO_ACTION = 0, + DRAIN_PIPE, + RESET_WAVES +}; + enum { MAX_TRAPID = 8, /* 3 bits in the bitfield. */ MAX_WATCH_ADDRESSES = 4 @@ -96,12 +102,15 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); @@ -126,6 +135,33 @@ static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid); + +/* Because of REG_GET_FIELD() being used, we put this function in the + * asic specific file. + */ +static int get_tile_config(struct kgd_dev *kgd, + struct tile_config *config) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + + config->gb_addr_config = adev->gfx.config.gb_addr_config; + config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFBANK); + config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFRANKS); + + config->tile_config_ptr = adev->gfx.config.tile_mode_array; + config->num_tile_configs = + ARRAY_SIZE(adev->gfx.config.tile_mode_array); + config->macro_tile_config_ptr = + adev->gfx.config.macrotile_mode_array; + config->num_macro_tile_configs = + ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); + + return 0; +} static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, @@ -133,6 +169,8 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_vmem_size = get_vmem_size, .get_gpu_clock_counter = get_gpu_clock_counter, .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, + .alloc_pasid = amdgpu_vm_alloc_pasid, + .free_pasid = amdgpu_vm_free_pasid, .program_sh_mem_settings = kgd_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, .init_pipeline = kgd_init_pipeline, @@ -150,7 +188,9 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid, .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, .write_vmid_invalidate_request = write_vmid_invalidate_request, - .get_fw_version = get_fw_version + .get_fw_version = get_fw_version, + .set_scratch_backing_va = set_scratch_backing_va, + .get_tile_config = get_tile_config, }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) @@ -186,7 +226,7 @@ static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, { struct amdgpu_device *adev = get_amdgpu_device(kgd); - uint32_t mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, queue_id, 0); @@ -290,20 +330,38 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) } static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - uint32_t wptr_shadow, is_wptr_shadow_valid; struct cik_mqd *m; + uint32_t *mqd_hqd; + uint32_t reg, wptr_val, data; m = get_mqd(mqd); - is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); - if (is_wptr_shadow_valid) - m->cp_hqd_pq_wptr = wptr_shadow; - acquire_queue(kgd, pipe_id, queue_id); - gfx_v7_0_mqd_commit(adev, m); + + /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */ + mqd_hqd = &m->cp_mqd_base_addr_lo; + + for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) + WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); + + /* Copy userspace write pointer value to register. + * Activate doorbell logic to monitor subsequent changes. + */ + data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, + CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); + + if (read_user_wptr(mm, wptr, wptr_val)) + WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); + + data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); + WREG32(mmCP_HQD_ACTIVE, data); + release_queue(kgd); return 0; @@ -382,30 +440,99 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) return false; } -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id) { struct amdgpu_device *adev = get_amdgpu_device(kgd); uint32_t temp; - int timeout = utimeout; + enum hqd_dequeue_request_type type; + unsigned long flags, end_jiffies; + int retry; acquire_queue(kgd, pipe_id, queue_id); WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); - WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type); + switch (reset_type) { + case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: + type = DRAIN_PIPE; + break; + case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: + type = RESET_WAVES; + break; + default: + type = DRAIN_PIPE; + break; + } + + /* Workaround: If IQ timer is active and the wait time is close to or + * equal to 0, dequeueing is not safe. Wait until either the wait time + * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is + * cleared before continuing. Also, ensure wait times are set to at + * least 0x3. + */ + local_irq_save(flags); + preempt_disable(); + retry = 5000; /* wait for 500 usecs at maximum */ + while (true) { + temp = RREG32(mmCP_HQD_IQ_TIMER); + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { + pr_debug("HW is processing IQ\n"); + goto loop; + } + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) + == 3) /* SEM-rearm is safe */ + break; + /* Wait time 3 is safe for CP, but our MMIO read/write + * time is close to 1 microsecond, so check for 10 to + * leave more buffer room + */ + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) + >= 10) + break; + pr_debug("IQ timer is active\n"); + } else + break; +loop: + if (!retry) { + pr_err("CP HQD IQ timer status time out\n"); + break; + } + ndelay(100); + --retry; + } + retry = 1000; + while (true) { + temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); + if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) + break; + pr_debug("Dequeue request is pending\n"); + if (!retry) { + pr_err("CP HQD dequeue request time out\n"); + break; + } + ndelay(100); + --retry; + } + local_irq_restore(flags); + preempt_enable(); + + WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); + + end_jiffies = (utimeout * HZ / 1000) + jiffies; while (true) { temp = RREG32(mmCP_HQD_ACTIVE); - if (temp & CP_HQD_ACTIVE__ACTIVE_MASK) + if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) break; - if (timeout <= 0) { - pr_err("kfd: cp queue preemption time out.\n"); + if (time_after(jiffies, end_jiffies)) { + pr_err("cp queue preemption time out\n"); release_queue(kgd); return -ETIME; } - msleep(20); - timeout -= 20; + usleep_range(500, 1000); } release_queue(kgd); @@ -556,6 +683,16 @@ static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); } +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid) +{ + struct amdgpu_device *adev = (struct amdgpu_device *) kgd; + + lock_srbm(kgd, 0, 0, 0, vmid); + WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); + unlock_srbm(kgd); +} + static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) { struct amdgpu_device *adev = (struct amdgpu_device *) kgd; @@ -566,42 +703,42 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) switch (type) { case KGD_ENGINE_PFP: hdr = (const union amdgpu_firmware_header *) - adev->gfx.pfp_fw->data; + adev->gfx.pfp_fw->data; break; case KGD_ENGINE_ME: hdr = (const union amdgpu_firmware_header *) - adev->gfx.me_fw->data; + adev->gfx.me_fw->data; break; case KGD_ENGINE_CE: hdr = (const union amdgpu_firmware_header *) - adev->gfx.ce_fw->data; + adev->gfx.ce_fw->data; break; case KGD_ENGINE_MEC1: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec_fw->data; + adev->gfx.mec_fw->data; break; case KGD_ENGINE_MEC2: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw->data; break; case KGD_ENGINE_RLC: hdr = (const union amdgpu_firmware_header *) - adev->gfx.rlc_fw->data; + adev->gfx.rlc_fw->data; break; case KGD_ENGINE_SDMA1: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[0].fw->data; + adev->sdma.instance[0].fw->data; break; case KGD_ENGINE_SDMA2: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[1].fw->data; + adev->sdma.instance[1].fw->data; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index 133d06671e46..c678c69936a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -39,6 +39,12 @@ #include "vi_structs.h" #include "vid.h" +enum hqd_dequeue_request_type { + NO_ACTION = 0, + DRAIN_PIPE, + RESET_WAVES +}; + struct cik_sdma_rlc_registers; /* @@ -55,12 +61,15 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id); static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, @@ -85,6 +94,33 @@ static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, uint8_t vmid); static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid); + +/* Because of REG_GET_FIELD() being used, we put this function in the + * asic specific file. + */ +static int get_tile_config(struct kgd_dev *kgd, + struct tile_config *config) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + + config->gb_addr_config = adev->gfx.config.gb_addr_config; + config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFBANK); + config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFRANKS); + + config->tile_config_ptr = adev->gfx.config.tile_mode_array; + config->num_tile_configs = + ARRAY_SIZE(adev->gfx.config.tile_mode_array); + config->macro_tile_config_ptr = + adev->gfx.config.macrotile_mode_array; + config->num_macro_tile_configs = + ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); + + return 0; +} static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, @@ -92,6 +128,8 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_vmem_size = get_vmem_size, .get_gpu_clock_counter = get_gpu_clock_counter, .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, + .alloc_pasid = amdgpu_vm_alloc_pasid, + .free_pasid = amdgpu_vm_free_pasid, .program_sh_mem_settings = kgd_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, .init_pipeline = kgd_init_pipeline, @@ -111,7 +149,9 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, .write_vmid_invalidate_request = write_vmid_invalidate_request, - .get_fw_version = get_fw_version + .get_fw_version = get_fw_version, + .set_scratch_backing_va = set_scratch_backing_va, + .get_tile_config = get_tile_config, }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) @@ -147,7 +187,7 @@ static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, { struct amdgpu_device *adev = get_amdgpu_device(kgd); - uint32_t mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, queue_id, 0); @@ -216,7 +256,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t mec; uint32_t pipe; - mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, 0, 0); @@ -244,20 +284,67 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) } static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm) { - struct vi_mqd *m; - uint32_t shadow_wptr, valid_wptr; struct amdgpu_device *adev = get_amdgpu_device(kgd); + struct vi_mqd *m; + uint32_t *mqd_hqd; + uint32_t reg, wptr_val, data; m = get_mqd(mqd); - valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr)); - if (valid_wptr == 0) - m->cp_hqd_pq_wptr = shadow_wptr; - acquire_queue(kgd, pipe_id, queue_id); - gfx_v8_0_mqd_commit(adev, mqd); + + /* HIQ is set during driver init period with vmid set to 0*/ + if (m->cp_hqd_vmid == 0) { + uint32_t value, mec, pipe; + + mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); + + pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", + mec, pipe, queue_id); + value = RREG32(mmRLC_CP_SCHEDULERS); + value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, + ((mec << 5) | (pipe << 3) | queue_id | 0x80)); + WREG32(mmRLC_CP_SCHEDULERS, value); + } + + /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ + mqd_hqd = &m->cp_mqd_base_addr_lo; + + for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) + WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); + + /* Tonga errata: EOP RPTR/WPTR should be left unmodified. + * This is safe since EOP RPTR==WPTR for any inactive HQD + * on ASICs that do not support context-save. + * EOP writes/reads can start anywhere in the ring. + */ + if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) { + WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); + WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); + WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); + } + + for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++) + WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); + + /* Copy userspace write pointer value to register. + * Activate doorbell logic to monitor subsequent changes. + */ + data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, + CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); + + if (read_user_wptr(mm, wptr, wptr_val)) + WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); + + data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); + WREG32(mmCP_HQD_ACTIVE, data); + release_queue(kgd); return 0; @@ -308,29 +395,102 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) return false; } -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id) { struct amdgpu_device *adev = get_amdgpu_device(kgd); uint32_t temp; - int timeout = utimeout; + enum hqd_dequeue_request_type type; + unsigned long flags, end_jiffies; + int retry; + struct vi_mqd *m = get_mqd(mqd); acquire_queue(kgd, pipe_id, queue_id); - WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type); + if (m->cp_hqd_vmid == 0) + WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); + switch (reset_type) { + case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: + type = DRAIN_PIPE; + break; + case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: + type = RESET_WAVES; + break; + default: + type = DRAIN_PIPE; + break; + } + + /* Workaround: If IQ timer is active and the wait time is close to or + * equal to 0, dequeueing is not safe. Wait until either the wait time + * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is + * cleared before continuing. Also, ensure wait times are set to at + * least 0x3. + */ + local_irq_save(flags); + preempt_disable(); + retry = 5000; /* wait for 500 usecs at maximum */ + while (true) { + temp = RREG32(mmCP_HQD_IQ_TIMER); + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { + pr_debug("HW is processing IQ\n"); + goto loop; + } + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) + == 3) /* SEM-rearm is safe */ + break; + /* Wait time 3 is safe for CP, but our MMIO read/write + * time is close to 1 microsecond, so check for 10 to + * leave more buffer room + */ + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) + >= 10) + break; + pr_debug("IQ timer is active\n"); + } else + break; +loop: + if (!retry) { + pr_err("CP HQD IQ timer status time out\n"); + break; + } + ndelay(100); + --retry; + } + retry = 1000; + while (true) { + temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); + if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) + break; + pr_debug("Dequeue request is pending\n"); + + if (!retry) { + pr_err("CP HQD dequeue request time out\n"); + break; + } + ndelay(100); + --retry; + } + local_irq_restore(flags); + preempt_enable(); + + WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); + + end_jiffies = (utimeout * HZ / 1000) + jiffies; while (true) { temp = RREG32(mmCP_HQD_ACTIVE); - if (temp & CP_HQD_ACTIVE__ACTIVE_MASK) + if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) break; - if (timeout <= 0) { - pr_err("kfd: cp queue preemption time out.\n"); + if (time_after(jiffies, end_jiffies)) { + pr_err("cp queue preemption time out.\n"); release_queue(kgd); return -ETIME; } - msleep(20); - timeout -= 20; + usleep_range(500, 1000); } release_queue(kgd); @@ -444,6 +604,16 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, return 0; } +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid) +{ + struct amdgpu_device *adev = (struct amdgpu_device *) kgd; + + lock_srbm(kgd, 0, 0, 0, vmid); + WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); + unlock_srbm(kgd); +} + static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) { struct amdgpu_device *adev = (struct amdgpu_device *) kgd; @@ -454,42 +624,42 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) switch (type) { case KGD_ENGINE_PFP: hdr = (const union amdgpu_firmware_header *) - adev->gfx.pfp_fw->data; + adev->gfx.pfp_fw->data; break; case KGD_ENGINE_ME: hdr = (const union amdgpu_firmware_header *) - adev->gfx.me_fw->data; + adev->gfx.me_fw->data; break; case KGD_ENGINE_CE: hdr = (const union amdgpu_firmware_header *) - adev->gfx.ce_fw->data; + adev->gfx.ce_fw->data; break; case KGD_ENGINE_MEC1: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec_fw->data; + adev->gfx.mec_fw->data; break; case KGD_ENGINE_MEC2: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw->data; break; case KGD_ENGINE_RLC: hdr = (const union amdgpu_firmware_header *) - adev->gfx.rlc_fw->data; + adev->gfx.rlc_fw->data; break; case KGD_ENGINE_SDMA1: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[0].fw->data; + adev->sdma.instance[0].fw->data; break; case KGD_ENGINE_SDMA2: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[1].fw->data; + adev->sdma.instance[1].fw->data; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index fd435a96481c..383204e911a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -45,7 +45,6 @@ struct amdgpu_cgs_device { static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, uint64_t size, uint64_t align, - uint64_t min_offset, uint64_t max_offset, cgs_handle_t *handle) { CGS_FUNC_ADEV; @@ -53,13 +52,6 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, int ret = 0; uint32_t domain = 0; struct amdgpu_bo *obj; - struct ttm_placement placement; - struct ttm_place place; - - if (min_offset > max_offset) { - BUG_ON(1); - return -EINVAL; - } /* fail if the alignment is not a power of 2 */ if (((align != 1) && (align & (align - 1))) @@ -73,41 +65,19 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; domain = AMDGPU_GEM_DOMAIN_VRAM; - if (max_offset > adev->mc.real_vram_size) - return -EINVAL; - place.fpfn = min_offset >> PAGE_SHIFT; - place.lpfn = max_offset >> PAGE_SHIFT; - place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | - TTM_PL_FLAG_VRAM; break; case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB: case CGS_GPU_MEM_TYPE__INVISIBLE_FB: flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; domain = AMDGPU_GEM_DOMAIN_VRAM; - if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { - place.fpfn = - max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT; - place.lpfn = - min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT; - place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | - TTM_PL_FLAG_VRAM; - } - break; case CGS_GPU_MEM_TYPE__GART_CACHEABLE: domain = AMDGPU_GEM_DOMAIN_GTT; - place.fpfn = min_offset >> PAGE_SHIFT; - place.lpfn = max_offset >> PAGE_SHIFT; - place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; break; case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE: flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; domain = AMDGPU_GEM_DOMAIN_GTT; - place.fpfn = min_offset >> PAGE_SHIFT; - place.lpfn = max_offset >> PAGE_SHIFT; - place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | - TTM_PL_FLAG_UNCACHED; break; default: return -EINVAL; @@ -116,15 +86,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, *handle = 0; - placement.placement = &place; - placement.num_placement = 1; - placement.busy_placement = &place; - placement.num_busy_placement = 1; - - ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE, - true, domain, flags, - NULL, &placement, NULL, - 0, &obj); + ret = amdgpu_bo_create(adev, size, align, true, domain, flags, + NULL, NULL, 0, &obj); if (ret) { DRM_ERROR("(%d) bo create failed\n", ret); return ret; @@ -155,19 +118,14 @@ static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t h uint64_t *mcaddr) { int r; - u64 min_offset, max_offset; struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; WARN_ON_ONCE(obj->placement.num_placement > 1); - min_offset = obj->placements[0].fpfn << PAGE_SHIFT; - max_offset = obj->placements[0].lpfn << PAGE_SHIFT; - r = amdgpu_bo_reserve(obj, true); if (unlikely(r != 0)) return r; - r = amdgpu_bo_pin_restricted(obj, obj->preferred_domains, - min_offset, max_offset, mcaddr); + r = amdgpu_bo_pin(obj, obj->preferred_domains, mcaddr); amdgpu_bo_unreserve(obj); return r; } @@ -675,6 +633,85 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, if (!adev->pm.fw) { switch (adev->asic_type) { + case CHIP_TAHITI: + strcpy(fw_name, "radeon/tahiti_smc.bin"); + break; + case CHIP_PITCAIRN: + if ((adev->pdev->revision == 0x81) && + ((adev->pdev->device == 0x6810) || + (adev->pdev->device == 0x6811))) { + info->is_kicker = true; + strcpy(fw_name, "radeon/pitcairn_k_smc.bin"); + } else { + strcpy(fw_name, "radeon/pitcairn_smc.bin"); + } + break; + case CHIP_VERDE: + if (((adev->pdev->device == 0x6820) && + ((adev->pdev->revision == 0x81) || + (adev->pdev->revision == 0x83))) || + ((adev->pdev->device == 0x6821) && + ((adev->pdev->revision == 0x83) || + (adev->pdev->revision == 0x87))) || + ((adev->pdev->revision == 0x87) && + ((adev->pdev->device == 0x6823) || + (adev->pdev->device == 0x682b)))) { + info->is_kicker = true; + strcpy(fw_name, "radeon/verde_k_smc.bin"); + } else { + strcpy(fw_name, "radeon/verde_smc.bin"); + } + break; + case CHIP_OLAND: + if (((adev->pdev->revision == 0x81) && + ((adev->pdev->device == 0x6600) || + (adev->pdev->device == 0x6604) || + (adev->pdev->device == 0x6605) || + (adev->pdev->device == 0x6610))) || + ((adev->pdev->revision == 0x83) && + (adev->pdev->device == 0x6610))) { + info->is_kicker = true; + strcpy(fw_name, "radeon/oland_k_smc.bin"); + } else { + strcpy(fw_name, "radeon/oland_smc.bin"); + } + break; + case CHIP_HAINAN: + if (((adev->pdev->revision == 0x81) && + (adev->pdev->device == 0x6660)) || + ((adev->pdev->revision == 0x83) && + ((adev->pdev->device == 0x6660) || + (adev->pdev->device == 0x6663) || + (adev->pdev->device == 0x6665) || + (adev->pdev->device == 0x6667)))) { + info->is_kicker = true; + strcpy(fw_name, "radeon/hainan_k_smc.bin"); + } else if ((adev->pdev->revision == 0xc3) && + (adev->pdev->device == 0x6665)) { + info->is_kicker = true; + strcpy(fw_name, "radeon/banks_k_2_smc.bin"); + } else { + strcpy(fw_name, "radeon/hainan_smc.bin"); + } + break; + case CHIP_BONAIRE: + if ((adev->pdev->revision == 0x80) || + (adev->pdev->revision == 0x81) || + (adev->pdev->device == 0x665f)) { + info->is_kicker = true; + strcpy(fw_name, "radeon/bonaire_k_smc.bin"); + } else { + strcpy(fw_name, "radeon/bonaire_smc.bin"); + } + break; + case CHIP_HAWAII: + if (adev->pdev->revision == 0x80) { + info->is_kicker = true; + strcpy(fw_name, "radeon/hawaii_k_smc.bin"); + } else { + strcpy(fw_name, "radeon/hawaii_smc.bin"); + } + break; case CHIP_TOPAZ: if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || @@ -838,6 +875,9 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID: sys_info->value = adev->pdev->subsystem_vendor; break; + case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN: + sys_info->value = adev->pdev->devfn; + break; default: return -ENODEV; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 8d1cf2d3e663..f51b41f094ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -346,10 +346,8 @@ static void amdgpu_connector_free_edid(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - if (amdgpu_connector->edid) { - kfree(amdgpu_connector->edid); - amdgpu_connector->edid = NULL; - } + kfree(amdgpu_connector->edid); + amdgpu_connector->edid = NULL; } static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index c05479ec825a..c6a214f1e991 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -246,7 +246,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, } total_vram = adev->mc.real_vram_size - adev->vram_pin_size; - used_vram = atomic64_read(&adev->vram_usage); + used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; spin_lock(&adev->mm_stats.lock); @@ -292,7 +292,8 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, /* Do the same for visible VRAM if half of it is free */ if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { u64 total_vis_vram = adev->mc.visible_vram_size; - u64 used_vis_vram = atomic64_read(&adev->vram_vis_usage); + u64 used_vis_vram = + amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); if (used_vis_vram < total_vis_vram) { u64 free_vis_vram = total_vis_vram - used_vis_vram; @@ -472,11 +473,16 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, return -EPERM; /* Check if we have user pages and nobody bound the BO already */ - if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) { - size_t size = sizeof(struct page *); - - size *= bo->tbo.ttm->num_pages; - memcpy(bo->tbo.ttm->pages, lobj->user_pages, size); + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + lobj->user_pages) { + amdgpu_ttm_placement_from_domain(bo, + AMDGPU_GEM_DOMAIN_CPU); + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, + false); + if (r) + return r; + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, + lobj->user_pages); binding_userptr = true; } @@ -501,7 +507,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_fpriv *fpriv = p->filp->driver_priv; struct amdgpu_bo_list_entry *e; struct list_head duplicates; - bool need_mmap_lock = false; unsigned i, tries = 10; int r; @@ -509,9 +514,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); if (p->bo_list) { - need_mmap_lock = p->bo_list->first_userptr != - p->bo_list->num_entries; amdgpu_bo_list_get_list(p->bo_list, &p->validated); + if (p->bo_list->first_userptr != p->bo_list->num_entries) + p->mn = amdgpu_mn_get(p->adev); } INIT_LIST_HEAD(&duplicates); @@ -520,9 +525,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, if (p->uf_entry.robj) list_add(&p->uf_entry.tv.head, &p->validated); - if (need_mmap_lock) - down_read(¤t->mm->mmap_sem); - while (1) { struct list_head need_pages; unsigned i; @@ -542,23 +544,25 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, INIT_LIST_HEAD(&need_pages); for (i = p->bo_list->first_userptr; i < p->bo_list->num_entries; ++i) { + struct amdgpu_bo *bo; e = &p->bo_list->array[i]; + bo = e->robj; - if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm, + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, &e->user_invalidated) && e->user_pages) { /* We acquired a page array, but somebody * invalidated it. Free it and try again */ release_pages(e->user_pages, - e->robj->tbo.ttm->num_pages, + bo->tbo.ttm->num_pages, false); kvfree(e->user_pages); e->user_pages = NULL; } - if (e->robj->tbo.ttm->state != tt_bound && + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && !e->user_pages) { list_del(&e->tv.head); list_add(&e->tv.head, &need_pages); @@ -635,9 +639,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved, p->bytes_moved_vis); - fpriv->vm.last_eviction_counter = - atomic64_read(&p->adev->num_evictions); - if (p->bo_list) { struct amdgpu_bo *gds = p->bo_list->gds_obj; struct amdgpu_bo *gws = p->bo_list->gws_obj; @@ -673,16 +674,11 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, } error_validate: - if (r) { - amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); + if (r) ttm_eu_backoff_reservation(&p->ticket, &p->validated); - } error_free_pages: - if (need_mmap_lock) - up_read(¤t->mm->mmap_sem); - if (p->bo_list) { for (i = p->bo_list->first_userptr; i < p->bo_list->num_entries; ++i) { @@ -724,21 +720,14 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) * If error is set than unvalidate buffer, otherwise just free memory * used by parsing context. **/ -static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) +static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, + bool backoff) { - struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; unsigned i; - if (!error) { - amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); - - ttm_eu_fence_buffer_objects(&parser->ticket, - &parser->validated, - parser->fence); - } else if (backoff) { + if (error && backoff) ttm_eu_backoff_reservation(&parser->ticket, &parser->validated); - } for (i = 0; i < parser->num_post_dep_syncobjs; i++) drm_syncobj_put(parser->post_dep_syncobjs[i]); @@ -772,10 +761,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) if (r) return r; - r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update); - if (r) - return r; - r = amdgpu_vm_clear_freed(adev, vm, NULL); if (r) return r; @@ -791,7 +776,8 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) if (amdgpu_sriov_vf(adev)) { struct dma_fence *f; - bo_va = vm->csa_bo_va; + + bo_va = fpriv->csa_va; BUG_ON(!bo_va); r = amdgpu_vm_bo_update(adev, bo_va, false); if (r) @@ -828,7 +814,13 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) } - r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync); + r = amdgpu_vm_handle_moved(adev, vm); + if (r) + return r; + + r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update); + if (r) + return r; if (amdgpu_vm_debug && p->bo_list) { /* Invalidate all BOs to test for userspace bugs */ @@ -838,7 +830,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) if (!bo) continue; - amdgpu_vm_bo_invalidate(adev, bo); + amdgpu_vm_bo_invalidate(adev, bo, false); } } @@ -863,7 +855,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, } if (p->job->vm) { - p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo); + p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo); r = amdgpu_bo_vm_update_pte(p); if (r) @@ -931,11 +923,11 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, uint64_t offset; uint8_t *kptr; - m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, - &aobj); - if (!aobj) { + r = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, + &aobj, &m); + if (r) { DRM_ERROR("IB va_start is invalid\n"); - return -EINVAL; + return r; } if ((chunk_ib->va_start + chunk_ib->ib_bytes) > @@ -1038,7 +1030,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, { int r; struct dma_fence *fence; - r = drm_syncobj_fence_get(p->filp, handle, &fence); + r = drm_syncobj_find_fence(p->filp, handle, &fence); if (r) return r; @@ -1082,6 +1074,9 @@ static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p, GFP_KERNEL); p->num_post_dep_syncobjs = 0; + if (!p->post_dep_syncobjs) + return -ENOMEM; + for (i = 0; i < num_deps; ++i) { p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle); if (!p->post_dep_syncobjs[i]) @@ -1133,14 +1128,31 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, struct amdgpu_ring *ring = p->job->ring; struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; struct amdgpu_job *job; + unsigned i; + uint64_t seq; + int r; + amdgpu_mn_lock(p->mn); + if (p->bo_list) { + for (i = p->bo_list->first_userptr; + i < p->bo_list->num_entries; ++i) { + struct amdgpu_bo *bo = p->bo_list->array[i].robj; + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { + amdgpu_mn_unlock(p->mn); + return -ERESTARTSYS; + } + } + } + job = p->job; p->job = NULL; r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp); if (r) { amdgpu_job_free(job); + amdgpu_mn_unlock(p->mn); return r; } @@ -1148,15 +1160,28 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, job->fence_ctx = entity->fence_context; p->fence = dma_fence_get(&job->base.s_fence->finished); + r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq); + if (r) { + dma_fence_put(p->fence); + dma_fence_put(&job->base.s_fence->finished); + amdgpu_job_free(job); + amdgpu_mn_unlock(p->mn); + return r; + } + amdgpu_cs_post_dependencies(p); - cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence); - job->uf_sequence = cs->out.handle; + cs->out.handle = seq; + job->uf_sequence = seq; + amdgpu_job_free_resources(job); - amdgpu_cs_parser_fini(p, 0, true); trace_amdgpu_cs_ioctl(job); amd_sched_entity_push_job(&job->base); + + ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence); + amdgpu_mn_unlock(p->mn); + return 0; } @@ -1211,10 +1236,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) goto out; r = amdgpu_cs_submit(&parser, cs); - if (r) - goto out; - return 0; out: amdgpu_cs_parser_fini(&parser, r, reserved_buffers); return r; @@ -1387,6 +1409,7 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, array[i] = fence; } else { /* NULL, the fence has been already signaled */ r = 1; + first = i; goto out; } } @@ -1466,78 +1489,36 @@ err_free_fences: * virtual memory address. Returns allocation structure when found, NULL * otherwise. */ -struct amdgpu_bo_va_mapping * -amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, - uint64_t addr, struct amdgpu_bo **bo) +int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, + uint64_t addr, struct amdgpu_bo **bo, + struct amdgpu_bo_va_mapping **map) { + struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va_mapping *mapping; - unsigned i; - - if (!parser->bo_list) - return NULL; + int r; addr /= AMDGPU_GPU_PAGE_SIZE; - for (i = 0; i < parser->bo_list->num_entries; i++) { - struct amdgpu_bo_list_entry *lobj; - - lobj = &parser->bo_list->array[i]; - if (!lobj->bo_va) - continue; - - list_for_each_entry(mapping, &lobj->bo_va->valids, list) { - if (mapping->start > addr || - addr > mapping->last) - continue; - - *bo = lobj->bo_va->bo; - return mapping; - } - - list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { - if (mapping->start > addr || - addr > mapping->last) - continue; + mapping = amdgpu_vm_bo_lookup_mapping(vm, addr); + if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo) + return -EINVAL; - *bo = lobj->bo_va->bo; - return mapping; - } - } + *bo = mapping->bo_va->base.bo; + *map = mapping; - return NULL; -} + /* Double check that the BO is reserved by this CS */ + if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket) + return -EINVAL; -/** - * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM - * - * @parser: command submission parser context - * - * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM. - */ -int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser) -{ - unsigned i; - int r; + r = amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem); + if (unlikely(r)) + return r; - if (!parser->bo_list) + if ((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) return 0; - for (i = 0; i < parser->bo_list->num_entries; i++) { - struct amdgpu_bo *bo = parser->bo_list->array[i].robj; - - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); - if (unlikely(r)) - return r; - - if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) - continue; - - bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); - if (unlikely(r)) - return r; - } - - return 0; + (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains); + return ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false, false); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index a11e44340b23..75c933b1a432 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -246,8 +246,8 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx) return 0; } -uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, - struct dma_fence *fence) +int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, + struct dma_fence *fence, uint64_t* handler) { struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; uint64_t seq = cring->sequence; @@ -258,9 +258,9 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, other = cring->fences[idx]; if (other) { signed long r; - r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); + r = dma_fence_wait_timeout(other, true, MAX_SCHEDULE_TIMEOUT); if (r < 0) - DRM_ERROR("Error (%ld) waiting for fence!\n", r); + return r; } dma_fence_get(fence); @@ -271,8 +271,10 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, spin_unlock(&ctx->ring_lock); dma_fence_put(other); + if (handler) + *handler = seq; - return seq; + return 0; } struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a6f6cb0f2e02..3e84ddf9e3b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -65,6 +65,7 @@ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); +static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev); static const char *amdgpu_asic_name[] = { "TAHITI", @@ -402,6 +403,15 @@ void amdgpu_pci_config_reset(struct amdgpu_device *adev) */ static int amdgpu_doorbell_init(struct amdgpu_device *adev) { + /* No doorbell on SI hardware generation */ + if (adev->asic_type < CHIP_BONAIRE) { + adev->doorbell.base = 0; + adev->doorbell.size = 0; + adev->doorbell.num_doorbells = 0; + adev->doorbell.ptr = NULL; + return 0; + } + /* doorbell bar mapping */ adev->doorbell.base = pci_resource_start(adev->pdev, 2); adev->doorbell.size = pci_resource_len(adev->pdev, 2); @@ -887,6 +897,20 @@ static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) return r; } +static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + struct atom_context *ctx = adev->mode_info.atom_context; + + return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version); +} + +static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, + NULL); + /** * amdgpu_atombios_fini - free the driver info and callbacks for atombios * @@ -906,6 +930,7 @@ static void amdgpu_atombios_fini(struct amdgpu_device *adev) adev->mode_info.atom_context = NULL; kfree(adev->mode_info.atom_card_info); adev->mode_info.atom_card_info = NULL; + device_remove_file(adev->dev, &dev_attr_vbios_version); } /** @@ -922,6 +947,7 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev) { struct card_info *atom_card_info = kzalloc(sizeof(struct card_info), GFP_KERNEL); + int ret; if (!atom_card_info) return -ENOMEM; @@ -958,6 +984,13 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev) amdgpu_atombios_scratch_regs_init(adev); amdgpu_atombios_allocate_fb_scratch(adev); } + + ret = device_create_file(adev->dev, &dev_attr_vbios_version); + if (ret) { + DRM_ERROR("Failed to create device file for VBIOS version\n"); + return ret; + } + return 0; } @@ -1062,11 +1095,11 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); } - if (amdgpu_gart_size < 32) { + if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { /* gart size must be greater or equal to 32M */ dev_warn(adev->dev, "gart size (%d) too small\n", amdgpu_gart_size); - amdgpu_gart_size = 32; + amdgpu_gart_size = -1; } if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { @@ -1076,6 +1109,13 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_gtt_size = -1; } + /* valid range is between 4 and 9 inclusive */ + if (amdgpu_vm_fragment_size != -1 && + (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { + dev_warn(adev->dev, "valid range is between 4 and 9\n"); + amdgpu_vm_fragment_size = -1; + } + amdgpu_check_vm_size(adev); amdgpu_check_block_size(adev); @@ -1750,10 +1790,8 @@ static int amdgpu_fini(struct amdgpu_device *adev) adev->ip_blocks[i].status.late_initialized = false; } - if (amdgpu_sriov_vf(adev)) { - amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); + if (amdgpu_sriov_vf(adev)) amdgpu_virt_release_full_gpu(adev, false); - } return 0; } @@ -2044,9 +2082,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); - if (adev->asic_type >= CHIP_BONAIRE) - /* doorbell bar mapping */ - amdgpu_doorbell_init(adev); + /* doorbell bar mapping */ + amdgpu_doorbell_init(adev); /* io port mapping */ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { @@ -2194,6 +2231,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (r) DRM_ERROR("registering firmware debugfs failed (%d).\n", r); + r = amdgpu_debugfs_vbios_dump_init(adev); + if (r) + DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r); + if ((amdgpu_testing & 1)) { if (adev->accel_working) amdgpu_test_moves(adev); @@ -2269,8 +2310,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev) adev->rio_mem = NULL; iounmap(adev->rmmio); adev->rmmio = NULL; - if (adev->asic_type >= CHIP_BONAIRE) - amdgpu_doorbell_fini(adev); + amdgpu_doorbell_fini(adev); amdgpu_debugfs_regs_cleanup(adev); } @@ -2539,7 +2579,8 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev) if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || - (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { + (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { if (adev->ip_blocks[i].status.hang) { DRM_INFO("Some block need full reset!\n"); return true; @@ -2615,12 +2656,6 @@ static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, goto err; } - r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem); - if (r) { - DRM_ERROR("%p bind failed\n", bo->shadow); - goto err; - } - r = amdgpu_bo_restore_from_shadow(adev, ring, bo, NULL, fence, true); if (r) { @@ -2653,7 +2688,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) mutex_lock(&adev->virt.lock_reset); atomic_inc(&adev->gpu_reset_counter); - adev->gfx.in_reset = true; + adev->in_sriov_reset = true; /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); @@ -2764,7 +2799,7 @@ give_up_reset: dev_info(adev->dev, "GPU reset successed!\n"); } - adev->gfx.in_reset = false; + adev->in_sriov_reset = false; mutex_unlock(&adev->virt.lock_reset); return r; } @@ -3462,10 +3497,7 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, valuesize = sizeof(values); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) - r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); - else if (adev->pm.funcs && adev->pm.funcs->read_sensor) - r = adev->pm.funcs->read_sensor(adev, idx, &values[0], - &valuesize); + r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); else return -EINVAL; @@ -3753,6 +3785,28 @@ int amdgpu_debugfs_init(struct drm_minor *minor) { return 0; } + +static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + + seq_write(m, adev->bios, adev->bios_size); + return 0; +} + +static const struct drm_info_list amdgpu_vbios_dump_list[] = { + {"amdgpu_vbios", + amdgpu_debugfs_get_vbios_dump, + 0, NULL}, +}; + +static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) +{ + return amdgpu_debugfs_add_files(adev, + amdgpu_vbios_dump_list, 1); +} #else static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) { @@ -3762,5 +3816,9 @@ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) { return 0; } +static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) +{ + return 0; +} static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 1cb52fd19060..e997ebbe43ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -960,8 +960,10 @@ u8 amdgpu_encode_pci_lane_width(u32 lanes) } struct amd_vce_state* -amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx) +amdgpu_get_vce_clock_state(void *handle, u32 idx) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (idx < adev->pm.dpm.num_of_vce_states) return &adev->pm.dpm.vce_states[idx]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index 8c96a4caa715..f79f9ea58b17 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -241,177 +241,119 @@ enum amdgpu_pcie_gen { AMDGPU_PCIE_GEN_INVALID = 0xffff }; -struct amdgpu_dpm_funcs { - int (*get_temperature)(struct amdgpu_device *adev); - int (*pre_set_power_state)(struct amdgpu_device *adev); - int (*set_power_state)(struct amdgpu_device *adev); - void (*post_set_power_state)(struct amdgpu_device *adev); - void (*display_configuration_changed)(struct amdgpu_device *adev); - u32 (*get_sclk)(struct amdgpu_device *adev, bool low); - u32 (*get_mclk)(struct amdgpu_device *adev, bool low); - void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); - void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); - int (*force_performance_level)(struct amdgpu_device *adev, enum amd_dpm_forced_level level); - bool (*vblank_too_short)(struct amdgpu_device *adev); - void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); - void (*powergate_vce)(struct amdgpu_device *adev, bool gate); - void (*enable_bapm)(struct amdgpu_device *adev, bool enable); - void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); - u32 (*get_fan_control_mode)(struct amdgpu_device *adev); - int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); - int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); - int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask); - int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); - int (*get_sclk_od)(struct amdgpu_device *adev); - int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); - int (*get_mclk_od)(struct amdgpu_device *adev); - int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); - int (*check_state_equal)(struct amdgpu_device *adev, - struct amdgpu_ps *cps, - struct amdgpu_ps *rps, - bool *equal); - int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value, - int *size); - - struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx); - int (*reset_power_profile_state)(struct amdgpu_device *adev, - struct amd_pp_profile *request); - int (*get_power_profile_state)(struct amdgpu_device *adev, - struct amd_pp_profile *query); - int (*set_power_profile_state)(struct amdgpu_device *adev, - struct amd_pp_profile *request); - int (*switch_power_profile)(struct amdgpu_device *adev, - enum amd_pp_profile_type type); -}; +#define amdgpu_dpm_pre_set_power_state(adev) \ + ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle)) + +#define amdgpu_dpm_set_power_state(adev) \ + ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle)) + +#define amdgpu_dpm_post_set_power_state(adev) \ + ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle)) + +#define amdgpu_dpm_display_configuration_changed(adev) \ + ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle)) -#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) -#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) -#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) -#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) -#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) -#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) -#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) +#define amdgpu_dpm_print_power_state(adev, ps) \ + ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps))) + +#define amdgpu_dpm_vblank_too_short(adev) \ + ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle)) + +#define amdgpu_dpm_enable_bapm(adev, e) \ + ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) #define amdgpu_dpm_read_sensor(adev, idx, value, size) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value), (size)) : \ - (adev)->pm.funcs->read_sensor((adev), (idx), (value), (size))) + ((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size))) #define amdgpu_dpm_get_temperature(adev) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ - (adev)->pm.funcs->get_temperature((adev))) + ((adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle)) #define amdgpu_dpm_set_fan_control_mode(adev, m) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ - (adev)->pm.funcs->set_fan_control_mode((adev), (m))) + ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m))) #define amdgpu_dpm_get_fan_control_mode(adev) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ - (adev)->pm.funcs->get_fan_control_mode((adev))) + ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle)) #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ - (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) + ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s))) #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ - (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) + ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s))) #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \ - -EINVAL) + ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s)) #define amdgpu_dpm_get_sclk(adev, l) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ - (adev)->pm.funcs->get_sclk((adev), (l))) + ((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l))) #define amdgpu_dpm_get_mclk(adev, l) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ - (adev)->pm.funcs->get_mclk((adev), (l))) - + ((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l))) #define amdgpu_dpm_force_performance_level(adev, l) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ - (adev)->pm.funcs->force_performance_level((adev), (l))) + ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l))) #define amdgpu_dpm_powergate_uvd(adev, g) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ - (adev)->pm.funcs->powergate_uvd((adev), (g))) + ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g))) #define amdgpu_dpm_powergate_vce(adev, g) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ - (adev)->pm.funcs->powergate_vce((adev), (g))) + ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g))) #define amdgpu_dpm_get_current_power_state(adev) \ - (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) + ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)) #define amdgpu_dpm_get_pp_num_states(adev, data) \ - (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) + ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)) #define amdgpu_dpm_get_pp_table(adev, table) \ - (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) + ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)) #define amdgpu_dpm_set_pp_table(adev, buf, size) \ - (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) + ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)) #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ - (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) + ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)) #define amdgpu_dpm_force_clock_level(adev, type, level) \ - (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) + ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)) #define amdgpu_dpm_get_sclk_od(adev) \ - (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle) + ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)) #define amdgpu_dpm_set_sclk_od(adev, value) \ - (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value) + ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)) #define amdgpu_dpm_get_mclk_od(adev) \ - ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) + ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) #define amdgpu_dpm_set_mclk_od(adev, value) \ - ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) + ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) -#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ - (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) +#define amdgpu_dpm_dispatch_task(adev, task_id, input, output) \ + ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output)) -#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal)) +#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ + ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal))) #define amdgpu_dpm_get_vce_clock_state(adev, i) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \ - (adev)->pm.funcs->get_vce_clock_state((adev), (i))) + ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i))) -#define amdgpu_dpm_get_performance_level(adev) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) : \ - (adev)->pm.dpm.forced_level) +#define amdgpu_dpm_get_performance_level(adev) \ + ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)) #define amdgpu_dpm_reset_power_profile_state(adev, request) \ - ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ + ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ (adev)->powerplay.pp_handle, request)) #define amdgpu_dpm_get_power_profile_state(adev, query) \ - ((adev)->powerplay.pp_funcs->get_power_profile_state(\ + ((adev)->powerplay.pp_funcs->get_power_profile_state(\ (adev)->powerplay.pp_handle, query)) #define amdgpu_dpm_set_power_profile_state(adev, request) \ - ((adev)->powerplay.pp_funcs->set_power_profile_state(\ + ((adev)->powerplay.pp_funcs->set_power_profile_state(\ (adev)->powerplay.pp_handle, request)) #define amdgpu_dpm_switch_power_profile(adev, type) \ - ((adev)->powerplay.pp_funcs->switch_power_profile(\ + ((adev)->powerplay.pp_funcs->switch_power_profile(\ (adev)->powerplay.pp_handle, type)) struct amdgpu_dpm { @@ -485,7 +427,6 @@ struct amdgpu_pm { struct amdgpu_dpm dpm; const struct firmware *fw; /* SMC firmware */ uint32_t fw_version; - const struct amdgpu_dpm_funcs *funcs; uint32_t pcie_gen_mask; uint32_t pcie_mlw_mask; struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ @@ -551,6 +492,6 @@ u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev, u8 amdgpu_encode_pci_lane_width(u32 lanes); struct amd_vce_state* -amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx); +amdgpu_get_vce_clock_state(void *handle, u32 idx); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 5e9ce8a29669..4f98960e47f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -68,14 +68,16 @@ * - 3.16.0 - Add reserved vmid support * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. * - 3.18.0 - Export gpu always on cu bitmap + * - 3.19.0 - Add support for UVD MJPEG decode + * - 3.20.0 - Add support for local BOs */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 18 +#define KMS_DRIVER_MINOR 20 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; int amdgpu_vis_vram_limit = 0; -unsigned amdgpu_gart_size = 256; +int amdgpu_gart_size = -1; /* auto */ int amdgpu_gtt_size = -1; /* auto */ int amdgpu_moverate = -1; /* auto */ int amdgpu_benchmarking = 0; @@ -90,10 +92,11 @@ int amdgpu_dpm = -1; int amdgpu_fw_load_type = -1; int amdgpu_aspm = -1; int amdgpu_runtime_pm = -1; -unsigned amdgpu_ip_block_mask = 0xffffffff; +uint amdgpu_ip_block_mask = 0xffffffff; int amdgpu_bapm = -1; int amdgpu_deep_color = 0; int amdgpu_vm_size = -1; +int amdgpu_vm_fragment_size = -1; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; @@ -104,14 +107,14 @@ int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; int amdgpu_no_evict = 0; int amdgpu_direct_gma_size = 0; -unsigned amdgpu_pcie_gen_cap = 0; -unsigned amdgpu_pcie_lane_cap = 0; -unsigned amdgpu_cg_mask = 0xffffffff; -unsigned amdgpu_pg_mask = 0xffffffff; -unsigned amdgpu_sdma_phase_quantum = 32; +uint amdgpu_pcie_gen_cap = 0; +uint amdgpu_pcie_lane_cap = 0; +uint amdgpu_cg_mask = 0xffffffff; +uint amdgpu_pg_mask = 0xffffffff; +uint amdgpu_sdma_phase_quantum = 32; char *amdgpu_disable_cu = NULL; char *amdgpu_virtual_display = NULL; -unsigned amdgpu_pp_feature_mask = 0xffffffff; +uint amdgpu_pp_feature_mask = 0xffffffff; int amdgpu_ngg = 0; int amdgpu_prim_buf_per_se = 0; int amdgpu_pos_buf_per_se = 0; @@ -126,7 +129,7 @@ module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); -MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc.)"); +MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); module_param_named(gartsize, amdgpu_gart_size, uint, 0600); MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); @@ -183,6 +186,9 @@ module_param_named(deep_color, amdgpu_deep_color, int, 0444); MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); module_param_named(vm_size, amdgpu_vm_size, int, 0444); +MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); +module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); + MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); @@ -603,6 +609,8 @@ amdgpu_pci_remove(struct pci_dev *pdev) drm_dev_unregister(dev); drm_dev_unref(dev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); } static void @@ -847,6 +855,7 @@ static struct drm_driver kms_driver = { .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, .gem_prime_vmap = amdgpu_gem_prime_vmap, .gem_prime_vunmap = amdgpu_gem_prime_vunmap, + .gem_prime_mmap = amdgpu_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 9afa9c097e1f..562930b17a6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -149,7 +149,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED, - true, &gobj); + true, NULL, &gobj); if (ret) { pr_err("failed to allocate framebuffer (%d)\n", aligned_size); return -ENOMEM; @@ -303,10 +303,10 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb if (rfb->obj) { amdgpufb_destroy_pinned_object(rfb->obj); rfb->obj = NULL; + drm_framebuffer_unregister_private(&rfb->base); + drm_framebuffer_cleanup(&rfb->base); } drm_fb_helper_fini(&rfbdev->helper); - drm_framebuffer_unregister_private(&rfb->base); - drm_framebuffer_cleanup(&rfb->base); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 94c1e2e8e34c..f4370081f6e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -57,18 +57,6 @@ */ /** - * amdgpu_gart_set_defaults - set the default gart_size - * - * @adev: amdgpu_device pointer - * - * Set the default gart_size based on parameters and available VRAM. - */ -void amdgpu_gart_set_defaults(struct amdgpu_device *adev) -{ - adev->mc.gart_size = (uint64_t)amdgpu_gart_size << 20; -} - -/** * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table * * @adev: amdgpu_device pointer diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index d4cce6936200..afbe803b1a13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -56,7 +56,6 @@ struct amdgpu_gart { const struct amdgpu_gart_funcs *gart_funcs; }; -void amdgpu_gart_set_defaults(struct amdgpu_device *adev); int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 81127ffcefb2..b0d45c8e6bb3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -44,11 +44,12 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj) } int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, - int alignment, u32 initial_domain, - u64 flags, bool kernel, - struct drm_gem_object **obj) + int alignment, u32 initial_domain, + u64 flags, bool kernel, + struct reservation_object *resv, + struct drm_gem_object **obj) { - struct amdgpu_bo *robj; + struct amdgpu_bo *bo; int r; *obj = NULL; @@ -59,7 +60,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, retry: r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, - flags, NULL, NULL, 0, &robj); + flags, NULL, resv, 0, &bo); if (r) { if (r != -ERESTARTSYS) { if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { @@ -71,7 +72,7 @@ retry: } return r; } - *obj = &robj->gem_base; + *obj = &bo->gem_base; return 0; } @@ -112,7 +113,17 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; + struct mm_struct *mm; int r; + + mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); + if (mm && mm != current->mm) + return -EPERM; + + if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && + abo->tbo.resv != vm->root.base.bo->tbo.resv) + return -EPERM; + r = amdgpu_bo_reserve(abo, false); if (r) return r; @@ -127,35 +138,6 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, return 0; } -static int amdgpu_gem_vm_check(void *param, struct amdgpu_bo *bo) -{ - /* if anything is swapped out don't swap it in here, - just abort and wait for the next CS */ - if (!amdgpu_bo_gpu_accessible(bo)) - return -ERESTARTSYS; - - if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow)) - return -ERESTARTSYS; - - return 0; -} - -static bool amdgpu_gem_vm_ready(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - struct list_head *list) -{ - struct ttm_validate_buffer *entry; - - list_for_each_entry(entry, list, head) { - struct amdgpu_bo *bo = - container_of(entry->bo, struct amdgpu_bo, tbo); - if (amdgpu_gem_vm_check(NULL, bo)) - return false; - } - - return !amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_vm_check, NULL); -} - void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv) { @@ -165,13 +147,14 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_list_entry vm_pd; - struct list_head list; + struct list_head list, duplicates; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct amdgpu_bo_va *bo_va; int r; INIT_LIST_HEAD(&list); + INIT_LIST_HEAD(&duplicates); tv.bo = &bo->tbo; tv.shared = true; @@ -179,7 +162,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); - r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL); + r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); if (r) { dev_err(adev->dev, "leaking bo va because " "we fail to reserve bo (%d)\n", r); @@ -189,7 +172,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, if (bo_va && --bo_va->ref_count == 0) { amdgpu_vm_bo_rmv(adev, bo_va); - if (amdgpu_gem_vm_ready(adev, vm, &list)) { + if (amdgpu_vm_ready(vm)) { struct dma_fence *fence = NULL; r = amdgpu_vm_clear_freed(adev, vm, &fence); @@ -214,20 +197,22 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; union drm_amdgpu_gem_create *args = data; + uint64_t flags = args->in.domain_flags; uint64_t size = args->in.bo_size; + struct reservation_object *resv = NULL; struct drm_gem_object *gobj; uint32_t handle; - bool kernel = false; int r; /* reject invalid gem flags */ - if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_NO_CPU_ACCESS | - AMDGPU_GEM_CREATE_CPU_GTT_USWC | - AMDGPU_GEM_CREATE_VRAM_CLEARED| - AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) + if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_NO_CPU_ACCESS | + AMDGPU_GEM_CREATE_CPU_GTT_USWC | + AMDGPU_GEM_CREATE_VRAM_CLEARED | + AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)) return -EINVAL; /* reject invalid gem domains */ @@ -242,7 +227,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { - kernel = true; + flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) size = size << AMDGPU_GDS_SHIFT; else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) @@ -254,10 +239,25 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, } size = roundup(size, PAGE_SIZE); + if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { + r = amdgpu_bo_reserve(vm->root.base.bo, false); + if (r) + return r; + + resv = vm->root.base.bo->tbo.resv; + } + r = amdgpu_gem_object_create(adev, size, args->in.alignment, (u32)(0xffffffff & args->in.domains), - args->in.domain_flags, - kernel, &gobj); + flags, false, resv, &gobj); + if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { + if (!r) { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); + + abo->parent = amdgpu_bo_ref(vm->root.base.bo); + } + amdgpu_bo_unreserve(vm->root.base.bo); + } if (r) return r; @@ -299,9 +299,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, } /* create a gem object to contain this object in */ - r = amdgpu_gem_object_create(adev, args->size, 0, - AMDGPU_GEM_DOMAIN_CPU, 0, - 0, &gobj); + r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, + 0, 0, NULL, &gobj); if (r) return r; @@ -319,8 +318,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, } if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { - down_read(¤t->mm->mmap_sem); - r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, bo->tbo.ttm->pages); if (r) @@ -335,8 +332,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, amdgpu_bo_unreserve(bo); if (r) goto free_pages; - - up_read(¤t->mm->mmap_sem); } r = drm_gem_handle_create(filp, gobj, &handle); @@ -513,10 +508,10 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, struct list_head *list, uint32_t operation) { - int r = -ERESTARTSYS; + int r; - if (!amdgpu_gem_vm_ready(adev, vm, list)) - goto error; + if (!amdgpu_vm_ready(vm)) + return; r = amdgpu_vm_update_directories(adev, vm); if (r) @@ -553,7 +548,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct amdgpu_bo_list_entry vm_pd; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; - struct list_head list; + struct list_head list, duplicates; uint64_t va_flags; int r = 0; @@ -589,6 +584,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, } INIT_LIST_HEAD(&list); + INIT_LIST_HEAD(&duplicates); if ((args->operation != AMDGPU_VA_OP_CLEAR) && !(args->flags & AMDGPU_VM_PAGE_PRT)) { gobj = drm_gem_object_lookup(filp, args->handle); @@ -605,7 +601,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); - r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); + r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); if (r) goto error_unref; @@ -623,7 +619,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, switch (args->operation) { case AMDGPU_VA_OP_MAP: - r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, + r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, args->map_size); if (r) goto error_backoff; @@ -643,7 +639,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, args->map_size); break; case AMDGPU_VA_OP_REPLACE: - r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, + r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, args->map_size); if (r) goto error_backoff; @@ -671,6 +667,7 @@ error_unref: int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct amdgpu_device *adev = dev->dev_private; struct drm_amdgpu_gem_op *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *robj; @@ -718,6 +715,9 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; + if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) + amdgpu_vm_bo_invalidate(adev, robj, true); + amdgpu_bo_unreserve(robj); break; default: @@ -747,8 +747,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, - ttm_bo_type_device, - &gobj); + false, NULL, &gobj); if (r) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 4f6c68fc1dd9..4fcd98e65998 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -260,8 +260,13 @@ int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev, /* create MQD for KIQ */ ring = &adev->gfx.kiq.ring; if (!ring->mqd_obj) { + /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must + * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD + * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for + * KIQ MQD no matter SRIOV or Bare-metal + */ r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj, &ring->mqd_gpu_addr, &ring->mqd_ptr); if (r) { dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 5e6b90c6794f..0d15eb7d31d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -28,7 +28,7 @@ struct amdgpu_gtt_mgr { struct drm_mm mm; spinlock_t lock; - uint64_t available; + atomic64_t available; }; /** @@ -54,7 +54,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man, size = (adev->mc.gart_size >> PAGE_SHIFT) - start; drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); - mgr->available = p_size; + atomic64_set(&mgr->available, p_size); man->priv = mgr; return 0; } @@ -108,10 +108,10 @@ bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem) * * Allocate the address space for a node. */ -int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, - struct ttm_buffer_object *tbo, - const struct ttm_place *place, - struct ttm_mem_reg *mem) +static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, + struct ttm_buffer_object *tbo, + const struct ttm_place *place, + struct ttm_mem_reg *mem) { struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); struct amdgpu_gtt_mgr *mgr = man->priv; @@ -143,25 +143,12 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, fpfn, lpfn, mode); spin_unlock(&mgr->lock); - if (!r) { + if (!r) mem->start = node->start; - if (&tbo->mem == mem) - tbo->offset = (tbo->mem.start << PAGE_SHIFT) + - tbo->bdev->man[tbo->mem.mem_type].gpu_offset; - } return r; } -void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager *man) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); - struct amdgpu_gtt_mgr *mgr = man->priv; - - seq_printf(m, "man size:%llu pages, gtt available:%llu pages, usage:%lluMB\n", - man->size, mgr->available, (u64)atomic64_read(&adev->gtt_usage) >> 20); - -} /** * amdgpu_gtt_mgr_new - allocate a new node * @@ -182,11 +169,11 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, int r; spin_lock(&mgr->lock); - if (mgr->available < mem->num_pages) { + if (atomic64_read(&mgr->available) < mem->num_pages) { spin_unlock(&mgr->lock); return 0; } - mgr->available -= mem->num_pages; + atomic64_sub(mem->num_pages, &mgr->available); spin_unlock(&mgr->lock); node = kzalloc(sizeof(*node), GFP_KERNEL); @@ -213,9 +200,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, return 0; err_out: - spin_lock(&mgr->lock); - mgr->available += mem->num_pages; - spin_unlock(&mgr->lock); + atomic64_add(mem->num_pages, &mgr->available); return r; } @@ -242,30 +227,47 @@ static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man, spin_lock(&mgr->lock); if (node->start != AMDGPU_BO_INVALID_OFFSET) drm_mm_remove_node(node); - mgr->available += mem->num_pages; spin_unlock(&mgr->lock); + atomic64_add(mem->num_pages, &mgr->available); kfree(node); mem->mm_node = NULL; } /** + * amdgpu_gtt_mgr_usage - return usage of GTT domain + * + * @man: TTM memory type manager + * + * Return how many bytes are used in the GTT domain + */ +uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man) +{ + struct amdgpu_gtt_mgr *mgr = man->priv; + + return (u64)(man->size - atomic64_read(&mgr->available)) * PAGE_SIZE; +} + +/** * amdgpu_gtt_mgr_debug - dump VRAM table * * @man: TTM memory type manager - * @prefix: text prefix + * @printer: DRM printer to use * * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_printer p = drm_debug_printer(prefix); spin_lock(&mgr->lock); - drm_mm_print(&mgr->mm, &p); + drm_mm_print(&mgr->mm, printer); spin_unlock(&mgr->lock); + + drm_printf(printer, "man size:%llu pages, gtt available:%llu pages, usage:%lluMB\n", + man->size, (u64)atomic64_read(&mgr->available), + amdgpu_gtt_mgr_usage(man) >> 20); } const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index 3ab4c65ecc8b..f5f27e4f0f7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -169,6 +169,12 @@ restart_ih: while (adev->irq.ih.rptr != wptr) { u32 ring_index = adev->irq.ih.rptr >> 2; + /* Prescreening of high-frequency interrupts */ + if (!amdgpu_ih_prescreen_iv(adev)) { + adev->irq.ih.rptr &= adev->irq.ih.ptr_mask; + continue; + } + /* Before dispatching irq to IP blocks, send it to amdkfd */ amdgpu_amdkfd_interrupt(adev, (const void *) &adev->irq.ih.ring[ring_index]); @@ -190,3 +196,79 @@ restart_ih: return IRQ_HANDLED; } + +/** + * amdgpu_ih_add_fault - Add a page fault record + * + * @adev: amdgpu device pointer + * @key: 64-bit encoding of PASID and address + * + * This should be called when a retry page fault interrupt is + * received. If this is a new page fault, it will be added to a hash + * table. The return value indicates whether this is a new fault, or + * a fault that was already known and is already being handled. + * + * If there are too many pending page faults, this will fail. Retry + * interrupts should be ignored in this case until there is enough + * free space. + * + * Returns 0 if the fault was added, 1 if the fault was already known, + * -ENOSPC if there are too many pending faults. + */ +int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key) +{ + unsigned long flags; + int r = -ENOSPC; + + if (WARN_ON_ONCE(!adev->irq.ih.faults)) + /* Should be allocated in <IP>_ih_sw_init on GPUs that + * support retry faults and require retry filtering. + */ + return r; + + spin_lock_irqsave(&adev->irq.ih.faults->lock, flags); + + /* Only let the hash table fill up to 50% for best performance */ + if (adev->irq.ih.faults->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1))) + goto unlock_out; + + r = chash_table_copy_in(&adev->irq.ih.faults->hash, key, NULL); + if (!r) + adev->irq.ih.faults->count++; + + /* chash_table_copy_in should never fail unless we're losing count */ + WARN_ON_ONCE(r < 0); + +unlock_out: + spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags); + return r; +} + +/** + * amdgpu_ih_clear_fault - Remove a page fault record + * + * @adev: amdgpu device pointer + * @key: 64-bit encoding of PASID and address + * + * This should be called when a page fault has been handled. Any + * future interrupt with this key will be processed as a new + * page fault. + */ +void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key) +{ + unsigned long flags; + int r; + + if (!adev->irq.ih.faults) + return; + + spin_lock_irqsave(&adev->irq.ih.faults->lock, flags); + + r = chash_table_remove(&adev->irq.ih.faults->hash, key, NULL); + if (!WARN_ON_ONCE(r < 0)) { + adev->irq.ih.faults->count--; + WARN_ON_ONCE(adev->irq.ih.faults->count < 0); + } + + spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index 3de8e74e5b3a..ada89358e220 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -24,6 +24,8 @@ #ifndef __AMDGPU_IH_H__ #define __AMDGPU_IH_H__ +#include <linux/chash.h> + struct amdgpu_device; /* * vega10+ IH clients @@ -69,6 +71,13 @@ enum amdgpu_ih_clientid #define AMDGPU_IH_CLIENTID_LEGACY 0 +#define AMDGPU_PAGEFAULT_HASH_BITS 8 +struct amdgpu_retryfault_hashtable { + DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0); + spinlock_t lock; + int count; +}; + /* * R6xx+ IH ring */ @@ -87,6 +96,7 @@ struct amdgpu_ih_ring { bool use_doorbell; bool use_bus_addr; dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */ + struct amdgpu_retryfault_hashtable *faults; }; #define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4 @@ -109,5 +119,7 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, bool use_bus_addr); void amdgpu_ih_ring_fini(struct amdgpu_device *adev); int amdgpu_ih_process(struct amdgpu_device *adev); +int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key); +void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 4bdd851f56d0..538e5f27d120 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -221,8 +221,9 @@ int amdgpu_irq_init(struct amdgpu_device *adev) spin_lock_init(&adev->irq.lock); - /* Disable vblank irqs aggressively for power-saving */ - adev->ddev->vblank_disable_immediate = true; + if (!adev->enable_virtual_display) + /* Disable vblank irqs aggressively for power-saving */ + adev->ddev->vblank_disable_immediate = true; r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index c908f972283c..4fd06f8d9768 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -455,13 +455,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_VRAM_USAGE: - ui64 = atomic64_read(&adev->vram_usage); + ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_VIS_VRAM_USAGE: - ui64 = atomic64_read(&adev->vram_vis_usage); + ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_GTT_USAGE: - ui64 = atomic64_read(&adev->gtt_usage); + ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_GDS_CONFIG: { struct drm_amdgpu_info_gds gds_info; @@ -497,7 +497,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file mem.vram.total_heap_size = adev->mc.real_vram_size; mem.vram.usable_heap_size = adev->mc.real_vram_size - adev->vram_pin_size; - mem.vram.heap_usage = atomic64_read(&adev->vram_usage); + mem.vram.heap_usage = + amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; mem.cpu_accessible_vram.total_heap_size = @@ -506,7 +507,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file adev->mc.visible_vram_size - (adev->vram_pin_size - adev->invisible_pin_size); mem.cpu_accessible_vram.heap_usage = - atomic64_read(&adev->vram_vis_usage); + amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); mem.cpu_accessible_vram.max_allocation = mem.cpu_accessible_vram.usable_heap_size * 3 / 4; @@ -514,7 +515,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file mem.gtt.total_heap_size *= PAGE_SIZE; mem.gtt.usable_heap_size = mem.gtt.total_heap_size - adev->gart_pin_size; - mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); + mem.gtt.heap_usage = + amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; return copy_to_user(out, &mem, @@ -588,11 +590,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); - dev_info.pte_fragment_size = - (1 << AMDGPU_LOG2_PAGES_PER_FRAG(adev)) * - AMDGPU_GPU_PAGE_SIZE; + dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; - dev_info.cu_active_number = adev->gfx.cu_info.number; dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; dev_info.ce_ram_size = adev->gfx.ce_ram_size; @@ -826,7 +825,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) } r = amdgpu_vm_init(adev, &fpriv->vm, - AMDGPU_VM_CONTEXT_GFX); + AMDGPU_VM_CONTEXT_GFX, 0); if (r) { kfree(fpriv); goto out_suspend; @@ -841,9 +840,12 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) } if (amdgpu_sriov_vf(adev)) { - r = amdgpu_map_static_csa(adev, &fpriv->vm); - if (r) + r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); + if (r) { + amdgpu_vm_fini(adev, &fpriv->vm); + kfree(fpriv); goto out_suspend; + } } mutex_init(&fpriv->bo_list_lock); @@ -894,8 +896,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, if (amdgpu_sriov_vf(adev)) { /* TODO: how to handle reserve failure */ BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); - amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va); - fpriv->vm.csa_bo_va = NULL; + amdgpu_vm_bo_rmv(adev, fpriv->csa_va); + fpriv->csa_va = NULL; amdgpu_bo_unreserve(adev->virt.csa_obj); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c index 6558a3ed57a7..bd67f4cb8e6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c @@ -50,8 +50,10 @@ struct amdgpu_mn { struct hlist_node node; /* objects protected by lock */ - struct mutex lock; - struct rb_root objects; + struct rw_semaphore lock; + struct rb_root_cached objects; + struct mutex read_lock; + atomic_t recursion; }; struct amdgpu_mn_node { @@ -74,17 +76,17 @@ static void amdgpu_mn_destroy(struct work_struct *work) struct amdgpu_bo *bo, *next_bo; mutex_lock(&adev->mn_lock); - mutex_lock(&rmn->lock); + down_write(&rmn->lock); hash_del(&rmn->node); - rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects, - it.rb) { + rbtree_postorder_for_each_entry_safe(node, next_node, + &rmn->objects.rb_root, it.rb) { list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { bo->mn = NULL; list_del_init(&bo->mn_list); } kfree(node); } - mutex_unlock(&rmn->lock); + up_write(&rmn->lock); mutex_unlock(&adev->mn_lock); mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm); kfree(rmn); @@ -106,6 +108,53 @@ static void amdgpu_mn_release(struct mmu_notifier *mn, schedule_work(&rmn->work); } + +/** + * amdgpu_mn_lock - take the write side lock for this mn + */ +void amdgpu_mn_lock(struct amdgpu_mn *mn) +{ + if (mn) + down_write(&mn->lock); +} + +/** + * amdgpu_mn_unlock - drop the write side lock for this mn + */ +void amdgpu_mn_unlock(struct amdgpu_mn *mn) +{ + if (mn) + up_write(&mn->lock); +} + +/** + * amdgpu_mn_read_lock - take the rmn read lock + * + * @rmn: our notifier + * + * Take the rmn read side lock. + */ +static void amdgpu_mn_read_lock(struct amdgpu_mn *rmn) +{ + mutex_lock(&rmn->read_lock); + if (atomic_inc_return(&rmn->recursion) == 1) + down_read_non_owner(&rmn->lock); + mutex_unlock(&rmn->read_lock); +} + +/** + * amdgpu_mn_read_unlock - drop the rmn read lock + * + * @rmn: our notifier + * + * Drop the rmn read side lock. + */ +static void amdgpu_mn_read_unlock(struct amdgpu_mn *rmn) +{ + if (atomic_dec_return(&rmn->recursion) == 0) + up_read_non_owner(&rmn->lock); +} + /** * amdgpu_mn_invalidate_node - unmap all BOs of a node * @@ -126,54 +175,13 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) continue; - r = amdgpu_bo_reserve(bo, true); - if (r) { - DRM_ERROR("(%ld) failed to reserve user bo\n", r); - continue; - } - r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false, MAX_SCHEDULE_TIMEOUT); if (r <= 0) DRM_ERROR("(%ld) failed to wait for user bo\n", r); - amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); - if (r) - DRM_ERROR("(%ld) failed to validate user bo\n", r); - - amdgpu_bo_unreserve(bo); - } -} - -/** - * amdgpu_mn_invalidate_page - callback to notify about mm change - * - * @mn: our notifier - * @mn: the mm this callback is about - * @address: address of invalidate page - * - * Invalidation of a single page. Blocks for all BOs mapping it - * and unmap them by move them into system domain again. - */ -static void amdgpu_mn_invalidate_page(struct mmu_notifier *mn, - struct mm_struct *mm, - unsigned long address) -{ - struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn); - struct interval_tree_node *it; - - mutex_lock(&rmn->lock); - - it = interval_tree_iter_first(&rmn->objects, address, address); - if (it) { - struct amdgpu_mn_node *node; - - node = container_of(it, struct amdgpu_mn_node, it); - amdgpu_mn_invalidate_node(node, address, address); + amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm); } - - mutex_unlock(&rmn->lock); } /** @@ -198,7 +206,7 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn, /* notification is exclusive, but interval is inclusive */ end -= 1; - mutex_lock(&rmn->lock); + amdgpu_mn_read_lock(rmn); it = interval_tree_iter_first(&rmn->objects, start, end); while (it) { @@ -209,14 +217,32 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn, amdgpu_mn_invalidate_node(node, start, end); } +} - mutex_unlock(&rmn->lock); +/** + * amdgpu_mn_invalidate_range_end - callback to notify about mm change + * + * @mn: our notifier + * @mn: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Release the lock again to allow new command submissions. + */ +static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +{ + struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn); + + amdgpu_mn_read_unlock(rmn); } static const struct mmu_notifier_ops amdgpu_mn_ops = { .release = amdgpu_mn_release, - .invalidate_page = amdgpu_mn_invalidate_page, .invalidate_range_start = amdgpu_mn_invalidate_range_start, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, }; /** @@ -226,7 +252,7 @@ static const struct mmu_notifier_ops amdgpu_mn_ops = { * * Creates a notifier context for current->mm. */ -static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev) +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev) { struct mm_struct *mm = current->mm; struct amdgpu_mn *rmn; @@ -251,8 +277,10 @@ static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev) rmn->adev = adev; rmn->mm = mm; rmn->mn.ops = &amdgpu_mn_ops; - mutex_init(&rmn->lock); - rmn->objects = RB_ROOT; + init_rwsem(&rmn->lock); + rmn->objects = RB_ROOT_CACHED; + mutex_init(&rmn->read_lock); + atomic_set(&rmn->recursion, 0); r = __mmu_notifier_register(&rmn->mn, mm); if (r) @@ -298,7 +326,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) INIT_LIST_HEAD(&bos); - mutex_lock(&rmn->lock); + down_write(&rmn->lock); while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) { kfree(node); @@ -312,7 +340,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) if (!node) { node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL); if (!node) { - mutex_unlock(&rmn->lock); + up_write(&rmn->lock); return -ENOMEM; } } @@ -327,7 +355,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) interval_tree_insert(&node->it, &rmn->objects); - mutex_unlock(&rmn->lock); + up_write(&rmn->lock); return 0; } @@ -353,7 +381,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo) return; } - mutex_lock(&rmn->lock); + down_write(&rmn->lock); /* save the next list entry for later */ head = bo->mn_list.next; @@ -368,6 +396,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo) kfree(node); } - mutex_unlock(&rmn->lock); + up_write(&rmn->lock); mutex_unlock(&adev->mn_lock); } + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h new file mode 100644 index 000000000000..d0095a3793b8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h @@ -0,0 +1,52 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ +#ifndef __AMDGPU_MN_H__ +#define __AMDGPU_MN_H__ + +/* + * MMU Notifier + */ +struct amdgpu_mn; + +#if defined(CONFIG_MMU_NOTIFIER) +void amdgpu_mn_lock(struct amdgpu_mn *mn); +void amdgpu_mn_unlock(struct amdgpu_mn *mn); +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev); +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_mn_unregister(struct amdgpu_bo *bo); +#else +static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} +static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} +static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev) +{ + return NULL; +} +static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + return -ENODEV; +} +static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +#endif + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 6e72fe7901ec..6982baeccd14 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -37,55 +37,6 @@ #include "amdgpu.h" #include "amdgpu_trace.h" - - -static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, - struct ttm_mem_reg *mem) -{ - if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size) - return 0; - - return ((mem->start << PAGE_SHIFT) + mem->size) > - adev->mc.visible_vram_size ? - adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : - mem->size; -} - -static void amdgpu_update_memory_usage(struct amdgpu_device *adev, - struct ttm_mem_reg *old_mem, - struct ttm_mem_reg *new_mem) -{ - u64 vis_size; - if (!adev) - return; - - if (new_mem) { - switch (new_mem->mem_type) { - case TTM_PL_TT: - atomic64_add(new_mem->size, &adev->gtt_usage); - break; - case TTM_PL_VRAM: - atomic64_add(new_mem->size, &adev->vram_usage); - vis_size = amdgpu_get_vis_part_size(adev, new_mem); - atomic64_add(vis_size, &adev->vram_vis_usage); - break; - } - } - - if (old_mem) { - switch (old_mem->mem_type) { - case TTM_PL_TT: - atomic64_sub(old_mem->size, &adev->gtt_usage); - break; - case TTM_PL_VRAM: - atomic64_sub(old_mem->size, &adev->vram_usage); - vis_size = amdgpu_get_vis_part_size(adev, old_mem); - atomic64_sub(vis_size, &adev->vram_vis_usage); - break; - } - } -} - static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); @@ -94,7 +45,6 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) bo = container_of(tbo, struct amdgpu_bo, tbo); amdgpu_bo_kunmap(bo); - amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL); drm_gem_object_release(&bo->gem_base); amdgpu_bo_unref(&bo->parent); @@ -114,11 +64,12 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) return false; } -static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, - struct ttm_placement *placement, - struct ttm_place *places, - u32 domain, u64 flags) +void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) { + struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); + struct ttm_placement *placement = &abo->placement; + struct ttm_place *places = abo->placements; + u64 flags = abo->flags; u32 c = 0; if (domain & AMDGPU_GEM_DOMAIN_VRAM) { @@ -141,7 +92,10 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, if (domain & AMDGPU_GEM_DOMAIN_GTT) { places[c].fpfn = 0; - places[c].lpfn = 0; + if (flags & AMDGPU_GEM_CREATE_SHADOW) + places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT; + else + places[c].lpfn = 0; places[c].flags = TTM_PL_FLAG_TT; if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) places[c].flags |= TTM_PL_FLAG_WC | @@ -198,27 +152,6 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, placement->busy_placement = places; } -void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); - - amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements, - domain, abo->flags); -} - -static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, - struct ttm_placement *placement) -{ - BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); - - memcpy(bo->placements, placement->placement, - placement->num_placement * sizeof(struct ttm_place)); - bo->placement.num_placement = placement->num_placement; - bo->placement.num_busy_placement = placement->num_busy_placement; - bo->placement.placement = bo->placements; - bo->placement.busy_placement = bo->placements; -} - /** * amdgpu_bo_create_reserved - create reserved BO for kernel use * @@ -350,14 +283,13 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, *cpu_addr = NULL; } -int amdgpu_bo_create_restricted(struct amdgpu_device *adev, - unsigned long size, int byte_align, - bool kernel, u32 domain, u64 flags, - struct sg_table *sg, - struct ttm_placement *placement, - struct reservation_object *resv, - uint64_t init_value, - struct amdgpu_bo **bo_ptr) +static int amdgpu_bo_do_create(struct amdgpu_device *adev, + unsigned long size, int byte_align, + bool kernel, u32 domain, u64 flags, + struct sg_table *sg, + struct reservation_object *resv, + uint64_t init_value, + struct amdgpu_bo **bo_ptr) { struct amdgpu_bo *bo; enum ttm_bo_type type; @@ -431,10 +363,11 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; #endif - amdgpu_fill_placement_to_bo(bo, placement); - /* Kernel allocation are uninterruptible */ + bo->tbo.bdev = &adev->mman.bdev; + amdgpu_ttm_placement_from_domain(bo, domain); initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); + /* Kernel allocation are uninterruptible */ r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, &bo->placement, page_align, !kernel, NULL, acc_size, sg, resv, &amdgpu_ttm_bo_destroy); @@ -489,28 +422,17 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, unsigned long size, int byte_align, struct amdgpu_bo *bo) { - struct ttm_placement placement = {0}; - struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; int r; if (bo->shadow) return 0; - bo->flags |= AMDGPU_GEM_CREATE_SHADOW; - memset(&placements, 0, - (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); - - amdgpu_ttm_placement_init(adev, &placement, - placements, AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_CPU_GTT_USWC); - - r = amdgpu_bo_create_restricted(adev, size, byte_align, true, - AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_CPU_GTT_USWC, - NULL, &placement, - bo->tbo.resv, - 0, - &bo->shadow); + r = amdgpu_bo_do_create(adev, size, byte_align, true, + AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_CREATE_CPU_GTT_USWC | + AMDGPU_GEM_CREATE_SHADOW, + NULL, bo->tbo.resv, 0, + &bo->shadow); if (!r) { bo->shadow->parent = amdgpu_bo_ref(bo); mutex_lock(&adev->shadow_list_lock); @@ -532,32 +454,23 @@ int amdgpu_bo_create(struct amdgpu_device *adev, uint64_t init_value, struct amdgpu_bo **bo_ptr) { - struct ttm_placement placement = {0}; - struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; + uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW; int r; - memset(&placements, 0, - (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); - - amdgpu_ttm_placement_init(adev, &placement, - placements, domain, flags); - - r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, - domain, flags, sg, &placement, - resv, init_value, bo_ptr); + r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain, + parent_flags, sg, resv, init_value, bo_ptr); if (r) return r; - if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) { - if (!resv) { - r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL); - WARN_ON(r != 0); - } + if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) { + if (!resv) + WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv, + NULL)); r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr)); if (!resv) - ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock); + reservation_object_unlock((*bo_ptr)->tbo.resv); if (r) amdgpu_bo_unref(bo_ptr); @@ -722,7 +635,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); int r, i; - unsigned fpfn, lpfn; if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) return -EPERM; @@ -754,22 +666,16 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, } bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + /* force to pin into visible video ram */ + if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) + bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; amdgpu_ttm_placement_from_domain(bo, domain); for (i = 0; i < bo->placement.num_placement; i++) { - /* force to pin into visible video ram */ - if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && - !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && - (!max_offset || max_offset > - adev->mc.visible_vram_size)) { - if (WARN_ON_ONCE(min_offset > - adev->mc.visible_vram_size)) - return -EINVAL; - fpfn = min_offset >> PAGE_SHIFT; - lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; - } else { - fpfn = min_offset >> PAGE_SHIFT; - lpfn = max_offset >> PAGE_SHIFT; - } + unsigned fpfn, lpfn; + + fpfn = min_offset >> PAGE_SHIFT; + lpfn = max_offset >> PAGE_SHIFT; + if (fpfn > bo->placements[i].fpfn) bo->placements[i].fpfn = fpfn; if (!bo->placements[i].lpfn || @@ -979,7 +885,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, return; abo = container_of(bo, struct amdgpu_bo, tbo); - amdgpu_vm_bo_invalidate(adev, abo); + amdgpu_vm_bo_invalidate(adev, abo, evict); amdgpu_bo_kunmap(abo); @@ -992,8 +898,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, return; /* move_notify is called before move happens */ - amdgpu_update_memory_usage(adev, &bo->mem, new_mem); - trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 9b7b4fcb047b..39b6bf6fb051 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -33,7 +33,9 @@ #define AMDGPU_BO_INVALID_OFFSET LONG_MAX +/* bo virtual addresses in a vm */ struct amdgpu_bo_va_mapping { + struct amdgpu_bo_va *bo_va; struct list_head list; struct rb_node rb; uint64_t start; @@ -43,26 +45,24 @@ struct amdgpu_bo_va_mapping { uint64_t flags; }; -/* bo virtual addresses in a specific vm */ +/* User space allocated BO in a VM */ struct amdgpu_bo_va { + struct amdgpu_vm_bo_base base; + /* protected by bo being reserved */ - struct list_head bo_list; - struct dma_fence *last_pt_update; unsigned ref_count; - /* protected by vm mutex and spinlock */ - struct list_head vm_status; + /* all other members protected by the VM PD being reserved */ + struct dma_fence *last_pt_update; /* mappings for this bo_va */ struct list_head invalids; struct list_head valids; - /* constant after initialization */ - struct amdgpu_vm *vm; - struct amdgpu_bo *bo; + /* If the mappings are cleared or filled */ + bool cleared; }; - struct amdgpu_bo { /* Protected by tbo.reserved */ u32 preferred_domains; @@ -195,14 +195,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev, struct reservation_object *resv, uint64_t init_value, struct amdgpu_bo **bo_ptr); -int amdgpu_bo_create_restricted(struct amdgpu_device *adev, - unsigned long size, int byte_align, - bool kernel, u32 domain, u64 flags, - struct sg_table *sg, - struct ttm_placement *placement, - struct reservation_object *resv, - uint64_t init_value, - struct amdgpu_bo **bo_ptr); int amdgpu_bo_create_reserved(struct amdgpu_device *adev, unsigned long size, int align, u32 domain, struct amdgpu_bo **bo_ptr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 7df503aedb69..f6ce52956e6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -74,7 +74,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) adev->pm.dpm.ac_power = true; else adev->pm.dpm.ac_power = false; - if (adev->pm.funcs->enable_bapm) + if (adev->powerplay.pp_funcs->enable_bapm) amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power); mutex_unlock(&adev->pm.mutex); } @@ -88,9 +88,9 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; enum amd_pm_state_type pm; - if (adev->pp_enabled) { + if (adev->powerplay.pp_funcs->get_current_power_state) pm = amdgpu_dpm_get_current_power_state(adev); - } else + else pm = adev->pm.dpm.user_state; return snprintf(buf, PAGE_SIZE, "%s\n", @@ -119,7 +119,7 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev, } if (adev->pp_enabled) { - amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL); + amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL); } else { mutex_lock(&adev->pm.mutex); adev->pm.dpm.user_state = state; @@ -140,13 +140,17 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; - enum amd_dpm_forced_level level; + enum amd_dpm_forced_level level = 0xff; if ((adev->flags & AMD_IS_PX) && (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) return snprintf(buf, PAGE_SIZE, "off\n"); - level = amdgpu_dpm_get_performance_level(adev); + if (adev->powerplay.pp_funcs->get_performance_level) + level = amdgpu_dpm_get_performance_level(adev); + else + level = adev->pm.dpm.forced_level; + return snprintf(buf, PAGE_SIZE, "%s\n", (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : @@ -167,7 +171,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; enum amd_dpm_forced_level level; - enum amd_dpm_forced_level current_level; + enum amd_dpm_forced_level current_level = 0xff; int ret = 0; /* Can't force performance level when the card is off */ @@ -175,7 +179,8 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) return -EINVAL; - current_level = amdgpu_dpm_get_performance_level(adev); + if (adev->powerplay.pp_funcs->get_performance_level) + current_level = amdgpu_dpm_get_performance_level(adev); if (strncmp("low", buf, strlen("low")) == 0) { level = AMD_DPM_FORCED_LEVEL_LOW; @@ -203,9 +208,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, if (current_level == level) return count; - if (adev->pp_enabled) - amdgpu_dpm_force_performance_level(adev, level); - else { + if (adev->powerplay.pp_funcs->force_performance_level) { mutex_lock(&adev->pm.mutex); if (adev->pm.dpm.thermal_active) { count = -EINVAL; @@ -233,7 +236,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev, struct pp_states_info data; int i, buf_len; - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->get_pp_num_states) amdgpu_dpm_get_pp_num_states(adev, &data); buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums); @@ -257,8 +260,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev, enum amd_pm_state_type pm = 0; int i = 0; - if (adev->pp_enabled) { - + if (adev->powerplay.pp_funcs->get_current_power_state + && adev->powerplay.pp_funcs->get_pp_num_states) { pm = amdgpu_dpm_get_current_power_state(adev); amdgpu_dpm_get_pp_num_states(adev, &data); @@ -280,25 +283,10 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; - struct pp_states_info data; - enum amd_pm_state_type pm = 0; - int i; - - if (adev->pp_force_state_enabled && adev->pp_enabled) { - pm = amdgpu_dpm_get_current_power_state(adev); - amdgpu_dpm_get_pp_num_states(adev, &data); - - for (i = 0; i < data.nums; i++) { - if (pm == data.states[i]) - break; - } - if (i == data.nums) - i = -EINVAL; - - return snprintf(buf, PAGE_SIZE, "%d\n", i); - - } else + if (adev->pp_force_state_enabled) + return amdgpu_get_pp_cur_state(dev, attr, buf); + else return snprintf(buf, PAGE_SIZE, "\n"); } @@ -330,7 +318,7 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev, if (state != POWER_STATE_TYPE_INTERNAL_BOOT && state != POWER_STATE_TYPE_DEFAULT) { amdgpu_dpm_dispatch_task(adev, - AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL); + AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL); adev->pp_force_state_enabled = true; } } @@ -347,7 +335,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev, char *table = NULL; int size; - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->get_pp_table) size = amdgpu_dpm_get_pp_table(adev, &table); else return 0; @@ -368,7 +356,7 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->set_pp_table) amdgpu_dpm_set_pp_table(adev, buf, count); return count; @@ -380,14 +368,11 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; - ssize_t size = 0; - if (adev->pp_enabled) - size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf); - else if (adev->pm.funcs->print_clock_levels) - size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf); - - return size; + if (adev->powerplay.pp_funcs->print_clock_levels) + return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf); + else + return snprintf(buf, PAGE_SIZE, "\n"); } static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, @@ -416,10 +401,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, mask |= 1 << level; } - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->force_clock_level) amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); - else if (adev->pm.funcs->force_clock_level) - adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask); + fail: return count; } @@ -430,14 +414,11 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; - ssize_t size = 0; - - if (adev->pp_enabled) - size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf); - else if (adev->pm.funcs->print_clock_levels) - size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf); - return size; + if (adev->powerplay.pp_funcs->print_clock_levels) + return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf); + else + return snprintf(buf, PAGE_SIZE, "\n"); } static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, @@ -465,11 +446,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, } mask |= 1 << level; } - - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->force_clock_level) amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); - else if (adev->pm.funcs->force_clock_level) - adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask); + fail: return count; } @@ -480,14 +459,11 @@ static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; - ssize_t size = 0; - - if (adev->pp_enabled) - size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf); - else if (adev->pm.funcs->print_clock_levels) - size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf); - return size; + if (adev->powerplay.pp_funcs->print_clock_levels) + return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf); + else + return snprintf(buf, PAGE_SIZE, "\n"); } static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, @@ -515,11 +491,9 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, } mask |= 1 << level; } - - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->force_clock_level) amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); - else if (adev->pm.funcs->force_clock_level) - adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask); + fail: return count; } @@ -532,10 +506,8 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; uint32_t value = 0; - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->get_sclk_od) value = amdgpu_dpm_get_sclk_od(adev); - else if (adev->pm.funcs->get_sclk_od) - value = adev->pm.funcs->get_sclk_od(adev); return snprintf(buf, PAGE_SIZE, "%d\n", value); } @@ -556,12 +528,12 @@ static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, count = -EINVAL; goto fail; } + if (adev->powerplay.pp_funcs->set_sclk_od) + amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); if (adev->pp_enabled) { - amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); - amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL); - } else if (adev->pm.funcs->set_sclk_od) { - adev->pm.funcs->set_sclk_od(adev, (uint32_t)value); + amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); + } else { adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; amdgpu_pm_compute_clocks(adev); } @@ -578,10 +550,8 @@ static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; uint32_t value = 0; - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->get_mclk_od) value = amdgpu_dpm_get_mclk_od(adev); - else if (adev->pm.funcs->get_mclk_od) - value = adev->pm.funcs->get_mclk_od(adev); return snprintf(buf, PAGE_SIZE, "%d\n", value); } @@ -602,12 +572,12 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, count = -EINVAL; goto fail; } + if (adev->powerplay.pp_funcs->set_mclk_od) + amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); if (adev->pp_enabled) { - amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); - amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL); - } else if (adev->pm.funcs->set_mclk_od) { - adev->pm.funcs->set_mclk_od(adev, (uint32_t)value); + amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); + } else { adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; amdgpu_pm_compute_clocks(adev); } @@ -621,14 +591,11 @@ static ssize_t amdgpu_get_pp_power_profile(struct device *dev, { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; - int ret = 0; + int ret = 0xff; - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->get_power_profile_state) ret = amdgpu_dpm_get_power_profile_state( adev, query); - else if (adev->pm.funcs->get_power_profile_state) - ret = adev->pm.funcs->get_power_profile_state( - adev, query); if (ret) return ret; @@ -675,15 +642,12 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev, char *sub_str, buf_cpy[128], *tmp_str; const char delimiter[3] = {' ', '\n', '\0'}; long int value; - int ret = 0; + int ret = 0xff; if (strncmp("reset", buf, strlen("reset")) == 0) { - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->reset_power_profile_state) ret = amdgpu_dpm_reset_power_profile_state( adev, request); - else if (adev->pm.funcs->reset_power_profile_state) - ret = adev->pm.funcs->reset_power_profile_state( - adev, request); if (ret) { count = -EINVAL; goto fail; @@ -692,12 +656,10 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev, } if (strncmp("set", buf, strlen("set")) == 0) { - if (adev->pp_enabled) + if (adev->powerplay.pp_funcs->set_power_profile_state) ret = amdgpu_dpm_set_power_profile_state( adev, request); - else if (adev->pm.funcs->set_power_profile_state) - ret = adev->pm.funcs->set_power_profile_state( - adev, request); + if (ret) { count = -EINVAL; goto fail; @@ -745,13 +707,8 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev, loop++; } - - if (adev->pp_enabled) - ret = amdgpu_dpm_set_power_profile_state( - adev, request); - else if (adev->pm.funcs->set_power_profile_state) - ret = adev->pm.funcs->set_power_profile_state( - adev, request); + if (adev->powerplay.pp_funcs->set_power_profile_state) + ret = amdgpu_dpm_set_power_profile_state(adev, request); if (ret) count = -EINVAL; @@ -831,7 +788,7 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev, (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) return -EINVAL; - if (!adev->pp_enabled && !adev->pm.funcs->get_temperature) + if (!adev->powerplay.pp_funcs->get_temperature) temp = 0; else temp = amdgpu_dpm_get_temperature(adev); @@ -862,7 +819,7 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, struct amdgpu_device *adev = dev_get_drvdata(dev); u32 pwm_mode = 0; - if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode) + if (!adev->powerplay.pp_funcs->get_fan_control_mode) return -EINVAL; pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); @@ -879,7 +836,7 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, int err; int value; - if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode) + if (!adev->powerplay.pp_funcs->set_fan_control_mode) return -EINVAL; err = kstrtoint(buf, 10, &value); @@ -919,9 +876,11 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, value = (value * 100) / 255; - err = amdgpu_dpm_set_fan_speed_percent(adev, value); - if (err) - return err; + if (adev->powerplay.pp_funcs->set_fan_speed_percent) { + err = amdgpu_dpm_set_fan_speed_percent(adev, value); + if (err) + return err; + } return count; } @@ -932,11 +891,13 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, { struct amdgpu_device *adev = dev_get_drvdata(dev); int err; - u32 speed; + u32 speed = 0; - err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); - if (err) - return err; + if (adev->powerplay.pp_funcs->get_fan_speed_percent) { + err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); + if (err) + return err; + } speed = (speed * 255) / 100; @@ -949,11 +910,13 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, { struct amdgpu_device *adev = dev_get_drvdata(dev); int err; - u32 speed; + u32 speed = 0; - err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); - if (err) - return err; + if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { + err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); + if (err) + return err; + } return sprintf(buf, "%i\n", speed); } @@ -1008,21 +971,21 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, return 0; /* mask fan attributes if we have no bindings for this asic to expose */ - if ((!adev->pm.funcs->get_fan_speed_percent && + if ((!adev->powerplay.pp_funcs->get_fan_speed_percent && attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ - (!adev->pm.funcs->get_fan_control_mode && + (!adev->powerplay.pp_funcs->get_fan_control_mode && attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ effective_mode &= ~S_IRUGO; - if ((!adev->pm.funcs->set_fan_speed_percent && + if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ - (!adev->pm.funcs->set_fan_control_mode && + (!adev->powerplay.pp_funcs->set_fan_control_mode && attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ effective_mode &= ~S_IWUSR; /* hide max/min values if we can't both query and manage the fan */ - if ((!adev->pm.funcs->set_fan_speed_percent && - !adev->pm.funcs->get_fan_speed_percent) && + if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && + !adev->powerplay.pp_funcs->get_fan_speed_percent) && (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) return 0; @@ -1055,7 +1018,7 @@ void amdgpu_dpm_thermal_work_handler(struct work_struct *work) if (!adev->pm.dpm_enabled) return; - if (adev->pm.funcs->get_temperature) { + if (adev->powerplay.pp_funcs->get_temperature) { int temp = amdgpu_dpm_get_temperature(adev); if (temp < adev->pm.dpm.thermal.min_temp) @@ -1087,7 +1050,7 @@ static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, true : false; /* check if the vblank period is too short to adjust the mclk */ - if (single_display && adev->pm.funcs->vblank_too_short) { + if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { if (amdgpu_dpm_vblank_too_short(adev)) single_display = false; } @@ -1216,7 +1179,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) struct amdgpu_ps *ps; enum amd_pm_state_type dpm_state; int ret; - bool equal; + bool equal = false; /* if dpm init failed */ if (!adev->pm.dpm_enabled) @@ -1236,7 +1199,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) else return; - if (amdgpu_dpm == 1) { + if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) { printk("switching from power state:\n"); amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); printk("switching to power state:\n"); @@ -1245,15 +1208,17 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) /* update whether vce is active */ ps->vce_active = adev->pm.dpm.vce_active; - - amdgpu_dpm_display_configuration_changed(adev); + if (adev->powerplay.pp_funcs->display_configuration_changed) + amdgpu_dpm_display_configuration_changed(adev); ret = amdgpu_dpm_pre_set_power_state(adev); if (ret) return; - if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))) - equal = false; + if (adev->powerplay.pp_funcs->check_state_equal) { + if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)) + equal = false; + } if (equal) return; @@ -1264,7 +1229,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; - if (adev->pm.funcs->force_performance_level) { + if (adev->powerplay.pp_funcs->force_performance_level) { if (adev->pm.dpm.thermal_active) { enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; /* force low perf level for thermal */ @@ -1280,7 +1245,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) { - if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) { + if (adev->powerplay.pp_funcs->powergate_uvd) { /* enable/disable UVD */ mutex_lock(&adev->pm.mutex); amdgpu_dpm_powergate_uvd(adev, !enable); @@ -1302,7 +1267,7 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) { - if (adev->pp_enabled || adev->pm.funcs->powergate_vce) { + if (adev->powerplay.pp_funcs->powergate_vce) { /* enable/disable VCE */ mutex_lock(&adev->pm.mutex); amdgpu_dpm_powergate_vce(adev, !enable); @@ -1337,8 +1302,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev) { int i; - if (adev->pp_enabled) - /* TO DO */ + if (adev->powerplay.pp_funcs->print_power_state == NULL) return; for (i = 0; i < adev->pm.dpm.num_ps; i++) @@ -1353,10 +1317,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) if (adev->pm.sysfs_initialized) return 0; - if (!adev->pp_enabled) { - if (adev->pm.funcs->get_temperature == NULL) - return 0; - } + if (adev->powerplay.pp_funcs->get_temperature == NULL) + return 0; adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, DRIVER_NAME, adev, @@ -1496,7 +1458,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) } if (adev->pp_enabled) { - amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL); + amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL); } else { mutex_lock(&adev->pm.mutex); adev->pm.dpm.new_active_crtcs = 0; @@ -1634,8 +1596,8 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) return amdgpu_debugfs_pm_info_pp(m, adev); } else { mutex_lock(&adev->pm.mutex); - if (adev->pm.funcs->debugfs_print_current_performance_level) - adev->pm.funcs->debugfs_print_current_performance_level(adev, m); + if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) + adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m); else seq_printf(m, "Debugfs support not implemented for this asic\n"); mutex_unlock(&adev->pm.mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index b7e1c026c0c8..2d2f0960b025 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -87,17 +87,28 @@ static int amdgpu_pp_early_init(void *handle) case CHIP_OLAND: case CHIP_HAINAN: amd_pp->ip_funcs = &si_dpm_ip_funcs; + amd_pp->pp_funcs = &si_dpm_funcs; break; #endif #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: case CHIP_HAWAII: - amd_pp->ip_funcs = &ci_dpm_ip_funcs; + if (amdgpu_dpm == -1) { + amd_pp->ip_funcs = &ci_dpm_ip_funcs; + amd_pp->pp_funcs = &ci_dpm_funcs; + } else { + adev->pp_enabled = true; + if (amdgpu_create_pp_handle(adev)) + return -EINVAL; + amd_pp->ip_funcs = &pp_ip_funcs; + amd_pp->pp_funcs = &pp_dpm_funcs; + } break; case CHIP_KABINI: case CHIP_MULLINS: case CHIP_KAVERI: amd_pp->ip_funcs = &kv_dpm_ip_funcs; + amd_pp->pp_funcs = &kv_dpm_funcs; break; #endif default: @@ -128,7 +139,7 @@ static int amdgpu_pp_late_init(void *handle) if (adev->pp_enabled && adev->pm.dpm_enabled) { amdgpu_pm_sysfs_init(adev); - amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL); + amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); } return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c index 5b3f92891f89..90af8e82b16a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -57,6 +57,40 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) ttm_bo_kunmap(&bo->dma_buf_vmap); } +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + unsigned asize = amdgpu_bo_size(bo); + int ret; + + if (!vma->vm_file) + return -ENODEV; + + if (adev == NULL) + return -ENODEV; + + /* Check for valid size. */ + if (asize < vma->vm_end - vma->vm_start) + return -EINVAL; + + if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || + (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { + return -EPERM; + } + vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; + + /* prime mmap does not need to check access, so allow here */ + ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); + if (ret) + return ret; + + ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); + drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); + + return ret; +} + struct drm_gem_object * amdgpu_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf_attachment *attach, @@ -136,7 +170,8 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, { struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); - if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) + if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || + bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) return ERR_PTR(-EPERM); return drm_gem_prime_export(dev, gobj, flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 8c2204c7b384..447d446b5015 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -57,21 +57,23 @@ static int psp_sw_init(void *handle) psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf; psp->ring_init = psp_v3_1_ring_init; psp->ring_create = psp_v3_1_ring_create; + psp->ring_stop = psp_v3_1_ring_stop; psp->ring_destroy = psp_v3_1_ring_destroy; psp->cmd_submit = psp_v3_1_cmd_submit; psp->compare_sram_data = psp_v3_1_compare_sram_data; psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk; + psp->mode1_reset = psp_v3_1_mode1_reset; break; case CHIP_RAVEN: -#if 0 psp->init_microcode = psp_v10_0_init_microcode; -#endif psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf; psp->ring_init = psp_v10_0_ring_init; psp->ring_create = psp_v10_0_ring_create; + psp->ring_stop = psp_v10_0_ring_stop; psp->ring_destroy = psp_v10_0_ring_destroy; psp->cmd_submit = psp_v10_0_cmd_submit; psp->compare_sram_data = psp_v10_0_compare_sram_data; + psp->mode1_reset = psp_v10_0_mode1_reset; break; default: return -EINVAL; @@ -90,6 +92,12 @@ static int psp_sw_init(void *handle) static int psp_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + release_firmware(adev->psp.sos_fw); + adev->psp.sos_fw = NULL; + release_firmware(adev->psp.asd_fw); + adev->psp.asd_fw = NULL; return 0; } @@ -253,15 +261,18 @@ static int psp_asd_load(struct psp_context *psp) static int psp_hw_start(struct psp_context *psp) { + struct amdgpu_device *adev = psp->adev; int ret; - ret = psp_bootloader_load_sysdrv(psp); - if (ret) - return ret; + if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) { + ret = psp_bootloader_load_sysdrv(psp); + if (ret) + return ret; - ret = psp_bootloader_load_sos(psp); - if (ret) - return ret; + ret = psp_bootloader_load_sos(psp); + if (ret) + return ret; + } ret = psp_ring_create(psp, PSP_RING_TYPE__KM); if (ret) @@ -453,6 +464,16 @@ static int psp_hw_fini(void *handle) static int psp_suspend(void *handle) { + int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct psp_context *psp = &adev->psp; + + ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); + if (ret) { + DRM_ERROR("PSP ring stop failed\n"); + return ret; + } + return 0; } @@ -487,6 +508,22 @@ failed: return ret; } +static bool psp_check_reset(void* handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (adev->flags & AMD_IS_APU) + return true; + + return false; +} + +static int psp_reset(void* handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return psp_mode1_reset(&adev->psp); +} + static bool psp_check_fw_loading_status(struct amdgpu_device *adev, enum AMDGPU_UCODE_ID ucode_type) { @@ -530,8 +567,9 @@ const struct amd_ip_funcs psp_ip_funcs = { .suspend = psp_suspend, .resume = psp_resume, .is_idle = NULL, + .check_soft_reset = psp_check_reset, .wait_for_idle = NULL, - .soft_reset = NULL, + .soft_reset = psp_reset, .set_clockgating_state = psp_set_clockgating_state, .set_powergating_state = psp_set_powergating_state, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 538fa9dbfb21..ce4654550416 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -66,6 +66,8 @@ struct psp_context struct psp_gfx_cmd_resp *cmd); int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type); + int (*ring_stop)(struct psp_context *psp, + enum psp_ring_type ring_type); int (*ring_destroy)(struct psp_context *psp, enum psp_ring_type ring_type); int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode, @@ -74,6 +76,7 @@ struct psp_context struct amdgpu_firmware_info *ucode, enum AMDGPU_UCODE_ID ucode_type); bool (*smu_reload_quirk)(struct psp_context *psp); + int (*mode1_reset)(struct psp_context *psp); /* fence buffer */ struct amdgpu_bo *fw_pri_bo; @@ -123,6 +126,7 @@ struct amdgpu_psp_funcs { #define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type)) #define psp_ring_init(psp, type) (psp)->ring_init((psp), (type)) #define psp_ring_create(psp, type) (psp)->ring_create((psp), (type)) +#define psp_ring_stop(psp, type) (psp)->ring_stop((psp), (type)) #define psp_ring_destroy(psp, type) ((psp)->ring_destroy((psp), (type))) #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ (psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) @@ -136,6 +140,8 @@ struct amdgpu_psp_funcs { ((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0) #define psp_smu_reload_quirk(psp) \ ((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false) +#define psp_mode1_reset(psp) \ + ((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false) extern const struct amd_ip_funcs psp_ip_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 6c5646b48d1a..5ce65280b396 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -170,6 +170,16 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned irq_type) { int r; + int sched_hw_submission = amdgpu_sched_hw_submission; + + /* Set the hw submission limit higher for KIQ because + * it's used for a number of gfx/compute tasks by both + * KFD and KGD which may have outstanding fences and + * it doesn't really use the gpu scheduler anyway; + * KIQ tasks get submitted directly to the ring. + */ + if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) + sched_hw_submission = max(sched_hw_submission, 256); if (ring->adev == NULL) { if (adev->num_rings >= AMDGPU_MAX_RINGS) @@ -178,8 +188,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, ring->adev = adev; ring->idx = adev->num_rings++; adev->rings[ring->idx] = ring; - r = amdgpu_fence_driver_init_ring(ring, - amdgpu_sched_hw_submission); + r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission); if (r) return r; } @@ -218,8 +227,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, return r; } - ring->ring_size = roundup_pow_of_two(max_dw * 4 * - amdgpu_sched_hw_submission); + ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission); ring->buf_mask = (ring->ring_size / 4) - 1; ring->ptr_mask = ring->funcs->support_64bit_ptrs ? diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index a6899180b265..c586f44312f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -244,6 +244,12 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct dma_fence *f = e->fence; struct amd_sched_fence *s_fence = to_amd_sched_fence(f); + if (dma_fence_is_signaled(f)) { + hash_del(&e->node); + dma_fence_put(f); + kmem_cache_free(amdgpu_sync_slab, e); + continue; + } if (ring && s_fence) { /* For fences from the same ring it is sufficient * when they are scheduled. @@ -256,13 +262,6 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, } } - if (dma_fence_is_signaled(f)) { - hash_del(&e->node); - dma_fence_put(f); - kmem_cache_free(amdgpu_sync_slab, e); - continue; - } - return f; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 9ab58245e518..213988f336ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -228,7 +228,7 @@ TRACE_EVENT(amdgpu_vm_bo_map, ), TP_fast_assign( - __entry->bo = bo_va ? bo_va->bo : NULL; + __entry->bo = bo_va ? bo_va->base.bo : NULL; __entry->start = mapping->start; __entry->last = mapping->last; __entry->offset = mapping->offset; @@ -252,7 +252,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap, ), TP_fast_assign( - __entry->bo = bo_va->bo; + __entry->bo = bo_va->base.bo; __entry->start = mapping->start; __entry->last = mapping->last; __entry->offset = mapping->offset; @@ -417,5 +417,5 @@ TRACE_EVENT(amdgpu_ttm_bo_move, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu #include <trace/define_trace.h> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c index 385b7e1d72f9..9ec96b9e85d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c @@ -1,4 +1,23 @@ /* Copyright Red Hat Inc 2010. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * * Author : Dave Airlie <airlied@redhat.com> */ #include <drm/drmP.h> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index c803b082324d..15a28578d458 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -42,7 +42,9 @@ #include <linux/swap.h> #include <linux/pagemap.h> #include <linux/debugfs.h> +#include <linux/iommu.h> #include "amdgpu.h" +#include "amdgpu_trace.h" #include "bif/bif_4_1_d.h" #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) @@ -607,6 +609,7 @@ struct amdgpu_ttm_tt { spinlock_t guptasklock; struct list_head guptasks; atomic_t mmu_invalidations; + uint32_t last_set_pages; struct list_head list; }; @@ -620,6 +623,8 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) flags |= FOLL_WRITE; + down_read(¤t->mm->mmap_sem); + if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { /* check that we only use anonymous memory to prevent problems with writeback */ @@ -627,8 +632,10 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) struct vm_area_struct *vma; vma = find_vma(gtt->usermm, gtt->userptr); - if (!vma || vma->vm_file || vma->vm_end < end) + if (!vma || vma->vm_file || vma->vm_end < end) { + up_read(¤t->mm->mmap_sem); return -EPERM; + } } do { @@ -655,13 +662,47 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) } while (pinned < ttm->num_pages); + up_read(¤t->mm->mmap_sem); return 0; release_pages: release_pages(pages, pinned, 0); + up_read(¤t->mm->mmap_sem); return r; } +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + gtt->last_set_pages = atomic_read(>t->mmu_invalidations); + for (i = 0; i < ttm->num_pages; ++i) { + if (ttm->pages[i]) + put_page(ttm->pages[i]); + + ttm->pages[i] = pages ? pages[i] : NULL; + } +} + +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + for (i = 0; i < ttm->num_pages; ++i) { + struct page *page = ttm->pages[i]; + + if (!page) + continue; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + set_page_dirty(page); + + mark_page_accessed(page); + } +} + /* prepare the sg table with the user pages */ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) { @@ -699,7 +740,6 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) { struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); struct amdgpu_ttm_tt *gtt = (void *)ttm; - struct sg_page_iter sg_iter; int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); enum dma_data_direction direction = write ? @@ -712,47 +752,16 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) /* free the sg table and pages again */ dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); - for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { - struct page *page = sg_page_iter_page(&sg_iter); - if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) - set_page_dirty(page); - - mark_page_accessed(page); - put_page(page); - } + amdgpu_ttm_tt_mark_user_pages(ttm); sg_free_table(ttm->sg); } -static int amdgpu_ttm_do_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) -{ - struct amdgpu_ttm_tt *gtt = (void *)ttm; - uint64_t flags; - int r; - - spin_lock(>t->adev->gtt_list_lock); - flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, mem); - gtt->offset = (u64)mem->start << PAGE_SHIFT; - r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, - ttm->pages, gtt->ttm.dma_address, flags); - - if (r) { - DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", - ttm->num_pages, gtt->offset); - goto error_gart_bind; - } - - list_add_tail(>t->list, >t->adev->gtt_list); -error_gart_bind: - spin_unlock(>t->adev->gtt_list_lock); - return r; - -} - static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) { struct amdgpu_ttm_tt *gtt = (void*)ttm; + uint64_t flags; int r = 0; if (gtt->userptr) { @@ -772,9 +781,24 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, bo_mem->mem_type == AMDGPU_PL_OA) return -EINVAL; - if (amdgpu_gtt_mgr_is_allocated(bo_mem)) - r = amdgpu_ttm_do_bind(ttm, bo_mem); + if (!amdgpu_gtt_mgr_is_allocated(bo_mem)) + return 0; + + spin_lock(>t->adev->gtt_list_lock); + flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); + gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; + r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, + ttm->pages, gtt->ttm.dma_address, flags); + if (r) { + DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", + ttm->num_pages, gtt->offset); + goto error_gart_bind; + } + + list_add_tail(>t->list, >t->adev->gtt_list); +error_gart_bind: + spin_unlock(>t->adev->gtt_list_lock); return r; } @@ -787,20 +811,38 @@ bool amdgpu_ttm_is_bound(struct ttm_tt *ttm) int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct ttm_tt *ttm = bo->ttm; + struct ttm_mem_reg tmp; + struct ttm_placement placement; + struct ttm_place placements; int r; if (!ttm || amdgpu_ttm_is_bound(ttm)) return 0; - r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo, - NULL, bo_mem); - if (r) { - DRM_ERROR("Failed to allocate GTT address space (%d)\n", r); + tmp = bo->mem; + tmp.mm_node = NULL; + placement.num_placement = 1; + placement.placement = &placements; + placement.num_busy_placement = 1; + placement.busy_placement = &placements; + placements.fpfn = 0; + placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT; + placements.flags = bo->mem.placement | TTM_PL_FLAG_TT; + + r = ttm_bo_mem_space(bo, &placement, &tmp, true, false); + if (unlikely(r)) return r; - } - return amdgpu_ttm_do_bind(ttm, bo_mem); + r = ttm_bo_move_ttm(bo, true, false, &tmp); + if (unlikely(r)) + ttm_bo_mem_put(bo, &tmp); + else + bo->offset = (bo->mem.start << PAGE_SHIFT) + + bo->bdev->man[bo->mem.mem_type].gpu_offset; + + return r; } int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) @@ -892,10 +934,8 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) { - struct amdgpu_device *adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); struct amdgpu_ttm_tt *gtt = (void *)ttm; - unsigned i; - int r; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); if (ttm->state != tt_unpopulated) @@ -918,44 +958,23 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) return 0; } - adev = amdgpu_ttm_adev(ttm->bdev); - #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { return ttm_dma_populate(>t->ttm, adev->dev); } #endif - r = ttm_pool_populate(ttm); - if (r) { - return r; - } - - for (i = 0; i < ttm->num_pages; i++) { - gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], - 0, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { - while (i--) { - pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - gtt->ttm.dma_address[i] = 0; - } - ttm_pool_unpopulate(ttm); - return -EFAULT; - } - } - return 0; + return ttm_populate_and_map_pages(adev->dev, >t->ttm); } static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) { struct amdgpu_device *adev; struct amdgpu_ttm_tt *gtt = (void *)ttm; - unsigned i; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); if (gtt && gtt->userptr) { + amdgpu_ttm_tt_set_user_pages(ttm, NULL); kfree(ttm->sg); ttm->page_flags &= ~TTM_PAGE_FLAG_SG; return; @@ -973,14 +992,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) } #endif - for (i = 0; i < ttm->num_pages; i++) { - if (gtt->ttm.dma_address[i]) { - pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - } - } - - ttm_pool_unpopulate(ttm); + ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm); } int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, @@ -997,6 +1009,7 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, spin_lock_init(>t->guptasklock); INIT_LIST_HEAD(>t->guptasks); atomic_set(>t->mmu_invalidations, 0); + gtt->last_set_pages = 0; return 0; } @@ -1049,6 +1062,16 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, return prev_invalidated != *last_invalidated; } +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL || !gtt->userptr) + return false; + + return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages; +} + bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) { struct amdgpu_ttm_tt *gtt = (void *)ttm; @@ -1148,14 +1171,14 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, } spin_lock_irqsave(&adev->mmio_idx_lock, flags); - WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); - WREG32(mmMM_INDEX_HI, aligned_pos >> 31); + WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); + WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); if (!write || mask != 0xffffffff) - value = RREG32(mmMM_DATA); + value = RREG32_NO_KIQ(mmMM_DATA); if (write) { value &= ~mask; value |= (*(uint32_t *)buf << shift) & mask; - WREG32(mmMM_DATA, value); + WREG32_NO_KIQ(mmMM_DATA, value); } spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); if (!write) { @@ -1503,8 +1526,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, struct dma_fence **fence) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/ - uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; + uint32_t max_bytes = 8 * + adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; struct drm_mm_node *mm_node; @@ -1536,8 +1559,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, ++mm_node; } - /* 10 double words for each SDMA_OP_PTEPDE cmd */ - num_dw = num_loops * 10; + /* num of dwords for each SDMA_OP_PTEPDE cmd */ + num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw; /* for IB padding */ num_dw += 64; @@ -1597,32 +1620,16 @@ error_free: #if defined(CONFIG_DEBUG_FS) -extern void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager - *man); static int amdgpu_mm_dump_table(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *)m->private; unsigned ttm_pl = *(int *)node->info_ent->data; struct drm_device *dev = node->minor->dev; struct amdgpu_device *adev = dev->dev_private; - struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; - struct ttm_bo_global *glob = adev->mman.bdev.glob; + struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl]; struct drm_printer p = drm_seq_file_printer(m); - spin_lock(&glob->lru_lock); - drm_mm_print(mm, &p); - spin_unlock(&glob->lru_lock); - switch (ttm_pl) { - case TTM_PL_VRAM: - seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", - adev->mman.bdev.man[ttm_pl].size, - (u64)atomic64_read(&adev->vram_usage) >> 20, - (u64)atomic64_read(&adev->vram_vis_usage) >> 20); - break; - case TTM_PL_TT: - amdgpu_gtt_mgr_print(m, &adev->mman.bdev.man[TTM_PL_TT]); - break; - } + man->func->debug(man, &p); return 0; } @@ -1659,9 +1666,9 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, return result; spin_lock_irqsave(&adev->mmio_idx_lock, flags); - WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); - WREG32(mmMM_INDEX_HI, *pos >> 31); - value = RREG32(mmMM_DATA); + WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); + WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); + value = RREG32_NO_KIQ(mmMM_DATA); spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); r = put_user(value, (uint32_t *)buf); @@ -1677,10 +1684,50 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, return result; } +static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + if (*pos >= adev->mc.mc_vram_size) + return -ENXIO; + + while (size) { + unsigned long flags; + uint32_t value; + + if (*pos >= adev->mc.mc_vram_size) + return result; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + spin_lock_irqsave(&adev->mmio_idx_lock, flags); + WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); + WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); + WREG32_NO_KIQ(mmMM_DATA, value); + spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + static const struct file_operations amdgpu_ttm_vram_fops = { .owner = THIS_MODULE, .read = amdgpu_ttm_vram_read, - .llseek = default_llseek + .write = amdgpu_ttm_vram_write, + .llseek = default_llseek, }; #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS @@ -1732,6 +1779,53 @@ static const struct file_operations amdgpu_ttm_gtt_fops = { #endif +static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + int r; + uint64_t phys; + struct iommu_domain *dom; + + // always return 8 bytes + if (size != 8) + return -EINVAL; + + // only accept page addresses + if (*pos & 0xFFF) + return -EINVAL; + + dom = iommu_get_domain_for_dev(adev->dev); + if (dom) + phys = iommu_iova_to_phys(dom, *pos); + else + phys = *pos; + + r = copy_to_user(buf, &phys, 8); + if (r) + return -EFAULT; + + return 8; +} + +static const struct file_operations amdgpu_ttm_iova_fops = { + .owner = THIS_MODULE, + .read = amdgpu_iova_to_phys_read, + .llseek = default_llseek +}; + +static const struct { + char *name; + const struct file_operations *fops; + int domain; +} ttm_debugfs_entries[] = { + { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS + { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, +#endif + { "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM }, +}; + #endif static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) @@ -1742,22 +1836,21 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) struct drm_minor *minor = adev->ddev->primary; struct dentry *ent, *root = minor->debugfs_root; - ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, - adev, &amdgpu_ttm_vram_fops); - if (IS_ERR(ent)) - return PTR_ERR(ent); - i_size_write(ent->d_inode, adev->mc.mc_vram_size); - adev->mman.vram = ent; - -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, - adev, &amdgpu_ttm_gtt_fops); - if (IS_ERR(ent)) - return PTR_ERR(ent); - i_size_write(ent->d_inode, adev->mc.gart_size); - adev->mman.gtt = ent; + for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { + ent = debugfs_create_file( + ttm_debugfs_entries[count].name, + S_IFREG | S_IRUGO, root, + adev, + ttm_debugfs_entries[count].fops); + if (IS_ERR(ent)) + return PTR_ERR(ent); + if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) + i_size_write(ent->d_inode, adev->mc.mc_vram_size); + else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) + i_size_write(ent->d_inode, adev->mc.gart_size); + adev->mman.debugfs_entries[count] = ent; + } -#endif count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); #ifdef CONFIG_SWIOTLB @@ -1767,7 +1860,6 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); #else - return 0; #endif } @@ -1775,14 +1867,9 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) { #if defined(CONFIG_DEBUG_FS) + unsigned i; - debugfs_remove(adev->mman.vram); - adev->mman.vram = NULL; - -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS - debugfs_remove(adev->mman.gtt); - adev->mman.gtt = NULL; -#endif - + for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++) + debugfs_remove(adev->mman.debugfs_entries[i]); #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 0e2399f32de7..7abae6867339 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -24,6 +24,7 @@ #ifndef __AMDGPU_TTM_H__ #define __AMDGPU_TTM_H__ +#include "amdgpu.h" #include "gpu_scheduler.h" #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) @@ -45,8 +46,7 @@ struct amdgpu_mman { bool initialized; #if defined(CONFIG_DEBUG_FS) - struct dentry *vram; - struct dentry *gtt; + struct dentry *debugfs_entries[8]; #endif /* buffer handling */ @@ -62,10 +62,10 @@ extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func; extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func; bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem); -int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, - struct ttm_buffer_object *tbo, - const struct ttm_place *place, - struct ttm_mem_reg *mem); +uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man); + +uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); +uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man); int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, @@ -82,4 +82,20 @@ bool amdgpu_ttm_is_bound(struct ttm_tt *ttm); int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem); int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); +int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm); +int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, + uint32_t flags); +bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); +struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); +bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, + unsigned long end); +bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, + int *last_invalidated); +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm); +bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); +uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, + struct ttm_mem_reg *mem); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 36c763310df5..65649026b836 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -270,12 +270,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) else return AMDGPU_FW_LOAD_SMU; case CHIP_VEGA10: - if (!load_type) - return AMDGPU_FW_LOAD_DIRECT; - else - return AMDGPU_FW_LOAD_PSP; case CHIP_RAVEN: - if (load_type != 2) + if (!load_type) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; @@ -364,8 +360,6 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, int amdgpu_ucode_init_bo(struct amdgpu_device *adev) { struct amdgpu_bo **bo = &adev->firmware.fw_buf; - uint64_t fw_mc_addr; - void *fw_buf_ptr = NULL; uint64_t fw_offset = 0; int i, err; struct amdgpu_firmware_info *ucode = NULL; @@ -376,37 +370,39 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) return 0; } - err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, - amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, 0, bo); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); - goto failed; - } + if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) { + err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, + amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + NULL, NULL, 0, bo); + if (err) { + dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); + goto failed; + } - err = amdgpu_bo_reserve(*bo, false); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); - goto failed_reserve; - } + err = amdgpu_bo_reserve(*bo, false); + if (err) { + dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); + goto failed_reserve; + } - err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - &fw_mc_addr); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); - goto failed_pin; - } + err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, + &adev->firmware.fw_buf_mc); + if (err) { + dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); + goto failed_pin; + } - err = amdgpu_bo_kmap(*bo, &fw_buf_ptr); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); - goto failed_kmap; - } + err = amdgpu_bo_kmap(*bo, &adev->firmware.fw_buf_ptr); + if (err) { + dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); + goto failed_kmap; + } - amdgpu_bo_unreserve(*bo); + amdgpu_bo_unreserve(*bo); + } - memset(fw_buf_ptr, 0, adev->firmware.fw_size); + memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); /* * if SMU loaded firmware, it needn't add SMC, UVD, and VCE @@ -425,14 +421,14 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) ucode = &adev->firmware.ucode[i]; if (ucode->fw) { header = (const struct common_firmware_header *)ucode->fw->data; - amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset, - (void *)((uint8_t *)fw_buf_ptr + fw_offset)); + amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, + adev->firmware.fw_buf_ptr + fw_offset); if (i == AMDGPU_UCODE_ID_CP_MEC1 && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { const struct gfx_firmware_header_v1_0 *cp_hdr; cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; - amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset, - fw_buf_ptr + fw_offset); + amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, + adev->firmware.fw_buf_ptr + fw_offset); fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); } fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index aefecf6c1e7b..e8bd50cf9785 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -269,6 +269,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) { + int i; kfree(adev->uvd.saved_bo); amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); @@ -279,6 +280,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) amdgpu_ring_fini(&adev->uvd.ring); + for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) + amdgpu_ring_fini(&adev->uvd.ring_enc[i]); + release_firmware(adev->uvd.fw); return 0; @@ -410,10 +414,10 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); int r = 0; - mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); - if (mapping == NULL) { + r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); + if (r) { DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); - return -EINVAL; + return r; } if (!ctx->parser->adev->uvd.address_64_bit) { @@ -588,6 +592,10 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, } break; + case 8: /* MJPEG */ + min_dpb_size = 0; + break; + case 16: /* H265 */ image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; image_size = ALIGN(image_size, 256); @@ -733,10 +741,10 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); int r; - mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); - if (mapping == NULL) { + r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); + if (r) { DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); - return -EINVAL; + return r; } start = amdgpu_bo_gpu_offset(bo); @@ -913,10 +921,6 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) return -EINVAL; } - r = amdgpu_cs_sysvm_access_required(parser); - if (r) - return r; - ctx.parser = parser; ctx.buf_sizes = buf_sizes; ctx.ib_idx = ib_idx; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index c855366521ab..b46280c1279f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -559,6 +559,7 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; uint64_t addr; + int r; if (index == 0xffffffff) index = 0; @@ -567,11 +568,11 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32; addr += ((uint64_t)size) * ((uint64_t)index); - mapping = amdgpu_cs_find_mapping(p, addr, &bo); - if (mapping == NULL) { + r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping); + if (r) { DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n", addr, lo, hi, size, index); - return -EINVAL; + return r; } if ((addr + (uint64_t)size) > @@ -652,10 +653,6 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) p->job->vm = NULL; ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); - r = amdgpu_cs_sysvm_access_required(p); - if (r) - return r; - while (idx < ib->length_dw) { uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 8a081e162d13..ab05121b9272 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -46,14 +46,14 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev) * address within META_DATA init package to support SRIOV gfx preemption. */ -int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm) +int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct amdgpu_bo_va **bo_va) { - int r; - struct amdgpu_bo_va *bo_va; struct ww_acquire_ctx ticket; struct list_head list; struct amdgpu_bo_list_entry pd; struct ttm_validate_buffer csa_tv; + int r; INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&csa_tv.head); @@ -69,34 +69,33 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm) return r; } - bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj); - if (!bo_va) { + *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj); + if (!*bo_va) { ttm_eu_backoff_reservation(&ticket, &list); DRM_ERROR("failed to create bo_va for static CSA\n"); return -ENOMEM; } - r = amdgpu_vm_alloc_pts(adev, bo_va->vm, AMDGPU_CSA_VADDR, - AMDGPU_CSA_SIZE); + r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, AMDGPU_CSA_VADDR, + AMDGPU_CSA_SIZE); if (r) { DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r); - amdgpu_vm_bo_rmv(adev, bo_va); + amdgpu_vm_bo_rmv(adev, *bo_va); ttm_eu_backoff_reservation(&ticket, &list); return r; } - r = amdgpu_vm_bo_map(adev, bo_va, AMDGPU_CSA_VADDR, 0,AMDGPU_CSA_SIZE, - AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | - AMDGPU_PTE_EXECUTABLE); + r = amdgpu_vm_bo_map(adev, *bo_va, AMDGPU_CSA_VADDR, 0, AMDGPU_CSA_SIZE, + AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | + AMDGPU_PTE_EXECUTABLE); if (r) { DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r); - amdgpu_vm_bo_rmv(adev, bo_va); + amdgpu_vm_bo_rmv(adev, *bo_va); ttm_eu_backoff_reservation(&ticket, &list); return r; } - vm->csa_bo_va = bo_va; ttm_eu_backoff_reservation(&ticket, &list); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index e5b1baf387c1..afcfb8bcfb65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -90,7 +90,8 @@ static inline bool is_virtual_machine(void) struct amdgpu_vm; int amdgpu_allocate_static_csa(struct amdgpu_device *adev); -int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm); +int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct amdgpu_bo_va **bo_va); void amdgpu_virt_init_setting(struct amdgpu_device *adev); uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 9ce36652029e..bbcc67038203 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -27,12 +27,59 @@ */ #include <linux/dma-fence-array.h> #include <linux/interval_tree_generic.h> +#include <linux/idr.h> #include <drm/drmP.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h" #include "amdgpu_trace.h" /* + * PASID manager + * + * PASIDs are global address space identifiers that can be shared + * between the GPU, an IOMMU and the driver. VMs on different devices + * may use the same PASID if they share the same address + * space. Therefore PASIDs are allocated using a global IDA. VMs are + * looked up from the PASID per amdgpu_device. + */ +static DEFINE_IDA(amdgpu_vm_pasid_ida); + +/** + * amdgpu_vm_alloc_pasid - Allocate a PASID + * @bits: Maximum width of the PASID in bits, must be at least 1 + * + * Allocates a PASID of the given width while keeping smaller PASIDs + * available if possible. + * + * Returns a positive integer on success. Returns %-EINVAL if bits==0. + * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on + * memory allocation failure. + */ +int amdgpu_vm_alloc_pasid(unsigned int bits) +{ + int pasid = -EINVAL; + + for (bits = min(bits, 31U); bits > 0; bits--) { + pasid = ida_simple_get(&amdgpu_vm_pasid_ida, + 1U << (bits - 1), 1U << bits, + GFP_KERNEL); + if (pasid != -ENOSPC) + break; + } + + return pasid; +} + +/** + * amdgpu_vm_free_pasid - Free a PASID + * @pasid: PASID to free + */ +void amdgpu_vm_free_pasid(unsigned int pasid) +{ + ida_simple_remove(&amdgpu_vm_pasid_ida, pasid); +} + +/* * GPUVM * GPUVM is similar to the legacy gart on older asics, however * rather than there being a single global gart table @@ -140,7 +187,7 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, struct amdgpu_bo_list_entry *entry) { - entry->robj = vm->root.bo; + entry->robj = vm->root.base.bo; entry->priority = 0; entry->tv.bo = &entry->robj->tbo; entry->tv.shared = true; @@ -149,54 +196,6 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, } /** - * amdgpu_vm_validate_layer - validate a single page table level - * - * @parent: parent page table level - * @validate: callback to do the validation - * @param: parameter for the validation callback - * - * Validate the page table BOs on command submission if neccessary. - */ -static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, - int (*validate)(void *, struct amdgpu_bo *), - void *param, bool use_cpu_for_update) -{ - unsigned i; - int r; - - if (use_cpu_for_update) { - r = amdgpu_bo_kmap(parent->bo, NULL); - if (r) - return r; - } - - if (!parent->entries) - return 0; - - for (i = 0; i <= parent->last_entry_used; ++i) { - struct amdgpu_vm_pt *entry = &parent->entries[i]; - - if (!entry->bo) - continue; - - r = validate(param, entry->bo); - if (r) - return r; - - /* - * Recurse into the sub directory. This is harmless because we - * have only a maximum of 5 layers. - */ - r = amdgpu_vm_validate_level(entry, validate, param, - use_cpu_for_update); - if (r) - return r; - } - - return r; -} - -/** * amdgpu_vm_validate_pt_bos - validate the page table BOs * * @adev: amdgpu device pointer @@ -210,64 +209,70 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, int (*validate)(void *p, struct amdgpu_bo *bo), void *param) { - uint64_t num_evictions; - - /* We only need to validate the page tables - * if they aren't already valid. - */ - num_evictions = atomic64_read(&adev->num_evictions); - if (num_evictions == vm->last_eviction_counter) - return 0; + struct ttm_bo_global *glob = adev->mman.bdev.glob; + int r; - return amdgpu_vm_validate_level(&vm->root, validate, param, - vm->use_cpu_for_update); -} + spin_lock(&vm->status_lock); + while (!list_empty(&vm->evicted)) { + struct amdgpu_vm_bo_base *bo_base; + struct amdgpu_bo *bo; -/** - * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail - * - * @adev: amdgpu device instance - * @vm: vm providing the BOs - * - * Move the PT BOs to the tail of the LRU. - */ -static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent) -{ - unsigned i; + bo_base = list_first_entry(&vm->evicted, + struct amdgpu_vm_bo_base, + vm_status); + spin_unlock(&vm->status_lock); - if (!parent->entries) - return; + bo = bo_base->bo; + BUG_ON(!bo); + if (bo->parent) { + r = validate(param, bo); + if (r) + return r; - for (i = 0; i <= parent->last_entry_used; ++i) { - struct amdgpu_vm_pt *entry = &parent->entries[i]; + spin_lock(&glob->lru_lock); + ttm_bo_move_to_lru_tail(&bo->tbo); + if (bo->shadow) + ttm_bo_move_to_lru_tail(&bo->shadow->tbo); + spin_unlock(&glob->lru_lock); + } - if (!entry->bo) - continue; + if (bo->tbo.type == ttm_bo_type_kernel && + vm->use_cpu_for_update) { + r = amdgpu_bo_kmap(bo, NULL); + if (r) + return r; + } - ttm_bo_move_to_lru_tail(&entry->bo->tbo); - amdgpu_vm_move_level_in_lru(entry); + spin_lock(&vm->status_lock); + if (bo->tbo.type != ttm_bo_type_kernel) + list_move(&bo_base->vm_status, &vm->moved); + else + list_move(&bo_base->vm_status, &vm->relocated); } + spin_unlock(&vm->status_lock); + + return 0; } /** - * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail + * amdgpu_vm_ready - check VM is ready for updates * - * @adev: amdgpu device instance - * @vm: vm providing the BOs + * @vm: VM to check * - * Move the PT BOs to the tail of the LRU. + * Check if all VM PDs/PTs are ready for updates */ -void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, - struct amdgpu_vm *vm) +bool amdgpu_vm_ready(struct amdgpu_vm *vm) { - struct ttm_bo_global *glob = adev->mman.bdev.glob; + bool ready; - spin_lock(&glob->lru_lock); - amdgpu_vm_move_level_in_lru(&vm->root); - spin_unlock(&glob->lru_lock); + spin_lock(&vm->status_lock); + ready = list_empty(&vm->evicted); + spin_unlock(&vm->status_lock); + + return ready; } - /** +/** * amdgpu_vm_alloc_levels - allocate the PD/PT levels * * @adev: amdgpu_device pointer @@ -330,11 +335,11 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, /* walk over the address space and allocate the page tables */ for (pt_idx = from; pt_idx <= to; ++pt_idx) { - struct reservation_object *resv = vm->root.bo->tbo.resv; + struct reservation_object *resv = vm->root.base.bo->tbo.resv; struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; struct amdgpu_bo *pt; - if (!entry->bo) { + if (!entry->base.bo) { r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, level), AMDGPU_GPU_PAGE_SIZE, true, @@ -355,11 +360,15 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, /* Keep a reference to the root directory to avoid * freeing them up in the wrong order. */ - pt->parent = amdgpu_bo_ref(vm->root.bo); - - entry->bo = pt; + pt->parent = amdgpu_bo_ref(parent->base.bo); + + entry->base.vm = vm; + entry->base.bo = pt; + list_add_tail(&entry->base.bo_list, &pt->va); + spin_lock(&vm->status_lock); + list_add(&entry->base.vm_status, &vm->relocated); + spin_unlock(&vm->status_lock); entry->addr = 0; - entry->huge_page = false; } if (level < adev->vm_manager.num_level) { @@ -899,8 +908,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, { struct amdgpu_bo_va *bo_va; - list_for_each_entry(bo_va, &bo->va, bo_list) { - if (bo_va->vm == vm) { + list_for_each_entry(bo_va, &bo->va, base.bo_list) { + if (bo_va->base.vm == vm) { return bo_va; } } @@ -1025,7 +1034,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, int r; amdgpu_sync_create(&sync); - amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.resv, owner); + amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner); r = amdgpu_sync_wait(&sync, true); amdgpu_sync_free(&sync); @@ -1044,18 +1053,17 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, */ static int amdgpu_vm_update_level(struct amdgpu_device *adev, struct amdgpu_vm *vm, - struct amdgpu_vm_pt *parent, - unsigned level) + struct amdgpu_vm_pt *parent) { struct amdgpu_bo *shadow; struct amdgpu_ring *ring = NULL; uint64_t pd_addr, shadow_addr = 0; - uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; unsigned count = 0, pt_idx, ndw = 0; struct amdgpu_job *job; struct amdgpu_pte_update_params params; struct dma_fence *fence = NULL; + uint32_t incr; int r; @@ -1064,21 +1072,16 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, memset(¶ms, 0, sizeof(params)); params.adev = adev; - shadow = parent->bo->shadow; + shadow = parent->base.bo->shadow; if (vm->use_cpu_for_update) { - pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo); + pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); if (unlikely(r)) return r; params.func = amdgpu_vm_cpu_set_ptes; } else { - if (shadow) { - r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); - if (r) - return r; - } ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); @@ -1088,7 +1091,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, /* assume the worst case */ ndw += parent->last_entry_used * 6; - pd_addr = amdgpu_bo_gpu_offset(parent->bo); + pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); if (shadow) { shadow_addr = amdgpu_bo_gpu_offset(shadow); @@ -1108,30 +1111,28 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, /* walk over the address space and update the directory */ for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { - struct amdgpu_bo *bo = parent->entries[pt_idx].bo; + struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; + struct amdgpu_bo *bo = entry->base.bo; uint64_t pde, pt; if (bo == NULL) continue; - if (bo->shadow) { - struct amdgpu_bo *pt_shadow = bo->shadow; - - r = amdgpu_ttm_bind(&pt_shadow->tbo, - &pt_shadow->tbo.mem); - if (r) - return r; - } + spin_lock(&vm->status_lock); + list_del_init(&entry->base.vm_status); + spin_unlock(&vm->status_lock); pt = amdgpu_bo_gpu_offset(bo); pt = amdgpu_gart_get_vm_pde(adev, pt); - if (parent->entries[pt_idx].addr == pt || - parent->entries[pt_idx].huge_page) + /* Don't update huge pages here */ + if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) || + parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID)) continue; - parent->entries[pt_idx].addr = pt; + parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID; pde = pd_addr + pt_idx * 8; + incr = amdgpu_bo_size(bo); if (((last_pde + 8 * count) != pde) || ((last_pt + incr * count) != pt) || (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { @@ -1159,7 +1160,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, } if (count) { - if (vm->root.bo->shadow) + if (vm->root.base.bo->shadow) params.func(¶ms, last_shadow, last_pt, count, incr, AMDGPU_PTE_VALID); @@ -1172,7 +1173,8 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, amdgpu_job_free(job); } else { amdgpu_ring_pad_ib(ring, params.ib); - amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv, + amdgpu_sync_resv(adev, &job->sync, + parent->base.bo->tbo.resv, AMDGPU_FENCE_OWNER_VM); if (shadow) amdgpu_sync_resv(adev, &job->sync, @@ -1185,26 +1187,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, if (r) goto error_free; - amdgpu_bo_fence(parent->bo, fence, true); - dma_fence_put(vm->last_dir_update); - vm->last_dir_update = dma_fence_get(fence); - dma_fence_put(fence); + amdgpu_bo_fence(parent->base.bo, fence, true); + dma_fence_put(vm->last_update); + vm->last_update = fence; } } - /* - * Recurse into the subdirectories. This recursion is harmless because - * we only have a maximum of 5 layers. - */ - for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { - struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; - - if (!entry->bo) - continue; - - r = amdgpu_vm_update_level(adev, vm, entry, level + 1); - if (r) - return r; - } return 0; @@ -1220,7 +1207,8 @@ error_free: * * Mark all PD level as invalid after an error. */ -static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent) +static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm, + struct amdgpu_vm_pt *parent) { unsigned pt_idx; @@ -1231,11 +1219,15 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent) for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; - if (!entry->bo) + if (!entry->base.bo) continue; entry->addr = ~0ULL; - amdgpu_vm_invalidate_level(entry); + spin_lock(&vm->status_lock); + if (list_empty(&entry->base.vm_status)) + list_add(&entry->base.vm_status, &vm->relocated); + spin_unlock(&vm->status_lock); + amdgpu_vm_invalidate_level(vm, entry); } } @@ -1253,9 +1245,38 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, { int r; - r = amdgpu_vm_update_level(adev, vm, &vm->root, 0); - if (r) - amdgpu_vm_invalidate_level(&vm->root); + spin_lock(&vm->status_lock); + while (!list_empty(&vm->relocated)) { + struct amdgpu_vm_bo_base *bo_base; + struct amdgpu_bo *bo; + + bo_base = list_first_entry(&vm->relocated, + struct amdgpu_vm_bo_base, + vm_status); + spin_unlock(&vm->status_lock); + + bo = bo_base->bo->parent; + if (bo) { + struct amdgpu_vm_bo_base *parent; + struct amdgpu_vm_pt *pt; + + parent = list_first_entry(&bo->va, + struct amdgpu_vm_bo_base, + bo_list); + pt = container_of(parent, struct amdgpu_vm_pt, base); + + r = amdgpu_vm_update_level(adev, vm, pt); + if (r) { + amdgpu_vm_invalidate_level(vm, &vm->root); + return r; + } + spin_lock(&vm->status_lock); + } else { + spin_lock(&vm->status_lock); + list_del_init(&bo_base->vm_status); + } + } + spin_unlock(&vm->status_lock); if (vm->use_cpu_for_update) { /* Flush HDP */ @@ -1286,7 +1307,7 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, *entry = &p->vm->root; while ((*entry)->entries) { idx = addr >> (p->adev->vm_manager.block_size * level--); - idx %= amdgpu_bo_size((*entry)->bo) / 8; + idx %= amdgpu_bo_size((*entry)->base.bo) / 8; *parent = *entry; *entry = &(*entry)->entries[idx]; } @@ -1307,55 +1328,62 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, * * Check if we can update the PD with a huge page. */ -static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, - struct amdgpu_vm_pt *entry, - struct amdgpu_vm_pt *parent, - unsigned nptes, uint64_t dst, - uint64_t flags) +static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, + struct amdgpu_vm_pt *entry, + struct amdgpu_vm_pt *parent, + unsigned nptes, uint64_t dst, + uint64_t flags) { bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes); uint64_t pd_addr, pde; - int r; /* In the case of a mixed PT the PDE must point to it*/ if (p->adev->asic_type < CHIP_VEGA10 || nptes != AMDGPU_VM_PTE_COUNT(p->adev) || - p->func == amdgpu_vm_do_copy_ptes || + p->src || !(flags & AMDGPU_PTE_VALID)) { - dst = amdgpu_bo_gpu_offset(entry->bo); + dst = amdgpu_bo_gpu_offset(entry->base.bo); dst = amdgpu_gart_get_vm_pde(p->adev, dst); flags = AMDGPU_PTE_VALID; } else { + /* Set the huge page flag to stop scanning at this PDE */ flags |= AMDGPU_PDE_PTE; } - if (entry->addr == dst && - entry->huge_page == !!(flags & AMDGPU_PDE_PTE)) - return 0; + if (entry->addr == (dst | flags)) + return; - entry->addr = dst; - entry->huge_page = !!(flags & AMDGPU_PDE_PTE); + entry->addr = (dst | flags); if (use_cpu_update) { - r = amdgpu_bo_kmap(parent->bo, (void *)&pd_addr); - if (r) - return r; + /* In case a huge page is replaced with a system + * memory mapping, p->pages_addr != NULL and + * amdgpu_vm_cpu_set_ptes would try to translate dst + * through amdgpu_vm_map_gart. But dst is already a + * GPU address (of the page table). Disable + * amdgpu_vm_map_gart temporarily. + */ + dma_addr_t *tmp; + + tmp = p->pages_addr; + p->pages_addr = NULL; + pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); pde = pd_addr + (entry - parent->entries) * 8; amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags); + + p->pages_addr = tmp; } else { - if (parent->bo->shadow) { - pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow); + if (parent->base.bo->shadow) { + pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow); pde = pd_addr + (entry - parent->entries) * 8; amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); } - pd_addr = amdgpu_bo_gpu_offset(parent->bo); + pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); pde = pd_addr + (entry - parent->entries) * 8; amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); } - - return 0; } /** @@ -1382,7 +1410,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, struct amdgpu_bo *pt; unsigned nptes; bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); - int r; /* walk over the address space and update the page tables */ for (addr = start; addr < end; addr += nptes, @@ -1398,15 +1425,13 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, else nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); - r = amdgpu_vm_handle_huge_pages(params, entry, parent, - nptes, dst, flags); - if (r) - return r; - - if (entry->huge_page) + amdgpu_vm_handle_huge_pages(params, entry, parent, + nptes, dst, flags); + /* We don't need to update PTEs for huge pages */ + if (entry->addr & AMDGPU_PDE_PTE) continue; - pt = entry->bo; + pt = entry->base.bo; if (use_cpu_update) { pe_start = (unsigned long)amdgpu_bo_kptr(pt); } else { @@ -1442,8 +1467,6 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, uint64_t start, uint64_t end, uint64_t dst, uint64_t flags) { - int r; - /** * The MC L1 TLB supports variable sized pages, based on a fragment * field in the PTE. When this field is set to a non-zero value, page @@ -1462,41 +1485,38 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, * Userspace can support this by aligning virtual base address and * allocation size to the fragment size. */ - - /* SI and newer are optimized for 64KB */ - unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev); - uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag); - uint64_t frag_align = 1 << pages_per_frag; - - uint64_t frag_start = ALIGN(start, frag_align); - uint64_t frag_end = end & ~(frag_align - 1); + unsigned max_frag = params->adev->vm_manager.fragment_size; + int r; /* system pages are non continuously */ - if (params->src || !(flags & AMDGPU_PTE_VALID) || - (frag_start >= frag_end)) + if (params->src || !(flags & AMDGPU_PTE_VALID)) return amdgpu_vm_update_ptes(params, start, end, dst, flags); - /* handle the 4K area at the beginning */ - if (start != frag_start) { - r = amdgpu_vm_update_ptes(params, start, frag_start, - dst, flags); + while (start != end) { + uint64_t frag_flags, frag_end; + unsigned frag; + + /* This intentionally wraps around if no bit is set */ + frag = min((unsigned)ffs(start) - 1, + (unsigned)fls64(end - start) - 1); + if (frag >= max_frag) { + frag_flags = AMDGPU_PTE_FRAG(max_frag); + frag_end = end & ~((1ULL << max_frag) - 1); + } else { + frag_flags = AMDGPU_PTE_FRAG(frag); + frag_end = start + (1 << frag); + } + + r = amdgpu_vm_update_ptes(params, start, frag_end, dst, + flags | frag_flags); if (r) return r; - dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; - } - - /* handle the area in the middle */ - r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, - flags | frag_flags); - if (r) - return r; - /* handle the 4K area at the end */ - if (frag_end != end) { - dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; - r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); + dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE; + start = frag_end; } - return r; + + return 0; } /** @@ -1504,7 +1524,6 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, * * @adev: amdgpu_device pointer * @exclusive: fence we need to sync to - * @src: address where to copy page table entries from * @pages_addr: DMA addresses to use for mapping * @vm: requested vm * @start: start of mapped range @@ -1518,7 +1537,6 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, */ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, struct dma_fence *exclusive, - uint64_t src, dma_addr_t *pages_addr, struct amdgpu_vm *vm, uint64_t start, uint64_t last, @@ -1536,7 +1554,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, memset(¶ms, 0, sizeof(params)); params.adev = adev; params.vm = vm; - params.src = src; /* sync to everything on unmapping */ if (!(flags & AMDGPU_PTE_VALID)) @@ -1565,10 +1582,12 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, nptes = last - start + 1; /* - * reserve space for one command every (1 << BLOCK_SIZE) + * reserve space for two commands every (1 << BLOCK_SIZE) * entries or 2k dwords (whatever is smaller) + * + * The second command is for the shadow pagetables. */ - ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; + ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; /* padding, etc. */ ndw = 64; @@ -1576,15 +1595,9 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, /* one PDE write for each huge page */ ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6; - if (src) { - /* only copy commands needed */ - ndw += ncmds * 7; - - params.func = amdgpu_vm_do_copy_ptes; - - } else if (pages_addr) { + if (pages_addr) { /* copy commands needed */ - ndw += ncmds * 7; + ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; /* and also PTEs */ ndw += nptes * 2; @@ -1593,10 +1606,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, } else { /* set page commands needed */ - ndw += ncmds * 10; + ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw; - /* two extra commands for begin/end of fragment */ - ndw += 2 * 10; + /* extra commands for begin/end fragments */ + ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw + * adev->vm_manager.fragment_size; params.func = amdgpu_vm_do_set_ptes; } @@ -1607,7 +1621,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, params.ib = &job->ibs[0]; - if (!src && pages_addr) { + if (pages_addr) { uint64_t *pte; unsigned i; @@ -1628,12 +1642,12 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (r) goto error_free; - r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, + r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, owner); if (r) goto error_free; - r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); + r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); if (r) goto error_free; @@ -1648,14 +1662,14 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (r) goto error_free; - amdgpu_bo_fence(vm->root.bo, f, true); + amdgpu_bo_fence(vm->root.base.bo, f, true); dma_fence_put(*fence); *fence = f; return 0; error_free: amdgpu_job_free(job); - amdgpu_vm_invalidate_level(&vm->root); + amdgpu_vm_invalidate_level(vm, &vm->root); return r; } @@ -1664,7 +1678,6 @@ error_free: * * @adev: amdgpu_device pointer * @exclusive: fence we need to sync to - * @gtt_flags: flags as they are used for GTT * @pages_addr: DMA addresses to use for mapping * @vm: requested vm * @mapping: mapped range and flags to use for the update @@ -1678,7 +1691,6 @@ error_free: */ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, struct dma_fence *exclusive, - uint64_t gtt_flags, dma_addr_t *pages_addr, struct amdgpu_vm *vm, struct amdgpu_bo_va_mapping *mapping, @@ -1686,7 +1698,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, struct drm_mm_node *nodes, struct dma_fence **fence) { - uint64_t pfn, src = 0, start = mapping->start; + uint64_t pfn, start = mapping->start; int r; /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here @@ -1733,11 +1745,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, } if (pages_addr) { - if (flags == gtt_flags) - src = adev->gart.table_addr + - (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; - else - max_entries = min(max_entries, 16ull * 1024ull); + max_entries = min(max_entries, 16ull * 1024ull); addr = 0; } else if (flags & AMDGPU_PTE_VALID) { addr += adev->vm_manager.vram_base_offset; @@ -1745,8 +1753,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, addr += pfn << PAGE_SHIFT; last = min((uint64_t)mapping->last, start + max_entries - 1); - r = amdgpu_vm_bo_update_mapping(adev, exclusive, - src, pages_addr, vm, + r = amdgpu_vm_bo_update_mapping(adev, exclusive, pages_addr, vm, start, last, flags, addr, fence); if (r) @@ -1778,75 +1785,75 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, bool clear) { - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_bo *bo = bo_va->base.bo; + struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_bo_va_mapping *mapping; dma_addr_t *pages_addr = NULL; - uint64_t gtt_flags, flags; struct ttm_mem_reg *mem; struct drm_mm_node *nodes; - struct dma_fence *exclusive; + struct dma_fence *exclusive, **last_update; + uint64_t flags; int r; - if (clear || !bo_va->bo) { + if (clear || !bo_va->base.bo) { mem = NULL; nodes = NULL; exclusive = NULL; } else { struct ttm_dma_tt *ttm; - mem = &bo_va->bo->tbo.mem; + mem = &bo_va->base.bo->tbo.mem; nodes = mem->mm_node; if (mem->mem_type == TTM_PL_TT) { - ttm = container_of(bo_va->bo->tbo.ttm, struct - ttm_dma_tt, ttm); + ttm = container_of(bo_va->base.bo->tbo.ttm, + struct ttm_dma_tt, ttm); pages_addr = ttm->dma_address; } - exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); + exclusive = reservation_object_get_excl(bo->tbo.resv); } - if (bo_va->bo) { - flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); - gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && - adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? - flags : 0; - } else { + if (bo) + flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); + else flags = 0x0; - gtt_flags = ~0x0; - } - spin_lock(&vm->status_lock); - if (!list_empty(&bo_va->vm_status)) + if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) + last_update = &vm->last_update; + else + last_update = &bo_va->last_pt_update; + + if (!clear && bo_va->base.moved) { + bo_va->base.moved = false; list_splice_init(&bo_va->valids, &bo_va->invalids); - spin_unlock(&vm->status_lock); + + } else if (bo_va->cleared != clear) { + list_splice_init(&bo_va->valids, &bo_va->invalids); + } list_for_each_entry(mapping, &bo_va->invalids, list) { - r = amdgpu_vm_bo_split_mapping(adev, exclusive, - gtt_flags, pages_addr, vm, + r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, mapping, flags, nodes, - &bo_va->last_pt_update); + last_update); if (r) return r; } - if (trace_amdgpu_vm_bo_mapping_enabled()) { - list_for_each_entry(mapping, &bo_va->valids, list) - trace_amdgpu_vm_bo_mapping(mapping); - - list_for_each_entry(mapping, &bo_va->invalids, list) - trace_amdgpu_vm_bo_mapping(mapping); + if (vm->use_cpu_for_update) { + /* Flush HDP */ + mb(); + amdgpu_gart_flush_gpu_tlb(adev, 0); } spin_lock(&vm->status_lock); - list_splice_init(&bo_va->invalids, &bo_va->valids); - list_del_init(&bo_va->vm_status); - if (clear) - list_add(&bo_va->vm_status, &vm->cleared); + list_del_init(&bo_va->base.vm_status); spin_unlock(&vm->status_lock); - if (vm->use_cpu_for_update) { - /* Flush HDP */ - mb(); - amdgpu_gart_flush_gpu_tlb(adev, 0); + list_splice_init(&bo_va->invalids, &bo_va->valids); + bo_va->cleared = clear; + + if (trace_amdgpu_vm_bo_mapping_enabled()) { + list_for_each_entry(mapping, &bo_va->valids, list) + trace_amdgpu_vm_bo_mapping(mapping); } return 0; @@ -1954,7 +1961,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, */ static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct reservation_object *resv = vm->root.bo->tbo.resv; + struct reservation_object *resv = vm->root.base.bo->tbo.resv; struct dma_fence *excl, **shared; unsigned i, shared_count; int r; @@ -2012,7 +2019,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, if (vm->pte_support_ats) init_pte_value = AMDGPU_PTE_SYSTEM; - r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm, + r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, mapping->start, mapping->last, init_pte_value, 0, &f); amdgpu_vm_free_mapping(adev, vm, mapping, f); @@ -2034,29 +2041,35 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, } /** - * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT + * amdgpu_vm_handle_moved - handle moved BOs in the PT * * @adev: amdgpu_device pointer * @vm: requested vm + * @sync: sync object to add fences to * - * Make sure all invalidated BOs are cleared in the PT. + * Make sure all BOs which are moved are updated in the PTs. * Returns 0 for success. * - * PTs have to be reserved and mutex must be locked! + * PTs have to be reserved! */ -int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, - struct amdgpu_vm *vm, struct amdgpu_sync *sync) +int amdgpu_vm_handle_moved(struct amdgpu_device *adev, + struct amdgpu_vm *vm) { - struct amdgpu_bo_va *bo_va = NULL; + bool clear; int r = 0; spin_lock(&vm->status_lock); - while (!list_empty(&vm->invalidated)) { - bo_va = list_first_entry(&vm->invalidated, - struct amdgpu_bo_va, vm_status); + while (!list_empty(&vm->moved)) { + struct amdgpu_bo_va *bo_va; + + bo_va = list_first_entry(&vm->moved, + struct amdgpu_bo_va, base.vm_status); spin_unlock(&vm->status_lock); - r = amdgpu_vm_bo_update(adev, bo_va, true); + /* Per VM BOs never need to bo cleared in the page tables */ + clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv; + + r = amdgpu_vm_bo_update(adev, bo_va, clear); if (r) return r; @@ -2064,9 +2077,6 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, } spin_unlock(&vm->status_lock); - if (bo_va) - r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); - return r; } @@ -2093,20 +2103,54 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, if (bo_va == NULL) { return NULL; } - bo_va->vm = vm; - bo_va->bo = bo; + bo_va->base.vm = vm; + bo_va->base.bo = bo; + INIT_LIST_HEAD(&bo_va->base.bo_list); + INIT_LIST_HEAD(&bo_va->base.vm_status); + bo_va->ref_count = 1; - INIT_LIST_HEAD(&bo_va->bo_list); INIT_LIST_HEAD(&bo_va->valids); INIT_LIST_HEAD(&bo_va->invalids); - INIT_LIST_HEAD(&bo_va->vm_status); if (bo) - list_add_tail(&bo_va->bo_list, &bo->va); + list_add_tail(&bo_va->base.bo_list, &bo->va); return bo_va; } + +/** + * amdgpu_vm_bo_insert_mapping - insert a new mapping + * + * @adev: amdgpu_device pointer + * @bo_va: bo_va to store the address + * @mapping: the mapping to insert + * + * Insert a new mapping into all structures. + */ +static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + struct amdgpu_bo_va_mapping *mapping) +{ + struct amdgpu_vm *vm = bo_va->base.vm; + struct amdgpu_bo *bo = bo_va->base.bo; + + mapping->bo_va = bo_va; + list_add(&mapping->list, &bo_va->invalids); + amdgpu_vm_it_insert(mapping, &vm->va); + + if (mapping->flags & AMDGPU_PTE_PRT) + amdgpu_vm_prt_get(adev); + + if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { + spin_lock(&vm->status_lock); + if (list_empty(&bo_va->base.vm_status)) + list_add(&bo_va->base.vm_status, &vm->moved); + spin_unlock(&vm->status_lock); + } + trace_amdgpu_vm_bo_map(bo_va, mapping); +} + /** * amdgpu_vm_bo_map - map bo inside a vm * @@ -2127,7 +2171,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, uint64_t size, uint64_t flags) { struct amdgpu_bo_va_mapping *mapping, *tmp; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_bo *bo = bo_va->base.bo; + struct amdgpu_vm *vm = bo_va->base.vm; uint64_t eaddr; /* validate the parameters */ @@ -2138,7 +2183,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, /* make sure object fit at this offset */ eaddr = saddr + size - 1; if (saddr >= eaddr || - (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) + (bo && offset + size > amdgpu_bo_size(bo))) return -EINVAL; saddr /= AMDGPU_GPU_PAGE_SIZE; @@ -2148,7 +2193,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, if (tmp) { /* bo and tmp overlap, invalid addr */ dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " - "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr, + "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, tmp->start, tmp->last + 1); return -EINVAL; } @@ -2157,17 +2202,12 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, if (!mapping) return -ENOMEM; - INIT_LIST_HEAD(&mapping->list); mapping->start = saddr; mapping->last = eaddr; mapping->offset = offset; mapping->flags = flags; - list_add(&mapping->list, &bo_va->invalids); - amdgpu_vm_it_insert(mapping, &vm->va); - - if (flags & AMDGPU_PTE_PRT) - amdgpu_vm_prt_get(adev); + amdgpu_vm_bo_insert_map(adev, bo_va, mapping); return 0; } @@ -2193,7 +2233,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, uint64_t size, uint64_t flags) { struct amdgpu_bo_va_mapping *mapping; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_bo *bo = bo_va->base.bo; uint64_t eaddr; int r; @@ -2205,7 +2245,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, /* make sure object fit at this offset */ eaddr = saddr + size - 1; if (saddr >= eaddr || - (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) + (bo && offset + size > amdgpu_bo_size(bo))) return -EINVAL; /* Allocate all the needed memory */ @@ -2213,7 +2253,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, if (!mapping) return -ENOMEM; - r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); + r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); if (r) { kfree(mapping); return r; @@ -2227,11 +2267,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, mapping->offset = offset; mapping->flags = flags; - list_add(&mapping->list, &bo_va->invalids); - amdgpu_vm_it_insert(mapping, &vm->va); - - if (flags & AMDGPU_PTE_PRT) - amdgpu_vm_prt_get(adev); + amdgpu_vm_bo_insert_map(adev, bo_va, mapping); return 0; } @@ -2253,7 +2289,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, uint64_t saddr) { struct amdgpu_bo_va_mapping *mapping; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_vm *vm = bo_va->base.vm; bool valid = true; saddr /= AMDGPU_GPU_PAGE_SIZE; @@ -2277,6 +2313,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, list_del(&mapping->list); amdgpu_vm_it_remove(mapping, &vm->va); + mapping->bo_va = NULL; trace_amdgpu_vm_bo_unmap(bo_va, mapping); if (valid) @@ -2362,6 +2399,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, if (tmp->last > eaddr) tmp->last = eaddr; + tmp->bo_va = NULL; list_add(&tmp->list, &vm->freed); trace_amdgpu_vm_bo_unmap(NULL, tmp); } @@ -2388,6 +2426,19 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, } /** + * amdgpu_vm_bo_lookup_mapping - find mapping by address + * + * @vm: the requested VM + * + * Find a mapping by it's address. + */ +struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, + uint64_t addr) +{ + return amdgpu_vm_it_iter_first(&vm->va, addr, addr); +} + +/** * amdgpu_vm_bo_rmv - remove a bo to a specific vm * * @adev: amdgpu_device pointer @@ -2401,17 +2452,18 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va) { struct amdgpu_bo_va_mapping *mapping, *next; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_vm *vm = bo_va->base.vm; - list_del(&bo_va->bo_list); + list_del(&bo_va->base.bo_list); spin_lock(&vm->status_lock); - list_del(&bo_va->vm_status); + list_del(&bo_va->base.vm_status); spin_unlock(&vm->status_lock); list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { list_del(&mapping->list); amdgpu_vm_it_remove(mapping, &vm->va); + mapping->bo_va = NULL; trace_amdgpu_vm_bo_unmap(bo_va, mapping); list_add(&mapping->list, &vm->freed); } @@ -2436,15 +2488,37 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, * Mark @bo as invalid. */ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, - struct amdgpu_bo *bo) + struct amdgpu_bo *bo, bool evicted) { - struct amdgpu_bo_va *bo_va; + struct amdgpu_vm_bo_base *bo_base; + + list_for_each_entry(bo_base, &bo->va, bo_list) { + struct amdgpu_vm *vm = bo_base->vm; + + bo_base->moved = true; + if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { + spin_lock(&bo_base->vm->status_lock); + if (bo->tbo.type == ttm_bo_type_kernel) + list_move(&bo_base->vm_status, &vm->evicted); + else + list_move_tail(&bo_base->vm_status, + &vm->evicted); + spin_unlock(&bo_base->vm->status_lock); + continue; + } + + if (bo->tbo.type == ttm_bo_type_kernel) { + spin_lock(&bo_base->vm->status_lock); + if (list_empty(&bo_base->vm_status)) + list_add(&bo_base->vm_status, &vm->relocated); + spin_unlock(&bo_base->vm->status_lock); + continue; + } - list_for_each_entry(bo_va, &bo->va, bo_list) { - spin_lock(&bo_va->vm->status_lock); - if (list_empty(&bo_va->vm_status)) - list_add(&bo_va->vm_status, &bo_va->vm->invalidated); - spin_unlock(&bo_va->vm->status_lock); + spin_lock(&bo_base->vm->status_lock); + if (list_empty(&bo_base->vm_status)) + list_add(&bo_base->vm_status, &vm->moved); + spin_unlock(&bo_base->vm->status_lock); } } @@ -2462,12 +2536,26 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) } /** - * amdgpu_vm_adjust_size - adjust vm size and block size + * amdgpu_vm_set_fragment_size - adjust fragment size in PTE + * + * @adev: amdgpu_device pointer + * @fragment_size_default: the default fragment size if it's set auto + */ +void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_size_default) +{ + if (amdgpu_vm_fragment_size == -1) + adev->vm_manager.fragment_size = fragment_size_default; + else + adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; +} + +/** + * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size * * @adev: amdgpu_device pointer * @vm_size: the default vm size if it's set auto */ -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_t fragment_size_default) { /* adjust vm size firstly */ if (amdgpu_vm_size == -1) @@ -2482,8 +2570,11 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) else adev->vm_manager.block_size = amdgpu_vm_block_size; - DRM_INFO("vm size is %llu GB, block size is %u-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); + amdgpu_vm_set_fragment_size(adev, fragment_size_default); + + DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", + adev->vm_manager.vm_size, adev->vm_manager.block_size, + adev->vm_manager.fragment_size); } /** @@ -2496,7 +2587,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) * Init @vm fields. */ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, - int vm_context) + int vm_context, unsigned int pasid) { const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, AMDGPU_VM_PTE_COUNT(adev) * 8); @@ -2507,13 +2598,14 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 flags; uint64_t init_pde_value = 0; - vm->va = RB_ROOT; + vm->va = RB_ROOT_CACHED; vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) vm->reserved_vmid[i] = NULL; spin_lock_init(&vm->status_lock); - INIT_LIST_HEAD(&vm->invalidated); - INIT_LIST_HEAD(&vm->cleared); + INIT_LIST_HEAD(&vm->evicted); + INIT_LIST_HEAD(&vm->relocated); + INIT_LIST_HEAD(&vm->moved); INIT_LIST_HEAD(&vm->freed); /* create scheduler entity for page table updates */ @@ -2544,7 +2636,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->use_cpu_for_update ? "CPU" : "SDMA"); WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), "CPU update of VM recommended only for large BAR system\n"); - vm->last_dir_update = NULL; + vm->last_update = NULL; flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED; @@ -2557,30 +2649,46 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, AMDGPU_GEM_DOMAIN_VRAM, flags, - NULL, NULL, init_pde_value, &vm->root.bo); + NULL, NULL, init_pde_value, &vm->root.base.bo); if (r) goto error_free_sched_entity; - r = amdgpu_bo_reserve(vm->root.bo, false); - if (r) - goto error_free_root; - - vm->last_eviction_counter = atomic64_read(&adev->num_evictions); + vm->root.base.vm = vm; + list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va); + INIT_LIST_HEAD(&vm->root.base.vm_status); if (vm->use_cpu_for_update) { - r = amdgpu_bo_kmap(vm->root.bo, NULL); + r = amdgpu_bo_reserve(vm->root.base.bo, false); + if (r) + goto error_free_root; + + r = amdgpu_bo_kmap(vm->root.base.bo, NULL); + amdgpu_bo_unreserve(vm->root.base.bo); if (r) goto error_free_root; } - amdgpu_bo_unreserve(vm->root.bo); + if (pasid) { + unsigned long flags; + + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, + GFP_ATOMIC); + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); + if (r < 0) + goto error_free_root; + + vm->pasid = pasid; + } + + INIT_KFIFO(vm->faults); return 0; error_free_root: - amdgpu_bo_unref(&vm->root.bo->shadow); - amdgpu_bo_unref(&vm->root.bo); - vm->root.bo = NULL; + amdgpu_bo_unref(&vm->root.base.bo->shadow); + amdgpu_bo_unref(&vm->root.base.bo); + vm->root.base.bo = NULL; error_free_sched_entity: amd_sched_entity_fini(&ring->sched, &vm->entity); @@ -2599,9 +2707,11 @@ static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) { unsigned i; - if (level->bo) { - amdgpu_bo_unref(&level->bo->shadow); - amdgpu_bo_unref(&level->bo); + if (level->base.bo) { + list_del(&level->base.bo_list); + list_del(&level->base.vm_status); + amdgpu_bo_unref(&level->base.bo->shadow); + amdgpu_bo_unref(&level->base.bo); } if (level->entries) @@ -2624,14 +2734,28 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct amdgpu_bo_va_mapping *mapping, *tmp; bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; + u64 fault; int i; + /* Clear pending page faults from IH when the VM is destroyed */ + while (kfifo_get(&vm->faults, &fault)) + amdgpu_ih_clear_fault(adev, fault); + + if (vm->pasid) { + unsigned long flags; + + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); + } + amd_sched_entity_fini(vm->entity.sched, &vm->entity); - if (!RB_EMPTY_ROOT(&vm->va)) { + if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { dev_err(adev->dev, "still active bo inside vm\n"); } - rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { + rbtree_postorder_for_each_entry_safe(mapping, tmp, + &vm->va.rb_root, rb) { list_del(&mapping->list); amdgpu_vm_it_remove(mapping, &vm->va); kfree(mapping); @@ -2647,7 +2771,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) } amdgpu_vm_free_levels(&vm->root); - dma_fence_put(vm->last_dir_update); + dma_fence_put(vm->last_update); for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) amdgpu_vm_free_reserved_vmid(adev, vm, i); } @@ -2705,6 +2829,8 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) adev->vm_manager.vm_update_mode = 0; #endif + idr_init(&adev->vm_manager.pasid_idr); + spin_lock_init(&adev->vm_manager.pasid_lock); } /** @@ -2718,6 +2844,9 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) { unsigned i, j; + WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); + idr_destroy(&adev->vm_manager.pasid_idr); + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[i]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 217ecba8f4cc..0af090667dfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -25,6 +25,7 @@ #define __AMDGPU_VM_H__ #include <linux/rbtree.h> +#include <linux/idr.h> #include "gpu_scheduler.h" #include "amdgpu_sync.h" @@ -50,11 +51,6 @@ struct amdgpu_bo_list_entry; /* PTBs (Page Table Blocks) need to be aligned to 32K */ #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 -/* LOG2 number of continuous pages for the fragment field */ -#define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \ - ((adev)->asic_type < CHIP_VEGA10 ? 4 : \ - (adev)->vm_manager.block_size) - #define AMDGPU_PTE_VALID (1ULL << 0) #define AMDGPU_PTE_SYSTEM (1ULL << 1) #define AMDGPU_PTE_SNOOPED (1ULL << 2) @@ -99,37 +95,57 @@ struct amdgpu_bo_list_entry; #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) +/* base structure for tracking BO usage in a VM */ +struct amdgpu_vm_bo_base { + /* constant after initialization */ + struct amdgpu_vm *vm; + struct amdgpu_bo *bo; + + /* protected by bo being reserved */ + struct list_head bo_list; + + /* protected by spinlock */ + struct list_head vm_status; + + /* protected by the BO being reserved */ + bool moved; +}; struct amdgpu_vm_pt { - struct amdgpu_bo *bo; - uint64_t addr; - bool huge_page; + struct amdgpu_vm_bo_base base; + uint64_t addr; /* array of page tables, one for each directory entry */ - struct amdgpu_vm_pt *entries; - unsigned last_entry_used; + struct amdgpu_vm_pt *entries; + unsigned last_entry_used; }; +#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr)) +#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48) +#define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL) + struct amdgpu_vm { /* tree of virtual addresses mapped */ - struct rb_root va; + struct rb_root_cached va; /* protecting invalidated */ spinlock_t status_lock; - /* BOs moved, but not yet updated in the PT */ - struct list_head invalidated; + /* BOs who needs a validation */ + struct list_head evicted; + + /* PT BOs which relocated and their parent need an update */ + struct list_head relocated; - /* BOs cleared in the PT because of a move */ - struct list_head cleared; + /* BOs moved, but not yet updated in the PT */ + struct list_head moved; /* BO mappings freed, but not yet updated in the PT */ struct list_head freed; /* contains the page directory */ struct amdgpu_vm_pt root; - struct dma_fence *last_dir_update; - uint64_t last_eviction_counter; + struct dma_fence *last_update; /* protecting freed */ spinlock_t freed_lock; @@ -137,18 +153,20 @@ struct amdgpu_vm { /* Scheduler entity for page table updates */ struct amd_sched_entity entity; - /* client id */ + /* client id and PASID (TODO: replace client_id with PASID) */ u64 client_id; + unsigned int pasid; /* dedicated to vm */ struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; - /* each VM will map on CSA */ - struct amdgpu_bo_va *csa_bo_va; /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ bool use_cpu_for_update; /* Flag to indicate ATS support from PTE for GFX9 */ bool pte_support_ats; + + /* Up to 128 pending page faults */ + DECLARE_KFIFO(faults, u64, 128); }; struct amdgpu_vm_id { @@ -191,6 +209,7 @@ struct amdgpu_vm_manager { uint32_t num_level; uint64_t vm_size; uint32_t block_size; + uint32_t fragment_size; /* vram base address for page table entry */ u64 vram_base_offset; /* vm pte handling */ @@ -210,21 +229,28 @@ struct amdgpu_vm_manager { * BIT1[= 0] Compute updated by SDMA [= 1] by CPU */ int vm_update_mode; + + /* PASID to VM mapping, will be used in interrupt context to + * look up VM of a page fault + */ + struct idr pasid_idr; + spinlock_t pasid_lock; }; +int amdgpu_vm_alloc_pasid(unsigned int bits); +void amdgpu_vm_free_pasid(unsigned int pasid); void amdgpu_vm_manager_init(struct amdgpu_device *adev); void amdgpu_vm_manager_fini(struct amdgpu_device *adev); int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, - int vm_context); + int vm_context, unsigned int pasid); void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, struct amdgpu_bo_list_entry *entry); +bool amdgpu_vm_ready(struct amdgpu_vm *vm); int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, int (*callback)(void *p, struct amdgpu_bo *bo), void *param); -void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, - struct amdgpu_vm *vm); int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t saddr, uint64_t size); @@ -240,13 +266,13 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence); -int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, - struct amdgpu_sync *sync); +int amdgpu_vm_handle_moved(struct amdgpu_device *adev, + struct amdgpu_vm *vm); int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, bool clear); void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, - struct amdgpu_bo *bo); + struct amdgpu_bo *bo, bool evicted); struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, struct amdgpu_bo *bo); struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, @@ -266,9 +292,14 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t saddr, uint64_t size); +struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, + uint64_t addr); void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); +void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, + uint32_t fragment_size_default); +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, + uint32_t fragment_size_default); int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, struct amdgpu_job *job); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index a2c59a08b2bd..26e900627971 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -28,6 +28,8 @@ struct amdgpu_vram_mgr { struct drm_mm mm; spinlock_t lock; + atomic64_t usage; + atomic64_t vis_usage; }; /** @@ -79,6 +81,27 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man) } /** + * amdgpu_vram_mgr_vis_size - Calculate visible node size + * + * @adev: amdgpu device structure + * @node: MM node structure + * + * Calculate how many bytes of the MM node are inside visible VRAM + */ +static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev, + struct drm_mm_node *node) +{ + uint64_t start = node->start << PAGE_SHIFT; + uint64_t end = (node->size + node->start) << PAGE_SHIFT; + + if (start >= adev->mc.visible_vram_size) + return 0; + + return (end > adev->mc.visible_vram_size ? + adev->mc.visible_vram_size : end) - start; +} + +/** * amdgpu_vram_mgr_new - allocate new ranges * * @man: TTM memory type manager @@ -93,11 +116,13 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, const struct ttm_place *place, struct ttm_mem_reg *mem) { + struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); struct amdgpu_vram_mgr *mgr = man->priv; struct drm_mm *mm = &mgr->mm; struct drm_mm_node *nodes; enum drm_mm_insert_mode mode; unsigned long lpfn, num_nodes, pages_per_node, pages_left; + uint64_t usage = 0, vis_usage = 0; unsigned i; int r; @@ -142,6 +167,9 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, if (unlikely(r)) goto error; + usage += nodes[i].size << PAGE_SHIFT; + vis_usage += amdgpu_vram_mgr_vis_size(adev, &nodes[i]); + /* Calculate a virtual BO start address to easily check if * everything is CPU accessible. */ @@ -155,6 +183,9 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, } spin_unlock(&mgr->lock); + atomic64_add(usage, &mgr->usage); + atomic64_add(vis_usage, &mgr->vis_usage); + mem->mm_node = nodes; return 0; @@ -181,8 +212,10 @@ error: static void amdgpu_vram_mgr_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { + struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); struct amdgpu_vram_mgr *mgr = man->priv; struct drm_mm_node *nodes = mem->mm_node; + uint64_t usage = 0, vis_usage = 0; unsigned pages = mem->num_pages; if (!mem->mm_node) @@ -192,31 +225,67 @@ static void amdgpu_vram_mgr_del(struct ttm_mem_type_manager *man, while (pages) { pages -= nodes->size; drm_mm_remove_node(nodes); + usage += nodes->size << PAGE_SHIFT; + vis_usage += amdgpu_vram_mgr_vis_size(adev, nodes); ++nodes; } spin_unlock(&mgr->lock); + atomic64_sub(usage, &mgr->usage); + atomic64_sub(vis_usage, &mgr->vis_usage); + kfree(mem->mm_node); mem->mm_node = NULL; } /** + * amdgpu_vram_mgr_usage - how many bytes are used in this domain + * + * @man: TTM memory type manager + * + * Returns how many bytes are used in this domain. + */ +uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man) +{ + struct amdgpu_vram_mgr *mgr = man->priv; + + return atomic64_read(&mgr->usage); +} + +/** + * amdgpu_vram_mgr_vis_usage - how many bytes are used in the visible part + * + * @man: TTM memory type manager + * + * Returns how many bytes are used in the visible part of VRAM + */ +uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man) +{ + struct amdgpu_vram_mgr *mgr = man->priv; + + return atomic64_read(&mgr->vis_usage); +} + +/** * amdgpu_vram_mgr_debug - dump VRAM table * * @man: TTM memory type manager - * @prefix: text prefix + * @printer: DRM printer to use * * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { struct amdgpu_vram_mgr *mgr = man->priv; - struct drm_printer p = drm_debug_printer(prefix); spin_lock(&mgr->lock); - drm_mm_print(&mgr->mm, &p); + drm_mm_print(&mgr->mm, printer); spin_unlock(&mgr->lock); + + drm_printf(printer, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", + man->size, amdgpu_vram_mgr_usage(man) >> 20, + amdgpu_vram_mgr_vis_usage(man) >> 20); } const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func = { diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index d69aa2e179bb..69500a8b4e2d 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1343,8 +1343,11 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) idx = 0x80; str = CSTR(idx); - if (*str != '\0') + if (*str != '\0') { pr_info("ATOM BIOS: %s\n", str); + strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version)); + } + return ctx; } diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index ddd8045accf3..a39170991afe 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -140,6 +140,7 @@ struct atom_context { int io_mode; uint32_t *scratch; int scratch_size_bytes; + char vbios_version[20]; }; extern int amdgpu_atom_debug; diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index cb508a211b2f..68ce1bdaf2fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -307,7 +307,6 @@ static int ci_set_power_limit(struct amdgpu_device *adev, u32 n); static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev, u32 target_tdp); static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate); -static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev); static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev); static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, @@ -883,8 +882,9 @@ static int ci_power_control_set_level(struct amdgpu_device *adev) return ret; } -static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) +static void ci_dpm_powergate_uvd(void *handle, bool gate) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); pi->uvd_power_gated = gate; @@ -901,8 +901,9 @@ static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) } } -static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev) +static bool ci_dpm_vblank_too_short(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; @@ -1210,11 +1211,12 @@ static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) } } -static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev, +static int ci_dpm_get_fan_speed_percent(void *handle, u32 *speed) { u32 duty, duty100; u64 tmp64; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->pm.no_fan) return -ENOENT; @@ -1237,12 +1239,13 @@ static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev, return 0; } -static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev, +static int ci_dpm_set_fan_speed_percent(void *handle, u32 speed) { u32 tmp; u32 duty, duty100; u64 tmp64; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); if (adev->pm.no_fan) @@ -1271,8 +1274,10 @@ static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev, return 0; } -static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) +static void ci_dpm_set_fan_control_mode(void *handle, u32 mode) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + switch (mode) { case AMD_FAN_CTRL_NONE: if (adev->pm.dpm.fan.ucode_fan_control) @@ -1292,8 +1297,9 @@ static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) } } -static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev) +static u32 ci_dpm_get_fan_control_mode(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); if (pi->fan_is_controlled_by_smc) @@ -4378,9 +4384,10 @@ static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev, } -static int ci_dpm_force_performance_level(struct amdgpu_device *adev, +static int ci_dpm_force_performance_level(void *handle, enum amd_dpm_forced_level level) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); u32 tmp, levels, i; int ret; @@ -5291,8 +5298,9 @@ static void ci_update_requested_ps(struct amdgpu_device *adev, adev->pm.dpm.requested_ps = &pi->requested_rps; } -static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev) +static int ci_dpm_pre_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; struct amdgpu_ps *new_ps = &requested_ps; @@ -5304,8 +5312,9 @@ static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev) return 0; } -static void ci_dpm_post_set_power_state(struct amdgpu_device *adev) +static void ci_dpm_post_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct amdgpu_ps *new_ps = &pi->requested_rps; @@ -5479,8 +5488,9 @@ static void ci_dpm_disable(struct amdgpu_device *adev) ci_update_current_ps(adev, boot_ps); } -static int ci_dpm_set_power_state(struct amdgpu_device *adev) +static int ci_dpm_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct amdgpu_ps *new_ps = &pi->requested_rps; struct amdgpu_ps *old_ps = &pi->current_rps; @@ -5551,8 +5561,10 @@ static void ci_dpm_reset_asic(struct amdgpu_device *adev) } #endif -static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev) +static void ci_dpm_display_configuration_changed(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + ci_program_display_gap(adev); } @@ -6105,9 +6117,10 @@ static int ci_dpm_init(struct amdgpu_device *adev) } static void -ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, +ci_dpm_debugfs_print_current_performance_level(void *handle, struct seq_file *m) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct amdgpu_ps *rps = &pi->current_rps; u32 sclk = ci_get_average_sclk_freq(adev); @@ -6131,12 +6144,13 @@ ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, seq_printf(m, "GPU load: %u %%\n", activity_percent); } -static void ci_dpm_print_power_state(struct amdgpu_device *adev, - struct amdgpu_ps *rps) +static void ci_dpm_print_power_state(void *handle, void *current_ps) { + struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; struct ci_ps *ps = ci_get_ps(rps); struct ci_pl *pl; int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; amdgpu_dpm_print_class_info(rps->class, rps->class2); amdgpu_dpm_print_cap_info(rps->caps); @@ -6158,20 +6172,23 @@ static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1, (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane)); } -static int ci_check_state_equal(struct amdgpu_device *adev, - struct amdgpu_ps *cps, - struct amdgpu_ps *rps, +static int ci_check_state_equal(void *handle, + void *current_ps, + void *request_ps, bool *equal) { struct ci_ps *ci_cps; struct ci_ps *ci_rps; int i; + struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) return -EINVAL; - ci_cps = ci_get_ps(cps); - ci_rps = ci_get_ps(rps); + ci_cps = ci_get_ps((struct amdgpu_ps *)cps); + ci_rps = ci_get_ps((struct amdgpu_ps *)rps); if (ci_cps == NULL) { *equal = false; @@ -6199,8 +6216,9 @@ static int ci_check_state_equal(struct amdgpu_device *adev, return 0; } -static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low) +static u32 ci_dpm_get_sclk(void *handle, bool low) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); @@ -6210,8 +6228,9 @@ static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low) return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; } -static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low) +static u32 ci_dpm_get_mclk(void *handle, bool low) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); @@ -6222,10 +6241,11 @@ static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low) } /* get temperature in millidegrees */ -static int ci_dpm_get_temp(struct amdgpu_device *adev) +static int ci_dpm_get_temp(void *handle) { u32 temp; int actual_temp = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; @@ -6261,7 +6281,6 @@ static int ci_dpm_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - ci_dpm_set_dpm_funcs(adev); ci_dpm_set_irq_funcs(adev); return 0; @@ -6551,9 +6570,10 @@ static int ci_dpm_set_powergating_state(void *handle, return 0; } -static int ci_dpm_print_clock_levels(struct amdgpu_device *adev, +static int ci_dpm_print_clock_levels(void *handle, enum pp_clock_type type, char *buf) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; @@ -6618,9 +6638,10 @@ static int ci_dpm_print_clock_levels(struct amdgpu_device *adev, return size; } -static int ci_dpm_force_clock_level(struct amdgpu_device *adev, +static int ci_dpm_force_clock_level(void *handle, enum pp_clock_type type, uint32_t mask) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO | @@ -6664,8 +6685,9 @@ static int ci_dpm_force_clock_level(struct amdgpu_device *adev, return 0; } -static int ci_dpm_get_sclk_od(struct amdgpu_device *adev) +static int ci_dpm_get_sclk_od(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table); struct ci_single_dpm_table *golden_sclk_table = @@ -6680,8 +6702,9 @@ static int ci_dpm_get_sclk_od(struct amdgpu_device *adev) return value; } -static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) +static int ci_dpm_set_sclk_od(void *handle, uint32_t value) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps); struct ci_single_dpm_table *golden_sclk_table = @@ -6698,8 +6721,9 @@ static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) return 0; } -static int ci_dpm_get_mclk_od(struct amdgpu_device *adev) +static int ci_dpm_get_mclk_od(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table); struct ci_single_dpm_table *golden_mclk_table = @@ -6714,8 +6738,9 @@ static int ci_dpm_get_mclk_od(struct amdgpu_device *adev) return value; } -static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) +static int ci_dpm_set_mclk_od(void *handle, uint32_t value) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps); struct ci_single_dpm_table *golden_mclk_table = @@ -6732,9 +6757,10 @@ static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) return 0; } -static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev, +static int ci_dpm_get_power_profile_state(void *handle, struct amd_pp_profile *query) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); if (!pi || !query) @@ -6851,9 +6877,10 @@ static int ci_set_power_profile_state(struct amdgpu_device *adev, return result; } -static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev, +static int ci_dpm_set_power_profile_state(void *handle, struct amd_pp_profile *request) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); int ret = -1; @@ -6906,9 +6933,10 @@ static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev, return 0; } -static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev, +static int ci_dpm_reset_power_profile_state(void *handle, struct amd_pp_profile *request) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); if (!pi || !request) @@ -6927,9 +6955,10 @@ static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev, return -EINVAL; } -static int ci_dpm_switch_power_profile(struct amdgpu_device *adev, +static int ci_dpm_switch_power_profile(void *handle, enum amd_pp_profile_type type) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct ci_power_info *pi = ci_get_pi(adev); struct amd_pp_profile request = {0}; @@ -6944,11 +6973,12 @@ static int ci_dpm_switch_power_profile(struct amdgpu_device *adev, return 0; } -static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx, +static int ci_dpm_read_sensor(void *handle, int idx, void *value, int *size) { u32 activity_percent = 50; int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* size must be at least 4 bytes for all sensors */ if (*size < 4) @@ -7003,7 +7033,7 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = { .set_powergating_state = ci_dpm_set_powergating_state, }; -static const struct amdgpu_dpm_funcs ci_dpm_funcs = { +const struct amd_pm_funcs ci_dpm_funcs = { .get_temperature = &ci_dpm_get_temp, .pre_set_power_state = &ci_dpm_pre_set_power_state, .set_power_state = &ci_dpm_set_power_state, @@ -7035,12 +7065,6 @@ static const struct amdgpu_dpm_funcs ci_dpm_funcs = { .read_sensor = ci_dpm_read_sensor, }; -static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev) -{ - if (adev->pm.funcs == NULL) - adev->pm.funcs = &ci_dpm_funcs; -} - static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = { .set = ci_dpm_set_interrupt_state, .process = ci_dpm_process_interrupt, diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h index b1c8e7b446ea..c7b4349f6319 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h @@ -26,5 +26,6 @@ extern const struct amd_ip_funcs ci_dpm_ip_funcs; extern const struct amd_ip_funcs kv_dpm_ip_funcs; - +extern const struct amd_pm_funcs ci_dpm_funcs; +extern const struct amd_pm_funcs kv_dpm_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index b8918432c572..07d3d895da10 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -228,6 +228,19 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev) * [127:96] - reserved */ +/** + * cik_ih_prescreen_iv - prescreen an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Returns true if the interrupt vector should be further processed. + */ +static bool cik_ih_prescreen_iv(struct amdgpu_device *adev) +{ + /* Process all interrupts */ + return true; +} + /** * cik_ih_decode_iv - decode an interrupt vector * @@ -433,6 +446,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = { static const struct amdgpu_ih_funcs cik_ih_funcs = { .get_wptr = cik_ih_get_wptr, + .prescreen_iv = cik_ih_prescreen_iv, .decode_iv = cik_ih_decode_iv, .set_rptr = cik_ih_set_rptr }; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index f508f4d01e4a..60cecd117705 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1387,8 +1387,13 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) } static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { + .copy_pte_num_dw = 7, .copy_pte = cik_sdma_vm_copy_pte, + .write_pte = cik_sdma_vm_write_pte, + + .set_max_nums_pte_pde = 0x1fffff >> 3, + .set_pte_pde_num_dw = 10, .set_pte_pde = cik_sdma_vm_set_pte_pde, }; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 0c1209cdd1cb..b6cdf4afaf46 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -208,6 +208,19 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev) } /** + * cz_ih_prescreen_iv - prescreen an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Returns true if the interrupt vector should be further processed. + */ +static bool cz_ih_prescreen_iv(struct amdgpu_device *adev) +{ + /* Process all interrupts */ + return true; +} + +/** * cz_ih_decode_iv - decode an interrupt vector * * @adev: amdgpu_device pointer @@ -414,6 +427,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = { static const struct amdgpu_ih_funcs cz_ih_funcs = { .get_wptr = cz_ih_get_wptr, + .prescreen_iv = cz_ih_prescreen_iv, .decode_iv = cz_ih_decode_iv, .set_rptr = cz_ih_set_rptr }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index d228f5a99044..dbbe986f90f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) NUM_BANKS(ADDR_SURF_2_BANK); for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); - } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) { + } else if (adev->asic_type == CHIP_OLAND) { + tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + NUM_BANKS(ADDR_SURF_8_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) + WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); + } else if (adev->asic_type == CHIP_HAINAN) { tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) | diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 53a4af7596c1..00868764a0dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -1921,6 +1921,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) ELEMENT_SIZE, 1); sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, INDEX_STRIDE, 3); + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); mutex_lock(&adev->srbm_mutex); for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { @@ -1934,7 +1935,6 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); WREG32(mmSH_MEM_BASES, sh_mem_base); - WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); } cik_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 0710b0b2e4b6..dfc10b1baea0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -125,24 +125,39 @@ MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin"); MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin"); MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin"); MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin"); MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin"); MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin"); MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin"); MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin"); MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin"); MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin"); MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); MODULE_FIRMWARE("amdgpu/polaris12_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin"); MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin"); MODULE_FIRMWARE("amdgpu/polaris12_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin"); MODULE_FIRMWARE("amdgpu/polaris12_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin"); MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin"); MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin"); static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = @@ -918,8 +933,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) BUG(); } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name); + err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (err == -ENOENT) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); + err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + } + } else { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); + err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + } if (err) goto out; err = amdgpu_ucode_validate(adev->gfx.pfp_fw); @@ -929,8 +953,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name); + err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (err == -ENOENT) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); + err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + } + } else { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); + err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + } if (err) goto out; err = amdgpu_ucode_validate(adev->gfx.me_fw); @@ -941,8 +974,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name); + err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (err == -ENOENT) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); + err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + } + } else { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); + err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + } if (err) goto out; err = amdgpu_ucode_validate(adev->gfx.ce_fw); @@ -1012,8 +1054,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name); + err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (err == -ENOENT) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); + err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + } + } else { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); + err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + } if (err) goto out; err = amdgpu_ucode_validate(adev->gfx.mec_fw); @@ -1025,8 +1076,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if ((adev->asic_type != CHIP_STONEY) && (adev->asic_type != CHIP_TOPAZ)) { - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (err == -ENOENT) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + } + } else { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + } if (!err) { err = amdgpu_ucode_validate(adev->gfx.mec2_fw); if (err) @@ -2053,6 +2113,7 @@ static int gfx_v8_0_sw_fini(void *handle) amdgpu_gfx_compute_mqd_sw_fini(adev); amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); amdgpu_gfx_kiq_fini(adev); + amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); gfx_v8_0_mec_fini(adev); gfx_v8_0_rlc_fini(adev); @@ -3707,6 +3768,8 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) ELEMENT_SIZE, 1); sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, INDEX_STRIDE, 3); + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); + mutex_lock(&adev->srbm_mutex); for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { vi_srbm_select(adev, 0, 0, 0, i); @@ -3730,7 +3793,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); - WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); } vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); @@ -4576,12 +4638,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) mqd->compute_static_thread_mgmt_se2 = 0xffffffff; mqd->compute_static_thread_mgmt_se3 = 0xffffffff; mqd->compute_misc_reserved = 0x00000003; - if (!(adev->flags & AMD_IS_APU)) { - mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr - + offsetof(struct vi_mqd_allocation, dyamic_cu_mask)); - mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr - + offsetof(struct vi_mqd_allocation, dyamic_cu_mask)); - } + mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr + + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); + mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr + + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); eop_base_addr = ring->eop_gpu_addr >> 8; mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); @@ -4752,7 +4812,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) gfx_v8_0_kiq_setting(ring); - if (adev->gfx.in_reset) { /* for GPU_RESET case */ + if (adev->in_sriov_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); @@ -4767,8 +4827,8 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) mutex_unlock(&adev->srbm_mutex); } else { memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); - ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF; - ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF; + ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; + ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; mutex_lock(&adev->srbm_mutex); vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); gfx_v8_0_mqd_init(ring); @@ -4789,10 +4849,10 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) struct vi_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!adev->gfx.in_reset && !adev->gfx.in_suspend) { + if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); - ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF; - ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF; + ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; + ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; mutex_lock(&adev->srbm_mutex); vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); gfx_v8_0_mqd_init(ring); @@ -4801,7 +4861,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); - } else if (adev->gfx.in_reset) { /* for GPU_RESET case */ + } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); @@ -4974,12 +5034,69 @@ static int gfx_v8_0_hw_init(void *handle) return r; } +static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = kiq_ring->adev; + uint32_t scratch, tmp = 0; + int r, i; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("Failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + + r = amdgpu_ring_alloc(kiq_ring, 10); + if (r) { + DRM_ERROR("Failed to lock KIQ (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + + /* unmap queues */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); + amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ + PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ + PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | + PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | + PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); + amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); + amdgpu_ring_write(kiq_ring, 0); + amdgpu_ring_write(kiq_ring, 0); + amdgpu_ring_write(kiq_ring, 0); + /* write to scratch for completion */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(kiq_ring, 0xDEADBEEF); + amdgpu_ring_commit(kiq_ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i >= adev->usec_timeout) { + DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + return r; +} + static int gfx_v8_0_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + + /* disable KCQ to avoid CPC touch memory not valid anymore */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) + gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); + if (amdgpu_sriov_vf(adev)) { pr_debug("For SRIOV client, shouldn't do anything.\n"); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index b39f81dda847..deeaee1457ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -66,38 +66,70 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)}, - {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), - SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)} + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) }, + { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), + SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), + SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) } }; static const u32 golden_settings_gc_9_0[] = @@ -352,6 +384,25 @@ err1: return r; } + +static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) +{ + release_firmware(adev->gfx.pfp_fw); + adev->gfx.pfp_fw = NULL; + release_firmware(adev->gfx.me_fw); + adev->gfx.me_fw = NULL; + release_firmware(adev->gfx.ce_fw); + adev->gfx.ce_fw = NULL; + release_firmware(adev->gfx.rlc_fw); + adev->gfx.rlc_fw = NULL; + release_firmware(adev->gfx.mec_fw); + adev->gfx.mec_fw = NULL; + release_firmware(adev->gfx.mec2_fw); + adev->gfx.mec2_fw = NULL; + + kfree(adev->gfx.rlc.register_list_format); +} + static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) { const char *chip_name; @@ -1120,30 +1171,22 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) { struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; int r; - u32 data; - u32 size; - u32 base; + u32 data, base; if (!amdgpu_ngg) return 0; /* Program buffer size */ - data = 0; - size = adev->gfx.ngg.buf[NGG_PRIM].size / 256; - data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size); - - size = adev->gfx.ngg.buf[NGG_POS].size / 256; - data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size); - + data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, + adev->gfx.ngg.buf[NGG_PRIM].size >> 8); + data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, + adev->gfx.ngg.buf[NGG_POS].size >> 8); WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); - data = 0; - size = adev->gfx.ngg.buf[NGG_CNTL].size / 256; - data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size); - - size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024; - data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size); - + data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, + adev->gfx.ngg.buf[NGG_CNTL].size >> 8); + data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, + adev->gfx.ngg.buf[NGG_PARAM].size >> 10); WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); /* Program buffer base address */ @@ -1306,7 +1349,10 @@ static int gfx_v9_0_sw_init(void *handle) for (i = 0; i < adev->gfx.num_gfx_rings; i++) { ring = &adev->gfx.gfx_ring[i]; ring->ring_obj = NULL; - sprintf(ring->name, "gfx"); + if (!i) + sprintf(ring->name, "gfx"); + else + sprintf(ring->name, "gfx_%d", i); ring->use_doorbell = true; ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; r = amdgpu_ring_init(adev, ring, 1024, @@ -1346,7 +1392,7 @@ static int gfx_v9_0_sw_init(void *handle) return r; /* create MQD for all compute queues as wel as KIQ for SRIOV case */ - r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd)); + r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); if (r) return r; @@ -1398,9 +1444,11 @@ static int gfx_v9_0_sw_fini(void *handle) amdgpu_gfx_compute_mqd_sw_fini(adev); amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); amdgpu_gfx_kiq_fini(adev); + amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); gfx_v9_0_mec_fini(adev); gfx_v9_0_ngg_fini(adev); + gfx_v9_0_free_microcode(adev); return 0; } @@ -1740,11 +1788,7 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) { - u32 tmp = 0; - - tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); - tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); + WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); } static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, @@ -1822,16 +1866,11 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev uint32_t default_data = 0; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - - if (enable == true) { - data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; - if (default_data != data) - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); - } else { - data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; - if(default_data != data) - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); - } + data = REG_SET_FIELD(data, RLC_PG_CNTL, + SMU_CLK_SLOWDOWN_ON_PU_ENABLE, + enable ? 1 : 0); + if (default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); } static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, @@ -1841,16 +1880,11 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *ad uint32_t default_data = 0; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - - if (enable == true) { - data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; - if(default_data != data) - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); - } else { - data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; - if(default_data != data) - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); - } + data = REG_SET_FIELD(data, RLC_PG_CNTL, + SMU_CLK_SLOWDOWN_ON_PD_ENABLE, + enable ? 1 : 0); + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); } static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, @@ -1860,16 +1894,11 @@ static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, uint32_t default_data = 0; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - - if (enable == true) { - data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK; - if(default_data != data) - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); - } else { - data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK; - if(default_data != data) - WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); - } + data = REG_SET_FIELD(data, RLC_PG_CNTL, + CP_PG_DISABLE, + enable ? 0 : 1); + if(default_data != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); } static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, @@ -1878,10 +1907,9 @@ static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, uint32_t data, default_data; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - if (enable == true) - data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; - else - data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; + data = REG_SET_FIELD(data, RLC_PG_CNTL, + GFX_POWER_GATING_ENABLE, + enable ? 1 : 0); if(default_data != data) WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); } @@ -1892,10 +1920,9 @@ static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, uint32_t data, default_data; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - if (enable == true) - data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK; - else - data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK; + data = REG_SET_FIELD(data, RLC_PG_CNTL, + GFX_PIPELINE_PG_ENABLE, + enable ? 1 : 0); if(default_data != data) WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); @@ -1910,10 +1937,9 @@ static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade uint32_t data, default_data; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - if (enable == true) - data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; - else - data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; + data = REG_SET_FIELD(data, RLC_PG_CNTL, + STATIC_PER_CU_PG_ENABLE, + enable ? 1 : 0); if(default_data != data) WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); } @@ -1924,10 +1950,9 @@ static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad uint32_t data, default_data; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - if (enable == true) - data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; - else - data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; + data = REG_SET_FIELD(data, RLC_PG_CNTL, + DYN_PER_CU_PG_ENABLE, + enable ? 1 : 0); if(default_data != data) WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); } @@ -1967,13 +1992,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev) void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) { - u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); - - tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); - WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); - + WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); gfx_v9_0_enable_gui_idle_interrupt(adev, false); - gfx_v9_0_wait_for_rlc_serdes(adev); } @@ -2045,8 +2065,10 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) { int r; - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev)) { + gfx_v9_0_init_csb(adev); return 0; + } gfx_v9_0_rlc_stop(adev); @@ -2157,7 +2179,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; const struct cs_section_def *sect = NULL; const struct cs_extent_def *ext = NULL; - int r, i; + int r, i, tmp; /* init the CP */ WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); @@ -2165,7 +2187,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_enable(adev, true); - r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4); + r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); if (r) { DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); return r; @@ -2203,6 +2225,12 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, 0x8000); amdgpu_ring_write(ring, 0x8000); + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); + tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | + (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0); + amdgpu_ring_commit(ring); return 0; @@ -2457,6 +2485,13 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) mqd->compute_static_thread_mgmt_se3 = 0xffffffff; mqd->compute_misc_reserved = 0x00000003; + mqd->dynamic_cu_mask_addr_lo = + lower_32_bits(ring->mqd_gpu_addr + + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); + mqd->dynamic_cu_mask_addr_hi = + upper_32_bits(ring->mqd_gpu_addr + + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); + eop_base_addr = ring->eop_gpu_addr >> 8; mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); @@ -2480,10 +2515,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) DOORBELL_SOURCE, 0); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); - } - else + } else { tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); + } mqd->cp_hqd_pq_doorbell_control = tmp; @@ -2686,10 +2721,10 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) gfx_v9_0_kiq_setting(ring); - if (adev->gfx.in_reset) { /* for GPU_RESET case */ + if (adev->in_sriov_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) - memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); + memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); /* reset ring buffer */ ring->wptr = 0; @@ -2701,7 +2736,9 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) soc15_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); } else { - memset((void *)mqd, 0, sizeof(*mqd)); + memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); + ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; + ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); gfx_v9_0_mqd_init(ring); @@ -2710,7 +2747,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) mutex_unlock(&adev->srbm_mutex); if (adev->gfx.mec.mqd_backup[mqd_idx]) - memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); + memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); } return 0; @@ -2722,8 +2759,10 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) struct v9_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!adev->gfx.in_reset && !adev->gfx.in_suspend) { - memset((void *)mqd, 0, sizeof(*mqd)); + if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { + memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); + ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; + ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); gfx_v9_0_mqd_init(ring); @@ -2731,11 +2770,11 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) mutex_unlock(&adev->srbm_mutex); if (adev->gfx.mec.mqd_backup[mqd_idx]) - memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); - } else if (adev->gfx.in_reset) { /* for GPU_RESET case */ + memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); + } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) - memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); + memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); /* reset ring buffer */ ring->wptr = 0; @@ -2876,12 +2915,70 @@ static int gfx_v9_0_hw_init(void *handle) return r; } +static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = kiq_ring->adev; + uint32_t scratch, tmp = 0; + int r, i; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("Failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + + r = amdgpu_ring_alloc(kiq_ring, 10); + if (r) { + DRM_ERROR("Failed to lock KIQ (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + + /* unmap queues */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); + amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ + PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ + PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | + PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | + PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); + amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); + amdgpu_ring_write(kiq_ring, 0); + amdgpu_ring_write(kiq_ring, 0); + amdgpu_ring_write(kiq_ring, 0); + /* write to scratch for completion */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(kiq_ring, 0xDEADBEEF); + amdgpu_ring_commit(kiq_ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i >= adev->usec_timeout) { + DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + return r; +} + + static int gfx_v9_0_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + + /* disable KCQ to avoid CPC touch memory not valid anymore */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) + gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); + if (amdgpu_sriov_vf(adev)) { pr_debug("For SRIOV client, shouldn't do anything.\n"); return 0; @@ -2924,15 +3021,10 @@ static bool gfx_v9_0_is_idle(void *handle) static int gfx_v9_0_wait_for_idle(void *handle) { unsigned i; - u32 tmp; struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { - /* read MC_STATUS */ - tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & - GRBM_STATUS__GUI_ACTIVE_MASK; - - if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) + if (gfx_v9_0_is_idle(handle)) return 0; udelay(1); } @@ -3493,7 +3585,9 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) u32 ref_and_mask, reg_mem_engine; struct nbio_hdp_flush_reg *nbio_hf_reg; - if (ring->adev->asic_type == CHIP_VEGA10) + if (ring->adev->flags & AMD_IS_APU) + nbio_hf_reg = &nbio_v7_0_hdp_flush_reg; + else nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { @@ -3522,7 +3616,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { gfx_v9_0_write_data_to_reg(ring, 0, true, - SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1); + SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); } static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, @@ -3751,6 +3845,12 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); } +static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); + amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ +} + static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) { uint32_t dw2 = 0; @@ -3758,6 +3858,8 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) if (amdgpu_sriov_vf(ring->adev)) gfx_v9_0_ring_emit_ce_meta(ring); + gfx_v9_0_ring_emit_tmz(ring, true); + dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ if (flags & AMDGPU_HAVE_CTX_SWITCH) { /* set load_global_config & load_global_uconfig */ @@ -3808,12 +3910,6 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne ring->ring[offset] = (ring->ring_size>>2) - offset + cur; } -static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) -{ - amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); - amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ -} - static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) { struct amdgpu_device *adev = ring->adev; diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 408723ef157c..c17996e18086 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -144,8 +144,8 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); tmp = mmVM_L2_CNTL3_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); tmp = mmVM_L2_CNTL4_DEFAULT; @@ -319,6 +319,12 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + if (!value) { + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_NO_RETRY_FAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_RETRY_FAULT, 1); + } WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 93c45f26b7c8..f4603a7c8ef3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -332,7 +332,24 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.visible_vram_size = adev->mc.aper_size; - amdgpu_gart_set_defaults(adev); + /* set the gart size */ + if (amdgpu_gart_size == -1) { + switch (adev->asic_type) { + case CHIP_HAINAN: /* no MM engines */ + default: + adev->mc.gart_size = 256ULL << 20; + break; + case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ + case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ + case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ + case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ + adev->mc.gart_size = 1024ULL << 20; + break; + } + } else { + adev->mc.gart_size = (u64)amdgpu_gart_size << 20; + } + gmc_v6_0_vram_gtt_location(adev, &adev->mc); return 0; @@ -461,6 +478,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) { int r, i; + u32 field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); @@ -488,10 +506,12 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) WREG32(mmVM_L2_CNTL2, VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); + + field = adev->vm_manager.fragment_size; WREG32(mmVM_L2_CNTL3, VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | - (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) | - (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); + (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | + (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); /* setup context0 */ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); @@ -811,7 +831,7 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - amdgpu_vm_adjust_size(adev, 64); + amdgpu_vm_adjust_size(adev, 64, 9); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; adev->mc.mc_mask = 0xffffffffffULL; @@ -881,6 +901,8 @@ static int gmc_v6_0_sw_fini(void *handle) gmc_v6_0_gart_fini(adev); amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); + release_firmware(adev->mc.fw); + adev->mc.fw = NULL; return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 4a9e84062874..b0528ca9207b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -386,7 +386,27 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) if (adev->mc.visible_vram_size > adev->mc.real_vram_size) adev->mc.visible_vram_size = adev->mc.real_vram_size; - amdgpu_gart_set_defaults(adev); + /* set the gart size */ + if (amdgpu_gart_size == -1) { + switch (adev->asic_type) { + case CHIP_TOPAZ: /* no MM engines */ + default: + adev->mc.gart_size = 256ULL << 20; + break; +#ifdef CONFIG_DRM_AMDGPU_CIK + case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ + case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ + case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ + case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ + case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ + adev->mc.gart_size = 1024ULL << 20; + break; +#endif + } + } else { + adev->mc.gart_size = (u64)amdgpu_gart_size << 20; + } + gmc_v7_0_vram_gtt_location(adev, &adev->mc); return 0; @@ -562,7 +582,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) { int r, i; - u32 tmp; + u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); @@ -592,10 +612,12 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32(mmVM_L2_CNTL2, tmp); + + field = adev->vm_manager.fragment_size; tmp = RREG32(mmVM_L2_CNTL3); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); WREG32(mmVM_L2_CNTL3, tmp); /* setup context0 */ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); @@ -948,7 +970,7 @@ static int gmc_v7_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64); + amdgpu_vm_adjust_size(adev, 64, 9); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; /* Set the internal MC address mask @@ -1028,6 +1050,8 @@ static int gmc_v7_0_sw_fini(void *handle) gmc_v7_0_gart_fini(adev); amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); + release_firmware(adev->mc.fw); + adev->mc.fw = NULL; return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 85c937b5e40b..f368cfe2f585 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -562,7 +562,26 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) if (adev->mc.visible_vram_size > adev->mc.real_vram_size) adev->mc.visible_vram_size = adev->mc.real_vram_size; - amdgpu_gart_set_defaults(adev); + /* set the gart size */ + if (amdgpu_gart_size == -1) { + switch (adev->asic_type) { + case CHIP_POLARIS11: /* all engines support GPUVM */ + case CHIP_POLARIS10: /* all engines support GPUVM */ + case CHIP_POLARIS12: /* all engines support GPUVM */ + default: + adev->mc.gart_size = 256ULL << 20; + break; + case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ + case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ + case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ + case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ + adev->mc.gart_size = 1024ULL << 20; + break; + } + } else { + adev->mc.gart_size = (u64)amdgpu_gart_size << 20; + } + gmc_v8_0_vram_gtt_location(adev, &adev->mc); return 0; @@ -762,7 +781,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) { int r, i; - u32 tmp; + u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); @@ -793,10 +812,12 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32(mmVM_L2_CNTL2, tmp); + + field = adev->vm_manager.fragment_size; tmp = RREG32(mmVM_L2_CNTL3); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); WREG32(mmVM_L2_CNTL3, tmp); /* XXX: set to enable PTE/PDE in system memory */ tmp = RREG32(mmVM_L2_CNTL4); @@ -1046,7 +1067,7 @@ static int gmc_v8_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64); + amdgpu_vm_adjust_size(adev, 64, 9); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; /* Set the internal MC address mask @@ -1126,6 +1147,8 @@ static int gmc_v8_0_sw_fini(void *handle) gmc_v8_0_gart_fini(adev); amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); + release_firmware(adev->mc.fw); + adev->mc.fw = NULL; return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index c22899a08106..621699331e09 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -32,6 +32,8 @@ #include "vega10/DC/dce_12_0_offset.h" #include "vega10/DC/dce_12_0_sh_mask.h" #include "vega10/vega10_enum.h" +#include "vega10/MMHUB/mmhub_1_0_offset.h" +#include "vega10/ATHUB/athub_1_0_offset.h" #include "soc15_common.h" @@ -71,13 +73,25 @@ static const u32 golden_settings_vega10_hdp[] = 0xf6e, 0x0fffffff, 0x00000000, }; +static const u32 golden_settings_mmhub_1_0_0[] = +{ + SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa, + SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565 +}; + +static const u32 golden_settings_athub_1_0_0[] = +{ + SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800, + SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008 +}; + static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) { struct amdgpu_vmhub *hub; - u32 tmp, reg, bits, i; + u32 tmp, reg, bits, i, j; bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | @@ -89,43 +103,26 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - /* MM HUB */ - hub = &adev->vmhub[AMDGPU_MMHUB]; - for (i = 0; i< 16; i++) { - reg = hub->vm_context0_cntl + i; - tmp = RREG32(reg); - tmp &= ~bits; - WREG32(reg, tmp); - } - - /* GFX HUB */ - hub = &adev->vmhub[AMDGPU_GFXHUB]; - for (i = 0; i < 16; i++) { - reg = hub->vm_context0_cntl + i; - tmp = RREG32(reg); - tmp &= ~bits; - WREG32(reg, tmp); + for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { + hub = &adev->vmhub[j]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); + tmp &= ~bits; + WREG32(reg, tmp); + } } break; case AMDGPU_IRQ_STATE_ENABLE: - /* MM HUB */ - hub = &adev->vmhub[AMDGPU_MMHUB]; - for (i = 0; i< 16; i++) { - reg = hub->vm_context0_cntl + i; - tmp = RREG32(reg); - tmp |= bits; - WREG32(reg, tmp); + for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { + hub = &adev->vmhub[j]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); + tmp |= bits; + WREG32(reg, tmp); + } } - - /* GFX HUB */ - hub = &adev->vmhub[AMDGPU_GFXHUB]; - for (i = 0; i < 16; i++) { - reg = hub->vm_context0_cntl + i; - tmp = RREG32(reg); - tmp |= bits; - WREG32(reg, tmp); - } - break; default: break; } @@ -499,7 +496,21 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) if (adev->mc.visible_vram_size > adev->mc.real_vram_size) adev->mc.visible_vram_size = adev->mc.real_vram_size; - amdgpu_gart_set_defaults(adev); + /* set the gart size */ + if (amdgpu_gart_size == -1) { + switch (adev->asic_type) { + case CHIP_VEGA10: /* all engines support GPUVM */ + default: + adev->mc.gart_size = 256ULL << 20; + break; + case CHIP_RAVEN: /* DCE SG support */ + adev->mc.gart_size = 1024ULL << 20; + break; + } + } else { + adev->mc.gart_size = (u64)amdgpu_gart_size << 20; + } + gmc_v9_0_vram_gtt_location(adev, &adev->mc); return 0; @@ -541,9 +552,10 @@ static int gmc_v9_0_sw_init(void *handle) adev->vm_manager.vm_size = 1U << 18; adev->vm_manager.block_size = 9; adev->vm_manager.num_level = 3; + amdgpu_vm_set_fragment_size(adev, 9); } else { - /* vm_size is 64GB for legacy 2-level page support*/ - amdgpu_vm_adjust_size(adev, 64); + /* vm_size is 64GB for legacy 2-level page support */ + amdgpu_vm_adjust_size(adev, 64, 9); adev->vm_manager.num_level = 1; } break; @@ -558,14 +570,16 @@ static int gmc_v9_0_sw_init(void *handle) adev->vm_manager.vm_size = 1U << 18; adev->vm_manager.block_size = 9; adev->vm_manager.num_level = 3; + amdgpu_vm_set_fragment_size(adev, 9); break; default: break; } - DRM_INFO("vm size is %llu GB, block size is %u-bit\n", + DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n", adev->vm_manager.vm_size, - adev->vm_manager.block_size); + adev->vm_manager.block_size, + adev->vm_manager.fragment_size); /* This interrupt is VMC page fault.*/ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, @@ -665,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_VEGA10: + amdgpu_program_register_sequence(adev, + golden_settings_mmhub_1_0_0, + (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0)); + amdgpu_program_register_sequence(adev, + golden_settings_athub_1_0_0, + (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); break; case CHIP_RAVEN: + amdgpu_program_register_sequence(adev, + golden_settings_athub_1_0_0, + (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); break; default: break; @@ -696,12 +719,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) if (r) return r; - /* After HDP is initialized, flush HDP.*/ - if (adev->flags & AMD_IS_APU) - nbio_v7_0_hdp_flush(adev); - else - nbio_v6_1_hdp_flush(adev); - switch (adev->asic_type) { case CHIP_RAVEN: mmhub_v1_0_initialize_power_gating(adev); @@ -719,13 +736,16 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) if (r) return r; - tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); - tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; - WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); + WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); + /* After HDP is initialized, flush HDP.*/ + if (adev->flags & AMD_IS_APU) + nbio_v7_0_hdp_flush(adev); + else + nbio_v6_1_hdp_flush(adev); if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) value = false; @@ -734,7 +754,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) gfxhub_v1_0_set_fault_enable_default(adev, value); mmhub_v1_0_set_fault_enable_default(adev, value); - gmc_v9_0_gart_flush_gpu_tlb(adev, 0); DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", @@ -753,17 +772,11 @@ static int gmc_v9_0_hw_init(void *handle) gmc_v9_0_init_golden_registers(adev); if (adev->mode_info.num_crtc) { - u32 tmp; - /* Lockout access through VGA aperture*/ - tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL); - tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); - WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp); + WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); /* disable VGA render */ - tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL); - tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); - WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp); + WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); } r = gmc_v9_0_gart_enable(adev); @@ -805,9 +818,7 @@ static int gmc_v9_0_suspend(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - gmc_v9_0_hw_fini(adev); - - return 0; + return gmc_v9_0_hw_fini(adev); } static int gmc_v9_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 7a0ea27ac429..65ed6d3a8f05 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -208,6 +208,19 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev) } /** + * iceland_ih_prescreen_iv - prescreen an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Returns true if the interrupt vector should be further processed. + */ +static bool iceland_ih_prescreen_iv(struct amdgpu_device *adev) +{ + /* Process all interrupts */ + return true; +} + +/** * iceland_ih_decode_iv - decode an interrupt vector * * @adev: amdgpu_device pointer @@ -412,6 +425,7 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = { static const struct amdgpu_ih_funcs iceland_ih_funcs = { .get_wptr = iceland_ih_get_wptr, + .prescreen_iv = iceland_ih_prescreen_iv, .decode_iv = iceland_ih_decode_iv, .set_rptr = iceland_ih_set_rptr }; diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 3bbf2ccfca89..b57399a462c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -42,7 +42,6 @@ #define KV_MINIMUM_ENGINE_CLOCK 800 #define SMC_RAM_END 0x40000 -static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev); static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev); static int kv_enable_nb_dpm(struct amdgpu_device *adev, bool enable); @@ -64,7 +63,7 @@ static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, int min_temp, int max_temp); static int kv_init_fps_limits(struct amdgpu_device *adev); -static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate); +static void kv_dpm_powergate_uvd(void *handle, bool gate); static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate); static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate); static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate); @@ -1245,8 +1244,9 @@ static void kv_update_requested_ps(struct amdgpu_device *adev, adev->pm.dpm.requested_ps = &pi->requested_rps; } -static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable) +static void kv_dpm_enable_bapm(void *handle, bool enable) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); int ret; @@ -1672,8 +1672,9 @@ static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) return kv_enable_acp_dpm(adev, !gate); } -static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) +static void kv_dpm_powergate_uvd(void *handle, bool gate) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); int ret; @@ -1868,10 +1869,11 @@ static int kv_enable_nb_dpm(struct amdgpu_device *adev, return ret; } -static int kv_dpm_force_performance_level(struct amdgpu_device *adev, +static int kv_dpm_force_performance_level(void *handle, enum amd_dpm_forced_level level) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (level == AMD_DPM_FORCED_LEVEL_HIGH) { ret = kv_force_dpm_highest(adev); @@ -1892,8 +1894,9 @@ static int kv_dpm_force_performance_level(struct amdgpu_device *adev, return 0; } -static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev) +static int kv_dpm_pre_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; struct amdgpu_ps *new_ps = &requested_ps; @@ -1907,8 +1910,9 @@ static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev) return 0; } -static int kv_dpm_set_power_state(struct amdgpu_device *adev) +static int kv_dpm_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); struct amdgpu_ps *new_ps = &pi->requested_rps; struct amdgpu_ps *old_ps = &pi->current_rps; @@ -1981,8 +1985,9 @@ static int kv_dpm_set_power_state(struct amdgpu_device *adev) return 0; } -static void kv_dpm_post_set_power_state(struct amdgpu_device *adev) +static void kv_dpm_post_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); struct amdgpu_ps *new_ps = &pi->requested_rps; @@ -2848,9 +2853,10 @@ static int kv_dpm_init(struct amdgpu_device *adev) } static void -kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, +kv_dpm_debugfs_print_current_performance_level(void *handle, struct seq_file *m) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); u32 current_index = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & @@ -2875,11 +2881,12 @@ kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, } static void -kv_dpm_print_power_state(struct amdgpu_device *adev, - struct amdgpu_ps *rps) +kv_dpm_print_power_state(void *handle, void *request_ps) { int i; + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; struct kv_ps *ps = kv_get_ps(rps); + struct amdgpu_device *adev = (struct amdgpu_device *)handle; amdgpu_dpm_print_class_info(rps->class, rps->class2); amdgpu_dpm_print_cap_info(rps->caps); @@ -2905,13 +2912,14 @@ static void kv_dpm_fini(struct amdgpu_device *adev) amdgpu_free_extended_power_table(adev); } -static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev) +static void kv_dpm_display_configuration_changed(void *handle) { } -static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low) +static u32 kv_dpm_get_sclk(void *handle, bool low) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); @@ -2921,18 +2929,20 @@ static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low) return requested_state->levels[requested_state->num_levels - 1].sclk; } -static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low) +static u32 kv_dpm_get_mclk(void *handle, bool low) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); return pi->sys_info.bootup_uma_clk; } /* get temperature in millidegrees */ -static int kv_dpm_get_temp(struct amdgpu_device *adev) +static int kv_dpm_get_temp(void *handle) { u32 temp; int actual_temp = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; temp = RREG32_SMC(0xC0300E0C); @@ -2950,7 +2960,6 @@ static int kv_dpm_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - kv_dpm_set_dpm_funcs(adev); kv_dpm_set_irq_funcs(adev); return 0; @@ -3222,14 +3231,17 @@ static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1, (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state)); } -static int kv_check_state_equal(struct amdgpu_device *adev, - struct amdgpu_ps *cps, - struct amdgpu_ps *rps, +static int kv_check_state_equal(void *handle, + void *current_ps, + void *request_ps, bool *equal) { struct kv_ps *kv_cps; struct kv_ps *kv_rps; int i; + struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) return -EINVAL; @@ -3262,9 +3274,10 @@ static int kv_check_state_equal(struct amdgpu_device *adev, return 0; } -static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx, +static int kv_dpm_read_sensor(void *handle, int idx, void *value, int *size) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct kv_power_info *pi = kv_get_pi(adev); uint32_t sclk; u32 pl_index = @@ -3312,7 +3325,7 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = { .set_powergating_state = kv_dpm_set_powergating_state, }; -static const struct amdgpu_dpm_funcs kv_dpm_funcs = { +const struct amd_pm_funcs kv_dpm_funcs = { .get_temperature = &kv_dpm_get_temp, .pre_set_power_state = &kv_dpm_pre_set_power_state, .set_power_state = &kv_dpm_set_power_state, @@ -3330,12 +3343,6 @@ static const struct amdgpu_dpm_funcs kv_dpm_funcs = { .read_sensor = &kv_dpm_read_sensor, }; -static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev) -{ - if (adev->pm.funcs == NULL) - adev->pm.funcs = &kv_dpm_funcs; -} - static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = { .set = kv_dpm_set_interrupt_state, .process = kv_dpm_process_interrupt, diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index ad8def3cc343..cc21c4bdec27 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -158,8 +158,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); tmp = mmVM_L2_CNTL3_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); tmp = mmVM_L2_CNTL4_DEFAULT; @@ -273,7 +273,7 @@ static const struct pctl_data pctl0_data[] = { {0x135, 0x12a810}, {0x149, 0x7a82c} }; -#define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0])) +#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data)) #define PCTL0_RENG_EXEC_END_PTR 0x151 #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640 @@ -309,7 +309,7 @@ static const struct pctl_data pctl1_data[] = { {0x1f0, 0x5000a7f6}, {0x1f1, 0x5000a7e4} }; -#define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0])) +#define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data)) #define PCTL1_RENG_EXEC_END_PTR 0x1f1 #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000 @@ -561,6 +561,13 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + if (!value) { + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_NO_RETRY_FAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + CRASH_ON_RETRY_FAULT, 1); + } + WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); } diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h index 1e91b9a1c591..67e78576a9eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h @@ -24,7 +24,7 @@ #ifndef __MXGPU_AI_H__ #define __MXGPU_AI_H__ -#define AI_MAILBOX_TIMEDOUT 5000 +#define AI_MAILBOX_TIMEDOUT 12000 enum idh_request { IDH_REQ_GPU_INIT_ACCESS = 1, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h index c791d73d2d54..f13dc6cc158f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h @@ -23,7 +23,7 @@ #ifndef __MXGPU_VI_H__ #define __MXGPU_VI_H__ -#define VI_MAILBOX_TIMEDOUT 5000 +#define VI_MAILBOX_TIMEDOUT 12000 #define VI_MAILBOX_RESET_TIME 12 /* VI mailbox messages request */ diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index f7cf994b1da2..dea7c909ca5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -35,6 +35,8 @@ #include "raven1/GC/gc_9_1_offset.h" #include "raven1/SDMA0/sdma0_4_1_offset.h" +MODULE_FIRMWARE("amdgpu/raven_asd.bin"); + static int psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) { @@ -136,15 +138,13 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm { int ret; uint64_t fw_mem_mc_addr = ucode->mc_addr; - struct common_firmware_header *header; memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); - header = (struct common_firmware_header *)ucode->fw; cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); - cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes); + cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); if (ret) @@ -209,7 +209,7 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type) return ret; } -int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) +int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type) { int ret = 0; struct psp_ring *ring; @@ -229,6 +229,19 @@ int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 0x80000000, 0x80000000, false); + return ret; +} + +int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) +{ + int ret = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + ret = psp_v10_0_ring_stop(psp, ring_type); + if (ret) + DRM_ERROR("Fail to stop psp ring\n"); + amdgpu_bo_free_kernel(&adev->firmware.rbuf, &ring->ring_mem_mc_addr, (void **)&ring->ring_mem); @@ -245,15 +258,20 @@ int psp_v10_0_cmd_submit(struct psp_context *psp, struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; struct psp_ring *ring = &psp->km_ring; struct amdgpu_device *adev = psp->adev; + uint32_t ring_size_dw = ring->ring_size / 4; + uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; /* KM (GPCOM) prepare write pointer */ psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); /* Update KM RB frame pointer to new frame */ - if ((psp_write_ptr_reg % ring->ring_size) == 0) + if ((psp_write_ptr_reg % ring_size_dw) == 0) write_frame = ring->ring_mem; else - write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4)); + write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw); + + /* Initialize KM RB frame */ + memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); /* Update KM RB frame */ write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); @@ -263,8 +281,7 @@ int psp_v10_0_cmd_submit(struct psp_context *psp, write_frame->fence_value = index; /* Update the write Pointer in DWORDs */ - psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4; - psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg; + psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); return 0; @@ -390,3 +407,10 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp, return true; } + + +int psp_v10_0_mode1_reset(struct psp_context *psp) +{ + DRM_INFO("psp mode 1 reset not supported now! \n"); + return -EINVAL; +} diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h index e76cde2f01f9..451e8308303f 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h @@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type); extern int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type); +extern int psp_v10_0_ring_stop(struct psp_context *psp, + enum psp_ring_type ring_type); extern int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type); extern int psp_v10_0_cmd_submit(struct psp_context *psp, @@ -43,4 +45,6 @@ extern int psp_v10_0_cmd_submit(struct psp_context *psp, extern bool psp_v10_0_compare_sram_data(struct psp_context *psp, struct amdgpu_firmware_info *ucode, enum AMDGPU_UCODE_ID ucode_type); + +extern int psp_v10_0_mode1_reset(struct psp_context *psp); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 2a535a4b8d5b..cee5c396b277 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -319,7 +319,7 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type) return ret; } -int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) +int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type) { int ret = 0; struct psp_ring *ring; @@ -339,6 +339,19 @@ int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 0x80000000, 0x80000000, false); + return ret; +} + +int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) +{ + int ret = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + ret = psp_v3_1_ring_stop(psp, ring_type); + if (ret) + DRM_ERROR("Fail to stop psp ring\n"); + amdgpu_bo_free_kernel(&adev->firmware.rbuf, &ring->ring_mem_mc_addr, (void **)&ring->ring_mem); @@ -517,3 +530,37 @@ bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; } + +int psp_v3_1_mode1_reset(struct psp_context *psp) +{ + int ret; + uint32_t offset; + struct amdgpu_device *adev = psp->adev; + + offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); + + ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); + + if (ret) { + DRM_INFO("psp is not working correctly before mode1 reset!\n"); + return -EINVAL; + } + + /*send the mode 1 reset command*/ + WREG32(offset, 0x70000); + + mdelay(1000); + + offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); + + ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); + + if (ret) { + DRM_INFO("psp mode 1 reset failed!\n"); + return -EINVAL; + } + + DRM_INFO("psp mode1 reset succeed \n"); + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h index 9dcd0b25c4c6..b05dbada7751 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h @@ -41,6 +41,8 @@ extern int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type); extern int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type); +extern int psp_v3_1_ring_stop(struct psp_context *psp, + enum psp_ring_type ring_type); extern int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type); extern int psp_v3_1_cmd_submit(struct psp_context *psp, @@ -51,4 +53,5 @@ extern bool psp_v3_1_compare_sram_data(struct psp_context *psp, struct amdgpu_firmware_info *ucode, enum AMDGPU_UCODE_ID ucode_type); extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp); +extern int psp_v3_1_mode1_reset(struct psp_context *psp); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index f2d0710258cb..acdee3a4602c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -1324,8 +1324,13 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) } static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { + .copy_pte_num_dw = 7, .copy_pte = sdma_v2_4_vm_copy_pte, + .write_pte = sdma_v2_4_vm_write_pte, + + .set_max_nums_pte_pde = 0x1fffff >> 3, + .set_pte_pde_num_dw = 10, .set_pte_pde = sdma_v2_4_vm_set_pte_pde, }; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index b1de44f22824..72f31cc7df00 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -379,8 +379,10 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring->use_doorbell) { + u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; + /* XXX check if swapping is necessary on BE */ - adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2; + WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); } else { int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; @@ -641,10 +643,11 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) { struct amdgpu_ring *ring; - u32 rb_cntl, ib_cntl; + u32 rb_cntl, ib_cntl, wptr_poll_cntl; u32 rb_bufsz; u32 wb_offset; u32 doorbell; + u64 wptr_gpu_addr; int i, j, r; for (i = 0; i < adev->sdma.num_instances; i++) { @@ -707,6 +710,20 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) } WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); + /* setup the wptr shadow polling */ + wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + + WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], + lower_32_bits(wptr_gpu_addr)); + WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], + upper_32_bits(wptr_gpu_addr)); + wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); + if (amdgpu_sriov_vf(adev)) + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); + else + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); + WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); + /* enable DMA RB */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); @@ -1713,11 +1730,11 @@ static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { - .copy_max_bytes = 0x1fffff, + .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ .copy_num_dw = 7, .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, - .fill_max_bytes = 0x1fffff, + .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ .fill_num_dw = 5, .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, }; @@ -1731,8 +1748,14 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) } static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, .copy_pte = sdma_v3_0_vm_copy_pte, + .write_pte = sdma_v3_0_vm_write_pte, + + /* not 0x3fffff due to HW limitation */ + .set_max_nums_pte_pde = 0x3fffe0 >> 3, + .set_pte_pde_num_dw = 10, .set_pte_pde = sdma_v3_0_vm_set_pte_pde, }; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index fd7c72aaafa6..c26d205ff3bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -54,7 +54,7 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); static const u32 golden_settings_sdma_4[] = { - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07, SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100, SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100, SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, @@ -89,7 +89,7 @@ static const u32 golden_settings_sdma_vg10[] = { static const u32 golden_settings_sdma_4_1[] = { - SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07, SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100, SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100, SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, @@ -398,7 +398,7 @@ static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0)); + amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE)); amdgpu_ring_write(ring, 1); } @@ -1264,6 +1264,11 @@ static int sdma_v4_0_sw_fini(void *handle) for (i = 0; i < adev->sdma.num_instances; i++) amdgpu_ring_fini(&adev->sdma.instance[i].ring); + for (i = 0; i < adev->sdma.num_instances; i++) { + release_firmware(adev->sdma.instance[i].fw); + adev->sdma.instance[i].fw = NULL; + } + return 0; } @@ -1714,8 +1719,13 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) } static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, .copy_pte = sdma_v4_0_vm_copy_pte, + .write_pte = sdma_v4_0_vm_write_pte, + + .set_max_nums_pte_pde = 0x400000 >> 3, + .set_pte_pde_num_dw = 10, .set_pte_pde = sdma_v4_0_vm_set_pte_pde, }; diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 112969f3301a..3fa2fbf8c9a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -887,8 +887,13 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) } static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { + .copy_pte_num_dw = 5, .copy_pte = si_dma_vm_copy_pte, + .write_pte = si_dma_vm_write_pte, + + .set_max_nums_pte_pde = 0xffff8 >> 3, + .set_pte_pde_num_dw = 9, .set_pte_pde = si_dma_vm_set_pte_pde, }; diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index d63873f3f574..9b8db6046271 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -1847,7 +1847,6 @@ static int si_calculate_sclk_params(struct amdgpu_device *adev, static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); -static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev); static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); static struct si_power_info *si_get_pi(struct amdgpu_device *adev) @@ -3060,9 +3059,9 @@ static int si_get_vce_clock_voltage(struct amdgpu_device *adev, return ret; } -static bool si_dpm_vblank_too_short(struct amdgpu_device *adev) +static bool si_dpm_vblank_too_short(void *handle) { - + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); /* we never hit the non-gddr5 limit so disable it */ u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; @@ -3871,9 +3870,10 @@ static int si_restrict_performance_levels_before_switch(struct amdgpu_device *ad 0 : -EINVAL; } -static int si_dpm_force_performance_level(struct amdgpu_device *adev, +static int si_dpm_force_performance_level(void *handle, enum amd_dpm_forced_level level) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ps *rps = adev->pm.dpm.current_ps; struct si_ps *ps = si_get_ps(rps); u32 levels = ps->performance_level_count; @@ -6575,11 +6575,12 @@ static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) } } -static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev, +static int si_dpm_get_fan_speed_percent(void *handle, u32 *speed) { u32 duty, duty100; u64 tmp64; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->pm.no_fan) return -ENOENT; @@ -6600,9 +6601,10 @@ static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev, return 0; } -static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev, +static int si_dpm_set_fan_speed_percent(void *handle, u32 speed) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct si_power_info *si_pi = si_get_pi(adev); u32 tmp; u32 duty, duty100; @@ -6633,8 +6635,10 @@ static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev, return 0; } -static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) +static void si_dpm_set_fan_control_mode(void *handle, u32 mode) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (mode) { /* stop auto-manage */ if (adev->pm.dpm.fan.ucode_fan_control) @@ -6649,8 +6653,9 @@ static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) } } -static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev) +static u32 si_dpm_get_fan_control_mode(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct si_power_info *si_pi = si_get_pi(adev); u32 tmp; @@ -6946,8 +6951,9 @@ static void si_dpm_disable(struct amdgpu_device *adev) ni_update_current_ps(adev, boot_ps); } -static int si_dpm_pre_set_power_state(struct amdgpu_device *adev) +static int si_dpm_pre_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; struct amdgpu_ps *new_ps = &requested_ps; @@ -6984,8 +6990,9 @@ static int si_power_control_set_level(struct amdgpu_device *adev) return 0; } -static int si_dpm_set_power_state(struct amdgpu_device *adev) +static int si_dpm_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct amdgpu_ps *new_ps = &eg_pi->requested_rps; struct amdgpu_ps *old_ps = &eg_pi->current_rps; @@ -7086,8 +7093,9 @@ static int si_dpm_set_power_state(struct amdgpu_device *adev) return 0; } -static void si_dpm_post_set_power_state(struct amdgpu_device *adev) +static void si_dpm_post_set_power_state(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct amdgpu_ps *new_ps = &eg_pi->requested_rps; @@ -7103,8 +7111,10 @@ void si_dpm_reset_asic(struct amdgpu_device *adev) } #endif -static void si_dpm_display_configuration_changed(struct amdgpu_device *adev) +static void si_dpm_display_configuration_changed(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + si_program_display_gap(adev); } @@ -7486,9 +7496,10 @@ static void si_dpm_fini(struct amdgpu_device *adev) amdgpu_free_extended_power_table(adev); } -static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, +static void si_dpm_debugfs_print_current_performance_level(void *handle, struct seq_file *m) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct amdgpu_ps *rps = &eg_pi->current_rps; struct si_ps *ps = si_get_ps(rps); @@ -7860,10 +7871,11 @@ static int si_dpm_set_powergating_state(void *handle, } /* get temperature in millidegrees */ -static int si_dpm_get_temp(struct amdgpu_device *adev) +static int si_dpm_get_temp(void *handle) { u32 temp; int actual_temp = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> CTF_TEMP_SHIFT; @@ -7878,8 +7890,9 @@ static int si_dpm_get_temp(struct amdgpu_device *adev) return actual_temp; } -static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low) +static u32 si_dpm_get_sclk(void *handle, bool low) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); @@ -7889,8 +7902,9 @@ static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low) return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; } -static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low) +static u32 si_dpm_get_mclk(void *handle, bool low) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); @@ -7900,9 +7914,11 @@ static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low) return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; } -static void si_dpm_print_power_state(struct amdgpu_device *adev, - struct amdgpu_ps *rps) +static void si_dpm_print_power_state(void *handle, + void *current_ps) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; struct si_ps *ps = si_get_ps(rps); struct rv7xx_pl *pl; int i; @@ -7927,7 +7943,6 @@ static int si_dpm_early_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; - si_dpm_set_dpm_funcs(adev); si_dpm_set_irq_funcs(adev); return 0; } @@ -7942,20 +7957,23 @@ static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, (si_cpl1->vddci == si_cpl2->vddci)); } -static int si_check_state_equal(struct amdgpu_device *adev, - struct amdgpu_ps *cps, - struct amdgpu_ps *rps, +static int si_check_state_equal(void *handle, + void *current_ps, + void *request_ps, bool *equal) { struct si_ps *si_cps; struct si_ps *si_rps; int i; + struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; + struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) return -EINVAL; - si_cps = si_get_ps(cps); - si_rps = si_get_ps(rps); + si_cps = si_get_ps((struct amdgpu_ps *)cps); + si_rps = si_get_ps((struct amdgpu_ps *)rps); if (si_cps == NULL) { printk("si_cps is NULL\n"); @@ -7983,9 +8001,10 @@ static int si_check_state_equal(struct amdgpu_device *adev, return 0; } -static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx, +static int si_dpm_read_sensor(void *handle, int idx, void *value, int *size) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); struct amdgpu_ps *rps = &eg_pi->current_rps; struct si_ps *ps = si_get_ps(rps); @@ -8041,7 +8060,7 @@ const struct amd_ip_funcs si_dpm_ip_funcs = { .set_powergating_state = si_dpm_set_powergating_state, }; -static const struct amdgpu_dpm_funcs si_dpm_funcs = { +const struct amd_pm_funcs si_dpm_funcs = { .get_temperature = &si_dpm_get_temp, .pre_set_power_state = &si_dpm_pre_set_power_state, .set_power_state = &si_dpm_set_power_state, @@ -8062,12 +8081,6 @@ static const struct amdgpu_dpm_funcs si_dpm_funcs = { .read_sensor = &si_dpm_read_sensor, }; -static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev) -{ - if (adev->pm.funcs == NULL) - adev->pm.funcs = &si_dpm_funcs; -} - static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { .set = si_dpm_set_interrupt_state, .process = si_dpm_process_interrupt, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.h b/drivers/gpu/drm/amd/amdgpu/si_dpm.h index 51ce21c5f4fb..9fe343de3477 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.h @@ -246,6 +246,7 @@ enum si_display_gap }; extern const struct amd_ip_funcs si_dpm_ip_funcs; +extern const struct amd_pm_funcs si_dpm_funcs; struct ni_leakage_coeffients { diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index ce25e03a077d..d2c6b80309c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -118,6 +118,19 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev) return (wptr & adev->irq.ih.ptr_mask); } +/** + * si_ih_prescreen_iv - prescreen an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Returns true if the interrupt vector should be further processed. + */ +static bool si_ih_prescreen_iv(struct amdgpu_device *adev) +{ + /* Process all interrupts */ + return true; +} + static void si_ih_decode_iv(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { @@ -288,6 +301,7 @@ static const struct amd_ip_funcs si_ih_ip_funcs = { static const struct amdgpu_ih_funcs si_ih_funcs = { .get_wptr = si_ih_get_wptr, + .prescreen_iv = si_ih_prescreen_iv, .decode_iv = si_ih_decode_iv, .set_rptr = si_ih_set_rptr }; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f2c3a49f73a0..245a18aeb389 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -407,18 +407,27 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, return -EINVAL; } -static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev) +static int soc15_asic_reset(struct amdgpu_device *adev) { u32 i; - dev_info(adev->dev, "GPU pci config reset\n"); + amdgpu_atombios_scratch_regs_engine_hung(adev, true); + + dev_info(adev->dev, "GPU reset\n"); /* disable BM */ pci_clear_master(adev->pdev); - /* reset */ - amdgpu_pci_config_reset(adev); - udelay(100); + pci_save_state(adev->pdev); + + for (i = 0; i < AMDGPU_MAX_IP_NUM; i++) { + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP){ + adev->ip_blocks[i].version->funcs->soft_reset((void *)adev); + break; + } + } + + pci_restore_state(adev->pdev); /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { @@ -430,14 +439,6 @@ static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev) udelay(1); } -} - -static int soc15_asic_reset(struct amdgpu_device *adev) -{ - amdgpu_atombios_scratch_regs_engine_hung(adev, true); - - soc15_gpu_pci_config_reset(adev); - amdgpu_atombios_scratch_regs_engine_hung(adev, false); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index e79befd80eed..7f408f85fdb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -250,6 +250,7 @@ #define PACKET3_SET_UCONFIG_REG 0x79 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28) #define PACKET3_SCRATCH_RAM_WRITE 0x7D #define PACKET3_SCRATCH_RAM_READ 0x7E #define PACKET3_LOAD_CONST_RAM 0x80 diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 923df2c0e535..5ed00692618e 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -219,6 +219,19 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev) } /** + * tonga_ih_prescreen_iv - prescreen an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Returns true if the interrupt vector should be further processed. + */ +static bool tonga_ih_prescreen_iv(struct amdgpu_device *adev) +{ + /* Process all interrupts */ + return true; +} + +/** * tonga_ih_decode_iv - decode an interrupt vector * * @adev: amdgpu_device pointer @@ -478,6 +491,7 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = { static const struct amdgpu_ih_funcs tonga_ih_funcs = { .get_wptr = tonga_ih_get_wptr, + .prescreen_iv = tonga_ih_prescreen_iv, .decode_iv = tonga_ih_decode_iv, .set_rptr = tonga_ih_set_rptr }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 23a85750edd6..b8ed8faf2003 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1161,7 +1161,7 @@ static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) */ static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { - amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0)); + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); amdgpu_ring_write(ring, 1); } diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 11134d5f7443..75745544600a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -1011,10 +1011,6 @@ static int vce_v4_0_process_interrupt(struct amdgpu_device *adev, { DRM_DEBUG("IH: VCE\n"); - WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_STATUS), - VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK, - ~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK); - switch (entry->src_data[0]) { case 0: case 1: diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 21e7b88401e1..1eb4d79d6e30 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -812,7 +812,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 */ static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { - amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0)); + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); amdgpu_ring_write(ring, 1); } diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 56150e8d1ed2..a3b30d84dbb3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -219,14 +219,92 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev) wptr, adev->irq.ih.rptr, tmp); adev->irq.ih.rptr = tmp; - tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); + WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); } return (wptr & adev->irq.ih.ptr_mask); } /** + * vega10_ih_prescreen_iv - prescreen an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Returns true if the interrupt vector should be further processed. + */ +static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev) +{ + u32 ring_index = adev->irq.ih.rptr >> 2; + u32 dw0, dw3, dw4, dw5; + u16 pasid; + u64 addr, key; + struct amdgpu_vm *vm; + int r; + + dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); + dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]); + dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]); + + /* Filter retry page faults, let only the first one pass. If + * there are too many outstanding faults, ignore them until + * some faults get cleared. + */ + switch (dw0 & 0xff) { + case AMDGPU_IH_CLIENTID_VMC: + case AMDGPU_IH_CLIENTID_UTCL2: + break; + default: + /* Not a VM fault */ + return true; + } + + /* Not a retry fault */ + if (!(dw5 & 0x80)) + return true; + + pasid = dw3 & 0xffff; + /* No PASID, can't identify faulting process */ + if (!pasid) + return true; + + addr = ((u64)(dw5 & 0xf) << 44) | ((u64)dw4 << 12); + key = AMDGPU_VM_FAULT(pasid, addr); + r = amdgpu_ih_add_fault(adev, key); + + /* Hash table is full or the fault is already being processed, + * ignore further page faults + */ + if (r != 0) + goto ignore_iv; + + /* Track retry faults in per-VM fault FIFO. */ + spin_lock(&adev->vm_manager.pasid_lock); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); + spin_unlock(&adev->vm_manager.pasid_lock); + if (WARN_ON_ONCE(!vm)) { + /* VM not found, process it normally */ + amdgpu_ih_clear_fault(adev, key); + return true; + } + /* No locking required with single writer and single reader */ + r = kfifo_put(&vm->faults, key); + if (!r) { + /* FIFO is full. Ignore it until there is space */ + amdgpu_ih_clear_fault(adev, key); + goto ignore_iv; + } + + /* It's the first fault for this address, process it normally */ + return true; + +ignore_iv: + adev->irq.ih.rptr += 32; + return false; +} + +/** * vega10_ih_decode_iv - decode an interrupt vector * * @adev: amdgpu_device pointer @@ -310,6 +388,14 @@ static int vega10_ih_sw_init(void *handle) adev->irq.ih.use_doorbell = true; adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1; + adev->irq.ih.faults = kmalloc(sizeof(*adev->irq.ih.faults), GFP_KERNEL); + if (!adev->irq.ih.faults) + return -ENOMEM; + INIT_CHASH_TABLE(adev->irq.ih.faults->hash, + AMDGPU_PAGEFAULT_HASH_BITS, 8, 0); + spin_lock_init(&adev->irq.ih.faults->lock); + adev->irq.ih.faults->count = 0; + r = amdgpu_irq_init(adev); return r; @@ -322,6 +408,9 @@ static int vega10_ih_sw_fini(void *handle) amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); + kfree(adev->irq.ih.faults); + adev->irq.ih.faults = NULL; + return 0; } @@ -410,6 +499,7 @@ const struct amd_ip_funcs vega10_ih_ip_funcs = { static const struct amdgpu_ih_funcs vega10_ih_funcs = { .get_wptr = vega10_ih_get_wptr, + .prescreen_iv = vega10_ih_prescreen_iv, .decode_iv = vega10_ih_decode_iv, .set_rptr = vega10_ih_set_rptr }; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 6cac291c96da..9ff69b90df36 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1028,8 +1028,7 @@ static int vi_common_early_init(void *handle) /* rev0 hardware requires workarounds to support PG */ adev->pg_flags = 0; if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { - adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | - AMD_PG_SUPPORT_GFX_SMG | + adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | AMD_PG_SUPPORT_GFX_PIPELINE | AMD_PG_SUPPORT_CP | AMD_PG_SUPPORT_UVD | diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6316aad43a73..660b3fbade41 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -142,12 +142,12 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, struct kfd_ioctl_create_queue_args *args) { if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { - pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); + pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); return -EINVAL; } if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { - pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); + pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); return -EINVAL; } @@ -155,26 +155,26 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, (!access_ok(VERIFY_WRITE, (const void __user *) args->ring_base_address, sizeof(uint64_t)))) { - pr_err("kfd: can't access ring base address\n"); + pr_err("Can't access ring base address\n"); return -EFAULT; } if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { - pr_err("kfd: ring size must be a power of 2 or 0\n"); + pr_err("Ring size must be a power of 2 or 0\n"); return -EINVAL; } if (!access_ok(VERIFY_WRITE, (const void __user *) args->read_pointer_address, sizeof(uint32_t))) { - pr_err("kfd: can't access read pointer\n"); + pr_err("Can't access read pointer\n"); return -EFAULT; } if (!access_ok(VERIFY_WRITE, (const void __user *) args->write_pointer_address, sizeof(uint32_t))) { - pr_err("kfd: can't access write pointer\n"); + pr_err("Can't access write pointer\n"); return -EFAULT; } @@ -182,7 +182,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, !access_ok(VERIFY_WRITE, (const void __user *) args->eop_buffer_address, sizeof(uint32_t))) { - pr_debug("kfd: can't access eop buffer"); + pr_debug("Can't access eop buffer"); return -EFAULT; } @@ -190,7 +190,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, !access_ok(VERIFY_WRITE, (const void __user *) args->ctx_save_restore_address, sizeof(uint32_t))) { - pr_debug("kfd: can't access ctx save restore buffer"); + pr_debug("Can't access ctx save restore buffer"); return -EFAULT; } @@ -219,27 +219,27 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, else q_properties->format = KFD_QUEUE_FORMAT_PM4; - pr_debug("Queue Percentage (%d, %d)\n", + pr_debug("Queue Percentage: %d, %d\n", q_properties->queue_percent, args->queue_percentage); - pr_debug("Queue Priority (%d, %d)\n", + pr_debug("Queue Priority: %d, %d\n", q_properties->priority, args->queue_priority); - pr_debug("Queue Address (0x%llX, 0x%llX)\n", + pr_debug("Queue Address: 0x%llX, 0x%llX\n", q_properties->queue_address, args->ring_base_address); - pr_debug("Queue Size (0x%llX, %u)\n", + pr_debug("Queue Size: 0x%llX, %u\n", q_properties->queue_size, args->ring_size); - pr_debug("Queue r/w Pointers (0x%llX, 0x%llX)\n", - (uint64_t) q_properties->read_ptr, - (uint64_t) q_properties->write_ptr); + pr_debug("Queue r/w Pointers: %p, %p\n", + q_properties->read_ptr, + q_properties->write_ptr); - pr_debug("Queue Format (%d)\n", q_properties->format); + pr_debug("Queue Format: %d\n", q_properties->format); - pr_debug("Queue EOP (0x%llX)\n", q_properties->eop_ring_buffer_address); + pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); - pr_debug("Queue CTX save arex (0x%llX)\n", + pr_debug("Queue CTX save area: 0x%llX\n", q_properties->ctx_save_restore_area_address); return 0; @@ -257,16 +257,16 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, memset(&q_properties, 0, sizeof(struct queue_properties)); - pr_debug("kfd: creating queue ioctl\n"); + pr_debug("Creating queue ioctl\n"); err = set_queue_properties_from_user(&q_properties, args); if (err) return err; - pr_debug("kfd: looking for gpu id 0x%x\n", args->gpu_id); + pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) { - pr_debug("kfd: gpu id 0x%x was not found\n", args->gpu_id); + if (!dev) { + pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); return -EINVAL; } @@ -278,7 +278,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, goto err_bind_process; } - pr_debug("kfd: creating queue for PASID %d on GPU 0x%x\n", + pr_debug("Creating queue for PASID %d on gpu 0x%x\n", p->pasid, dev->id); @@ -296,15 +296,15 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, mutex_unlock(&p->mutex); - pr_debug("kfd: queue id %d was created successfully\n", args->queue_id); + pr_debug("Queue id %d was created successfully\n", args->queue_id); - pr_debug("ring buffer address == 0x%016llX\n", + pr_debug("Ring buffer address == 0x%016llX\n", args->ring_base_address); - pr_debug("read ptr address == 0x%016llX\n", + pr_debug("Read ptr address == 0x%016llX\n", args->read_pointer_address); - pr_debug("write ptr address == 0x%016llX\n", + pr_debug("Write ptr address == 0x%016llX\n", args->write_pointer_address); return 0; @@ -321,7 +321,7 @@ static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, int retval; struct kfd_ioctl_destroy_queue_args *args = data; - pr_debug("kfd: destroying queue id %d for PASID %d\n", + pr_debug("Destroying queue id %d for pasid %d\n", args->queue_id, p->pasid); @@ -341,12 +341,12 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, struct queue_properties properties; if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { - pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); + pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); return -EINVAL; } if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { - pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); + pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); return -EINVAL; } @@ -354,12 +354,12 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, (!access_ok(VERIFY_WRITE, (const void __user *) args->ring_base_address, sizeof(uint64_t)))) { - pr_err("kfd: can't access ring base address\n"); + pr_err("Can't access ring base address\n"); return -EFAULT; } if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { - pr_err("kfd: ring size must be a power of 2 or 0\n"); + pr_err("Ring size must be a power of 2 or 0\n"); return -EINVAL; } @@ -368,7 +368,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, properties.queue_percent = args->queue_percentage; properties.priority = args->queue_priority; - pr_debug("kfd: updating queue id %d for PASID %d\n", + pr_debug("Updating queue id %d for pasid %d\n", args->queue_id, p->pasid); mutex_lock(&p->mutex); @@ -400,7 +400,7 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, } dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; mutex_lock(&p->mutex); @@ -443,7 +443,7 @@ static int kfd_ioctl_dbg_register(struct file *filep, long status = 0; dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -460,12 +460,11 @@ static int kfd_ioctl_dbg_register(struct file *filep, */ pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { - mutex_unlock(&p->mutex); - mutex_unlock(kfd_get_dbgmgr_mutex()); - return PTR_ERR(pdd); + status = PTR_ERR(pdd); + goto out; } - if (dev->dbgmgr == NULL) { + if (!dev->dbgmgr) { /* In case of a legal call, we have no dbgmgr yet */ create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev); if (create_ok) { @@ -480,6 +479,7 @@ static int kfd_ioctl_dbg_register(struct file *filep, status = -EINVAL; } +out: mutex_unlock(&p->mutex); mutex_unlock(kfd_get_dbgmgr_mutex()); @@ -494,7 +494,7 @@ static int kfd_ioctl_dbg_unregister(struct file *filep, long status; dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -505,7 +505,7 @@ static int kfd_ioctl_dbg_unregister(struct file *filep, mutex_lock(kfd_get_dbgmgr_mutex()); status = kfd_dbgmgr_unregister(dev->dbgmgr, p); - if (status == 0) { + if (!status) { kfd_dbgmgr_destroy(dev->dbgmgr); dev->dbgmgr = NULL; } @@ -539,7 +539,7 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info)); dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -580,8 +580,8 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points; if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) { - kfree(args_buff); - return -EINVAL; + status = -EINVAL; + goto out; } watch_mask_value = (uint64_t) args_buff[args_idx]; @@ -604,8 +604,8 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, } if (args_idx >= args->buf_size_in_bytes - sizeof(args)) { - kfree(args_buff); - return -EINVAL; + status = -EINVAL; + goto out; } /* Currently HSA Event is not supported for DBG */ @@ -617,6 +617,7 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, mutex_unlock(kfd_get_dbgmgr_mutex()); +out: kfree(args_buff); return status; @@ -646,7 +647,7 @@ static int kfd_ioctl_dbg_wave_control(struct file *filep, sizeof(wac_info.trapId); dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -782,8 +783,9 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, "scratch_limit %llX\n", pdd->scratch_limit); args->num_of_nodes++; - } while ((pdd = kfd_get_next_process_device_data(p, pdd)) != NULL && - (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS)); + + pdd = kfd_get_next_process_device_data(p, pdd); + } while (pdd && (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS)); } mutex_unlock(&p->mutex); @@ -846,9 +848,86 @@ static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, return err; } +static int kfd_ioctl_set_scratch_backing_va(struct file *filep, + struct kfd_process *p, void *data) +{ + struct kfd_ioctl_set_scratch_backing_va_args *args = data; + struct kfd_process_device *pdd; + struct kfd_dev *dev; + long err; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + mutex_lock(&p->mutex); + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + err = PTR_ERR(pdd); + goto bind_process_to_device_fail; + } + + pdd->qpd.sh_hidden_private_base = args->va_addr; + + mutex_unlock(&p->mutex); + + if (sched_policy == KFD_SCHED_POLICY_NO_HWS && pdd->qpd.vmid != 0) + dev->kfd2kgd->set_scratch_backing_va( + dev->kgd, args->va_addr, pdd->qpd.vmid); + + return 0; + +bind_process_to_device_fail: + mutex_unlock(&p->mutex); + return err; +} + +static int kfd_ioctl_get_tile_config(struct file *filep, + struct kfd_process *p, void *data) +{ + struct kfd_ioctl_get_tile_config_args *args = data; + struct kfd_dev *dev; + struct tile_config config; + int err = 0; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + dev->kfd2kgd->get_tile_config(dev->kgd, &config); + + args->gb_addr_config = config.gb_addr_config; + args->num_banks = config.num_banks; + args->num_ranks = config.num_ranks; + + if (args->num_tile_configs > config.num_tile_configs) + args->num_tile_configs = config.num_tile_configs; + err = copy_to_user((void __user *)args->tile_config_ptr, + config.tile_config_ptr, + args->num_tile_configs * sizeof(uint32_t)); + if (err) { + args->num_tile_configs = 0; + return -EFAULT; + } + + if (args->num_macro_tile_configs > config.num_macro_tile_configs) + args->num_macro_tile_configs = + config.num_macro_tile_configs; + err = copy_to_user((void __user *)args->macro_tile_config_ptr, + config.macro_tile_config_ptr, + args->num_macro_tile_configs * sizeof(uint32_t)); + if (err) { + args->num_macro_tile_configs = 0; + return -EFAULT; + } + + return 0; +} #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ - [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl} + [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ + .cmd_drv = 0, .name = #ioctl} /** Ioctl table */ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { @@ -899,6 +978,12 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL, kfd_ioctl_dbg_wave_control, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, + kfd_ioctl_set_scratch_backing_va, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, + kfd_ioctl_get_tile_config, 0) }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index d5e19b5fbbfb..0aa021aa0aa1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -42,8 +42,6 @@ static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev) { - BUG_ON(!dev || !dev->kfd2kgd); - dev->kfd2kgd->address_watch_disable(dev->kgd); } @@ -62,7 +60,8 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, unsigned int *ib_packet_buff; int status; - BUG_ON(!dbgdev || !dbgdev->kq || !packet_buff || !size_in_bytes); + if (WARN_ON(!size_in_bytes)) + return -EINVAL; kq = dbgdev->kq; @@ -77,8 +76,8 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, status = kq->ops.acquire_packet_buffer(kq, pq_packets_size_in_bytes / sizeof(uint32_t), &ib_packet_buff); - if (status != 0) { - pr_err("amdkfd: acquire_packet_buffer failed\n"); + if (status) { + pr_err("acquire_packet_buffer failed\n"); return status; } @@ -115,8 +114,8 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, status = kfd_gtt_sa_allocate(dbgdev->dev, sizeof(uint64_t), &mem_obj); - if (status != 0) { - pr_err("amdkfd: Failed to allocate GART memory\n"); + if (status) { + pr_err("Failed to allocate GART memory\n"); kq->ops.rollback_packet(kq); return status; } @@ -168,8 +167,6 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, static int dbgdev_register_nodiq(struct kfd_dbgdev *dbgdev) { - BUG_ON(!dbgdev); - /* * no action is needed in this case, * just make sure diq will not be used @@ -187,14 +184,12 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev) struct kernel_queue *kq = NULL; int status; - BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->dev); - status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL, &properties, 0, KFD_QUEUE_TYPE_DIQ, &qid); if (status) { - pr_err("amdkfd: Failed to create DIQ\n"); + pr_err("Failed to create DIQ\n"); return status; } @@ -202,8 +197,8 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev) kq = pqm_get_kernel_queue(dbgdev->pqm, qid); - if (kq == NULL) { - pr_err("amdkfd: Error getting DIQ\n"); + if (!kq) { + pr_err("Error getting DIQ\n"); pqm_destroy_queue(dbgdev->pqm, qid); return -EFAULT; } @@ -215,8 +210,6 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev) static int dbgdev_unregister_nodiq(struct kfd_dbgdev *dbgdev) { - BUG_ON(!dbgdev || !dbgdev->dev); - /* disable watch address */ dbgdev_address_watch_disable_nodiq(dbgdev->dev); return 0; @@ -227,8 +220,6 @@ static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev) /* todo - disable address watch */ int status; - BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->kq); - status = pqm_destroy_queue(dbgdev->pqm, dbgdev->kq->queue->properties.queue_id); dbgdev->kq = NULL; @@ -245,14 +236,12 @@ static void dbgdev_address_watch_set_registers( { union ULARGE_INTEGER addr; - BUG_ON(!adw_info || !addrHi || !addrLo || !cntl); - addr.quad_part = 0; addrHi->u32All = 0; addrLo->u32All = 0; cntl->u32All = 0; - if (adw_info->watch_mask != NULL) + if (adw_info->watch_mask) cntl->bitfields.mask = (uint32_t) (adw_info->watch_mask[index] & ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK); @@ -279,7 +268,7 @@ static void dbgdev_address_watch_set_registers( } static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, - struct dbg_address_watch_info *adw_info) + struct dbg_address_watch_info *adw_info) { union TCP_WATCH_ADDR_H_BITS addrHi; union TCP_WATCH_ADDR_L_BITS addrLo; @@ -287,13 +276,11 @@ static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, struct kfd_process_device *pdd; unsigned int i; - BUG_ON(!dbgdev || !dbgdev->dev || !adw_info); - /* taking the vmid for that process on the safe way using pdd */ pdd = kfd_get_process_device_data(dbgdev->dev, adw_info->process); if (!pdd) { - pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n"); + pr_err("Failed to get pdd for wave control no DIQ\n"); return -EFAULT; } @@ -303,17 +290,16 @@ static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) || (adw_info->num_watch_points == 0)) { - pr_err("amdkfd: num_watch_points is invalid\n"); + pr_err("num_watch_points is invalid\n"); return -EINVAL; } - if ((adw_info->watch_mode == NULL) || - (adw_info->watch_address == NULL)) { - pr_err("amdkfd: adw_info fields are not valid\n"); + if (!adw_info->watch_mode || !adw_info->watch_address) { + pr_err("adw_info fields are not valid\n"); return -EINVAL; } - for (i = 0 ; i < adw_info->num_watch_points ; i++) { + for (i = 0; i < adw_info->num_watch_points; i++) { dbgdev_address_watch_set_registers(adw_info, &addrHi, &addrLo, &cntl, i, pdd->qpd.vmid); @@ -348,7 +334,7 @@ static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, } static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, - struct dbg_address_watch_info *adw_info) + struct dbg_address_watch_info *adw_info) { struct pm4__set_config_reg *packets_vec; union TCP_WATCH_ADDR_H_BITS addrHi; @@ -363,28 +349,25 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, /* we do not control the vmid in DIQ mode, just a place holder */ unsigned int vmid = 0; - BUG_ON(!dbgdev || !dbgdev->dev || !adw_info); - addrHi.u32All = 0; addrLo.u32All = 0; cntl.u32All = 0; if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) || (adw_info->num_watch_points == 0)) { - pr_err("amdkfd: num_watch_points is invalid\n"); + pr_err("num_watch_points is invalid\n"); return -EINVAL; } - if ((NULL == adw_info->watch_mode) || - (NULL == adw_info->watch_address)) { - pr_err("amdkfd: adw_info fields are not valid\n"); + if (!adw_info->watch_mode || !adw_info->watch_address) { + pr_err("adw_info fields are not valid\n"); return -EINVAL; } status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj); - if (status != 0) { - pr_err("amdkfd: Failed to allocate GART memory\n"); + if (status) { + pr_err("Failed to allocate GART memory\n"); return status; } @@ -442,8 +425,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_CNTL); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[0].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; @@ -455,8 +436,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_ADDR_HI); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[1].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[1].reg_data[0] = addrHi.u32All; @@ -467,8 +446,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_ADDR_LO); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[2].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[2].reg_data[0] = addrLo.u32All; @@ -485,8 +462,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_CNTL); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[3].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[3].reg_data[0] = cntl.u32All; @@ -498,8 +473,8 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, packet_buff_uint, ib_size); - if (status != 0) { - pr_err("amdkfd: Failed to submit IB to DIQ\n"); + if (status) { + pr_err("Failed to submit IB to DIQ\n"); break; } } @@ -518,8 +493,6 @@ static int dbgdev_wave_control_set_registers( union GRBM_GFX_INDEX_BITS reg_gfx_index; struct HsaDbgWaveMsgAMDGen2 *pMsg; - BUG_ON(!wac_info || !in_reg_sq_cmd || !in_reg_gfx_index); - reg_sq_cmd.u32All = 0; reg_gfx_index.u32All = 0; pMsg = &wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2; @@ -620,18 +593,16 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, struct pm4__set_config_reg *packets_vec; size_t ib_size = sizeof(struct pm4__set_config_reg) * 3; - BUG_ON(!dbgdev || !wac_info); - reg_sq_cmd.u32All = 0; status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd, ®_gfx_index); if (status) { - pr_err("amdkfd: Failed to set wave control registers\n"); + pr_err("Failed to set wave control registers\n"); return status; } - /* we do not control the VMID in DIQ,so reset it to a known value */ + /* we do not control the VMID in DIQ, so reset it to a known value */ reg_sq_cmd.bits.vm_id = 0; pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); @@ -667,7 +638,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj); if (status != 0) { - pr_err("amdkfd: Failed to allocate GART memory\n"); + pr_err("Failed to allocate GART memory\n"); return status; } @@ -719,8 +690,8 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, packet_buff_uint, ib_size); - if (status != 0) - pr_err("amdkfd: Failed to submit IB to DIQ\n"); + if (status) + pr_err("Failed to submit IB to DIQ\n"); kfd_gtt_sa_free(dbgdev->dev, mem_obj); @@ -735,21 +706,19 @@ static int dbgdev_wave_control_nodiq(struct kfd_dbgdev *dbgdev, union GRBM_GFX_INDEX_BITS reg_gfx_index; struct kfd_process_device *pdd; - BUG_ON(!dbgdev || !dbgdev->dev || !wac_info); - reg_sq_cmd.u32All = 0; /* taking the VMID for that process on the safe way using PDD */ pdd = kfd_get_process_device_data(dbgdev->dev, wac_info->process); if (!pdd) { - pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n"); + pr_err("Failed to get pdd for wave control no DIQ\n"); return -EFAULT; } status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd, ®_gfx_index); if (status) { - pr_err("amdkfd: Failed to set wave control registers\n"); + pr_err("Failed to set wave control registers\n"); return status; } @@ -818,12 +787,13 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. * ATC_VMID15_PASID_MAPPING - * to check which VMID the current process is mapped to. */ + * to check which VMID the current process is mapped to. + */ for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid (dev->kgd, vmid)) { - if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid + if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid (dev->kgd, vmid) == p->pasid) { pr_debug("Killing wave fronts of vmid %d and pasid %d\n", vmid, p->pasid); @@ -833,7 +803,7 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) } if (vmid > last_vmid_to_scan) { - pr_err("amdkfd: didn't found vmid for pasid (%d)\n", p->pasid); + pr_err("Didn't find vmid for pasid %d\n", p->pasid); return -EFAULT; } @@ -860,8 +830,6 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, enum DBGDEV_TYPE type) { - BUG_ON(!pdbgdev || !pdev); - pdbgdev->dev = pdev; pdbgdev->kq = NULL; pdbgdev->type = type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c index 56d676396342..3da25f7bda6b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c @@ -44,8 +44,6 @@ struct mutex *kfd_get_dbgmgr_mutex(void) static void kfd_dbgmgr_uninitialize(struct kfd_dbgmgr *pmgr) { - BUG_ON(!pmgr); - kfree(pmgr->dbgdev); pmgr->dbgdev = NULL; @@ -55,7 +53,7 @@ static void kfd_dbgmgr_uninitialize(struct kfd_dbgmgr *pmgr) void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr) { - if (pmgr != NULL) { + if (pmgr) { kfd_dbgmgr_uninitialize(pmgr); kfree(pmgr); } @@ -66,12 +64,12 @@ bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev) enum DBGDEV_TYPE type = DBGDEV_TYPE_DIQ; struct kfd_dbgmgr *new_buff; - BUG_ON(pdev == NULL); - BUG_ON(!pdev->init_complete); + if (WARN_ON(!pdev->init_complete)) + return false; new_buff = kfd_alloc_struct(new_buff); if (!new_buff) { - pr_err("amdkfd: Failed to allocate dbgmgr instance\n"); + pr_err("Failed to allocate dbgmgr instance\n"); return false; } @@ -79,7 +77,7 @@ bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev) new_buff->dev = pdev; new_buff->dbgdev = kfd_alloc_struct(new_buff->dbgdev); if (!new_buff->dbgdev) { - pr_err("amdkfd: Failed to allocate dbgdev instance\n"); + pr_err("Failed to allocate dbgdev instance\n"); kfree(new_buff); return false; } @@ -96,8 +94,6 @@ bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev) long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p) { - BUG_ON(!p || !pmgr || !pmgr->dbgdev); - if (pmgr->pasid != 0) { pr_debug("H/W debugger is already active using pasid %d\n", pmgr->pasid); @@ -118,8 +114,6 @@ long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p) long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p) { - BUG_ON(!p || !pmgr || !pmgr->dbgdev); - /* Is the requests coming from the already registered process? */ if (pmgr->pasid != p->pasid) { pr_debug("H/W debugger is not registered by calling pasid %d\n", @@ -137,8 +131,6 @@ long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p) long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, struct dbg_wave_control_info *wac_info) { - BUG_ON(!pmgr || !pmgr->dbgdev || !wac_info); - /* Is the requests coming from the already registered process? */ if (pmgr->pasid != wac_info->process->pasid) { pr_debug("H/W debugger support was not registered for requester pasid %d\n", @@ -152,9 +144,6 @@ long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr, struct dbg_address_watch_info *adw_info) { - BUG_ON(!pmgr || !pmgr->dbgdev || !adw_info); - - /* Is the requests coming from the already registered process? */ if (pmgr->pasid != adw_info->process->pasid) { pr_debug("H/W debugger support was not registered for requester pasid %d\n", diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h index 257a745ad0b5..a04a1fe1d0d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h @@ -30,13 +30,11 @@ #pragma pack(push, 4) enum HSA_DBG_WAVEOP { - HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */ - HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */ - HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */ - HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter - debug mode */ - HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take - a trap */ + HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */ + HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */ + HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */ + HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter dbg mode */ + HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take a trap */ HSA_DBG_NUM_WAVEOP = 5, HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF }; @@ -81,15 +79,13 @@ struct HsaDbgWaveMsgAMDGen2 { uint32_t UserData:8; /* user data */ uint32_t ShaderArray:1; /* Shader array */ uint32_t Priv:1; /* Privileged */ - uint32_t Reserved0:4; /* This field is reserved, - should be 0 */ + uint32_t Reserved0:4; /* Reserved, should be 0 */ uint32_t WaveId:4; /* wave id */ uint32_t SIMD:2; /* SIMD id */ uint32_t HSACU:4; /* Compute unit */ uint32_t ShaderEngine:2;/* Shader engine */ uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */ - uint32_t Reserved1:4; /* This field is reserved, - should be 0 */ + uint32_t Reserved1:4; /* Reserved, should be 0 */ } ui32; uint32_t Value; }; @@ -121,20 +117,23 @@ struct HsaDbgWaveMessage { * in the user mode instruction stream. The OS scheduler event is typically * associated and signaled by an interrupt issued by the GPU, but other HSA * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced - * by the KFD by this mechanism, too. */ + * by the KFD by this mechanism, too. + */ /* these are the new definitions for events */ enum HSA_EVENTTYPE { HSA_EVENTTYPE_SIGNAL = 0, /* user-mode generated GPU signal */ HSA_EVENTTYPE_NODECHANGE = 1, /* HSA node change (attach/detach) */ HSA_EVENTTYPE_DEVICESTATECHANGE = 2, /* HSA device state change - (start/stop) */ + * (start/stop) + */ HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */ HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */ HSA_EVENTTYPE_DEBUG_EVENT = 5, /* GPU signal for debugging */ HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */ HSA_EVENTTYPE_QUEUE_EVENT = 7, /* GPU signal queue idle state - (EOP pm4) */ + * (EOP pm4) + */ /* ... */ HSA_EVENTTYPE_MAXID, HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 3f95f7cb4019..5df12b287201 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -26,7 +26,7 @@ #include <linux/slab.h> #include "kfd_priv.h" #include "kfd_device_queue_manager.h" -#include "kfd_pm4_headers.h" +#include "kfd_pm4_headers_vi.h" #define MQD_SIZE_ALIGNED 768 @@ -98,11 +98,14 @@ static const struct kfd_device_info *lookup_device_info(unsigned short did) for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { if (supported_devices[i].did == did) { - BUG_ON(supported_devices[i].device_info == NULL); + WARN_ON(!supported_devices[i].device_info); return supported_devices[i].device_info; } } + dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", + did); + return NULL; } @@ -114,8 +117,10 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, const struct kfd_device_info *device_info = lookup_device_info(pdev->device); - if (!device_info) + if (!device_info) { + dev_err(kfd_device, "kgd2kfd_probe failed\n"); return NULL; + } kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); if (!kfd) @@ -152,23 +157,17 @@ static bool device_iommu_pasid_init(struct kfd_dev *kfd) } if ((iommu_info.flags & required_iommu_flags) != required_iommu_flags) { - dev_err(kfd_device, "error required iommu flags ats(%i), pri(%i), pasid(%i)\n", + dev_err(kfd_device, "error required iommu flags ats %i, pri %i, pasid %i\n", (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP) != 0, (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP) != 0, - (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) != 0); + (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) + != 0); return false; } pasid_limit = min_t(unsigned int, - (unsigned int)1 << kfd->device_info->max_pasid_bits, + (unsigned int)(1 << kfd->device_info->max_pasid_bits), iommu_info.max_pasids); - /* - * last pasid is used for kernel queues doorbells - * in the future the last pasid might be used for a kernel thread. - */ - pasid_limit = min_t(unsigned int, - pasid_limit, - kfd->doorbell_process_limit - 1); err = amd_iommu_init_device(kfd->pdev, pasid_limit); if (err < 0) { @@ -211,9 +210,8 @@ static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid, flags); dev = kfd_device_by_pci_dev(pdev); - BUG_ON(dev == NULL); - - kfd_signal_iommu_event(dev, pasid, address, + if (!WARN_ON(!dev)) + kfd_signal_iommu_event(dev, pasid, address, flags & PPR_FAULT_WRITE, flags & PPR_FAULT_EXEC); return AMD_IOMMU_INV_PRI_RSP_INVALID; @@ -234,9 +232,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, * calculate max size of runlist packet. * There can be only 2 packets at once */ - size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_map_process) + - max_num_of_queues_per_device * - sizeof(struct pm4_map_queues) + sizeof(struct pm4_runlist)) * 2; + size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + + max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) + + sizeof(struct pm4_mes_runlist)) * 2; /* Add size of HIQ & DIQ */ size += KFD_KERNEL_QUEUE_SIZE * 2; @@ -247,42 +245,37 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, if (kfd->kfd2kgd->init_gtt_mem_allocation( kfd->kgd, size, &kfd->gtt_mem, &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr)){ - dev_err(kfd_device, - "Could not allocate %d bytes for device (%x:%x)\n", - size, kfd->pdev->vendor, kfd->pdev->device); + dev_err(kfd_device, "Could not allocate %d bytes\n", size); goto out; } - dev_info(kfd_device, - "Allocated %d bytes on gart for device(%x:%x)\n", - size, kfd->pdev->vendor, kfd->pdev->device); + dev_info(kfd_device, "Allocated %d bytes on gart\n", size); /* Initialize GTT sa with 512 byte chunk size */ if (kfd_gtt_sa_init(kfd, size, 512) != 0) { - dev_err(kfd_device, - "Error initializing gtt sub-allocator\n"); + dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); goto kfd_gtt_sa_init_error; } - kfd_doorbell_init(kfd); - - if (kfd_topology_add_device(kfd) != 0) { + if (kfd_doorbell_init(kfd)) { dev_err(kfd_device, - "Error adding device (%x:%x) to topology\n", - kfd->pdev->vendor, kfd->pdev->device); + "Error initializing doorbell aperture\n"); + goto kfd_doorbell_error; + } + + if (kfd_topology_add_device(kfd)) { + dev_err(kfd_device, "Error adding device to topology\n"); goto kfd_topology_add_device_error; } if (kfd_interrupt_init(kfd)) { - dev_err(kfd_device, - "Error initializing interrupts for device (%x:%x)\n", - kfd->pdev->vendor, kfd->pdev->device); + dev_err(kfd_device, "Error initializing interrupts\n"); goto kfd_interrupt_error; } if (!device_iommu_pasid_init(kfd)) { dev_err(kfd_device, - "Error initializing iommuv2 for device (%x:%x)\n", + "Error initializing iommuv2 for device %x:%x\n", kfd->pdev->vendor, kfd->pdev->device); goto device_iommu_pasid_error; } @@ -292,15 +285,13 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd->dqm = device_queue_manager_init(kfd); if (!kfd->dqm) { - dev_err(kfd_device, - "Error initializing queue manager for device (%x:%x)\n", - kfd->pdev->vendor, kfd->pdev->device); + dev_err(kfd_device, "Error initializing queue manager\n"); goto device_queue_manager_error; } - if (kfd->dqm->ops.start(kfd->dqm) != 0) { + if (kfd->dqm->ops.start(kfd->dqm)) { dev_err(kfd_device, - "Error starting queuen manager for device (%x:%x)\n", + "Error starting queue manager for device %x:%x\n", kfd->pdev->vendor, kfd->pdev->device); goto dqm_start_error; } @@ -308,10 +299,10 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd->dbgmgr = NULL; kfd->init_complete = true; - dev_info(kfd_device, "added device (%x:%x)\n", kfd->pdev->vendor, + dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, kfd->pdev->device); - pr_debug("kfd: Starting kfd with the following scheduling policy %d\n", + pr_debug("Starting kfd with the following scheduling policy %d\n", sched_policy); goto out; @@ -325,11 +316,13 @@ device_iommu_pasid_error: kfd_interrupt_error: kfd_topology_remove_device(kfd); kfd_topology_add_device_error: + kfd_doorbell_fini(kfd); +kfd_doorbell_error: kfd_gtt_sa_fini(kfd); kfd_gtt_sa_init_error: kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); dev_err(kfd_device, - "device (%x:%x) NOT added due to errors\n", + "device %x:%x NOT added due to errors\n", kfd->pdev->vendor, kfd->pdev->device); out: return kfd->init_complete; @@ -342,6 +335,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) amd_iommu_free_device(kfd->pdev); kfd_interrupt_exit(kfd); kfd_topology_remove_device(kfd); + kfd_doorbell_fini(kfd); kfd_gtt_sa_fini(kfd); kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); } @@ -351,8 +345,6 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) void kgd2kfd_suspend(struct kfd_dev *kfd) { - BUG_ON(kfd == NULL); - if (kfd->init_complete) { kfd->dqm->ops.stop(kfd->dqm); amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL); @@ -366,14 +358,15 @@ int kgd2kfd_resume(struct kfd_dev *kfd) unsigned int pasid_limit; int err; - BUG_ON(kfd == NULL); - pasid_limit = kfd_get_pasid_limit(); if (kfd->init_complete) { err = amd_iommu_init_device(kfd->pdev, pasid_limit); - if (err < 0) + if (err < 0) { + dev_err(kfd_device, "failed to initialize iommu\n"); return -ENXIO; + } + amd_iommu_set_invalidate_ctx_cb(kfd->pdev, iommu_pasid_shutdown_callback); amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb); @@ -402,26 +395,27 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, unsigned int chunk_size) { - unsigned int num_of_bits; + unsigned int num_of_longs; - BUG_ON(!kfd); - BUG_ON(!kfd->gtt_mem); - BUG_ON(buf_size < chunk_size); - BUG_ON(buf_size == 0); - BUG_ON(chunk_size == 0); + if (WARN_ON(buf_size < chunk_size)) + return -EINVAL; + if (WARN_ON(buf_size == 0)) + return -EINVAL; + if (WARN_ON(chunk_size == 0)) + return -EINVAL; kfd->gtt_sa_chunk_size = chunk_size; kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; - num_of_bits = kfd->gtt_sa_num_of_chunks / BITS_PER_BYTE; - BUG_ON(num_of_bits == 0); + num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / + BITS_PER_LONG; - kfd->gtt_sa_bitmap = kzalloc(num_of_bits, GFP_KERNEL); + kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); if (!kfd->gtt_sa_bitmap) return -ENOMEM; - pr_debug("kfd: gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", + pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); mutex_init(&kfd->gtt_sa_lock); @@ -455,8 +449,6 @@ int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, { unsigned int found, start_search, cur_size; - BUG_ON(!kfd); - if (size == 0) return -EINVAL; @@ -467,7 +459,7 @@ int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, if ((*mem_obj) == NULL) return -ENOMEM; - pr_debug("kfd: allocated mem_obj = %p for size = %d\n", *mem_obj, size); + pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); start_search = 0; @@ -479,7 +471,7 @@ kfd_gtt_restart_search: kfd->gtt_sa_num_of_chunks, start_search); - pr_debug("kfd: found = %d\n", found); + pr_debug("Found = %d\n", found); /* If there wasn't any free chunk, bail out */ if (found == kfd->gtt_sa_num_of_chunks) @@ -497,12 +489,12 @@ kfd_gtt_restart_search: found, kfd->gtt_sa_chunk_size); - pr_debug("kfd: gpu_addr = %p, cpu_addr = %p\n", + pr_debug("gpu_addr = %p, cpu_addr = %p\n", (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); /* If we need only one chunk, mark it as allocated and get out */ if (size <= kfd->gtt_sa_chunk_size) { - pr_debug("kfd: single bit\n"); + pr_debug("Single bit\n"); set_bit(found, kfd->gtt_sa_bitmap); goto kfd_gtt_out; } @@ -537,7 +529,7 @@ kfd_gtt_restart_search: } while (cur_size > 0); - pr_debug("kfd: range_start = %d, range_end = %d\n", + pr_debug("range_start = %d, range_end = %d\n", (*mem_obj)->range_start, (*mem_obj)->range_end); /* Mark the chunks as allocated */ @@ -551,7 +543,7 @@ kfd_gtt_out: return 0; kfd_gtt_no_free_chunk: - pr_debug("kfd: allocation failed with mem_obj = %p\n", mem_obj); + pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); mutex_unlock(&kfd->gtt_sa_lock); kfree(mem_obj); return -ENOMEM; @@ -561,13 +553,11 @@ int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) { unsigned int bit; - BUG_ON(!kfd); - /* Act like kfree when trying to free a NULL object */ if (!mem_obj) return 0; - pr_debug("kfd: free mem_obj = %p, range_start = %d, range_end = %d\n", + pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", mem_obj, mem_obj->range_start, mem_obj->range_end); mutex_lock(&kfd->gtt_sa_lock); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 42de22bbe14c..53a66e821624 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -79,20 +79,17 @@ static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) unsigned int get_queues_num(struct device_queue_manager *dqm) { - BUG_ON(!dqm || !dqm->dev); return bitmap_weight(dqm->dev->shared_resources.queue_bitmap, KGD_MAX_QUEUES); } unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) { - BUG_ON(!dqm || !dqm->dev); return dqm->dev->shared_resources.num_queue_per_pipe; } unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) { - BUG_ON(!dqm || !dqm->dev); return dqm->dev->shared_resources.num_pipe_per_mec; } @@ -121,7 +118,7 @@ static int allocate_vmid(struct device_queue_manager *dqm, /* Kaveri kfd vmid's starts from vmid 8 */ allocated_vmid = bit + KFD_VMID_START_OFFSET; - pr_debug("kfd: vmid allocation %d\n", allocated_vmid); + pr_debug("vmid allocation %d\n", allocated_vmid); qpd->vmid = allocated_vmid; q->properties.vmid = allocated_vmid; @@ -152,42 +149,38 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, { int retval; - BUG_ON(!dqm || !q || !qpd || !allocated_vmid); - - pr_debug("kfd: In func %s\n", __func__); print_queue(q); mutex_lock(&dqm->lock); if (dqm->total_queue_count >= max_num_of_queues_per_device) { - pr_warn("amdkfd: Can't create new usermode queue because %d queues were already created\n", + pr_warn("Can't create new usermode queue because %d queues were already created\n", dqm->total_queue_count); - mutex_unlock(&dqm->lock); - return -EPERM; + retval = -EPERM; + goto out_unlock; } if (list_empty(&qpd->queues_list)) { retval = allocate_vmid(dqm, qpd, q); - if (retval != 0) { - mutex_unlock(&dqm->lock); - return retval; - } + if (retval) + goto out_unlock; } *allocated_vmid = qpd->vmid; q->properties.vmid = qpd->vmid; if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) retval = create_compute_queue_nocpsch(dqm, q, qpd); - if (q->properties.type == KFD_QUEUE_TYPE_SDMA) + else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) retval = create_sdma_queue_nocpsch(dqm, q, qpd); + else + retval = -EINVAL; - if (retval != 0) { + if (retval) { if (list_empty(&qpd->queues_list)) { deallocate_vmid(dqm, qpd, q); *allocated_vmid = 0; } - mutex_unlock(&dqm->lock); - return retval; + goto out_unlock; } list_add(&q->list, &qpd->queues_list); @@ -205,8 +198,9 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, pr_debug("Total of %d queues are accountable so far\n", dqm->total_queue_count); +out_unlock: mutex_unlock(&dqm->lock); - return 0; + return retval; } static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) @@ -216,7 +210,8 @@ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) set = false; - for (pipe = dqm->next_pipe_to_allocate, i = 0; i < get_pipes_per_mec(dqm); + for (pipe = dqm->next_pipe_to_allocate, i = 0; + i < get_pipes_per_mec(dqm); pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { if (!is_pipe_enabled(dqm, 0, pipe)) @@ -239,8 +234,7 @@ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) if (!set) return -EBUSY; - pr_debug("kfd: DQM %s hqd slot - pipe (%d) queue(%d)\n", - __func__, q->pipe, q->queue); + pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); /* horizontal hqd allocation */ dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); @@ -260,36 +254,38 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm, int retval; struct mqd_manager *mqd; - BUG_ON(!dqm || !q || !qpd); - mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE); - if (mqd == NULL) + if (!mqd) return -ENOMEM; retval = allocate_hqd(dqm, q); - if (retval != 0) + if (retval) return retval; retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); - if (retval != 0) { - deallocate_hqd(dqm, q); - return retval; - } + if (retval) + goto out_deallocate_hqd; - pr_debug("kfd: loading mqd to hqd on pipe (%d) queue (%d)\n", - q->pipe, - q->queue); + pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", + q->pipe, q->queue); - retval = mqd->load_mqd(mqd, q->mqd, q->pipe, - q->queue, (uint32_t __user *) q->properties.write_ptr); - if (retval != 0) { - deallocate_hqd(dqm, q); - mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); - return retval; - } + dqm->dev->kfd2kgd->set_scratch_backing_va( + dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid); + + retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue, &q->properties, + q->process->mm); + if (retval) + goto out_uninit_mqd; return 0; + +out_uninit_mqd: + mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); +out_deallocate_hqd: + deallocate_hqd(dqm, q); + + return retval; } static int destroy_queue_nocpsch(struct device_queue_manager *dqm, @@ -299,12 +295,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, int retval; struct mqd_manager *mqd; - BUG_ON(!dqm || !q || !q->mqd || !qpd); - retval = 0; - pr_debug("kfd: In Func %s\n", __func__); - mutex_lock(&dqm->lock); if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { @@ -323,7 +315,7 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, dqm->sdma_queue_count--; deallocate_sdma_queue(dqm, q->sdma_id); } else { - pr_debug("q->properties.type is invalid (%d)\n", + pr_debug("q->properties.type %d is invalid\n", q->properties.type); retval = -EINVAL; goto out; @@ -334,7 +326,7 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS, q->pipe, q->queue); - if (retval != 0) + if (retval) goto out; mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); @@ -364,14 +356,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) struct mqd_manager *mqd; bool prev_active = false; - BUG_ON(!dqm || !q || !q->mqd); - mutex_lock(&dqm->lock); mqd = dqm->ops.get_mqd_manager(dqm, get_mqd_type_from_queue_type(q->properties.type)); - if (mqd == NULL) { - mutex_unlock(&dqm->lock); - return -ENOMEM; + if (!mqd) { + retval = -ENOMEM; + goto out_unlock; } if (q->properties.is_active) @@ -385,12 +375,13 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) retval = mqd->update_mqd(mqd, q->mqd, &q->properties); if ((q->properties.is_active) && (!prev_active)) dqm->queue_count++; - else if ((!q->properties.is_active) && (prev_active)) + else if (!q->properties.is_active && prev_active) dqm->queue_count--; if (sched_policy != KFD_SCHED_POLICY_NO_HWS) retval = execute_queues_cpsch(dqm, false); +out_unlock: mutex_unlock(&dqm->lock); return retval; } @@ -400,15 +391,16 @@ static struct mqd_manager *get_mqd_manager_nocpsch( { struct mqd_manager *mqd; - BUG_ON(!dqm || type >= KFD_MQD_TYPE_MAX); + if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) + return NULL; - pr_debug("kfd: In func %s mqd type %d\n", __func__, type); + pr_debug("mqd type %d\n", type); mqd = dqm->mqds[type]; if (!mqd) { mqd = mqd_manager_init(type, dqm->dev); - if (mqd == NULL) - pr_err("kfd: mqd manager is NULL"); + if (!mqd) + pr_err("mqd manager is NULL"); dqm->mqds[type] = mqd; } @@ -421,11 +413,7 @@ static int register_process_nocpsch(struct device_queue_manager *dqm, struct device_process_node *n; int retval; - BUG_ON(!dqm || !qpd); - - pr_debug("kfd: In func %s\n", __func__); - - n = kzalloc(sizeof(struct device_process_node), GFP_KERNEL); + n = kzalloc(sizeof(*n), GFP_KERNEL); if (!n) return -ENOMEM; @@ -449,10 +437,6 @@ static int unregister_process_nocpsch(struct device_queue_manager *dqm, int retval; struct device_process_node *cur, *next; - BUG_ON(!dqm || !qpd); - - pr_debug("In func %s\n", __func__); - pr_debug("qpd->queues_list is %s\n", list_empty(&qpd->queues_list) ? "empty" : "not empty"); @@ -493,51 +477,39 @@ static void init_interrupts(struct device_queue_manager *dqm) { unsigned int i; - BUG_ON(dqm == NULL); - for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) if (is_pipe_enabled(dqm, 0, i)) dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i); } -static int init_scheduler(struct device_queue_manager *dqm) -{ - int retval = 0; - - BUG_ON(!dqm); - - pr_debug("kfd: In %s\n", __func__); - - return retval; -} - static int initialize_nocpsch(struct device_queue_manager *dqm) { - int i; + int pipe, queue; - BUG_ON(!dqm); + pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); - pr_debug("kfd: In func %s num of pipes: %d\n", - __func__, get_pipes_per_mec(dqm)); + dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), + sizeof(unsigned int), GFP_KERNEL); + if (!dqm->allocated_queues) + return -ENOMEM; mutex_init(&dqm->lock); INIT_LIST_HEAD(&dqm->queues); dqm->queue_count = dqm->next_pipe_to_allocate = 0; dqm->sdma_queue_count = 0; - dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), - sizeof(unsigned int), GFP_KERNEL); - if (!dqm->allocated_queues) { - mutex_destroy(&dqm->lock); - return -ENOMEM; - } - for (i = 0; i < get_pipes_per_mec(dqm); i++) - dqm->allocated_queues[i] = (1 << get_queues_per_pipe(dqm)) - 1; + for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { + int pipe_offset = pipe * get_queues_per_pipe(dqm); + + for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) + if (test_bit(pipe_offset + queue, + dqm->dev->shared_resources.queue_bitmap)) + dqm->allocated_queues[pipe] |= 1 << queue; + } dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1; dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1; - init_scheduler(dqm); return 0; } @@ -545,9 +517,7 @@ static void uninitialize_nocpsch(struct device_queue_manager *dqm) { int i; - BUG_ON(!dqm); - - BUG_ON(dqm->queue_count > 0 || dqm->processes_count > 0); + WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0); kfree(dqm->allocated_queues); for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) @@ -604,33 +574,34 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, return -ENOMEM; retval = allocate_sdma_queue(dqm, &q->sdma_id); - if (retval != 0) + if (retval) return retval; q->properties.sdma_queue_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE; q->properties.sdma_engine_id = q->sdma_id / CIK_SDMA_ENGINE_NUM; - pr_debug("kfd: sdma id is: %d\n", q->sdma_id); - pr_debug(" sdma queue id: %d\n", q->properties.sdma_queue_id); - pr_debug(" sdma engine id: %d\n", q->properties.sdma_engine_id); + pr_debug("SDMA id is: %d\n", q->sdma_id); + pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); + pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd); retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); - if (retval != 0) { - deallocate_sdma_queue(dqm, q->sdma_id); - return retval; - } + if (retval) + goto out_deallocate_sdma_queue; - retval = mqd->load_mqd(mqd, q->mqd, 0, - 0, NULL); - if (retval != 0) { - deallocate_sdma_queue(dqm, q->sdma_id); - mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); - return retval; - } + retval = mqd->load_mqd(mqd, q->mqd, 0, 0, &q->properties, NULL); + if (retval) + goto out_uninit_mqd; return 0; + +out_uninit_mqd: + mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); +out_deallocate_sdma_queue: + deallocate_sdma_queue(dqm, q->sdma_id); + + return retval; } /* @@ -642,10 +613,6 @@ static int set_sched_resources(struct device_queue_manager *dqm) int i, mec; struct scheduling_resources res; - BUG_ON(!dqm); - - pr_debug("kfd: In func %s\n", __func__); - res.vmid_mask = (1 << VMID_PER_DEVICE) - 1; res.vmid_mask <<= KFD_VMID_START_OFFSET; @@ -663,7 +630,8 @@ static int set_sched_resources(struct device_queue_manager *dqm) /* This situation may be hit in the future if a new HW * generation exposes more than 64 queues. If so, the - * definition of res.queue_mask needs updating */ + * definition of res.queue_mask needs updating + */ if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { pr_err("Invalid queue enabled by amdgpu: %d\n", i); break; @@ -674,9 +642,9 @@ static int set_sched_resources(struct device_queue_manager *dqm) res.gws_mask = res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; - pr_debug("kfd: scheduling resources:\n" - " vmid mask: 0x%8X\n" - " queue mask: 0x%8llX\n", + pr_debug("Scheduling resources:\n" + "vmid mask: 0x%8X\n" + "queue mask: 0x%8llX\n", res.vmid_mask, res.queue_mask); return pm_send_set_resources(&dqm->packets, &res); @@ -686,10 +654,7 @@ static int initialize_cpsch(struct device_queue_manager *dqm) { int retval; - BUG_ON(!dqm); - - pr_debug("kfd: In func %s num of pipes: %d\n", - __func__, get_pipes_per_mec(dqm)); + pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); mutex_init(&dqm->lock); INIT_LIST_HEAD(&dqm->queues); @@ -697,13 +662,9 @@ static int initialize_cpsch(struct device_queue_manager *dqm) dqm->sdma_queue_count = 0; dqm->active_runlist = false; retval = dqm->ops_asic_specific.initialize(dqm); - if (retval != 0) - goto fail_init_pipelines; - - return 0; + if (retval) + mutex_destroy(&dqm->lock); -fail_init_pipelines: - mutex_destroy(&dqm->lock); return retval; } @@ -712,25 +673,23 @@ static int start_cpsch(struct device_queue_manager *dqm) struct device_process_node *node; int retval; - BUG_ON(!dqm); - retval = 0; retval = pm_init(&dqm->packets, dqm); - if (retval != 0) + if (retval) goto fail_packet_manager_init; retval = set_sched_resources(dqm); - if (retval != 0) + if (retval) goto fail_set_sched_resources; - pr_debug("kfd: allocating fence memory\n"); + pr_debug("Allocating fence memory\n"); /* allocate fence memory on the gart */ retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), &dqm->fence_mem); - if (retval != 0) + if (retval) goto fail_allocate_vidmem; dqm->fence_addr = dqm->fence_mem->cpu_ptr; @@ -758,8 +717,6 @@ static int stop_cpsch(struct device_queue_manager *dqm) struct device_process_node *node; struct kfd_process_device *pdd; - BUG_ON(!dqm); - destroy_queues_cpsch(dqm, true, true); list_for_each_entry(node, &dqm->queues, list) { @@ -776,13 +733,9 @@ static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, struct kernel_queue *kq, struct qcm_process_device *qpd) { - BUG_ON(!dqm || !kq || !qpd); - - pr_debug("kfd: In func %s\n", __func__); - mutex_lock(&dqm->lock); if (dqm->total_queue_count >= max_num_of_queues_per_device) { - pr_warn("amdkfd: Can't create new kernel queue because %d queues were already created\n", + pr_warn("Can't create new kernel queue because %d queues were already created\n", dqm->total_queue_count); mutex_unlock(&dqm->lock); return -EPERM; @@ -809,10 +762,6 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, struct kernel_queue *kq, struct qcm_process_device *qpd) { - BUG_ON(!dqm || !kq); - - pr_debug("kfd: In %s\n", __func__); - mutex_lock(&dqm->lock); /* here we actually preempt the DIQ */ destroy_queues_cpsch(dqm, true, false); @@ -844,8 +793,6 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, int retval; struct mqd_manager *mqd; - BUG_ON(!dqm || !q || !qpd); - retval = 0; if (allocate_vmid) @@ -854,7 +801,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, mutex_lock(&dqm->lock); if (dqm->total_queue_count >= max_num_of_queues_per_device) { - pr_warn("amdkfd: Can't create new usermode queue because %d queues were already created\n", + pr_warn("Can't create new usermode queue because %d queues were already created\n", dqm->total_queue_count); retval = -EPERM; goto out; @@ -866,15 +813,15 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, mqd = dqm->ops.get_mqd_manager(dqm, get_mqd_type_from_queue_type(q->properties.type)); - if (mqd == NULL) { - mutex_unlock(&dqm->lock); - return -ENOMEM; + if (!mqd) { + retval = -ENOMEM; + goto out; } dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd); retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); - if (retval != 0) + if (retval) goto out; list_add(&q->list, &qpd->queues_list); @@ -884,7 +831,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, } if (q->properties.type == KFD_QUEUE_TYPE_SDMA) - dqm->sdma_queue_count++; + dqm->sdma_queue_count++; /* * Unconditionally increment this counter, regardless of the queue's * type or whether the queue is active. @@ -903,12 +850,11 @@ int amdkfd_fence_wait_timeout(unsigned int *fence_addr, unsigned int fence_value, unsigned long timeout) { - BUG_ON(!fence_addr); timeout += jiffies; while (*fence_addr != fence_value) { if (time_after(jiffies, timeout)) { - pr_err("kfd: qcm fence wait loop timeout expired\n"); + pr_err("qcm fence wait loop timeout expired\n"); return -ETIME; } schedule(); @@ -932,8 +878,6 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, enum kfd_preempt_type_filter preempt_type; struct kfd_process_device *pdd; - BUG_ON(!dqm); - retval = 0; if (lock) @@ -941,7 +885,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, if (!dqm->active_runlist) goto out; - pr_debug("kfd: Before destroying queues, sdma queue count is : %u\n", + pr_debug("Before destroying queues, sdma queue count is : %u\n", dqm->sdma_queue_count); if (dqm->sdma_queue_count > 0) { @@ -955,7 +899,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE, preempt_type, 0, false, 0); - if (retval != 0) + if (retval) goto out; *dqm->fence_addr = KFD_FENCE_INIT; @@ -964,7 +908,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, /* should be timed out */ retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS); - if (retval != 0) { + if (retval) { pdd = kfd_get_process_device_data(dqm->dev, kfd_get_process(current)); pdd->reset_wavefronts = true; @@ -983,14 +927,12 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock) { int retval; - BUG_ON(!dqm); - if (lock) mutex_lock(&dqm->lock); retval = destroy_queues_cpsch(dqm, false, false); - if (retval != 0) { - pr_err("kfd: the cp might be in an unrecoverable state due to an unsuccessful queues preemption"); + if (retval) { + pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption"); goto out; } @@ -1005,8 +947,8 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock) } retval = pm_send_runlist(&dqm->packets, &dqm->queues); - if (retval != 0) { - pr_err("kfd: failed to execute runlist"); + if (retval) { + pr_err("failed to execute runlist"); goto out; } dqm->active_runlist = true; @@ -1025,8 +967,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, struct mqd_manager *mqd; bool preempt_all_queues; - BUG_ON(!dqm || !qpd || !q); - preempt_all_queues = false; retval = 0; @@ -1098,8 +1038,6 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, { bool retval; - pr_debug("kfd: In func %s\n", __func__); - mutex_lock(&dqm->lock); if (alternate_aperture_size == 0) { @@ -1120,14 +1058,11 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, uint64_t base = (uintptr_t)alternate_aperture_base; uint64_t limit = base + alternate_aperture_size - 1; - if (limit <= base) - goto out; - - if ((base & APE1_FIXED_BITS_MASK) != 0) - goto out; - - if ((limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) + if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || + (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { + retval = false; goto out; + } qpd->sh_mem_ape1_base = base >> 16; qpd->sh_mem_ape1_limit = limit >> 16; @@ -1144,27 +1079,22 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, if ((sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) program_sh_mem_settings(dqm, qpd); - pr_debug("kfd: sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", + pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", qpd->sh_mem_config, qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit); - mutex_unlock(&dqm->lock); - return retval; - out: mutex_unlock(&dqm->lock); - return false; + return retval; } struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) { struct device_queue_manager *dqm; - BUG_ON(!dev); + pr_debug("Loading device queue manager\n"); - pr_debug("kfd: loading device queue manager\n"); - - dqm = kzalloc(sizeof(struct device_queue_manager), GFP_KERNEL); + dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); if (!dqm) return NULL; @@ -1202,8 +1132,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) dqm->ops.set_cache_memory_policy = set_cache_memory_policy; break; default: - BUG(); - break; + pr_err("Invalid scheduling policy %d\n", sched_policy); + goto out_free; } switch (dev->device_info->asic_family) { @@ -1216,18 +1146,16 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) break; } - if (dqm->ops.initialize(dqm) != 0) { - kfree(dqm); - return NULL; - } + if (!dqm->ops.initialize(dqm)) + return dqm; - return dqm; +out_free: + kfree(dqm); + return NULL; } void device_queue_manager_uninit(struct device_queue_manager *dqm) { - BUG_ON(!dqm); - dqm->ops.uninitialize(dqm); kfree(dqm); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c index 48dc0561b402..72c3cbabc0a7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c @@ -24,6 +24,7 @@ #include "kfd_device_queue_manager.h" #include "cik_regs.h" #include "oss/oss_2_4_sh_mask.h" +#include "gca/gfx_7_2_sh_mask.h" static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, struct qcm_process_device *qpd, @@ -65,7 +66,7 @@ static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) * for LDS/Scratch and GPUVM. */ - BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || + WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || top_address_nybble == 0); return PRIVATE_BASE(top_address_nybble << 12) | @@ -104,8 +105,6 @@ static int register_process_cik(struct device_queue_manager *dqm, struct kfd_process_device *pdd; unsigned int temp; - BUG_ON(!dqm || !qpd); - pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ @@ -125,9 +124,10 @@ static int register_process_cik(struct device_queue_manager *dqm, } else { temp = get_sh_mem_bases_nybble_64(pdd); qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); + qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__PRIVATE_ATC__SHIFT; } - pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", + pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c index 7e9cae9d349b..40e9ddd096cd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c @@ -67,7 +67,7 @@ static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) * for LDS/Scratch and GPUVM. */ - BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || + WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || top_address_nybble == 0); return top_address_nybble << 12 | @@ -110,8 +110,6 @@ static int register_process_vi(struct device_queue_manager *dqm, struct kfd_process_device *pdd; unsigned int temp; - BUG_ON(!dqm || !qpd); - pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ @@ -137,9 +135,11 @@ static int register_process_vi(struct device_queue_manager *dqm, qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT; + qpd->sh_mem_config |= 1 << + SH_MEM_CONFIG__PRIVATE_ATC__SHIFT; } - pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", + pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 453c5d66e5c3..feb76c235b1a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -24,16 +24,15 @@ #include <linux/mman.h> #include <linux/slab.h> #include <linux/io.h> +#include <linux/idr.h> /* - * This extension supports a kernel level doorbells management for - * the kernel queues. - * Basically the last doorbells page is devoted to kernel queues - * and that's assures that any user process won't get access to the - * kernel doorbells page + * This extension supports a kernel level doorbells management for the + * kernel queues using the first doorbell page reserved for the kernel. */ -#define KERNEL_DOORBELL_PASID 1 +static DEFINE_IDA(doorbell_ida); +static unsigned int max_doorbell_slices; #define KFD_SIZE_OF_DOORBELL_IN_BYTES 4 /* @@ -59,7 +58,7 @@ static inline size_t doorbell_process_allocation(void) } /* Doorbell calculations for device init. */ -void kfd_doorbell_init(struct kfd_dev *kfd) +int kfd_doorbell_init(struct kfd_dev *kfd) { size_t doorbell_start_offset; size_t doorbell_aperture_size; @@ -84,37 +83,49 @@ void kfd_doorbell_init(struct kfd_dev *kfd) (doorbell_aperture_size - doorbell_start_offset) / doorbell_process_allocation(); else - doorbell_process_limit = 0; + return -ENOSPC; + + if (!max_doorbell_slices || + doorbell_process_limit < max_doorbell_slices) + max_doorbell_slices = doorbell_process_limit; kfd->doorbell_base = kfd->shared_resources.doorbell_physical_address + doorbell_start_offset; kfd->doorbell_id_offset = doorbell_start_offset / sizeof(u32); - kfd->doorbell_process_limit = doorbell_process_limit - 1; kfd->doorbell_kernel_ptr = ioremap(kfd->doorbell_base, doorbell_process_allocation()); - BUG_ON(!kfd->doorbell_kernel_ptr); + if (!kfd->doorbell_kernel_ptr) + return -ENOMEM; - pr_debug("kfd: doorbell initialization:\n"); - pr_debug("kfd: doorbell base == 0x%08lX\n", + pr_debug("Doorbell initialization:\n"); + pr_debug("doorbell base == 0x%08lX\n", (uintptr_t)kfd->doorbell_base); - pr_debug("kfd: doorbell_id_offset == 0x%08lX\n", + pr_debug("doorbell_id_offset == 0x%08lX\n", kfd->doorbell_id_offset); - pr_debug("kfd: doorbell_process_limit == 0x%08lX\n", + pr_debug("doorbell_process_limit == 0x%08lX\n", doorbell_process_limit); - pr_debug("kfd: doorbell_kernel_offset == 0x%08lX\n", + pr_debug("doorbell_kernel_offset == 0x%08lX\n", (uintptr_t)kfd->doorbell_base); - pr_debug("kfd: doorbell aperture size == 0x%08lX\n", + pr_debug("doorbell aperture size == 0x%08lX\n", kfd->shared_resources.doorbell_aperture_size); - pr_debug("kfd: doorbell kernel address == 0x%08lX\n", + pr_debug("doorbell kernel address == 0x%08lX\n", (uintptr_t)kfd->doorbell_kernel_ptr); + + return 0; +} + +void kfd_doorbell_fini(struct kfd_dev *kfd) +{ + if (kfd->doorbell_kernel_ptr) + iounmap(kfd->doorbell_kernel_ptr); } int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma) @@ -131,7 +142,7 @@ int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma) /* Find kfd device according to gpu id */ dev = kfd_device_by_id(vma->vm_pgoff); - if (dev == NULL) + if (!dev) return -EINVAL; /* Calculate physical address of doorbell */ @@ -142,12 +153,11 @@ int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("kfd: mapping doorbell page in %s\n" + pr_debug("Mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - __func__, (unsigned long long) vma->vm_start, address, vma->vm_flags, doorbell_process_allocation()); @@ -166,8 +176,6 @@ u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, { u32 inx; - BUG_ON(!kfd || !doorbell_off); - mutex_lock(&kfd->doorbell_mutex); inx = find_first_zero_bit(kfd->doorbell_available_index, KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); @@ -179,13 +187,12 @@ u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, return NULL; /* - * Calculating the kernel doorbell offset using "faked" kernel - * pasid that allocated for kernel queues only + * Calculating the kernel doorbell offset using the first + * doorbell page. */ - *doorbell_off = KERNEL_DOORBELL_PASID * (doorbell_process_allocation() / - sizeof(u32)) + inx; + *doorbell_off = kfd->doorbell_id_offset + inx; - pr_debug("kfd: get kernel queue doorbell\n" + pr_debug("Get kernel queue doorbell\n" " doorbell offset == 0x%08X\n" " kernel address == 0x%08lX\n", *doorbell_off, (uintptr_t)(kfd->doorbell_kernel_ptr + inx)); @@ -197,8 +204,6 @@ void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr) { unsigned int inx; - BUG_ON(!kfd || !db_addr); - inx = (unsigned int)(db_addr - kfd->doorbell_kernel_ptr); mutex_lock(&kfd->doorbell_mutex); @@ -210,7 +215,7 @@ inline void write_kernel_doorbell(u32 __iomem *db, u32 value) { if (db) { writel(value, db); - pr_debug("writing %d to doorbell address 0x%p\n", value, db); + pr_debug("Writing %d to doorbell address 0x%p\n", value, db); } } @@ -224,11 +229,12 @@ unsigned int kfd_queue_id_to_doorbell(struct kfd_dev *kfd, { /* * doorbell_id_offset accounts for doorbells taken by KGD. - * pasid * doorbell_process_allocation/sizeof(u32) adjusts - * to the process's doorbells + * index * doorbell_process_allocation/sizeof(u32) adjusts to + * the process's doorbells. */ return kfd->doorbell_id_offset + - process->pasid * (doorbell_process_allocation()/sizeof(u32)) + + process->doorbell_index + * doorbell_process_allocation() / sizeof(u32) + queue_id; } @@ -246,5 +252,21 @@ phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev, struct kfd_process *process) { return dev->doorbell_base + - process->pasid * doorbell_process_allocation(); + process->doorbell_index * doorbell_process_allocation(); +} + +int kfd_alloc_process_doorbells(struct kfd_process *process) +{ + int r = ida_simple_get(&doorbell_ida, 1, max_doorbell_slices, + GFP_KERNEL); + if (r > 0) + process->doorbell_index = r; + + return r; +} + +void kfd_free_process_doorbells(struct kfd_process *process) +{ + if (process->doorbell_index) + ida_simple_remove(&doorbell_ida, process->doorbell_index); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index d1ce83d73a87..944abfad39c1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -110,7 +110,7 @@ static bool allocate_free_slot(struct kfd_process *process, *out_page = page; *out_slot_index = slot; - pr_debug("allocated event signal slot in page %p, slot %d\n", + pr_debug("Allocated event signal slot in page %p, slot %d\n", page, slot); return true; @@ -155,9 +155,9 @@ static bool allocate_signal_page(struct file *devkfd, struct kfd_process *p) struct signal_page, event_pages)->page_index + 1; - pr_debug("allocated new event signal page at %p, for process %p\n", + pr_debug("Allocated new event signal page at %p, for process %p\n", page, p); - pr_debug("page index is %d\n", page->page_index); + pr_debug("Page index is %d\n", page->page_index); list_add(&page->event_pages, &p->signal_event_pages); @@ -194,7 +194,8 @@ static void release_event_notification_slot(struct signal_page *page, page->free_slots++; /* We don't free signal pages, they are retained by the process - * and reused until it exits. */ + * and reused until it exits. + */ } static struct signal_page *lookup_signal_page_by_index(struct kfd_process *p, @@ -246,7 +247,7 @@ static u32 make_nonsignal_event_id(struct kfd_process *p) for (id = p->next_nonsignal_event_id; id < KFD_LAST_NONSIGNAL_EVENT_ID && - lookup_event_by_id(p, id) != NULL; + lookup_event_by_id(p, id); id++) ; @@ -265,7 +266,7 @@ static u32 make_nonsignal_event_id(struct kfd_process *p) for (id = KFD_FIRST_NONSIGNAL_EVENT_ID; id < KFD_LAST_NONSIGNAL_EVENT_ID && - lookup_event_by_id(p, id) != NULL; + lookup_event_by_id(p, id); id++) ; @@ -291,13 +292,16 @@ static int create_signal_event(struct file *devkfd, struct kfd_event *ev) { if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) { - pr_warn("amdkfd: Signal event wasn't created because limit was reached\n"); + if (!p->signal_event_limit_reached) { + pr_warn("Signal event wasn't created because limit was reached\n"); + p->signal_event_limit_reached = true; + } return -ENOMEM; } if (!allocate_event_notification_slot(devkfd, p, &ev->signal_page, &ev->signal_slot_index)) { - pr_warn("amdkfd: Signal event wasn't created because out of kernel memory\n"); + pr_warn("Signal event wasn't created because out of kernel memory\n"); return -ENOMEM; } @@ -309,11 +313,7 @@ static int create_signal_event(struct file *devkfd, ev->event_id = make_signal_event_id(ev->signal_page, ev->signal_slot_index); - pr_debug("signal event number %zu created with id %d, address %p\n", - p->signal_event_count, ev->event_id, - ev->user_signal_address); - - pr_debug("signal event number %zu created with id %d, address %p\n", + pr_debug("Signal event number %zu created with id %d, address %p\n", p->signal_event_count, ev->event_id, ev->user_signal_address); @@ -345,7 +345,7 @@ void kfd_event_init_process(struct kfd_process *p) static void destroy_event(struct kfd_process *p, struct kfd_event *ev) { - if (ev->signal_page != NULL) { + if (ev->signal_page) { release_event_notification_slot(ev->signal_page, ev->signal_slot_index); p->signal_event_count--; @@ -584,7 +584,7 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, * search faster. */ struct signal_page *page; - unsigned i; + unsigned int i; list_for_each_entry(page, &p->signal_event_pages, event_pages) for (i = 0; i < SLOTS_PER_PAGE; i++) @@ -816,7 +816,7 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) /* check required size is logical */ if (get_order(KFD_SIGNAL_EVENT_LIMIT * 8) != get_order(vma->vm_end - vma->vm_start)) { - pr_err("amdkfd: event page mmap requested illegal size\n"); + pr_err("Event page mmap requested illegal size\n"); return -EINVAL; } @@ -825,7 +825,7 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) page = lookup_signal_page_by_index(p, page_index); if (!page) { /* Probably KFD bug, but mmap is user-accessible. */ - pr_debug("signal page could not be found for page_index %u\n", + pr_debug("Signal page could not be found for page_index %u\n", page_index); return -EINVAL; } @@ -836,7 +836,7 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | VM_DONTDUMP | VM_PFNMAP; - pr_debug("mapping signal page\n"); + pr_debug("Mapping signal page\n"); pr_debug(" start user address == 0x%08lx\n", vma->vm_start); pr_debug(" end user address == 0x%08lx\n", vma->vm_end); pr_debug(" pfn == 0x%016lX\n", pfn); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c index 2b655103ba79..c59384bbbc5f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c @@ -304,7 +304,7 @@ int kfd_init_apertures(struct kfd_process *process) id < NUM_OF_SUPPORTED_GPUS) { pdd = kfd_create_process_device_data(dev, process); - if (pdd == NULL) { + if (!pdd) { pr_err("Failed to create process device data\n"); return -1; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c index 7f134aa9bfd3..70b3a99cffc2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c @@ -179,7 +179,7 @@ static void interrupt_wq(struct work_struct *work) bool interrupt_is_wanted(struct kfd_dev *dev, const uint32_t *ih_ring_entry) { /* integer and bitwise OR so there is no boolean short-circuiting */ - unsigned wanted = 0; + unsigned int wanted = 0; wanted |= dev->device_info->event_interrupt_class->interrupt_isr(dev, ih_ring_entry); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index d135cd002a95..ed71ad40e8f7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -41,11 +41,11 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, int retval; union PM4_MES_TYPE_3_HEADER nop; - BUG_ON(!kq || !dev); - BUG_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ); + if (WARN_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ)) + return false; - pr_debug("amdkfd: In func %s initializing queue type %d size %d\n", - __func__, KFD_QUEUE_TYPE_HIQ, queue_size); + pr_debug("Initializing queue type %d size %d\n", KFD_QUEUE_TYPE_HIQ, + queue_size); memset(&prop, 0, sizeof(prop)); memset(&nop, 0, sizeof(nop)); @@ -63,23 +63,23 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, KFD_MQD_TYPE_HIQ); break; default: - BUG(); - break; + pr_err("Invalid queue type %d\n", type); + return false; } - if (kq->mqd == NULL) + if (!kq->mqd) return false; prop.doorbell_ptr = kfd_get_kernel_doorbell(dev, &prop.doorbell_off); - if (prop.doorbell_ptr == NULL) { - pr_err("amdkfd: error init doorbell"); + if (!prop.doorbell_ptr) { + pr_err("Failed to initialize doorbell"); goto err_get_kernel_doorbell; } retval = kfd_gtt_sa_allocate(dev, queue_size, &kq->pq); if (retval != 0) { - pr_err("amdkfd: error init pq queues size (%d)\n", queue_size); + pr_err("Failed to init pq queues size %d\n", queue_size); goto err_pq_allocate_vidmem; } @@ -87,7 +87,7 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, kq->pq_gpu_addr = kq->pq->gpu_addr; retval = kq->ops_asic_specific.initialize(kq, dev, type, queue_size); - if (retval == false) + if (!retval) goto err_eop_allocate_vidmem; retval = kfd_gtt_sa_allocate(dev, sizeof(*kq->rptr_kernel), @@ -139,11 +139,12 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, /* assign HIQ to HQD */ if (type == KFD_QUEUE_TYPE_HIQ) { - pr_debug("assigning hiq to hqd\n"); + pr_debug("Assigning hiq to hqd\n"); kq->queue->pipe = KFD_CIK_HIQ_PIPE; kq->queue->queue = KFD_CIK_HIQ_QUEUE; kq->mqd->load_mqd(kq->mqd, kq->queue->mqd, kq->queue->pipe, - kq->queue->queue, NULL); + kq->queue->queue, &kq->queue->properties, + NULL); } else { /* allocate fence for DIQ */ @@ -180,12 +181,10 @@ err_get_kernel_doorbell: static void uninitialize(struct kernel_queue *kq) { - BUG_ON(!kq); - if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ) kq->mqd->destroy_mqd(kq->mqd, - NULL, - false, + kq->queue->mqd, + KFD_PREEMPT_TYPE_WAVEFRONT_RESET, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS, kq->queue->pipe, kq->queue->queue); @@ -211,8 +210,11 @@ static int acquire_packet_buffer(struct kernel_queue *kq, uint32_t wptr, rptr; unsigned int *queue_address; - BUG_ON(!kq || !buffer_ptr); - + /* When rptr == wptr, the buffer is empty. + * When rptr == wptr + 1, the buffer is full. + * It is always rptr that advances to the position of wptr, rather than + * the opposite. So we can only use up to queue_size_dwords - 1 dwords. + */ rptr = *kq->rptr_kernel; wptr = *kq->wptr_kernel; queue_address = (unsigned int *)kq->pq_kernel_addr; @@ -222,11 +224,10 @@ static int acquire_packet_buffer(struct kernel_queue *kq, pr_debug("wptr: %d\n", wptr); pr_debug("queue_address 0x%p\n", queue_address); - available_size = (rptr - 1 - wptr + queue_size_dwords) % + available_size = (rptr + queue_size_dwords - 1 - wptr) % queue_size_dwords; - if (packet_size_in_dwords >= queue_size_dwords || - packet_size_in_dwords >= available_size) { + if (packet_size_in_dwords > available_size) { /* * make sure calling functions know * acquire_packet_buffer() failed @@ -236,6 +237,14 @@ static int acquire_packet_buffer(struct kernel_queue *kq, } if (wptr + packet_size_in_dwords >= queue_size_dwords) { + /* make sure after rolling back to position 0, there is + * still enough space. + */ + if (packet_size_in_dwords >= rptr) { + *buffer_ptr = NULL; + return -ENOMEM; + } + /* fill nops, roll back and start at position 0 */ while (wptr > 0) { queue_address[wptr] = kq->nop_packet; wptr = (wptr + 1) % queue_size_dwords; @@ -252,11 +261,7 @@ static void submit_packet(struct kernel_queue *kq) { #ifdef DEBUG int i; -#endif - BUG_ON(!kq); - -#ifdef DEBUG for (i = *kq->wptr_kernel; i < kq->pending_wptr; i++) { pr_debug("0x%2X ", kq->pq_kernel_addr[i]); if (i % 15 == 0) @@ -272,7 +277,6 @@ static void submit_packet(struct kernel_queue *kq) static void rollback_packet(struct kernel_queue *kq) { - BUG_ON(!kq); kq->pending_wptr = *kq->queue->properties.write_ptr; } @@ -281,9 +285,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, { struct kernel_queue *kq; - BUG_ON(!dev); - - kq = kzalloc(sizeof(struct kernel_queue), GFP_KERNEL); + kq = kzalloc(sizeof(*kq), GFP_KERNEL); if (!kq) return NULL; @@ -304,7 +306,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, } if (!kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE)) { - pr_err("amdkfd: failed to init kernel queue\n"); + pr_err("Failed to init kernel queue\n"); kfree(kq); return NULL; } @@ -313,32 +315,37 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, void kernel_queue_uninit(struct kernel_queue *kq) { - BUG_ON(!kq); - kq->ops.uninitialize(kq); kfree(kq); } +/* FIXME: Can this test be removed? */ static __attribute__((unused)) void test_kq(struct kfd_dev *dev) { struct kernel_queue *kq; uint32_t *buffer, i; int retval; - BUG_ON(!dev); - - pr_err("amdkfd: starting kernel queue test\n"); + pr_err("Starting kernel queue test\n"); kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ); - BUG_ON(!kq); + if (unlikely(!kq)) { + pr_err(" Failed to initialize HIQ\n"); + pr_err("Kernel queue test failed\n"); + return; + } retval = kq->ops.acquire_packet_buffer(kq, 5, &buffer); - BUG_ON(retval != 0); + if (unlikely(retval != 0)) { + pr_err(" Failed to acquire packet buffer\n"); + pr_err("Kernel queue test failed\n"); + return; + } for (i = 0; i < 5; i++) buffer[i] = kq->nop_packet; kq->ops.submit_packet(kq); - pr_err("amdkfd: ending kernel queue test\n"); + pr_err("Ending kernel queue test\n"); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 850a5623661f..6c5a9cab55de 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -61,7 +61,8 @@ MODULE_PARM_DESC(send_sigterm, static int amdkfd_init_completed; -int kgd2kfd_init(unsigned interface_version, const struct kgd2kfd_calls **g2f) +int kgd2kfd_init(unsigned int interface_version, + const struct kgd2kfd_calls **g2f) { if (!amdkfd_init_completed) return -EPROBE_DEFER; @@ -90,7 +91,7 @@ static int __init kfd_module_init(void) /* Verify module parameters */ if ((sched_policy < KFD_SCHED_POLICY_HWS) || (sched_policy > KFD_SCHED_POLICY_NO_HWS)) { - pr_err("kfd: sched_policy has invalid value\n"); + pr_err("sched_policy has invalid value\n"); return -1; } @@ -98,14 +99,10 @@ static int __init kfd_module_init(void) if ((max_num_of_queues_per_device < 1) || (max_num_of_queues_per_device > KFD_MAX_NUM_OF_QUEUES_PER_DEVICE)) { - pr_err("kfd: max_num_of_queues_per_device must be between 1 to KFD_MAX_NUM_OF_QUEUES_PER_DEVICE\n"); + pr_err("max_num_of_queues_per_device must be between 1 to KFD_MAX_NUM_OF_QUEUES_PER_DEVICE\n"); return -1; } - err = kfd_pasid_init(); - if (err < 0) - goto err_pasid; - err = kfd_chardev_init(); if (err < 0) goto err_ioctl; @@ -125,8 +122,6 @@ static int __init kfd_module_init(void) err_topology: kfd_chardev_exit(); err_ioctl: - kfd_pasid_exit(); -err_pasid: return err; } @@ -137,7 +132,6 @@ static void __exit kfd_module_exit(void) kfd_process_destroy_wq(); kfd_topology_shutdown(); kfd_chardev_exit(); - kfd_pasid_exit(); dev_info(kfd_device, "Removed module\n"); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 213a71e0b6c7..1f3a6ba7eed2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -67,7 +67,8 @@ struct mqd_manager { int (*load_mqd)(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, - uint32_t __user *wptr); + struct queue_properties *p, + struct mm_struct *mms); int (*update_mqd)(struct mqd_manager *mm, void *mqd, struct queue_properties *q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 6acc4313363e..44ffd23348fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -44,10 +44,6 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, struct cik_mqd *m; int retval; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), mqd_mem_obj); @@ -101,7 +97,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_iq_rptr = AQL_ENABLE; *mqd = m; - if (gart_addr != NULL) + if (gart_addr) *gart_addr = addr; retval = mm->update_mqd(mm, m, q); @@ -115,8 +111,6 @@ static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, int retval; struct cik_sdma_rlc_registers *m; - BUG_ON(!mm || !mqd || !mqd_mem_obj); - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_sdma_rlc_registers), mqd_mem_obj); @@ -129,7 +123,7 @@ static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); *mqd = m; - if (gart_addr != NULL) + if (gart_addr) *gart_addr = (*mqd_mem_obj)->gpu_addr; retval = mm->update_mqd(mm, m, q); @@ -140,27 +134,31 @@ static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, static void uninit_mqd(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - BUG_ON(!mm || !mqd); kfd_gtt_sa_free(mm->dev, mqd_mem_obj); } static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - BUG_ON(!mm || !mqd); kfd_gtt_sa_free(mm->dev, mqd_mem_obj); } static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, struct queue_properties *p, + struct mm_struct *mms) { - return mm->dev->kfd2kgd->hqd_load - (mm->dev->kgd, mqd, pipe_id, queue_id, wptr); + /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ + uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); + uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1); + + return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, + (uint32_t __user *)p->write_ptr, + wptr_shift, wptr_mask, mms); } static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, - uint32_t pipe_id, uint32_t queue_id, - uint32_t __user *wptr) + uint32_t pipe_id, uint32_t queue_id, + struct queue_properties *p, struct mm_struct *mms) { return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd); } @@ -170,10 +168,6 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, { struct cik_mqd *m; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - m = get_mqd(mqd); m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN; @@ -188,21 +182,17 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); - m->cp_hqd_pq_doorbell_control = DOORBELL_EN | - DOORBELL_OFFSET(q->doorbell_off); + m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); m->cp_hqd_vmid = q->vmid; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_pq_control |= NO_UPDATE_RPTR; - } - m->cp_hqd_active = 0; q->is_active = false; if (q->queue_size > 0 && q->queue_address != 0 && q->queue_percent > 0) { - m->cp_hqd_active = 1; q->is_active = true; } @@ -214,8 +204,6 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, { struct cik_sdma_rlc_registers *m; - BUG_ON(!mm || !mqd || !q); - m = get_sdma_mqd(mqd); m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | @@ -254,7 +242,7 @@ static int destroy_mqd(struct mqd_manager *mm, void *mqd, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id) { - return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, type, timeout, + return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout, pipe_id, queue_id); } @@ -301,10 +289,6 @@ static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, struct cik_mqd *m; int retval; - BUG_ON(!mm || !q || !mqd || !mqd_mem_obj); - - pr_debug("kfd: In func %s\n", __func__); - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), mqd_mem_obj); @@ -359,10 +343,6 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, { struct cik_mqd *m; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - m = get_mqd(mqd); m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | DEFAULT_MIN_AVAIL_SIZE | @@ -400,8 +380,6 @@ struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) { struct cik_sdma_rlc_registers *m; - BUG_ON(!mqd); - m = (struct cik_sdma_rlc_registers *)mqd; return m; @@ -412,12 +390,10 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, { struct mqd_manager *mqd; - BUG_ON(!dev); - BUG_ON(type >= KFD_MQD_TYPE_MAX); - - pr_debug("kfd: In func %s\n", __func__); + if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) + return NULL; - mqd = kzalloc(sizeof(struct mqd_manager), GFP_KERNEL); + mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); if (!mqd) return NULL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index a9b9882a9a77..73cbfe186dd2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -85,7 +85,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_iq_rptr = 1; *mqd = m; - if (gart_addr != NULL) + if (gart_addr) *gart_addr = addr; retval = mm->update_mqd(mm, m, q); @@ -94,10 +94,15 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, - uint32_t __user *wptr) + struct queue_properties *p, struct mm_struct *mms) { - return mm->dev->kfd2kgd->hqd_load - (mm->dev->kgd, mqd, pipe_id, queue_id, wptr); + /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ + uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); + uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1); + + return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, + (uint32_t __user *)p->write_ptr, + wptr_shift, wptr_mask, mms); } static int __update_mqd(struct mqd_manager *mm, void *mqd, @@ -106,10 +111,6 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, { struct vi_mqd *m; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - m = get_mqd(mqd); m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | @@ -117,7 +118,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT; m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; - pr_debug("kfd: cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); + pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); @@ -126,10 +127,9 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); m->cp_hqd_pq_doorbell_control = - 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT | q->doorbell_off << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; - pr_debug("kfd: cp_hqd_pq_doorbell_control 0x%x\n", + pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", m->cp_hqd_pq_doorbell_control); m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT | @@ -139,8 +139,15 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT; - m->cp_hqd_eop_control |= - ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1; + /* + * HW does not clamp this field correctly. Maximum EOP queue size + * is constrained by per-SE EOP done signal count, which is 8-bit. + * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit + * more than (EOP entry count - 1) so a queue size of 0x800 dwords + * is safe, giving a maximum field value of 0xA. + */ + m->cp_hqd_eop_control |= min(0xA, + ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); m->cp_hqd_eop_base_addr_lo = lower_32_bits(q->eop_ring_buffer_address >> 8); m->cp_hqd_eop_base_addr_hi = @@ -156,12 +163,10 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; } - m->cp_hqd_active = 0; q->is_active = false; if (q->queue_size > 0 && q->queue_address != 0 && q->queue_percent > 0) { - m->cp_hqd_active = 1; q->is_active = true; } @@ -181,14 +186,13 @@ static int destroy_mqd(struct mqd_manager *mm, void *mqd, uint32_t queue_id) { return mm->dev->kfd2kgd->hqd_destroy - (mm->dev->kgd, type, timeout, + (mm->dev->kgd, mqd, type, timeout, pipe_id, queue_id); } static void uninit_mqd(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - BUG_ON(!mm || !mqd); kfd_gtt_sa_free(mm->dev, mqd_mem_obj); } @@ -238,12 +242,10 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, { struct mqd_manager *mqd; - BUG_ON(!dev); - BUG_ON(type >= KFD_MQD_TYPE_MAX); - - pr_debug("kfd: In func %s\n", __func__); + if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) + return NULL; - mqd = kzalloc(sizeof(struct mqd_manager), GFP_KERNEL); + mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); if (!mqd) return NULL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 7131998848d7..1d312603de9f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -26,7 +26,6 @@ #include "kfd_device_queue_manager.h" #include "kfd_kernel_queue.h" #include "kfd_priv.h" -#include "kfd_pm4_headers.h" #include "kfd_pm4_headers_vi.h" #include "kfd_pm4_opcodes.h" @@ -35,7 +34,8 @@ static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes, { unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t); - BUG_ON((temp * sizeof(uint32_t)) > buffer_size_bytes); + WARN((temp * sizeof(uint32_t)) > buffer_size_bytes, + "Runlist IB overflow"); *wptr = temp; } @@ -43,12 +43,12 @@ static unsigned int build_pm4_header(unsigned int opcode, size_t packet_size) { union PM4_MES_TYPE_3_HEADER header; - header.u32all = 0; + header.u32All = 0; header.opcode = opcode; header.count = packet_size/sizeof(uint32_t) - 2; header.type = PM4_TYPE_3; - return header.u32all; + return header.u32All; } static void pm_calc_rlib_size(struct packet_manager *pm, @@ -58,8 +58,6 @@ static void pm_calc_rlib_size(struct packet_manager *pm, unsigned int process_count, queue_count; unsigned int map_queue_size; - BUG_ON(!pm || !rlib_size || !over_subscription); - process_count = pm->dqm->processes_count; queue_count = pm->dqm->queue_count; @@ -67,15 +65,12 @@ static void pm_calc_rlib_size(struct packet_manager *pm, *over_subscription = false; if ((process_count > 1) || queue_count > get_queues_num(pm->dqm)) { *over_subscription = true; - pr_debug("kfd: over subscribed runlist\n"); + pr_debug("Over subscribed runlist\n"); } - map_queue_size = - (pm->dqm->dev->device_info->asic_family == CHIP_CARRIZO) ? - sizeof(struct pm4_mes_map_queues) : - sizeof(struct pm4_map_queues); + map_queue_size = sizeof(struct pm4_mes_map_queues); /* calculate run list ib allocation size */ - *rlib_size = process_count * sizeof(struct pm4_map_process) + + *rlib_size = process_count * sizeof(struct pm4_mes_map_process) + queue_count * map_queue_size; /* @@ -83,9 +78,9 @@ static void pm_calc_rlib_size(struct packet_manager *pm, * when over subscription */ if (*over_subscription) - *rlib_size += sizeof(struct pm4_runlist); + *rlib_size += sizeof(struct pm4_mes_runlist); - pr_debug("kfd: runlist ib size %d\n", *rlib_size); + pr_debug("runlist ib size %d\n", *rlib_size); } static int pm_allocate_runlist_ib(struct packet_manager *pm, @@ -96,17 +91,16 @@ static int pm_allocate_runlist_ib(struct packet_manager *pm, { int retval; - BUG_ON(!pm); - BUG_ON(pm->allocated); - BUG_ON(is_over_subscription == NULL); + if (WARN_ON(pm->allocated)) + return -EINVAL; pm_calc_rlib_size(pm, rl_buffer_size, is_over_subscription); retval = kfd_gtt_sa_allocate(pm->dqm->dev, *rl_buffer_size, &pm->ib_buffer_obj); - if (retval != 0) { - pr_err("kfd: failed to allocate runlist IB\n"); + if (retval) { + pr_err("Failed to allocate runlist IB\n"); return retval; } @@ -121,15 +115,16 @@ static int pm_allocate_runlist_ib(struct packet_manager *pm, static int pm_create_runlist(struct packet_manager *pm, uint32_t *buffer, uint64_t ib, size_t ib_size_in_dwords, bool chain) { - struct pm4_runlist *packet; + struct pm4_mes_runlist *packet; - BUG_ON(!pm || !buffer || !ib); + if (WARN_ON(!ib)) + return -EFAULT; - packet = (struct pm4_runlist *)buffer; + packet = (struct pm4_mes_runlist *)buffer; - memset(buffer, 0, sizeof(struct pm4_runlist)); - packet->header.u32all = build_pm4_header(IT_RUN_LIST, - sizeof(struct pm4_runlist)); + memset(buffer, 0, sizeof(struct pm4_mes_runlist)); + packet->header.u32All = build_pm4_header(IT_RUN_LIST, + sizeof(struct pm4_mes_runlist)); packet->bitfields4.ib_size = ib_size_in_dwords; packet->bitfields4.chain = chain ? 1 : 0; @@ -144,20 +139,16 @@ static int pm_create_runlist(struct packet_manager *pm, uint32_t *buffer, static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer, struct qcm_process_device *qpd) { - struct pm4_map_process *packet; + struct pm4_mes_map_process *packet; struct queue *cur; uint32_t num_queues; - BUG_ON(!pm || !buffer || !qpd); - - packet = (struct pm4_map_process *)buffer; - - pr_debug("kfd: In func %s\n", __func__); + packet = (struct pm4_mes_map_process *)buffer; - memset(buffer, 0, sizeof(struct pm4_map_process)); + memset(buffer, 0, sizeof(struct pm4_mes_map_process)); - packet->header.u32all = build_pm4_header(IT_MAP_PROCESS, - sizeof(struct pm4_map_process)); + packet->header.u32All = build_pm4_header(IT_MAP_PROCESS, + sizeof(struct pm4_mes_map_process)); packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; packet->bitfields2.process_quantum = 1; packet->bitfields2.pasid = qpd->pqm->process->pasid; @@ -175,27 +166,26 @@ static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer, packet->sh_mem_ape1_base = qpd->sh_mem_ape1_base; packet->sh_mem_ape1_limit = qpd->sh_mem_ape1_limit; + /* TODO: scratch support */ + packet->sh_hidden_private_base_vmid = 0; + packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); return 0; } -static int pm_create_map_queue_vi(struct packet_manager *pm, uint32_t *buffer, +static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, struct queue *q, bool is_static) { struct pm4_mes_map_queues *packet; bool use_static = is_static; - BUG_ON(!pm || !buffer || !q); - - pr_debug("kfd: In func %s\n", __func__); - packet = (struct pm4_mes_map_queues *)buffer; - memset(buffer, 0, sizeof(struct pm4_map_queues)); + memset(buffer, 0, sizeof(struct pm4_mes_map_queues)); - packet->header.u32all = build_pm4_header(IT_MAP_QUEUES, - sizeof(struct pm4_map_queues)); + packet->header.u32All = build_pm4_header(IT_MAP_QUEUES, + sizeof(struct pm4_mes_map_queues)); packet->bitfields2.alloc_format = alloc_format__mes_map_queues__one_per_pipe_vi; packet->bitfields2.num_queues = 1; @@ -223,10 +213,8 @@ static int pm_create_map_queue_vi(struct packet_manager *pm, uint32_t *buffer, use_static = false; /* no static queues under SDMA */ break; default: - pr_err("kfd: in %s queue type %d\n", __func__, - q->properties.type); - BUG(); - break; + WARN(1, "queue type %d", q->properties.type); + return -EINVAL; } packet->bitfields3.doorbell_offset = q->properties.doorbell_off; @@ -246,68 +234,6 @@ static int pm_create_map_queue_vi(struct packet_manager *pm, uint32_t *buffer, return 0; } -static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, - struct queue *q, bool is_static) -{ - struct pm4_map_queues *packet; - bool use_static = is_static; - - BUG_ON(!pm || !buffer || !q); - - pr_debug("kfd: In func %s\n", __func__); - - packet = (struct pm4_map_queues *)buffer; - memset(buffer, 0, sizeof(struct pm4_map_queues)); - - packet->header.u32all = build_pm4_header(IT_MAP_QUEUES, - sizeof(struct pm4_map_queues)); - packet->bitfields2.alloc_format = - alloc_format__mes_map_queues__one_per_pipe; - packet->bitfields2.num_queues = 1; - packet->bitfields2.queue_sel = - queue_sel__mes_map_queues__map_to_hws_determined_queue_slots; - - packet->bitfields2.vidmem = (q->properties.is_interop) ? - vidmem__mes_map_queues__uses_video_memory : - vidmem__mes_map_queues__uses_no_video_memory; - - switch (q->properties.type) { - case KFD_QUEUE_TYPE_COMPUTE: - case KFD_QUEUE_TYPE_DIQ: - packet->bitfields2.engine_sel = - engine_sel__mes_map_queues__compute; - break; - case KFD_QUEUE_TYPE_SDMA: - packet->bitfields2.engine_sel = - engine_sel__mes_map_queues__sdma0; - use_static = false; /* no static queues under SDMA */ - break; - default: - BUG(); - break; - } - - packet->mes_map_queues_ordinals[0].bitfields3.doorbell_offset = - q->properties.doorbell_off; - - packet->mes_map_queues_ordinals[0].bitfields3.is_static = - (use_static) ? 1 : 0; - - packet->mes_map_queues_ordinals[0].mqd_addr_lo = - lower_32_bits(q->gart_mqd_addr); - - packet->mes_map_queues_ordinals[0].mqd_addr_hi = - upper_32_bits(q->gart_mqd_addr); - - packet->mes_map_queues_ordinals[0].wptr_addr_lo = - lower_32_bits((uint64_t)q->properties.write_ptr); - - packet->mes_map_queues_ordinals[0].wptr_addr_hi = - upper_32_bits((uint64_t)q->properties.write_ptr); - - return 0; -} - static int pm_create_runlist_ib(struct packet_manager *pm, struct list_head *queues, uint64_t *rl_gpu_addr, @@ -322,19 +248,16 @@ static int pm_create_runlist_ib(struct packet_manager *pm, struct kernel_queue *kq; bool is_over_subscription; - BUG_ON(!pm || !queues || !rl_size_bytes || !rl_gpu_addr); - rl_wptr = retval = proccesses_mapped = 0; retval = pm_allocate_runlist_ib(pm, &rl_buffer, rl_gpu_addr, &alloc_size_bytes, &is_over_subscription); - if (retval != 0) + if (retval) return retval; *rl_size_bytes = alloc_size_bytes; - pr_debug("kfd: In func %s\n", __func__); - pr_debug("kfd: building runlist ib process count: %d queues count %d\n", + pr_debug("Building runlist ib process count: %d queues count %d\n", pm->dqm->processes_count, pm->dqm->queue_count); /* build the run list ib packet */ @@ -342,42 +265,35 @@ static int pm_create_runlist_ib(struct packet_manager *pm, qpd = cur->qpd; /* build map process packet */ if (proccesses_mapped >= pm->dqm->processes_count) { - pr_debug("kfd: not enough space left in runlist IB\n"); + pr_debug("Not enough space left in runlist IB\n"); pm_release_ib(pm); return -ENOMEM; } retval = pm_create_map_process(pm, &rl_buffer[rl_wptr], qpd); - if (retval != 0) + if (retval) return retval; proccesses_mapped++; - inc_wptr(&rl_wptr, sizeof(struct pm4_map_process), + inc_wptr(&rl_wptr, sizeof(struct pm4_mes_map_process), alloc_size_bytes); list_for_each_entry(kq, &qpd->priv_queue_list, list) { if (!kq->queue->properties.is_active) continue; - pr_debug("kfd: static_queue, mapping kernel q %d, is debug status %d\n", + pr_debug("static_queue, mapping kernel q %d, is debug status %d\n", kq->queue->queue, qpd->is_debug); - if (pm->dqm->dev->device_info->asic_family == - CHIP_CARRIZO) - retval = pm_create_map_queue_vi(pm, - &rl_buffer[rl_wptr], - kq->queue, - qpd->is_debug); - else - retval = pm_create_map_queue(pm, + retval = pm_create_map_queue(pm, &rl_buffer[rl_wptr], kq->queue, qpd->is_debug); - if (retval != 0) + if (retval) return retval; inc_wptr(&rl_wptr, - sizeof(struct pm4_map_queues), + sizeof(struct pm4_mes_map_queues), alloc_size_bytes); } @@ -385,51 +301,44 @@ static int pm_create_runlist_ib(struct packet_manager *pm, if (!q->properties.is_active) continue; - pr_debug("kfd: static_queue, mapping user queue %d, is debug status %d\n", + pr_debug("static_queue, mapping user queue %d, is debug status %d\n", q->queue, qpd->is_debug); - if (pm->dqm->dev->device_info->asic_family == - CHIP_CARRIZO) - retval = pm_create_map_queue_vi(pm, - &rl_buffer[rl_wptr], - q, - qpd->is_debug); - else - retval = pm_create_map_queue(pm, + retval = pm_create_map_queue(pm, &rl_buffer[rl_wptr], q, qpd->is_debug); - if (retval != 0) + if (retval) return retval; inc_wptr(&rl_wptr, - sizeof(struct pm4_map_queues), + sizeof(struct pm4_mes_map_queues), alloc_size_bytes); } } - pr_debug("kfd: finished map process and queues to runlist\n"); + pr_debug("Finished map process and queues to runlist\n"); if (is_over_subscription) - pm_create_runlist(pm, &rl_buffer[rl_wptr], *rl_gpu_addr, - alloc_size_bytes / sizeof(uint32_t), true); + retval = pm_create_runlist(pm, &rl_buffer[rl_wptr], + *rl_gpu_addr, + alloc_size_bytes / sizeof(uint32_t), + true); for (i = 0; i < alloc_size_bytes / sizeof(uint32_t); i++) pr_debug("0x%2X ", rl_buffer[i]); pr_debug("\n"); - return 0; + return retval; } int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) { - BUG_ON(!dqm); - pm->dqm = dqm; mutex_init(&pm->lock); pm->priv_queue = kernel_queue_init(dqm->dev, KFD_QUEUE_TYPE_HIQ); - if (pm->priv_queue == NULL) { + if (!pm->priv_queue) { mutex_destroy(&pm->lock); return -ENOMEM; } @@ -440,8 +349,6 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) void pm_uninit(struct packet_manager *pm) { - BUG_ON(!pm); - mutex_destroy(&pm->lock); kernel_queue_uninit(pm->priv_queue); } @@ -449,25 +356,22 @@ void pm_uninit(struct packet_manager *pm) int pm_send_set_resources(struct packet_manager *pm, struct scheduling_resources *res) { - struct pm4_set_resources *packet; - - BUG_ON(!pm || !res); - - pr_debug("kfd: In func %s\n", __func__); + struct pm4_mes_set_resources *packet; + int retval = 0; mutex_lock(&pm->lock); pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, sizeof(*packet) / sizeof(uint32_t), - (unsigned int **)&packet); - if (packet == NULL) { - mutex_unlock(&pm->lock); - pr_err("kfd: failed to allocate buffer on kernel queue\n"); - return -ENOMEM; + (unsigned int **)&packet); + if (!packet) { + pr_err("Failed to allocate buffer on kernel queue\n"); + retval = -ENOMEM; + goto out; } - memset(packet, 0, sizeof(struct pm4_set_resources)); - packet->header.u32all = build_pm4_header(IT_SET_RESOURCES, - sizeof(struct pm4_set_resources)); + memset(packet, 0, sizeof(struct pm4_mes_set_resources)); + packet->header.u32All = build_pm4_header(IT_SET_RESOURCES, + sizeof(struct pm4_mes_set_resources)); packet->bitfields2.queue_type = queue_type__mes_set_resources__hsa_interface_queue_hiq; @@ -485,9 +389,10 @@ int pm_send_set_resources(struct packet_manager *pm, pm->priv_queue->ops.submit_packet(pm->priv_queue); +out: mutex_unlock(&pm->lock); - return 0; + return retval; } int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) @@ -497,26 +402,24 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) size_t rl_ib_size, packet_size_dwords; int retval; - BUG_ON(!pm || !dqm_queues); - retval = pm_create_runlist_ib(pm, dqm_queues, &rl_gpu_ib_addr, &rl_ib_size); - if (retval != 0) + if (retval) goto fail_create_runlist_ib; - pr_debug("kfd: runlist IB address: 0x%llX\n", rl_gpu_ib_addr); + pr_debug("runlist IB address: 0x%llX\n", rl_gpu_ib_addr); - packet_size_dwords = sizeof(struct pm4_runlist) / sizeof(uint32_t); + packet_size_dwords = sizeof(struct pm4_mes_runlist) / sizeof(uint32_t); mutex_lock(&pm->lock); retval = pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, packet_size_dwords, &rl_buffer); - if (retval != 0) + if (retval) goto fail_acquire_packet_buffer; retval = pm_create_runlist(pm, rl_buffer, rl_gpu_ib_addr, rl_ib_size / sizeof(uint32_t), false); - if (retval != 0) + if (retval) goto fail_create_runlist; pm->priv_queue->ops.submit_packet(pm->priv_queue); @@ -530,8 +433,7 @@ fail_create_runlist: fail_acquire_packet_buffer: mutex_unlock(&pm->lock); fail_create_runlist_ib: - if (pm->allocated) - pm_release_ib(pm); + pm_release_ib(pm); return retval; } @@ -539,20 +441,21 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, uint32_t fence_value) { int retval; - struct pm4_query_status *packet; + struct pm4_mes_query_status *packet; - BUG_ON(!pm || !fence_address); + if (WARN_ON(!fence_address)) + return -EFAULT; mutex_lock(&pm->lock); retval = pm->priv_queue->ops.acquire_packet_buffer( pm->priv_queue, - sizeof(struct pm4_query_status) / sizeof(uint32_t), + sizeof(struct pm4_mes_query_status) / sizeof(uint32_t), (unsigned int **)&packet); - if (retval != 0) + if (retval) goto fail_acquire_packet_buffer; - packet->header.u32all = build_pm4_header(IT_QUERY_STATUS, - sizeof(struct pm4_query_status)); + packet->header.u32All = build_pm4_header(IT_QUERY_STATUS, + sizeof(struct pm4_mes_query_status)); packet->bitfields2.context_id = 0; packet->bitfields2.interrupt_sel = @@ -566,9 +469,6 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, packet->data_lo = lower_32_bits((uint64_t)fence_value); pm->priv_queue->ops.submit_packet(pm->priv_queue); - mutex_unlock(&pm->lock); - - return 0; fail_acquire_packet_buffer: mutex_unlock(&pm->lock); @@ -582,24 +482,22 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, { int retval; uint32_t *buffer; - struct pm4_unmap_queues *packet; - - BUG_ON(!pm); + struct pm4_mes_unmap_queues *packet; mutex_lock(&pm->lock); retval = pm->priv_queue->ops.acquire_packet_buffer( pm->priv_queue, - sizeof(struct pm4_unmap_queues) / sizeof(uint32_t), + sizeof(struct pm4_mes_unmap_queues) / sizeof(uint32_t), &buffer); - if (retval != 0) + if (retval) goto err_acquire_packet_buffer; - packet = (struct pm4_unmap_queues *)buffer; - memset(buffer, 0, sizeof(struct pm4_unmap_queues)); - pr_debug("kfd: static_queue: unmapping queues: mode is %d , reset is %d , type is %d\n", + packet = (struct pm4_mes_unmap_queues *)buffer; + memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues)); + pr_debug("static_queue: unmapping queues: mode is %d , reset is %d , type is %d\n", mode, reset, type); - packet->header.u32all = build_pm4_header(IT_UNMAP_QUEUES, - sizeof(struct pm4_unmap_queues)); + packet->header.u32All = build_pm4_header(IT_UNMAP_QUEUES, + sizeof(struct pm4_mes_unmap_queues)); switch (type) { case KFD_QUEUE_TYPE_COMPUTE: case KFD_QUEUE_TYPE_DIQ: @@ -611,8 +509,9 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, engine_sel__mes_unmap_queues__sdma0 + sdma_engine; break; default: - BUG(); - break; + WARN(1, "queue type %d", type); + retval = -EINVAL; + goto err_invalid; } if (reset) @@ -636,16 +535,17 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, break; case KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES: packet->bitfields2.queue_sel = - queue_sel__mes_unmap_queues__perform_request_on_all_active_queues; + queue_sel__mes_unmap_queues__unmap_all_queues; break; case KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES: /* in this case, we do not preempt static queues */ packet->bitfields2.queue_sel = - queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only; + queue_sel__mes_unmap_queues__unmap_all_non_static_queues; break; default: - BUG(); - break; + WARN(1, "filter %d", mode); + retval = -EINVAL; + goto err_invalid; } pm->priv_queue->ops.submit_packet(pm->priv_queue); @@ -653,6 +553,8 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, mutex_unlock(&pm->lock); return 0; +err_invalid: + pm->priv_queue->ops.rollback_packet(pm->priv_queue); err_acquire_packet_buffer: mutex_unlock(&pm->lock); return retval; @@ -660,8 +562,6 @@ err_acquire_packet_buffer: void pm_release_ib(struct packet_manager *pm) { - BUG_ON(!pm); - mutex_lock(&pm->lock); if (pm->allocated) { kfd_gtt_sa_free(pm->dqm->dev, pm->ib_buffer_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c index 6cfe7f1f18cf..d6a796144269 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c @@ -20,77 +20,64 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <linux/slab.h> #include <linux/types.h> #include "kfd_priv.h" -static unsigned long *pasid_bitmap; -static unsigned int pasid_limit; -static DEFINE_MUTEX(pasid_mutex); - -int kfd_pasid_init(void) -{ - pasid_limit = KFD_MAX_NUM_OF_PROCESSES; - - pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long), GFP_KERNEL); - if (!pasid_bitmap) - return -ENOMEM; - - set_bit(0, pasid_bitmap); /* PASID 0 is reserved. */ - - return 0; -} - -void kfd_pasid_exit(void) -{ - kfree(pasid_bitmap); -} +static unsigned int pasid_bits = 16; +static const struct kfd2kgd_calls *kfd2kgd; bool kfd_set_pasid_limit(unsigned int new_limit) { - if (new_limit < pasid_limit) { - bool ok; - - mutex_lock(&pasid_mutex); - - /* ensure that no pasids >= new_limit are in-use */ - ok = (find_next_bit(pasid_bitmap, pasid_limit, new_limit) == - pasid_limit); - if (ok) - pasid_limit = new_limit; - - mutex_unlock(&pasid_mutex); - - return ok; + if (new_limit < 2) + return false; + + if (new_limit < (1U << pasid_bits)) { + if (kfd2kgd) + /* We've already allocated user PASIDs, too late to + * change the limit + */ + return false; + + while (new_limit < (1U << pasid_bits)) + pasid_bits--; } return true; } -inline unsigned int kfd_get_pasid_limit(void) +unsigned int kfd_get_pasid_limit(void) { - return pasid_limit; + return 1U << pasid_bits; } unsigned int kfd_pasid_alloc(void) { - unsigned int found; - - mutex_lock(&pasid_mutex); - - found = find_first_zero_bit(pasid_bitmap, pasid_limit); - if (found == pasid_limit) - found = 0; - else - set_bit(found, pasid_bitmap); + int r; + + /* Find the first best KFD device for calling KGD */ + if (!kfd2kgd) { + struct kfd_dev *dev = NULL; + unsigned int i = 0; + + while ((dev = kfd_topology_enum_kfd_devices(i)) != NULL) { + if (dev && dev->kfd2kgd) { + kfd2kgd = dev->kfd2kgd; + break; + } + i++; + } + + if (!kfd2kgd) + return false; + } - mutex_unlock(&pasid_mutex); + r = kfd2kgd->alloc_pasid(pasid_bits); - return found; + return r > 0 ? r : 0; } void kfd_pasid_free(unsigned int pasid) { - BUG_ON(pasid == 0 || pasid >= pasid_limit); - clear_bit(pasid, pasid_bitmap); + if (kfd2kgd) + kfd2kgd->free_pasid(pasid); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h index 5b393f3e34a9..e50f73d25de6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h @@ -28,112 +28,19 @@ #define PM4_MES_HEADER_DEFINED union PM4_MES_TYPE_3_HEADER { struct { - uint32_t reserved1:8; /* < reserved */ - uint32_t opcode:8; /* < IT opcode */ - uint32_t count:14; /* < number of DWORDs - 1 - * in the information body. - */ - uint32_t type:2; /* < packet identifier. - * It should be 3 for type 3 packets - */ + /* reserved */ + uint32_t reserved1:8; + /* IT opcode */ + uint32_t opcode:8; + /* number of DWORDs - 1 in the information body */ + uint32_t count:14; + /* packet identifier. It should be 3 for type 3 packets */ + uint32_t type:2; }; uint32_t u32all; }; #endif /* PM4_MES_HEADER_DEFINED */ -/* --------------------MES_SET_RESOURCES-------------------- */ - -#ifndef PM4_MES_SET_RESOURCES_DEFINED -#define PM4_MES_SET_RESOURCES_DEFINED -enum set_resources_queue_type_enum { - queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, - queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, - queue_type__mes_set_resources__hsa_debug_interface_queue = 4 -}; - -struct pm4_set_resources { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t vmid_mask:16; - uint32_t unmap_latency:8; - uint32_t reserved1:5; - enum set_resources_queue_type_enum queue_type:3; - } bitfields2; - uint32_t ordinal2; - }; - - uint32_t queue_mask_lo; - uint32_t queue_mask_hi; - uint32_t gws_mask_lo; - uint32_t gws_mask_hi; - - union { - struct { - uint32_t oac_mask:16; - uint32_t reserved2:16; - } bitfields7; - uint32_t ordinal7; - }; - - union { - struct { - uint32_t gds_heap_base:6; - uint32_t reserved3:5; - uint32_t gds_heap_size:6; - uint32_t reserved4:15; - } bitfields8; - uint32_t ordinal8; - }; - -}; -#endif - -/*--------------------MES_RUN_LIST-------------------- */ - -#ifndef PM4_MES_RUN_LIST_DEFINED -#define PM4_MES_RUN_LIST_DEFINED - -struct pm4_runlist { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t reserved1:2; - uint32_t ib_base_lo:30; - } bitfields2; - uint32_t ordinal2; - }; - - union { - struct { - uint32_t ib_base_hi:16; - uint32_t reserved2:16; - } bitfields3; - uint32_t ordinal3; - }; - - union { - struct { - uint32_t ib_size:20; - uint32_t chain:1; - uint32_t offload_polling:1; - uint32_t reserved3:1; - uint32_t valid:1; - uint32_t reserved4:8; - } bitfields4; - uint32_t ordinal4; - }; - -}; -#endif /*--------------------MES_MAP_PROCESS-------------------- */ @@ -186,217 +93,58 @@ struct pm4_map_process { }; #endif -/*--------------------MES_MAP_QUEUES--------------------*/ - -#ifndef PM4_MES_MAP_QUEUES_DEFINED -#define PM4_MES_MAP_QUEUES_DEFINED -enum map_queues_queue_sel_enum { - queue_sel__mes_map_queues__map_to_specified_queue_slots = 0, - queue_sel__mes_map_queues__map_to_hws_determined_queue_slots = 1, - queue_sel__mes_map_queues__enable_process_queues = 2 -}; +#ifndef PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH +#define PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH -enum map_queues_vidmem_enum { - vidmem__mes_map_queues__uses_no_video_memory = 0, - vidmem__mes_map_queues__uses_video_memory = 1 -}; - -enum map_queues_alloc_format_enum { - alloc_format__mes_map_queues__one_per_pipe = 0, - alloc_format__mes_map_queues__all_on_one_pipe = 1 -}; - -enum map_queues_engine_sel_enum { - engine_sel__mes_map_queues__compute = 0, - engine_sel__mes_map_queues__sdma0 = 2, - engine_sel__mes_map_queues__sdma1 = 3 -}; - -struct pm4_map_queues { +struct pm4_map_process_scratch_kv { union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t reserved1:4; - enum map_queues_queue_sel_enum queue_sel:2; - uint32_t reserved2:2; - uint32_t vmid:4; - uint32_t reserved3:4; - enum map_queues_vidmem_enum vidmem:2; - uint32_t reserved4:6; - enum map_queues_alloc_format_enum alloc_format:2; - enum map_queues_engine_sel_enum engine_sel:3; - uint32_t num_queues:3; - } bitfields2; - uint32_t ordinal2; - }; - - struct { - union { - struct { - uint32_t is_static:1; - uint32_t reserved5:1; - uint32_t doorbell_offset:21; - uint32_t reserved6:3; - uint32_t queue:6; - } bitfields3; - uint32_t ordinal3; - }; - - uint32_t mqd_addr_lo; - uint32_t mqd_addr_hi; - uint32_t wptr_addr_lo; - uint32_t wptr_addr_hi; - - } mes_map_queues_ordinals[1]; /* 1..N of these ordinal groups */ - -}; -#endif - -/*--------------------MES_QUERY_STATUS--------------------*/ - -#ifndef PM4_MES_QUERY_STATUS_DEFINED -#define PM4_MES_QUERY_STATUS_DEFINED -enum query_status_interrupt_sel_enum { - interrupt_sel__mes_query_status__completion_status = 0, - interrupt_sel__mes_query_status__process_status = 1, - interrupt_sel__mes_query_status__queue_status = 2 -}; - -enum query_status_command_enum { - command__mes_query_status__interrupt_only = 0, - command__mes_query_status__fence_only_immediate = 1, - command__mes_query_status__fence_only_after_write_ack = 2, - command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 -}; - -enum query_status_engine_sel_enum { - engine_sel__mes_query_status__compute = 0, - engine_sel__mes_query_status__sdma0_queue = 2, - engine_sel__mes_query_status__sdma1_queue = 3 -}; - -struct pm4_query_status { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t context_id:28; - enum query_status_interrupt_sel_enum interrupt_sel:2; - enum query_status_command_enum command:2; - } bitfields2; - uint32_t ordinal2; + union PM4_MES_TYPE_3_HEADER header; /* header */ + uint32_t ordinal1; }; union { struct { uint32_t pasid:16; - uint32_t reserved1:16; - } bitfields3a; - struct { - uint32_t reserved2:2; - uint32_t doorbell_offset:21; - uint32_t reserved3:3; - enum query_status_engine_sel_enum engine_sel:3; - uint32_t reserved4:3; - } bitfields3b; - uint32_t ordinal3; - }; - - uint32_t addr_lo; - uint32_t addr_hi; - uint32_t data_lo; - uint32_t data_hi; -}; -#endif - -/*--------------------MES_UNMAP_QUEUES--------------------*/ - -#ifndef PM4_MES_UNMAP_QUEUES_DEFINED -#define PM4_MES_UNMAP_QUEUES_DEFINED -enum unmap_queues_action_enum { - action__mes_unmap_queues__preempt_queues = 0, - action__mes_unmap_queues__reset_queues = 1, - action__mes_unmap_queues__disable_process_queues = 2 -}; - -enum unmap_queues_queue_sel_enum { - queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, - queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, - queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2, - queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only = 3 -}; - -enum unmap_queues_engine_sel_enum { - engine_sel__mes_unmap_queues__compute = 0, - engine_sel__mes_unmap_queues__sdma0 = 2, - engine_sel__mes_unmap_queues__sdma1 = 3 -}; - -struct pm4_unmap_queues { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - enum unmap_queues_action_enum action:2; - uint32_t reserved1:2; - enum unmap_queues_queue_sel_enum queue_sel:2; - uint32_t reserved2:20; - enum unmap_queues_engine_sel_enum engine_sel:3; - uint32_t num_queues:3; + uint32_t reserved1:8; + uint32_t diq_enable:1; + uint32_t process_quantum:7; } bitfields2; uint32_t ordinal2; }; union { struct { - uint32_t pasid:16; - uint32_t reserved3:16; - } bitfields3a; - struct { - uint32_t reserved4:2; - uint32_t doorbell_offset0:21; - uint32_t reserved5:9; - } bitfields3b; + uint32_t page_table_base:28; + uint32_t reserved2:4; + } bitfields3; uint32_t ordinal3; }; - union { - struct { - uint32_t reserved6:2; - uint32_t doorbell_offset1:21; - uint32_t reserved7:9; - } bitfields4; - uint32_t ordinal4; - }; - - union { - struct { - uint32_t reserved8:2; - uint32_t doorbell_offset2:21; - uint32_t reserved9:9; - } bitfields5; - uint32_t ordinal5; - }; + uint32_t reserved3; + uint32_t sh_mem_bases; + uint32_t sh_mem_config; + uint32_t sh_mem_ape1_base; + uint32_t sh_mem_ape1_limit; + uint32_t sh_hidden_private_base_vmid; + uint32_t reserved4; + uint32_t reserved5; + uint32_t gds_addr_lo; + uint32_t gds_addr_hi; union { struct { - uint32_t reserved10:2; - uint32_t doorbell_offset3:21; - uint32_t reserved11:9; - } bitfields6; - uint32_t ordinal6; + uint32_t num_gws:6; + uint32_t reserved6:2; + uint32_t num_oac:4; + uint32_t reserved7:4; + uint32_t gds_size:6; + uint32_t num_queues:10; + } bitfields14; + uint32_t ordinal14; }; + uint32_t completion_signal_lo32; +uint32_t completion_signal_hi32; }; #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h index 08c721922812..7c8d9b357749 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h @@ -30,10 +30,12 @@ union PM4_MES_TYPE_3_HEADER { struct { uint32_t reserved1 : 8; /* < reserved */ uint32_t opcode : 8; /* < IT opcode */ - uint32_t count : 14;/* < number of DWORDs - 1 in the - information body. */ - uint32_t type : 2; /* < packet identifier. - It should be 3 for type 3 packets */ + uint32_t count : 14;/* < Number of DWORDS - 1 in the + * information body + */ + uint32_t type : 2; /* < packet identifier + * It should be 3 for type 3 packets + */ }; uint32_t u32All; }; @@ -124,9 +126,10 @@ struct pm4_mes_runlist { uint32_t ib_size:20; uint32_t chain:1; uint32_t offload_polling:1; - uint32_t reserved3:1; + uint32_t reserved2:1; uint32_t valid:1; - uint32_t reserved4:8; + uint32_t process_cnt:4; + uint32_t reserved3:4; } bitfields4; uint32_t ordinal4; }; @@ -141,8 +144,8 @@ struct pm4_mes_runlist { struct pm4_mes_map_process { union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; + union PM4_MES_TYPE_3_HEADER header; /* header */ + uint32_t ordinal1; }; union { @@ -153,36 +156,48 @@ struct pm4_mes_map_process { uint32_t process_quantum:7; } bitfields2; uint32_t ordinal2; -}; + }; union { struct { uint32_t page_table_base:28; - uint32_t reserved2:4; + uint32_t reserved3:4; } bitfields3; uint32_t ordinal3; }; + uint32_t reserved; + uint32_t sh_mem_bases; + uint32_t sh_mem_config; uint32_t sh_mem_ape1_base; uint32_t sh_mem_ape1_limit; - uint32_t sh_mem_config; + + uint32_t sh_hidden_private_base_vmid; + + uint32_t reserved2; + uint32_t reserved3; + uint32_t gds_addr_lo; uint32_t gds_addr_hi; union { struct { uint32_t num_gws:6; - uint32_t reserved3:2; + uint32_t reserved4:2; uint32_t num_oac:4; - uint32_t reserved4:4; + uint32_t reserved5:4; uint32_t gds_size:6; uint32_t num_queues:10; } bitfields10; uint32_t ordinal10; }; + uint32_t completion_signal_lo; + uint32_t completion_signal_hi; + }; + #endif /*--------------------MES_MAP_QUEUES--------------------*/ @@ -335,7 +350,7 @@ enum mes_unmap_queues_engine_sel_enum { engine_sel__mes_unmap_queues__sdmal = 3 }; -struct PM4_MES_UNMAP_QUEUES { +struct pm4_mes_unmap_queues { union { union PM4_MES_TYPE_3_HEADER header; /* header */ uint32_t ordinal1; @@ -395,4 +410,101 @@ struct PM4_MES_UNMAP_QUEUES { }; #endif +#ifndef PM4_MEC_RELEASE_MEM_DEFINED +#define PM4_MEC_RELEASE_MEM_DEFINED +enum RELEASE_MEM_event_index_enum { + event_index___release_mem__end_of_pipe = 5, + event_index___release_mem__shader_done = 6 +}; + +enum RELEASE_MEM_cache_policy_enum { + cache_policy___release_mem__lru = 0, + cache_policy___release_mem__stream = 1, + cache_policy___release_mem__bypass = 2 +}; + +enum RELEASE_MEM_dst_sel_enum { + dst_sel___release_mem__memory_controller = 0, + dst_sel___release_mem__tc_l2 = 1, + dst_sel___release_mem__queue_write_pointer_register = 2, + dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 +}; + +enum RELEASE_MEM_int_sel_enum { + int_sel___release_mem__none = 0, + int_sel___release_mem__send_interrupt_only = 1, + int_sel___release_mem__send_interrupt_after_write_confirm = 2, + int_sel___release_mem__send_data_after_write_confirm = 3 +}; + +enum RELEASE_MEM_data_sel_enum { + data_sel___release_mem__none = 0, + data_sel___release_mem__send_32_bit_low = 1, + data_sel___release_mem__send_64_bit_data = 2, + data_sel___release_mem__send_gpu_clock_counter = 3, + data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, + data_sel___release_mem__store_gds_data_to_memory = 5 +}; + +struct pm4_mec_release_mem { + union { + union PM4_MES_TYPE_3_HEADER header; /*header */ + unsigned int ordinal1; + }; + + union { + struct { + unsigned int event_type:6; + unsigned int reserved1:2; + enum RELEASE_MEM_event_index_enum event_index:4; + unsigned int tcl1_vol_action_ena:1; + unsigned int tc_vol_action_ena:1; + unsigned int reserved2:1; + unsigned int tc_wb_action_ena:1; + unsigned int tcl1_action_ena:1; + unsigned int tc_action_ena:1; + unsigned int reserved3:6; + unsigned int atc:1; + enum RELEASE_MEM_cache_policy_enum cache_policy:2; + unsigned int reserved4:5; + } bitfields2; + unsigned int ordinal2; + }; + + union { + struct { + unsigned int reserved5:16; + enum RELEASE_MEM_dst_sel_enum dst_sel:2; + unsigned int reserved6:6; + enum RELEASE_MEM_int_sel_enum int_sel:3; + unsigned int reserved7:2; + enum RELEASE_MEM_data_sel_enum data_sel:3; + } bitfields3; + unsigned int ordinal3; + }; + + union { + struct { + unsigned int reserved8:2; + unsigned int address_lo_32b:30; + } bitfields4; + struct { + unsigned int reserved9:3; + unsigned int address_lo_64b:29; + } bitfields5; + unsigned int ordinal4; + }; + + unsigned int address_hi; + + unsigned int data_lo; + + unsigned int data_hi; +}; +#endif + +enum { + CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 +}; + #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4750cabe4252..634083e340d1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -157,9 +157,6 @@ struct kfd_dev { * to HW doorbell, GFX reserved some * at the start) */ - size_t doorbell_process_limit; /* Number of processes we have doorbell - * space for. - */ u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells * page used by kernel queue */ @@ -239,11 +236,6 @@ enum kfd_preempt_type_filter { KFD_PREEMPT_TYPE_FILTER_BY_PASID }; -enum kfd_preempt_type { - KFD_PREEMPT_TYPE_WAVEFRONT, - KFD_PREEMPT_TYPE_WAVEFRONT_RESET -}; - /** * enum kfd_queue_type * @@ -294,13 +286,13 @@ enum kfd_queue_format { * @write_ptr: Defines the number of dwords written to the ring buffer. * * @doorbell_ptr: This field aim is to notify the H/W of new packet written to - * the queue ring buffer. This field should be similar to write_ptr and the user - * should update this field after he updated the write_ptr. + * the queue ring buffer. This field should be similar to write_ptr and the + * user should update this field after he updated the write_ptr. * * @doorbell_off: The doorbell offset in the doorbell pci-bar. * - * @is_interop: Defines if this is a interop queue. Interop queue means that the - * queue can access both graphics and compute resources. + * @is_interop: Defines if this is a interop queue. Interop queue means that + * the queue can access both graphics and compute resources. * * @is_active: Defines if the queue is active or not. * @@ -352,9 +344,10 @@ struct queue_properties { * @properties: The queue properties. * * @mec: Used only in no cp scheduling mode and identifies to micro engine id - * that the queue should be execute on. + * that the queue should be execute on. * - * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe id. + * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe + * id. * * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. * @@ -436,6 +429,7 @@ struct qcm_process_device { uint32_t gds_size; uint32_t num_gws; uint32_t num_oac; + uint32_t sh_hidden_private_base; }; /* Data that is per-process-per device. */ @@ -498,6 +492,7 @@ struct kfd_process { struct rcu_head rcu; unsigned int pasid; + unsigned int doorbell_index; /* * List of kfd_process_device structures, @@ -520,10 +515,11 @@ struct kfd_process { struct mutex event_mutex; /* All events in process hashed by ID, linked on kfd_event.events. */ DECLARE_HASHTABLE(events, 4); - struct list_head signal_event_pages; /* struct slot_page_header. - event_pages */ + /* struct slot_page_header.event_pages */ + struct list_head signal_event_pages; u32 next_nonsignal_event_id; size_t signal_event_count; + bool signal_event_limit_reached; }; /** @@ -559,8 +555,10 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, struct kfd_process *p); /* Process device data iterator */ -struct kfd_process_device *kfd_get_first_process_device_data(struct kfd_process *p); -struct kfd_process_device *kfd_get_next_process_device_data(struct kfd_process *p, +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p); +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, struct kfd_process_device *pdd); bool kfd_has_process_device_data(struct kfd_process *p); @@ -573,7 +571,8 @@ unsigned int kfd_pasid_alloc(void); void kfd_pasid_free(unsigned int pasid); /* Doorbells */ -void kfd_doorbell_init(struct kfd_dev *kfd); +int kfd_doorbell_init(struct kfd_dev *kfd); +void kfd_doorbell_fini(struct kfd_dev *kfd); int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma); u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, unsigned int *doorbell_off); @@ -583,6 +582,10 @@ void write_kernel_doorbell(u32 __iomem *db, u32 value); unsigned int kfd_queue_id_to_doorbell(struct kfd_dev *kfd, struct kfd_process *process, unsigned int queue_id); +phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev, + struct kfd_process *process); +int kfd_alloc_process_doorbells(struct kfd_process *process); +void kfd_free_process_doorbells(struct kfd_process *process); /* GTT Sub-Allocator */ @@ -694,8 +697,6 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, void pm_release_ib(struct packet_manager *pm); uint64_t kfd_get_number_elems(struct kfd_dev *kfd); -phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev, - struct kfd_process *process); /* Events */ extern const struct kfd_event_interrupt_class event_interrupt_class_cik; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 035bbc98a63d..9e65ce3c1967 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -79,9 +79,7 @@ struct kfd_process *kfd_create_process(const struct task_struct *thread) { struct kfd_process *process; - BUG_ON(!kfd_process_wq); - - if (thread->mm == NULL) + if (!thread->mm) return ERR_PTR(-EINVAL); /* Only the pthreads threading model is supported. */ @@ -101,7 +99,7 @@ struct kfd_process *kfd_create_process(const struct task_struct *thread) /* A prior open of /dev/kfd could have already created the process. */ process = find_process(thread); if (process) - pr_debug("kfd: process already found\n"); + pr_debug("Process already found\n"); if (!process) process = create_process(thread); @@ -117,7 +115,7 @@ struct kfd_process *kfd_get_process(const struct task_struct *thread) { struct kfd_process *process; - if (thread->mm == NULL) + if (!thread->mm) return ERR_PTR(-EINVAL); /* Only the pthreads threading model is supported. */ @@ -185,6 +183,7 @@ static void kfd_process_wq_release(struct work_struct *work) kfd_event_free_process(p); kfd_pasid_free(p->pasid); + kfd_free_process_doorbells(p); mutex_unlock(&p->mutex); @@ -202,10 +201,8 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) struct kfd_process_release_work *work; struct kfd_process *p; - BUG_ON(!kfd_process_wq); - p = container_of(rcu, struct kfd_process, rcu); - BUG_ON(atomic_read(&p->mm->mm_count) <= 0); + WARN_ON(atomic_read(&p->mm->mm_count) <= 0); mmdrop(p->mm); @@ -229,7 +226,8 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, * mmu_notifier srcu is read locked */ p = container_of(mn, struct kfd_process, mmu_notifier); - BUG_ON(p->mm != mm); + if (WARN_ON(p->mm != mm)) + return; mutex_lock(&kfd_processes_mutex); hash_del_rcu(&p->kfd_processes); @@ -250,7 +248,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, kfd_dbgmgr_destroy(pdd->dev->dbgmgr); if (pdd->reset_wavefronts) { - pr_warn("amdkfd: Resetting all wave fronts\n"); + pr_warn("Resetting all wave fronts\n"); dbgdev_wave_reset_wavefronts(pdd->dev, p); pdd->reset_wavefronts = false; } @@ -291,6 +289,9 @@ static struct kfd_process *create_process(const struct task_struct *thread) if (process->pasid == 0) goto err_alloc_pasid; + if (kfd_alloc_process_doorbells(process) < 0) + goto err_alloc_doorbells; + mutex_init(&process->mutex); process->mm = thread->mm; @@ -332,6 +333,8 @@ err_process_pqm_init: mmu_notifier_unregister_no_release(&process->mmu_notifier, process->mm); err_mmu_notifier: mutex_destroy(&process->mutex); + kfd_free_process_doorbells(process); +err_alloc_doorbells: kfd_pasid_free(process->pasid); err_alloc_pasid: kfree(process->queues); @@ -407,8 +410,6 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid) struct kfd_process *p; struct kfd_process_device *pdd; - BUG_ON(dev == NULL); - /* * Look for the process that matches the pasid. If there is no such * process, we either released it in amdkfd's own notifier, or there @@ -449,14 +450,16 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid) mutex_unlock(&p->mutex); } -struct kfd_process_device *kfd_get_first_process_device_data(struct kfd_process *p) +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p) { return list_first_entry(&p->per_device_data, struct kfd_process_device, per_device_list); } -struct kfd_process_device *kfd_get_next_process_device_data(struct kfd_process *p, +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, struct kfd_process_device *pdd) { if (list_is_last(&pdd->per_device_list, &p->per_device_data)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 32cdf2b483db..03bec765b03d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -32,12 +32,9 @@ static inline struct process_queue_node *get_queue_by_qid( { struct process_queue_node *pqn; - BUG_ON(!pqm); - list_for_each_entry(pqn, &pqm->queues, process_queue_list) { - if (pqn->q && pqn->q->properties.queue_id == qid) - return pqn; - if (pqn->kq && pqn->kq->queue->properties.queue_id == qid) + if ((pqn->q && pqn->q->properties.queue_id == qid) || + (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) return pqn; } @@ -49,17 +46,13 @@ static int find_available_queue_slot(struct process_queue_manager *pqm, { unsigned long found; - BUG_ON(!pqm || !qid); - - pr_debug("kfd: in %s\n", __func__); - found = find_first_zero_bit(pqm->queue_slot_bitmap, KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); - pr_debug("kfd: the new slot id %lu\n", found); + pr_debug("The new slot id %lu\n", found); if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { - pr_info("amdkfd: Can not open more queues for process with pasid %d\n", + pr_info("Cannot open more queues for process with pasid %d\n", pqm->process->pasid); return -ENOMEM; } @@ -72,13 +65,11 @@ static int find_available_queue_slot(struct process_queue_manager *pqm, int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) { - BUG_ON(!pqm); - INIT_LIST_HEAD(&pqm->queues); pqm->queue_slot_bitmap = kzalloc(DIV_ROUND_UP(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, BITS_PER_BYTE), GFP_KERNEL); - if (pqm->queue_slot_bitmap == NULL) + if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; @@ -90,10 +81,6 @@ void pqm_uninit(struct process_queue_manager *pqm) int retval; struct process_queue_node *pqn, *next; - BUG_ON(!pqm); - - pr_debug("In func %s\n", __func__); - list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { retval = pqm_destroy_queue( pqm, @@ -102,7 +89,7 @@ void pqm_uninit(struct process_queue_manager *pqm) pqn->kq->queue->properties.queue_id); if (retval != 0) { - pr_err("kfd: failed to destroy queue\n"); + pr_err("failed to destroy queue\n"); return; } } @@ -117,8 +104,6 @@ static int create_cp_queue(struct process_queue_manager *pqm, { int retval; - retval = 0; - /* Doorbell initialized in user space*/ q_properties->doorbell_ptr = NULL; @@ -131,16 +116,13 @@ static int create_cp_queue(struct process_queue_manager *pqm, retval = init_queue(q, q_properties); if (retval != 0) - goto err_init_queue; + return retval; (*q)->device = dev; (*q)->process = pqm->process; - pr_debug("kfd: PQM After init queue"); - - return retval; + pr_debug("PQM After init queue"); -err_init_queue: return retval; } @@ -161,9 +143,6 @@ int pqm_create_queue(struct process_queue_manager *pqm, int num_queues = 0; struct queue *cur; - BUG_ON(!pqm || !dev || !properties || !qid); - - memset(&q_properties, 0, sizeof(struct queue_properties)); memcpy(&q_properties, properties, sizeof(struct queue_properties)); q = NULL; kq = NULL; @@ -185,7 +164,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, list_for_each_entry(cur, &pdd->qpd.queues_list, list) num_queues++; if (num_queues >= dev->device_info->max_no_of_hqd/2) - return (-ENOSPC); + return -ENOSPC; } retval = find_available_queue_slot(pqm, qid); @@ -197,7 +176,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); } - pqn = kzalloc(sizeof(struct process_queue_node), GFP_KERNEL); + pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); if (!pqn) { retval = -ENOMEM; goto err_allocate_pqn; @@ -210,7 +189,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, if ((sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && ((dev->dqm->processes_count >= VMID_PER_DEVICE) || (dev->dqm->queue_count >= get_queues_num(dev->dqm)))) { - pr_err("kfd: over-subscription is not allowed in radeon_kfd.sched_policy == 1\n"); + pr_err("Over-subscription is not allowed in radeon_kfd.sched_policy == 1\n"); retval = -EPERM; goto err_create_queue; } @@ -227,7 +206,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, break; case KFD_QUEUE_TYPE_DIQ: kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ); - if (kq == NULL) { + if (!kq) { retval = -ENOMEM; goto err_create_queue; } @@ -238,22 +217,22 @@ int pqm_create_queue(struct process_queue_manager *pqm, kq, &pdd->qpd); break; default: - BUG(); - break; + WARN(1, "Invalid queue type %d", type); + retval = -EINVAL; } if (retval != 0) { - pr_debug("Error dqm create queue\n"); + pr_err("DQM create queue failed\n"); goto err_create_queue; } - pr_debug("kfd: PQM After DQM create queue\n"); + pr_debug("PQM After DQM create queue\n"); list_add(&pqn->process_queue_list, &pqm->queues); if (q) { *properties = q->properties; - pr_debug("kfd: PQM done creating queue\n"); + pr_debug("PQM done creating queue\n"); print_queue_properties(properties); } @@ -279,14 +258,11 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) dqm = NULL; - BUG_ON(!pqm); retval = 0; - pr_debug("kfd: In Func %s\n", __func__); - pqn = get_queue_by_qid(pqm, qid); - if (pqn == NULL) { - pr_err("kfd: queue id does not match any known queue\n"); + if (!pqn) { + pr_err("Queue id does not match any known queue\n"); return -EINVAL; } @@ -295,7 +271,8 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) dev = pqn->kq->dev; if (pqn->q) dev = pqn->q->device; - BUG_ON(!dev); + if (WARN_ON(!dev)) + return -ENODEV; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { @@ -335,12 +312,9 @@ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid, int retval; struct process_queue_node *pqn; - BUG_ON(!pqm); - pqn = get_queue_by_qid(pqm, qid); if (!pqn) { - pr_debug("amdkfd: No queue %d exists for update operation\n", - qid); + pr_debug("No queue %d exists for update operation\n", qid); return -EFAULT; } @@ -363,8 +337,6 @@ struct kernel_queue *pqm_get_kernel_queue( { struct process_queue_node *pqn; - BUG_ON(!pqm); - pqn = get_queue_by_qid(pqm, qid); if (pqn && pqn->kq) return pqn->kq; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c index 0ab197077f2d..a5315d4f1c95 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c @@ -65,17 +65,15 @@ void print_queue(struct queue *q) int init_queue(struct queue **q, const struct queue_properties *properties) { - struct queue *tmp; + struct queue *tmp_q; - BUG_ON(!q); - - tmp = kzalloc(sizeof(struct queue), GFP_KERNEL); - if (!tmp) + tmp_q = kzalloc(sizeof(*tmp_q), GFP_KERNEL); + if (!tmp_q) return -ENOMEM; - memcpy(&tmp->properties, properties, sizeof(struct queue_properties)); + memcpy(&tmp_q->properties, properties, sizeof(*properties)); - *q = tmp; + *q = tmp_q; return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 1e5064749959..19ce59028d6b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -108,9 +108,6 @@ static int kfd_topology_get_crat_acpi(void *crat_image, size_t *size) static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, struct crat_subtype_computeunit *cu) { - BUG_ON(!dev); - BUG_ON(!cu); - dev->node_props.cpu_cores_count = cu->num_cpu_cores; dev->node_props.cpu_core_id_base = cu->processor_id_low; if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT) @@ -123,9 +120,6 @@ static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, struct crat_subtype_computeunit *cu) { - BUG_ON(!dev); - BUG_ON(!cu); - dev->node_props.simd_id_base = cu->processor_id_low; dev->node_props.simd_count = cu->num_simd_cores; dev->node_props.lds_size_in_kb = cu->lds_size_in_kb; @@ -148,8 +142,6 @@ static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu) struct kfd_topology_device *dev; int i = 0; - BUG_ON(!cu); - pr_info("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", cu->proximity_domain, cu->hsa_capability); list_for_each_entry(dev, &topology_device_list, list) { @@ -177,8 +169,6 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem) struct kfd_topology_device *dev; int i = 0; - BUG_ON(!mem); - pr_info("Found memory entry in CRAT table with proximity_domain=%d\n", mem->promixity_domain); list_for_each_entry(dev, &topology_device_list, list) { @@ -223,8 +213,6 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) struct kfd_topology_device *dev; uint32_t id; - BUG_ON(!cache); - id = cache->processor_id_low; pr_info("Found cache entry in CRAT table with processor_id=%d\n", id); @@ -274,8 +262,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink) uint32_t id_from; uint32_t id_to; - BUG_ON(!iolink); - id_from = iolink->proximity_domain_from; id_to = iolink->proximity_domain_to; @@ -323,8 +309,6 @@ static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) struct crat_subtype_iolink *iolink; int ret = 0; - BUG_ON(!sub_type_hdr); - switch (sub_type_hdr->type) { case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY: cu = (struct crat_subtype_computeunit *)sub_type_hdr; @@ -368,8 +352,6 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; - BUG_ON(!dev); - list_del(&dev->list); while (dev->mem_props.next != &dev->mem_props) { @@ -416,7 +398,7 @@ static struct kfd_topology_device *kfd_create_topology_device(void) struct kfd_topology_device *dev; dev = kfd_alloc_struct(dev); - if (dev == NULL) { + if (!dev) { pr_err("No memory to allocate a topology device"); return NULL; } @@ -666,7 +648,7 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, dev->node_props.simd_count); if (dev->mem_bank_count < dev->node_props.mem_banks_count) { - pr_info_once("kfd: mem_banks_count truncated from %d to %d\n", + pr_info_once("mem_banks_count truncated from %d to %d\n", dev->node_props.mem_banks_count, dev->mem_bank_count); sysfs_show_32bit_prop(buffer, "mem_banks_count", @@ -763,8 +745,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; - BUG_ON(!dev); - if (dev->kobj_iolink) { list_for_each_entry(iolink, &dev->io_link_props, list) if (iolink->kobj) { @@ -819,12 +799,12 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, int ret; uint32_t i; - BUG_ON(!dev); + if (WARN_ON(dev->kobj_node)) + return -EEXIST; /* * Creating the sysfs folders */ - BUG_ON(dev->kobj_node); dev->kobj_node = kfd_alloc_struct(dev->kobj_node); if (!dev->kobj_node) return -ENOMEM; @@ -957,7 +937,7 @@ static int kfd_topology_update_sysfs(void) int ret; pr_info("Creating topology SYSFS entries\n"); - if (sys_props.kobj_topology == NULL) { + if (!sys_props.kobj_topology) { sys_props.kobj_topology = kfd_alloc_struct(sys_props.kobj_topology); if (!sys_props.kobj_topology) @@ -1117,10 +1097,8 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu) struct kfd_topology_device *dev; struct kfd_topology_device *out_dev = NULL; - BUG_ON(!gpu); - list_for_each_entry(dev, &topology_device_list, list) - if (dev->gpu == NULL && dev->node_props.simd_count > 0) { + if (!dev->gpu && (dev->node_props.simd_count > 0)) { dev->gpu = gpu; out_dev = dev; break; @@ -1143,11 +1121,9 @@ int kfd_topology_add_device(struct kfd_dev *gpu) struct kfd_topology_device *dev; int res; - BUG_ON(!gpu); - gpu_id = kfd_generate_gpu_id(gpu); - pr_debug("kfd: Adding new GPU (ID: 0x%x) to topology\n", gpu_id); + pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id); down_write(&topology_lock); /* @@ -1170,8 +1146,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu) * GPU vBIOS */ - /* - * Update the SYSFS tree, since we added another topology device + /* Update the SYSFS tree, since we added another topology + * device */ if (kfd_topology_update_sysfs() < 0) kfd_topology_release_sysfs(); @@ -1190,7 +1166,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) { dev->node_props.capability |= HSA_CAP_DOORBELL_PACKET_TYPE; - pr_info("amdkfd: adding doorbell packet type capability\n"); + pr_info("Adding doorbell packet type capability\n"); } res = 0; @@ -1210,8 +1186,6 @@ int kfd_topology_remove_device(struct kfd_dev *gpu) uint32_t gpu_id; int res = -ENODEV; - BUG_ON(!gpu); - down_write(&topology_lock); list_for_each_entry(dev, &topology_device_list, list) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 70e8c20acb2f..20457bb5a906 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -25,6 +25,8 @@ #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ +struct seq_file; + /* * Supported ASIC types */ @@ -144,6 +146,12 @@ enum amd_fan_ctrl_mode { AMD_FAN_CTRL_AUTO = 2, }; +enum pp_clock_type { + PP_SCLK, + PP_MCLK, + PP_PCIE, +}; + /* CG flags */ #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) @@ -249,4 +257,62 @@ struct amd_ip_funcs { void (*get_clockgating_state)(void *handle, u32 *flags); }; +enum amd_pp_task; + +struct pp_states_info; + +struct amd_pm_funcs { + int (*get_temperature)(void *handle); + int (*pre_set_power_state)(void *handle); + int (*set_power_state)(void *handle); + void (*post_set_power_state)(void *handle); + void (*display_configuration_changed)(void *handle); + u32 (*get_sclk)(void *handle, bool low); + u32 (*get_mclk)(void *handle, bool low); + void (*print_power_state)(void *handle, void *ps); + void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); + int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); + bool (*vblank_too_short)(void *handle); + void (*powergate_uvd)(void *handle, bool gate); + void (*powergate_vce)(void *handle, bool gate); + void (*enable_bapm)(void *handle, bool enable); + void (*set_fan_control_mode)(void *handle, u32 mode); + u32 (*get_fan_control_mode)(void *handle); + int (*set_fan_speed_percent)(void *handle, u32 speed); + int (*get_fan_speed_percent)(void *handle, u32 *speed); + int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); + int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); + int (*get_sclk_od)(void *handle); + int (*set_sclk_od)(void *handle, uint32_t value); + int (*get_mclk_od)(void *handle); + int (*set_mclk_od)(void *handle, uint32_t value); + int (*check_state_equal)(void *handle, + void *cps, + void *rps, + bool *equal); + int (*read_sensor)(void *handle, int idx, void *value, + int *size); + + struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx); + int (*reset_power_profile_state)(void *handle, + struct amd_pp_profile *request); + int (*get_power_profile_state)(void *handle, + struct amd_pp_profile *query); + int (*set_power_profile_state)(void *handle, + struct amd_pp_profile *request); + int (*switch_power_profile)(void *handle, + enum amd_pp_profile_type type); + int (*load_firmware)(void *handle); + int (*wait_for_fw_loading_complete)(void *handle); + enum amd_dpm_forced_level (*get_performance_level)(void *handle); + enum amd_pm_state_type (*get_current_power_state)(void *handle); + int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, + void *input, void *output); + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); + int (*get_pp_num_states)(void *handle, struct pp_states_info *data); + int (*get_pp_table)(void *handle, char **table); + int (*set_pp_table)(void *handle, const char *buf, size_t size); +}; + + #endif /* __AMD_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h index 34c6ff52710e..6af9f0217b34 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h @@ -5454,5 +5454,7 @@ #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 #define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002 #define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004 +#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en_MASK 0x1 +#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en__SHIFT 0 #endif /* SMU_7_0_1_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 837296db9628..7c92f4707085 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1017,6 +1017,19 @@ struct atom_14nm_combphy_tmds_vs_set uint8_t margin_deemph_lane0__deemph_sel_val; }; +struct atom_i2c_reg_info { + uint8_t ucI2cRegIndex; + uint8_t ucI2cRegVal; +}; + +struct atom_hdmi_retimer_redriver_set { + uint8_t HdmiSlvAddr; + uint8_t HdmiRegNum; + uint8_t Hdmi6GRegNum; + struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use + struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. +}; + struct atom_integrated_system_info_v1_11 { struct atom_common_table_header table_header; @@ -1052,7 +1065,11 @@ struct atom_integrated_system_info_v1_11 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; struct atom_camera_data camera_info; - uint32_t reserved[138]; + struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 + struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 + struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 + struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 + uint32_t reserved[108]; }; diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h index 0214f63f52fc..030b14649c4e 100644 --- a/drivers/gpu/drm/amd/include/cgs_common.h +++ b/drivers/gpu/drm/amd/include/cgs_common.h @@ -100,6 +100,7 @@ enum cgs_system_info_id { CGS_SYSTEM_INFO_GFX_SE_INFO, CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID, CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID, + CGS_SYSTEM_INFO_PCIE_BUS_DEVFN, CGS_SYSTEM_INFO_ID_MAXIMUM, }; @@ -193,8 +194,6 @@ struct cgs_acpi_method_info { * @type: memory type * @size: size in bytes * @align: alignment in bytes - * @min_offset: minimum offset from start of heap - * @max_offset: maximum offset from start of heap * @handle: memory handle (output) * * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous @@ -216,7 +215,6 @@ struct cgs_acpi_method_info { */ typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, uint64_t size, uint64_t align, - uint64_t min_offset, uint64_t max_offset, cgs_handle_t *handle); /** @@ -310,6 +308,22 @@ typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, unsigned index, uint32_t value); +#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT +#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK + +#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ + (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \ + (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field)))) + +#define CGS_REG_GET_FIELD(value, reg, field) \ + (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD(device, reg, field, val) \ + cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ + cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) + /** * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) * @cgs_device: opaque device handle @@ -463,8 +477,8 @@ struct cgs_device #define CGS_OS_CALL(func,dev,...) \ (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) -#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ - CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) +#define cgs_alloc_gpu_mem(dev,type,size,align,handle) \ + CGS_CALL(alloc_gpu_mem,dev,type,size,align,handle) #define cgs_free_gpu_mem(dev,handle) \ CGS_CALL(free_gpu_mem,dev,handle) #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 36f376677a53..f516fd10e6ba 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -41,6 +41,11 @@ struct kgd_dev; struct kgd_mem; +enum kfd_preempt_type { + KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0, + KFD_PREEMPT_TYPE_WAVEFRONT_RESET, +}; + enum kgd_memory_pool { KGD_POOL_SYSTEM_CACHEABLE = 1, KGD_POOL_SYSTEM_WRITECOMBINE = 2, @@ -82,6 +87,17 @@ struct kgd2kfd_shared_resources { size_t doorbell_start_offset; }; +struct tile_config { + uint32_t *tile_config_ptr; + uint32_t *macro_tile_config_ptr; + uint32_t num_tile_configs; + uint32_t num_macro_tile_configs; + + uint32_t gb_addr_config; + uint32_t num_banks; + uint32_t num_ranks; +}; + /** * struct kfd2kgd_calls * @@ -96,6 +112,9 @@ struct kgd2kfd_shared_resources { * * @get_max_engine_clock_in_mhz: Retrieves maximum GPU clock in MHz * + * @alloc_pasid: Allocate a PASID + * @free_pasid: Free a PASID + * * @program_sh_mem_settings: A function that should initiate the memory * properties such as main aperture memory type (cache / non cached) and * secondary aperture base address, size and memory type. @@ -123,6 +142,11 @@ struct kgd2kfd_shared_resources { * * @get_fw_version: Returns FW versions from the header * + * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID. + * Only used for no cp scheduling mode + * + * @get_tile_config: Returns GPU-specific tiling mode information + * * This structure contains function pointers to services that the kgd driver * provides to amdkfd driver. * @@ -139,6 +163,9 @@ struct kfd2kgd_calls { uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd); + int (*alloc_pasid)(unsigned int bits); + void (*free_pasid)(unsigned int pasid); + /* Register access functions */ void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid, uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, @@ -153,14 +180,16 @@ struct kfd2kgd_calls { int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id); int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd); bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); - int (*hqd_destroy)(struct kgd_dev *kgd, uint32_t reset_type, + int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id); @@ -192,6 +221,9 @@ struct kfd2kgd_calls { uint16_t (*get_fw_version)(struct kgd_dev *kgd, enum kgd_engine_type type); + void (*set_scratch_backing_va)(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid); + int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config); }; /** diff --git a/drivers/gpu/drm/amd/include/linux/chash.h b/drivers/gpu/drm/amd/include/linux/chash.h new file mode 100644 index 000000000000..6dc159924ed1 --- /dev/null +++ b/drivers/gpu/drm/amd/include/linux/chash.h @@ -0,0 +1,366 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _LINUX_CHASH_H +#define _LINUX_CHASH_H + +#include <linux/types.h> +#include <linux/hash.h> +#include <linux/bug.h> +#include <asm/bitsperlong.h> + +#if BITS_PER_LONG == 32 +# define _CHASH_LONG_SHIFT 5 +#elif BITS_PER_LONG == 64 +# define _CHASH_LONG_SHIFT 6 +#else +# error "Unexpected BITS_PER_LONG" +#endif + +struct __chash_table { + u8 bits; + u8 key_size; + unsigned int value_size; + u32 size_mask; + unsigned long *occup_bitmap, *valid_bitmap; + union { + u32 *keys32; + u64 *keys64; + }; + u8 *values; + +#ifdef CONFIG_CHASH_STATS + u64 hits, hits_steps, hits_time_ns; + u64 miss, miss_steps, miss_time_ns; + u64 relocs, reloc_dist; +#endif +}; + +#define __CHASH_BITMAP_SIZE(bits) \ + (((1 << (bits)) + BITS_PER_LONG - 1) / BITS_PER_LONG) +#define __CHASH_ARRAY_SIZE(bits, size) \ + ((((size) << (bits)) + sizeof(long) - 1) / sizeof(long)) + +#define __CHASH_DATA_SIZE(bits, key_size, value_size) \ + (__CHASH_BITMAP_SIZE(bits) * 2 + \ + __CHASH_ARRAY_SIZE(bits, key_size) + \ + __CHASH_ARRAY_SIZE(bits, value_size)) + +#define STRUCT_CHASH_TABLE(bits, key_size, value_size) \ + struct { \ + struct __chash_table table; \ + unsigned long data \ + [__CHASH_DATA_SIZE(bits, key_size, value_size)];\ + } + +/** + * struct chash_table - Dynamically allocated closed hash table + * + * Use this struct for dynamically allocated hash tables (using + * chash_table_alloc and chash_table_free), where the size is + * determined at runtime. + */ +struct chash_table { + struct __chash_table table; + unsigned long *data; +}; + +/** + * DECLARE_CHASH_TABLE - macro to declare a closed hash table + * @table: name of the declared hash table + * @bts: Table size will be 2^bits entries + * @key_sz: Size of hash keys in bytes, 4 or 8 + * @val_sz: Size of data values in bytes, can be 0 + * + * This declares the hash table variable with a static size. + * + * The closed hash table stores key-value pairs with low memory and + * lookup overhead. In operation it performs no dynamic memory + * management. The data being stored does not require any + * list_heads. The hash table performs best with small @val_sz and as + * long as some space (about 50%) is left free in the table. But the + * table can still work reasonably efficiently even when filled up to + * about 90%. If bigger data items need to be stored and looked up, + * store the pointer to it as value in the hash table. + * + * @val_sz may be 0. This can be useful when all the stored + * information is contained in the key itself and the fact that it is + * in the hash table (or not). + */ +#define DECLARE_CHASH_TABLE(table, bts, key_sz, val_sz) \ + STRUCT_CHASH_TABLE(bts, key_sz, val_sz) table + +#ifdef CONFIG_CHASH_STATS +#define __CHASH_STATS_INIT(prefix), \ + prefix.hits = 0, \ + prefix.hits_steps = 0, \ + prefix.hits_time_ns = 0, \ + prefix.miss = 0, \ + prefix.miss_steps = 0, \ + prefix.miss_time_ns = 0, \ + prefix.relocs = 0, \ + prefix.reloc_dist = 0 +#else +#define __CHASH_STATS_INIT(prefix) +#endif + +#define __CHASH_TABLE_INIT(prefix, data, bts, key_sz, val_sz) \ + prefix.bits = (bts), \ + prefix.key_size = (key_sz), \ + prefix.value_size = (val_sz), \ + prefix.size_mask = ((1 << bts) - 1), \ + prefix.occup_bitmap = &data[0], \ + prefix.valid_bitmap = &data \ + [__CHASH_BITMAP_SIZE(bts)], \ + prefix.keys64 = (u64 *)&data \ + [__CHASH_BITMAP_SIZE(bts) * 2], \ + prefix.values = (u8 *)&data \ + [__CHASH_BITMAP_SIZE(bts) * 2 + \ + __CHASH_ARRAY_SIZE(bts, key_sz)] \ + __CHASH_STATS_INIT(prefix) + +/** + * DEFINE_CHASH_TABLE - macro to define and initialize a closed hash table + * @tbl: name of the declared hash table + * @bts: Table size will be 2^bits entries + * @key_sz: Size of hash keys in bytes, 4 or 8 + * @val_sz: Size of data values in bytes, can be 0 + * + * Note: the macro can be used for global and local hash table variables. + */ +#define DEFINE_CHASH_TABLE(tbl, bts, key_sz, val_sz) \ + DECLARE_CHASH_TABLE(tbl, bts, key_sz, val_sz) = { \ + .table = { \ + __CHASH_TABLE_INIT(, (tbl).data, bts, key_sz, val_sz) \ + }, \ + .data = {0} \ + } + +/** + * INIT_CHASH_TABLE - Initialize a hash table declared by DECLARE_CHASH_TABLE + * @tbl: name of the declared hash table + * @bts: Table size will be 2^bits entries + * @key_sz: Size of hash keys in bytes, 4 or 8 + * @val_sz: Size of data values in bytes, can be 0 + */ +#define INIT_CHASH_TABLE(tbl, bts, key_sz, val_sz) \ + __CHASH_TABLE_INIT(((tbl).table), (tbl).data, bts, key_sz, val_sz) + +int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size, + unsigned int value_size, gfp_t gfp_mask); +void chash_table_free(struct chash_table *table); + +/** + * chash_table_dump_stats - Dump statistics of a closed hash table + * @tbl: Pointer to the table structure + * + * Dumps some performance statistics of the table gathered in operation + * in the kernel log using pr_debug. If CONFIG_DYNAMIC_DEBUG is enabled, + * user must turn on messages for chash.c (file chash.c +p). + */ +#ifdef CONFIG_CHASH_STATS +#define chash_table_dump_stats(tbl) __chash_table_dump_stats(&(*tbl).table) + +void __chash_table_dump_stats(struct __chash_table *table); +#else +#define chash_table_dump_stats(tbl) +#endif + +/** + * chash_table_reset_stats - Reset statistics of a closed hash table + * @tbl: Pointer to the table structure + */ +#ifdef CONFIG_CHASH_STATS +#define chash_table_reset_stats(tbl) __chash_table_reset_stats(&(*tbl).table) + +static inline void __chash_table_reset_stats(struct __chash_table *table) +{ + (void)table __CHASH_STATS_INIT((*table)); +} +#else +#define chash_table_reset_stats(tbl) +#endif + +/** + * chash_table_copy_in - Copy a new value into the hash table + * @tbl: Pointer to the table structure + * @key: Key of the entry to add or update + * @value: Pointer to value to copy, may be NULL + * + * If @key already has an entry, its value is replaced. Otherwise a + * new entry is added. If @value is NULL, the value is left unchanged + * or uninitialized. Returns 1 if an entry already existed, 0 if a new + * entry was added or %-ENOMEM if there was no free space in the + * table. + */ +#define chash_table_copy_in(tbl, key, value) \ + __chash_table_copy_in(&(*tbl).table, key, value) + +int __chash_table_copy_in(struct __chash_table *table, u64 key, + const void *value); + +/** + * chash_table_copy_out - Copy a value out of the hash table + * @tbl: Pointer to the table structure + * @key: Key of the entry to find + * @value: Pointer to value to copy, may be NULL + * + * If @value is not NULL and the table has a non-0 value_size, the + * value at @key is copied to @value. Returns the slot index of the + * entry or %-EINVAL if @key was not found. + */ +#define chash_table_copy_out(tbl, key, value) \ + __chash_table_copy_out(&(*tbl).table, key, value, false) + +int __chash_table_copy_out(struct __chash_table *table, u64 key, + void *value, bool remove); + +/** + * chash_table_remove - Remove an entry from the hash table + * @tbl: Pointer to the table structure + * @key: Key of the entry to find + * @value: Pointer to value to copy, may be NULL + * + * If @value is not NULL and the table has a non-0 value_size, the + * value at @key is copied to @value. The entry is removed from the + * table. Returns the slot index of the removed entry or %-EINVAL if + * @key was not found. + */ +#define chash_table_remove(tbl, key, value) \ + __chash_table_copy_out(&(*tbl).table, key, value, true) + +/* + * Low level iterator API used internally by the above functions. + */ +struct chash_iter { + struct __chash_table *table; + unsigned long mask; + int slot; +}; + +/** + * CHASH_ITER_INIT - Initialize a hash table iterator + * @tbl: Pointer to hash table to iterate over + * @s: Initial slot number + */ +#define CHASH_ITER_INIT(table, s) { \ + table, \ + 1UL << ((s) & (BITS_PER_LONG - 1)), \ + s \ + } +/** + * CHASH_ITER_SET - Set hash table iterator to new slot + * @iter: Iterator + * @s: Slot number + */ +#define CHASH_ITER_SET(iter, s) \ + (iter).mask = 1UL << ((s) & (BITS_PER_LONG - 1)), \ + (iter).slot = (s) +/** + * CHASH_ITER_INC - Increment hash table iterator + * @table: Hash table to iterate over + * + * Wraps around at the end. + */ +#define CHASH_ITER_INC(iter) do { \ + (iter).mask = (iter).mask << 1 | \ + (iter).mask >> (BITS_PER_LONG - 1); \ + (iter).slot = ((iter).slot + 1) & (iter).table->size_mask; \ + } while (0) + +static inline bool chash_iter_is_valid(const struct chash_iter iter) +{ + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + return !!(iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] & + iter.mask); +} +static inline bool chash_iter_is_empty(const struct chash_iter iter) +{ + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + return !(iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] & + iter.mask); +} + +static inline void chash_iter_set_valid(const struct chash_iter iter) +{ + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask; + iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask; +} +static inline void chash_iter_set_invalid(const struct chash_iter iter) +{ + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask; +} +static inline void chash_iter_set_empty(const struct chash_iter iter) +{ + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask; +} + +static inline u32 chash_iter_key32(const struct chash_iter iter) +{ + BUG_ON(iter.table->key_size != 4); + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + return iter.table->keys32[iter.slot]; +} +static inline u64 chash_iter_key64(const struct chash_iter iter) +{ + BUG_ON(iter.table->key_size != 8); + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + return iter.table->keys64[iter.slot]; +} +static inline u64 chash_iter_key(const struct chash_iter iter) +{ + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + return (iter.table->key_size == 4) ? + iter.table->keys32[iter.slot] : iter.table->keys64[iter.slot]; +} + +static inline u32 chash_iter_hash32(const struct chash_iter iter) +{ + BUG_ON(iter.table->key_size != 4); + return hash_32(chash_iter_key32(iter), iter.table->bits); +} + +static inline u32 chash_iter_hash64(const struct chash_iter iter) +{ + BUG_ON(iter.table->key_size != 8); + return hash_64(chash_iter_key64(iter), iter.table->bits); +} + +static inline u32 chash_iter_hash(const struct chash_iter iter) +{ + return (iter.table->key_size == 4) ? + hash_32(chash_iter_key32(iter), iter.table->bits) : + hash_64(chash_iter_key64(iter), iter.table->bits); +} + +static inline void *chash_iter_value(const struct chash_iter iter) +{ + BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits)); + return iter.table->values + + ((unsigned long)iter.slot * iter.table->value_size); +} + +#endif /* _LINUX_CHASH_H */ diff --git a/drivers/gpu/drm/amd/include/v9_structs.h b/drivers/gpu/drm/amd/include/v9_structs.h index 9a9e6c7e89ea..2fb25abaf7c8 100644 --- a/drivers/gpu/drm/amd/include/v9_structs.h +++ b/drivers/gpu/drm/amd/include/v9_structs.h @@ -284,8 +284,8 @@ struct v9_mqd { uint32_t gds_save_mask_hi; uint32_t ctx_save_base_addr_lo; uint32_t ctx_save_base_addr_hi; - uint32_t reserved_126; - uint32_t reserved_127; + uint32_t dynamic_cu_mask_addr_lo; + uint32_t dynamic_cu_mask_addr_hi; uint32_t cp_mqd_base_addr_lo; uint32_t cp_mqd_base_addr_hi; uint32_t cp_hqd_active; @@ -672,6 +672,14 @@ struct v9_mqd { uint32_t reserved_511; }; +struct v9_mqd_allocation { + struct v9_mqd mqd; + uint32_t wptr_poll_mem; + uint32_t rptr_report_mem; + uint32_t dynamic_cu_mask; + uint32_t dynamic_rb_mask; +}; + /* from vega10 all CSA format is shifted to chain ib compatible mode */ struct v9_ce_ib_state { /* section of non chained ib part */ diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h index ca93b5160ba6..20234820194b 100644 --- a/drivers/gpu/drm/amd/include/vi_structs.h +++ b/drivers/gpu/drm/amd/include/vi_structs.h @@ -419,267 +419,8 @@ struct vi_mqd_allocation { struct vi_mqd mqd; uint32_t wptr_poll_mem; uint32_t rptr_report_mem; - uint32_t dyamic_cu_mask; - uint32_t dyamic_rb_mask; -}; - -struct cz_mqd { - uint32_t header; - uint32_t compute_dispatch_initiator; - uint32_t compute_dim_x; - uint32_t compute_dim_y; - uint32_t compute_dim_z; - uint32_t compute_start_x; - uint32_t compute_start_y; - uint32_t compute_start_z; - uint32_t compute_num_thread_x; - uint32_t compute_num_thread_y; - uint32_t compute_num_thread_z; - uint32_t compute_pipelinestat_enable; - uint32_t compute_perfcount_enable; - uint32_t compute_pgm_lo; - uint32_t compute_pgm_hi; - uint32_t compute_tba_lo; - uint32_t compute_tba_hi; - uint32_t compute_tma_lo; - uint32_t compute_tma_hi; - uint32_t compute_pgm_rsrc1; - uint32_t compute_pgm_rsrc2; - uint32_t compute_vmid; - uint32_t compute_resource_limits; - uint32_t compute_static_thread_mgmt_se0; - uint32_t compute_static_thread_mgmt_se1; - uint32_t compute_tmpring_size; - uint32_t compute_static_thread_mgmt_se2; - uint32_t compute_static_thread_mgmt_se3; - uint32_t compute_restart_x; - uint32_t compute_restart_y; - uint32_t compute_restart_z; - uint32_t compute_thread_trace_enable; - uint32_t compute_misc_reserved; - uint32_t compute_dispatch_id; - uint32_t compute_threadgroup_id; - uint32_t compute_relaunch; - uint32_t compute_wave_restore_addr_lo; - uint32_t compute_wave_restore_addr_hi; - uint32_t compute_wave_restore_control; - uint32_t reserved_39; - uint32_t reserved_40; - uint32_t reserved_41; - uint32_t reserved_42; - uint32_t reserved_43; - uint32_t reserved_44; - uint32_t reserved_45; - uint32_t reserved_46; - uint32_t reserved_47; - uint32_t reserved_48; - uint32_t reserved_49; - uint32_t reserved_50; - uint32_t reserved_51; - uint32_t reserved_52; - uint32_t reserved_53; - uint32_t reserved_54; - uint32_t reserved_55; - uint32_t reserved_56; - uint32_t reserved_57; - uint32_t reserved_58; - uint32_t reserved_59; - uint32_t reserved_60; - uint32_t reserved_61; - uint32_t reserved_62; - uint32_t reserved_63; - uint32_t reserved_64; - uint32_t compute_user_data_0; - uint32_t compute_user_data_1; - uint32_t compute_user_data_2; - uint32_t compute_user_data_3; - uint32_t compute_user_data_4; - uint32_t compute_user_data_5; - uint32_t compute_user_data_6; - uint32_t compute_user_data_7; - uint32_t compute_user_data_8; - uint32_t compute_user_data_9; - uint32_t compute_user_data_10; - uint32_t compute_user_data_11; - uint32_t compute_user_data_12; - uint32_t compute_user_data_13; - uint32_t compute_user_data_14; - uint32_t compute_user_data_15; - uint32_t cp_compute_csinvoc_count_lo; - uint32_t cp_compute_csinvoc_count_hi; - uint32_t reserved_83; - uint32_t reserved_84; - uint32_t reserved_85; - uint32_t cp_mqd_query_time_lo; - uint32_t cp_mqd_query_time_hi; - uint32_t cp_mqd_connect_start_time_lo; - uint32_t cp_mqd_connect_start_time_hi; - uint32_t cp_mqd_connect_end_time_lo; - uint32_t cp_mqd_connect_end_time_hi; - uint32_t cp_mqd_connect_end_wf_count; - uint32_t cp_mqd_connect_end_pq_rptr; - uint32_t cp_mqd_connect_end_pq_wptr; - uint32_t cp_mqd_connect_end_ib_rptr; - uint32_t reserved_96; - uint32_t reserved_97; - uint32_t cp_mqd_save_start_time_lo; - uint32_t cp_mqd_save_start_time_hi; - uint32_t cp_mqd_save_end_time_lo; - uint32_t cp_mqd_save_end_time_hi; - uint32_t cp_mqd_restore_start_time_lo; - uint32_t cp_mqd_restore_start_time_hi; - uint32_t cp_mqd_restore_end_time_lo; - uint32_t cp_mqd_restore_end_time_hi; - uint32_t reserved_106; - uint32_t reserved_107; - uint32_t gds_cs_ctxsw_cnt0; - uint32_t gds_cs_ctxsw_cnt1; - uint32_t gds_cs_ctxsw_cnt2; - uint32_t gds_cs_ctxsw_cnt3; - uint32_t reserved_112; - uint32_t reserved_113; - uint32_t cp_pq_exe_status_lo; - uint32_t cp_pq_exe_status_hi; - uint32_t cp_packet_id_lo; - uint32_t cp_packet_id_hi; - uint32_t cp_packet_exe_status_lo; - uint32_t cp_packet_exe_status_hi; - uint32_t gds_save_base_addr_lo; - uint32_t gds_save_base_addr_hi; - uint32_t gds_save_mask_lo; - uint32_t gds_save_mask_hi; - uint32_t ctx_save_base_addr_lo; - uint32_t ctx_save_base_addr_hi; - uint32_t reserved_126; - uint32_t reserved_127; - uint32_t cp_mqd_base_addr_lo; - uint32_t cp_mqd_base_addr_hi; - uint32_t cp_hqd_active; - uint32_t cp_hqd_vmid; - uint32_t cp_hqd_persistent_state; - uint32_t cp_hqd_pipe_priority; - uint32_t cp_hqd_queue_priority; - uint32_t cp_hqd_quantum; - uint32_t cp_hqd_pq_base_lo; - uint32_t cp_hqd_pq_base_hi; - uint32_t cp_hqd_pq_rptr; - uint32_t cp_hqd_pq_rptr_report_addr_lo; - uint32_t cp_hqd_pq_rptr_report_addr_hi; - uint32_t cp_hqd_pq_wptr_poll_addr_lo; - uint32_t cp_hqd_pq_wptr_poll_addr_hi; - uint32_t cp_hqd_pq_doorbell_control; - uint32_t cp_hqd_pq_wptr; - uint32_t cp_hqd_pq_control; - uint32_t cp_hqd_ib_base_addr_lo; - uint32_t cp_hqd_ib_base_addr_hi; - uint32_t cp_hqd_ib_rptr; - uint32_t cp_hqd_ib_control; - uint32_t cp_hqd_iq_timer; - uint32_t cp_hqd_iq_rptr; - uint32_t cp_hqd_dequeue_request; - uint32_t cp_hqd_dma_offload; - uint32_t cp_hqd_sema_cmd; - uint32_t cp_hqd_msg_type; - uint32_t cp_hqd_atomic0_preop_lo; - uint32_t cp_hqd_atomic0_preop_hi; - uint32_t cp_hqd_atomic1_preop_lo; - uint32_t cp_hqd_atomic1_preop_hi; - uint32_t cp_hqd_hq_status0; - uint32_t cp_hqd_hq_control0; - uint32_t cp_mqd_control; - uint32_t cp_hqd_hq_status1; - uint32_t cp_hqd_hq_control1; - uint32_t cp_hqd_eop_base_addr_lo; - uint32_t cp_hqd_eop_base_addr_hi; - uint32_t cp_hqd_eop_control; - uint32_t cp_hqd_eop_rptr; - uint32_t cp_hqd_eop_wptr; - uint32_t cp_hqd_eop_done_events; - uint32_t cp_hqd_ctx_save_base_addr_lo; - uint32_t cp_hqd_ctx_save_base_addr_hi; - uint32_t cp_hqd_ctx_save_control; - uint32_t cp_hqd_cntl_stack_offset; - uint32_t cp_hqd_cntl_stack_size; - uint32_t cp_hqd_wg_state_offset; - uint32_t cp_hqd_ctx_save_size; - uint32_t cp_hqd_gds_resource_state; - uint32_t cp_hqd_error; - uint32_t cp_hqd_eop_wptr_mem; - uint32_t cp_hqd_eop_dones; - uint32_t reserved_182; - uint32_t reserved_183; - uint32_t reserved_184; - uint32_t reserved_185; - uint32_t reserved_186; - uint32_t reserved_187; - uint32_t reserved_188; - uint32_t reserved_189; - uint32_t reserved_190; - uint32_t reserved_191; - uint32_t iqtimer_pkt_header; - uint32_t iqtimer_pkt_dw0; - uint32_t iqtimer_pkt_dw1; - uint32_t iqtimer_pkt_dw2; - uint32_t iqtimer_pkt_dw3; - uint32_t iqtimer_pkt_dw4; - uint32_t iqtimer_pkt_dw5; - uint32_t iqtimer_pkt_dw6; - uint32_t iqtimer_pkt_dw7; - uint32_t iqtimer_pkt_dw8; - uint32_t iqtimer_pkt_dw9; - uint32_t iqtimer_pkt_dw10; - uint32_t iqtimer_pkt_dw11; - uint32_t iqtimer_pkt_dw12; - uint32_t iqtimer_pkt_dw13; - uint32_t iqtimer_pkt_dw14; - uint32_t iqtimer_pkt_dw15; - uint32_t iqtimer_pkt_dw16; - uint32_t iqtimer_pkt_dw17; - uint32_t iqtimer_pkt_dw18; - uint32_t iqtimer_pkt_dw19; - uint32_t iqtimer_pkt_dw20; - uint32_t iqtimer_pkt_dw21; - uint32_t iqtimer_pkt_dw22; - uint32_t iqtimer_pkt_dw23; - uint32_t iqtimer_pkt_dw24; - uint32_t iqtimer_pkt_dw25; - uint32_t iqtimer_pkt_dw26; - uint32_t iqtimer_pkt_dw27; - uint32_t iqtimer_pkt_dw28; - uint32_t iqtimer_pkt_dw29; - uint32_t iqtimer_pkt_dw30; - uint32_t iqtimer_pkt_dw31; - uint32_t reserved_225; - uint32_t reserved_226; - uint32_t reserved_227; - uint32_t set_resources_header; - uint32_t set_resources_dw1; - uint32_t set_resources_dw2; - uint32_t set_resources_dw3; - uint32_t set_resources_dw4; - uint32_t set_resources_dw5; - uint32_t set_resources_dw6; - uint32_t set_resources_dw7; - uint32_t reserved_236; - uint32_t reserved_237; - uint32_t reserved_238; - uint32_t reserved_239; - uint32_t queue_doorbell_id0; - uint32_t queue_doorbell_id1; - uint32_t queue_doorbell_id2; - uint32_t queue_doorbell_id3; - uint32_t queue_doorbell_id4; - uint32_t queue_doorbell_id5; - uint32_t queue_doorbell_id6; - uint32_t queue_doorbell_id7; - uint32_t queue_doorbell_id8; - uint32_t queue_doorbell_id9; - uint32_t queue_doorbell_id10; - uint32_t queue_doorbell_id11; - uint32_t queue_doorbell_id12; - uint32_t queue_doorbell_id13; - uint32_t queue_doorbell_id14; - uint32_t queue_doorbell_id15; + uint32_t dynamic_cu_mask; + uint32_t dynamic_rb_mask; }; struct vi_ce_ib_state { diff --git a/drivers/gpu/drm/amd/lib/Kconfig b/drivers/gpu/drm/amd/lib/Kconfig new file mode 100644 index 000000000000..03ee7ad21ac3 --- /dev/null +++ b/drivers/gpu/drm/amd/lib/Kconfig @@ -0,0 +1,27 @@ +menu "AMD Library routines" + +# +# Closed hash table +# +config CHASH + tristate "Closed hash table" + help + Statically sized closed hash table implementation with low + memory and CPU overhead. + +config CHASH_STATS + bool "Closed hash table performance statistics" + depends on CHASH + default n + help + Enable collection of performance statistics for closed hash tables. + +config CHASH_SELFTEST + bool "Closed hash table self test" + depends on CHASH + default n + help + Runs a selftest during module load. Several module parameters + are available to modify the behaviour of the test. + +endmenu diff --git a/drivers/gpu/drm/amd/lib/Makefile b/drivers/gpu/drm/amd/lib/Makefile new file mode 100644 index 000000000000..87cd7009e80f --- /dev/null +++ b/drivers/gpu/drm/amd/lib/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for AMD library routines, which are used by AMD driver +# components. +# +# This is for common library routines that can be shared between AMD +# driver components or later moved to kernel/lib for sharing with +# other drivers. + +ccflags-y := -I$(src)/../include + +obj-$(CONFIG_CHASH) += chash.o diff --git a/drivers/gpu/drm/amd/lib/chash.c b/drivers/gpu/drm/amd/lib/chash.c new file mode 100644 index 000000000000..e07e6f3030d6 --- /dev/null +++ b/drivers/gpu/drm/amd/lib/chash.c @@ -0,0 +1,638 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <linux/types.h> +#include <linux/hash.h> +#include <linux/bug.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/sched/clock.h> +#include <asm/div64.h> +#include <linux/chash.h> + +/** + * chash_table_alloc - Allocate closed hash table + * @table: Pointer to the table structure + * @bits: Table size will be 2^bits entries + * @key_size: Size of hash keys in bytes, 4 or 8 + * @value_size: Size of data values in bytes, can be 0 + */ +int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size, + unsigned int value_size, gfp_t gfp_mask) +{ + if (bits > 31) + return -EINVAL; + + if (key_size != 4 && key_size != 8) + return -EINVAL; + + table->data = kcalloc(__CHASH_DATA_SIZE(bits, key_size, value_size), + sizeof(long), gfp_mask); + if (!table->data) + return -ENOMEM; + + __CHASH_TABLE_INIT(table->table, table->data, + bits, key_size, value_size); + + return 0; +} +EXPORT_SYMBOL(chash_table_alloc); + +/** + * chash_table_free - Free closed hash table + * @table: Pointer to the table structure + */ +void chash_table_free(struct chash_table *table) +{ + kfree(table->data); +} +EXPORT_SYMBOL(chash_table_free); + +#ifdef CONFIG_CHASH_STATS + +#define DIV_FRAC(nom, denom, quot, frac, frac_digits) do { \ + u64 __nom = (nom); \ + u64 __denom = (denom); \ + u64 __quot, __frac; \ + u32 __rem; \ + \ + while (__denom >> 32) { \ + __nom >>= 1; \ + __denom >>= 1; \ + } \ + __quot = __nom; \ + __rem = do_div(__quot, __denom); \ + __frac = __rem * (frac_digits) + (__denom >> 1); \ + do_div(__frac, __denom); \ + (quot) = __quot; \ + (frac) = __frac; \ + } while (0) + +void __chash_table_dump_stats(struct __chash_table *table) +{ + struct chash_iter iter = CHASH_ITER_INIT(table, 0); + u32 filled = 0, empty = 0, tombstones = 0; + u64 quot1, quot2; + u32 frac1, frac2; + + do { + if (chash_iter_is_valid(iter)) + filled++; + else if (chash_iter_is_empty(iter)) + empty++; + else + tombstones++; + CHASH_ITER_INC(iter); + } while (iter.slot); + + pr_debug("chash: key size %u, value size %u\n", + table->key_size, table->value_size); + pr_debug(" Slots total/filled/empty/tombstones: %u / %u / %u / %u\n", + 1 << table->bits, filled, empty, tombstones); + if (table->hits > 0) { + DIV_FRAC(table->hits_steps, table->hits, quot1, frac1, 1000); + DIV_FRAC(table->hits * 1000, table->hits_time_ns, + quot2, frac2, 1000); + } else { + quot1 = quot2 = 0; + frac1 = frac2 = 0; + } + pr_debug(" Hits (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n", + table->hits, quot1, frac1, quot2, frac2); + if (table->miss > 0) { + DIV_FRAC(table->miss_steps, table->miss, quot1, frac1, 1000); + DIV_FRAC(table->miss * 1000, table->miss_time_ns, + quot2, frac2, 1000); + } else { + quot1 = quot2 = 0; + frac1 = frac2 = 0; + } + pr_debug(" Misses (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n", + table->miss, quot1, frac1, quot2, frac2); + if (table->hits + table->miss > 0) { + DIV_FRAC(table->hits_steps + table->miss_steps, + table->hits + table->miss, quot1, frac1, 1000); + DIV_FRAC((table->hits + table->miss) * 1000, + (table->hits_time_ns + table->miss_time_ns), + quot2, frac2, 1000); + } else { + quot1 = quot2 = 0; + frac1 = frac2 = 0; + } + pr_debug(" Total (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n", + table->hits + table->miss, quot1, frac1, quot2, frac2); + if (table->relocs > 0) { + DIV_FRAC(table->hits + table->miss, table->relocs, + quot1, frac1, 1000); + DIV_FRAC(table->reloc_dist, table->relocs, quot2, frac2, 1000); + pr_debug(" Relocations (freq, avg.dist): %llu (1:%llu.%03u, %llu.%03u)\n", + table->relocs, quot1, frac1, quot2, frac2); + } else { + pr_debug(" No relocations\n"); + } +} +EXPORT_SYMBOL(__chash_table_dump_stats); + +#undef DIV_FRAC +#endif + +#define CHASH_INC(table, a) ((a) = ((a) + 1) & (table)->size_mask) +#define CHASH_ADD(table, a, b) (((a) + (b)) & (table)->size_mask) +#define CHASH_SUB(table, a, b) (((a) - (b)) & (table)->size_mask) +#define CHASH_IN_RANGE(table, slot, first, last) \ + (CHASH_SUB(table, slot, first) <= CHASH_SUB(table, last, first)) + +/*#define CHASH_DEBUG Uncomment this to enable verbose debug output*/ +#ifdef CHASH_DEBUG +static void chash_table_dump(struct __chash_table *table) +{ + struct chash_iter iter = CHASH_ITER_INIT(table, 0); + + do { + if ((iter.slot & 3) == 0) + pr_debug("%04x: ", iter.slot); + + if (chash_iter_is_valid(iter)) + pr_debug("[%016llx] ", chash_iter_key(iter)); + else if (chash_iter_is_empty(iter)) + pr_debug("[ <empty> ] "); + else + pr_debug("[ <tombstone> ] "); + + if ((iter.slot & 3) == 3) + pr_debug("\n"); + + CHASH_ITER_INC(iter); + } while (iter.slot); + + if ((iter.slot & 3) != 0) + pr_debug("\n"); +} + +static int chash_table_check(struct __chash_table *table) +{ + u32 hash; + struct chash_iter iter = CHASH_ITER_INIT(table, 0); + struct chash_iter cur = CHASH_ITER_INIT(table, 0); + + do { + if (!chash_iter_is_valid(iter)) { + CHASH_ITER_INC(iter); + continue; + } + + hash = chash_iter_hash(iter); + CHASH_ITER_SET(cur, hash); + while (cur.slot != iter.slot) { + if (chash_iter_is_empty(cur)) { + pr_err("Path to element at %x with hash %x broken at slot %x\n", + iter.slot, hash, cur.slot); + chash_table_dump(table); + return -EINVAL; + } + CHASH_ITER_INC(cur); + } + + CHASH_ITER_INC(iter); + } while (iter.slot); + + return 0; +} +#endif + +static void chash_iter_relocate(struct chash_iter dst, struct chash_iter src) +{ + BUG_ON(src.table == dst.table && src.slot == dst.slot); + BUG_ON(src.table->key_size != src.table->key_size); + BUG_ON(src.table->value_size != src.table->value_size); + + if (dst.table->key_size == 4) + dst.table->keys32[dst.slot] = src.table->keys32[src.slot]; + else + dst.table->keys64[dst.slot] = src.table->keys64[src.slot]; + + if (dst.table->value_size) + memcpy(chash_iter_value(dst), chash_iter_value(src), + dst.table->value_size); + + chash_iter_set_valid(dst); + chash_iter_set_invalid(src); + +#ifdef CONFIG_CHASH_STATS + if (src.table == dst.table) { + dst.table->relocs++; + dst.table->reloc_dist += + CHASH_SUB(dst.table, src.slot, dst.slot); + } +#endif +} + +/** + * __chash_table_find - Helper for looking up a hash table entry + * @iter: Pointer to hash table iterator + * @key: Key of the entry to find + * @for_removal: set to true if the element will be removed soon + * + * Searches for an entry in the hash table with a given key. iter must + * be initialized by the caller to point to the home position of the + * hypothetical entry, i.e. it must be initialized with the hash table + * and the key's hash as the initial slot for the search. + * + * This function also does some local clean-up to speed up future + * look-ups by relocating entries to better slots and removing + * tombstones that are no longer needed. + * + * If @for_removal is true, the function avoids relocating the entry + * that is being returned. + * + * Returns 0 if the search is successful. In this case iter is updated + * to point to the found entry. Otherwise %-EINVAL is returned and the + * iter is updated to point to the first available slot for the given + * key. If the table is full, the slot is set to -1. + */ +static int chash_table_find(struct chash_iter *iter, u64 key, + bool for_removal) +{ +#ifdef CONFIG_CHASH_STATS + u64 ts1 = local_clock(); +#endif + u32 hash = iter->slot; + struct chash_iter first_redundant = CHASH_ITER_INIT(iter->table, -1); + int first_avail = (for_removal ? -2 : -1); + + while (!chash_iter_is_valid(*iter) || chash_iter_key(*iter) != key) { + if (chash_iter_is_empty(*iter)) { + /* Found an empty slot, which ends the + * search. Clean up any preceding tombstones + * that are no longer needed because they lead + * to no-where + */ + if ((int)first_redundant.slot < 0) + goto not_found; + while (first_redundant.slot != iter->slot) { + if (!chash_iter_is_valid(first_redundant)) + chash_iter_set_empty(first_redundant); + CHASH_ITER_INC(first_redundant); + } +#ifdef CHASH_DEBUG + chash_table_check(iter->table); +#endif + goto not_found; + } else if (!chash_iter_is_valid(*iter)) { + /* Found a tombstone. Remember it as candidate + * for relocating the entry we're looking for + * or for adding a new entry with the given key + */ + if (first_avail == -1) + first_avail = iter->slot; + /* Or mark it as the start of a series of + * potentially redundant tombstones + */ + else if (first_redundant.slot == -1) + CHASH_ITER_SET(first_redundant, iter->slot); + } else if (first_redundant.slot >= 0) { + /* Found a valid, occupied slot with a + * preceding series of tombstones. Relocate it + * to a better position that no longer depends + * on those tombstones + */ + u32 cur_hash = chash_iter_hash(*iter); + + if (!CHASH_IN_RANGE(iter->table, cur_hash, + first_redundant.slot + 1, + iter->slot)) { + /* This entry has a hash at or before + * the first tombstone we found. We + * can relocate it to that tombstone + * and advance to the next tombstone + */ + chash_iter_relocate(first_redundant, *iter); + do { + CHASH_ITER_INC(first_redundant); + } while (chash_iter_is_valid(first_redundant)); + } else if (cur_hash != iter->slot) { + /* Relocate entry to its home position + * or as close as possible so it no + * longer depends on any preceding + * tombstones + */ + struct chash_iter new_iter = + CHASH_ITER_INIT(iter->table, cur_hash); + + while (new_iter.slot != iter->slot && + chash_iter_is_valid(new_iter)) + CHASH_ITER_INC(new_iter); + + if (new_iter.slot != iter->slot) + chash_iter_relocate(new_iter, *iter); + } + } + + CHASH_ITER_INC(*iter); + if (iter->slot == hash) { + iter->slot = -1; + goto not_found; + } + } + +#ifdef CONFIG_CHASH_STATS + iter->table->hits++; + iter->table->hits_steps += CHASH_SUB(iter->table, iter->slot, hash) + 1; +#endif + + if (first_avail >= 0) { + CHASH_ITER_SET(first_redundant, first_avail); + chash_iter_relocate(first_redundant, *iter); + iter->slot = first_redundant.slot; + iter->mask = first_redundant.mask; + } + +#ifdef CONFIG_CHASH_STATS + iter->table->hits_time_ns += local_clock() - ts1; +#endif + + return 0; + +not_found: +#ifdef CONFIG_CHASH_STATS + iter->table->miss++; + iter->table->miss_steps += (iter->slot < 0) ? + (1 << iter->table->bits) : + CHASH_SUB(iter->table, iter->slot, hash) + 1; +#endif + + if (first_avail >= 0) + CHASH_ITER_SET(*iter, first_avail); + +#ifdef CONFIG_CHASH_STATS + iter->table->miss_time_ns += local_clock() - ts1; +#endif + + return -EINVAL; +} + +int __chash_table_copy_in(struct __chash_table *table, u64 key, + const void *value) +{ + u32 hash = (table->key_size == 4) ? + hash_32(key, table->bits) : hash_64(key, table->bits); + struct chash_iter iter = CHASH_ITER_INIT(table, hash); + int r = chash_table_find(&iter, key, false); + + /* Found an existing entry */ + if (!r) { + if (value && table->value_size) + memcpy(chash_iter_value(iter), value, + table->value_size); + return 1; + } + + /* Is there a place to add a new entry? */ + if (iter.slot < 0) { + pr_err("Hash table overflow\n"); + return -ENOMEM; + } + + chash_iter_set_valid(iter); + + if (table->key_size == 4) + table->keys32[iter.slot] = key; + else + table->keys64[iter.slot] = key; + if (value && table->value_size) + memcpy(chash_iter_value(iter), value, table->value_size); + + return 0; +} +EXPORT_SYMBOL(__chash_table_copy_in); + +int __chash_table_copy_out(struct __chash_table *table, u64 key, + void *value, bool remove) +{ + u32 hash = (table->key_size == 4) ? + hash_32(key, table->bits) : hash_64(key, table->bits); + struct chash_iter iter = CHASH_ITER_INIT(table, hash); + int r = chash_table_find(&iter, key, remove); + + if (r < 0) + return r; + + if (value && table->value_size) + memcpy(value, chash_iter_value(iter), table->value_size); + + if (remove) + chash_iter_set_invalid(iter); + + return iter.slot; +} +EXPORT_SYMBOL(__chash_table_copy_out); + +#ifdef CONFIG_CHASH_SELFTEST +/** + * chash_self_test - Run a self-test of the hash table implementation + * @bits: Table size will be 2^bits entries + * @key_size: Size of hash keys in bytes, 4 or 8 + * @min_fill: Minimum fill level during the test + * @max_fill: Maximum fill level during the test + * @iterations: Number of test iterations + * + * The test adds and removes entries from a hash table, cycling the + * fill level between min_fill and max_fill entries. Also tests lookup + * and value retrieval. + */ +static int __init chash_self_test(u8 bits, u8 key_size, + int min_fill, int max_fill, + u64 iterations) +{ + struct chash_table table; + int ret; + u64 add_count, rmv_count; + u64 value; + + if (key_size == 4 && iterations > 0xffffffff) + return -EINVAL; + if (min_fill >= max_fill) + return -EINVAL; + + ret = chash_table_alloc(&table, bits, key_size, sizeof(u64), + GFP_KERNEL); + if (ret) { + pr_err("chash_table_alloc failed: %d\n", ret); + return ret; + } + + for (add_count = 0, rmv_count = 0; add_count < iterations; + add_count++) { + /* When we hit the max_fill level, remove entries down + * to min_fill + */ + if (add_count - rmv_count == max_fill) { + u64 find_count = rmv_count; + + /* First try to find all entries that we're + * about to remove, confirm their value, test + * writing them back a second time. + */ + for (; add_count - find_count > min_fill; + find_count++) { + ret = chash_table_copy_out(&table, find_count, + &value); + if (ret < 0) { + pr_err("chash_table_copy_out failed: %d\n", + ret); + goto out; + } + if (value != ~find_count) { + pr_err("Wrong value retrieved for key 0x%llx, expected 0x%llx got 0x%llx\n", + find_count, ~find_count, value); +#ifdef CHASH_DEBUG + chash_table_dump(&table.table); +#endif + ret = -EFAULT; + goto out; + } + ret = chash_table_copy_in(&table, find_count, + &value); + if (ret != 1) { + pr_err("copy_in second time returned %d, expected 1\n", + ret); + ret = -EFAULT; + goto out; + } + } + /* Remove them until we hit min_fill level */ + for (; add_count - rmv_count > min_fill; rmv_count++) { + ret = chash_table_remove(&table, rmv_count, + NULL); + if (ret < 0) { + pr_err("chash_table_remove failed: %d\n", + ret); + goto out; + } + } + } + + /* Add a new value */ + value = ~add_count; + ret = chash_table_copy_in(&table, add_count, &value); + if (ret != 0) { + pr_err("copy_in first time returned %d, expected 0\n", + ret); + ret = -EFAULT; + goto out; + } + } + + chash_table_dump_stats(&table); + chash_table_reset_stats(&table); + +out: + chash_table_free(&table); + return ret; +} + +static unsigned int chash_test_bits = 10; +MODULE_PARM_DESC(test_bits, + "Selftest number of hash bits ([4..20], default=10)"); +module_param_named(test_bits, chash_test_bits, uint, 0444); + +static unsigned int chash_test_keysize = 8; +MODULE_PARM_DESC(test_keysize, "Selftest keysize (4 or 8, default=8)"); +module_param_named(test_keysize, chash_test_keysize, uint, 0444); + +static unsigned int chash_test_minfill; +MODULE_PARM_DESC(test_minfill, "Selftest minimum #entries (default=50%)"); +module_param_named(test_minfill, chash_test_minfill, uint, 0444); + +static unsigned int chash_test_maxfill; +MODULE_PARM_DESC(test_maxfill, "Selftest maximum #entries (default=80%)"); +module_param_named(test_maxfill, chash_test_maxfill, uint, 0444); + +static unsigned long chash_test_iters; +MODULE_PARM_DESC(test_iters, "Selftest iterations (default=1000 x #entries)"); +module_param_named(test_iters, chash_test_iters, ulong, 0444); + +static int __init chash_init(void) +{ + int ret; + u64 ts1_ns; + + /* Skip self test on user errors */ + if (chash_test_bits < 4 || chash_test_bits > 20) { + pr_err("chash: test_bits out of range [4..20].\n"); + return 0; + } + if (chash_test_keysize != 4 && chash_test_keysize != 8) { + pr_err("chash: test_keysize invalid. Must be 4 or 8.\n"); + return 0; + } + + if (!chash_test_minfill) + chash_test_minfill = (1 << chash_test_bits) / 2; + if (!chash_test_maxfill) + chash_test_maxfill = (1 << chash_test_bits) * 4 / 5; + if (!chash_test_iters) + chash_test_iters = (1 << chash_test_bits) * 1000; + + if (chash_test_minfill >= (1 << chash_test_bits)) { + pr_err("chash: test_minfill too big. Must be < table size.\n"); + return 0; + } + if (chash_test_maxfill >= (1 << chash_test_bits)) { + pr_err("chash: test_maxfill too big. Must be < table size.\n"); + return 0; + } + if (chash_test_minfill >= chash_test_maxfill) { + pr_err("chash: test_minfill must be < test_maxfill.\n"); + return 0; + } + if (chash_test_keysize == 4 && chash_test_iters > 0xffffffff) { + pr_err("chash: test_iters must be < 4G for 4 byte keys.\n"); + return 0; + } + + ts1_ns = local_clock(); + ret = chash_self_test(chash_test_bits, chash_test_keysize, + chash_test_minfill, chash_test_maxfill, + chash_test_iters); + if (!ret) { + u64 ts_delta_us = local_clock() - ts1_ns; + u64 iters_per_second = (u64)chash_test_iters * 1000000; + + do_div(ts_delta_us, 1000); + do_div(iters_per_second, ts_delta_us); + pr_info("chash: self test took %llu us, %llu iterations/s\n", + ts_delta_us, iters_per_second); + } else { + pr_err("chash: self test failed: %d\n", ret); + } + + return ret; +} + +module_init(chash_init); + +#endif /* CONFIG_CHASH_SELFTEST */ + +MODULE_DESCRIPTION("Closed hash table"); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile index 4e132b936e3d..68b417ac94dd 100644 --- a/drivers/gpu/drm/amd/powerplay/Makefile +++ b/drivers/gpu/drm/amd/powerplay/Makefile @@ -4,12 +4,11 @@ subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ -I$(FULL_AMD_PATH)/powerplay/smumgr\ - -I$(FULL_AMD_PATH)/powerplay/hwmgr \ - -I$(FULL_AMD_PATH)/powerplay/eventmgr + -I$(FULL_AMD_PATH)/powerplay/hwmgr AMD_PP_PATH = ../powerplay -PP_LIBS = smumgr hwmgr eventmgr +PP_LIBS = smumgr hwmgr AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(PP_LIBS))) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index f73e80c4bf33..9f3f3b8cf64f 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -29,22 +29,19 @@ #include "amd_powerplay.h" #include "pp_instance.h" #include "power_state.h" -#include "eventmanager.h" - static inline int pp_check(struct pp_instance *handle) { if (handle == NULL || handle->pp_valid != PP_VALID) return -EINVAL; - if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL) + if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL) return -EINVAL; if (handle->pm_en == 0) return PP_DPM_DISABLED; - if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL - || handle->eventmgr == NULL) + if (handle->hwmgr->hwmgr_func == NULL) return PP_DPM_DISABLED; return 0; @@ -55,46 +52,32 @@ static int pp_early_init(void *handle) int ret; struct pp_instance *pp_handle = (struct pp_instance *)handle; - ret = smum_early_init(pp_handle); + ret = hwmgr_early_init(pp_handle); if (ret) - return ret; + return -EINVAL; if ((pp_handle->pm_en == 0) || cgs_is_virtualization_enabled(pp_handle->device)) return PP_DPM_DISABLED; - ret = hwmgr_early_init(pp_handle); - if (ret) { - pp_handle->pm_en = 0; - return PP_DPM_DISABLED; - } - - ret = eventmgr_early_init(pp_handle); - if (ret) { - kfree(pp_handle->hwmgr); - pp_handle->hwmgr = NULL; - pp_handle->pm_en = 0; - return PP_DPM_DISABLED; - } - return 0; } static int pp_sw_init(void *handle) { - struct pp_smumgr *smumgr; + struct pp_hwmgr *hwmgr; int ret = 0; struct pp_instance *pp_handle = (struct pp_instance *)handle; ret = pp_check(pp_handle); if (ret == 0 || ret == PP_DPM_DISABLED) { - smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->smu_init == NULL) + if (hwmgr->smumgr_funcs->smu_init == NULL) return -EINVAL; - ret = smumgr->smumgr_funcs->smu_init(smumgr); + ret = hwmgr->smumgr_funcs->smu_init(hwmgr); pr_info("amdgpu: powerplay sw initialized\n"); } @@ -103,40 +86,39 @@ static int pp_sw_init(void *handle) static int pp_sw_fini(void *handle) { - struct pp_smumgr *smumgr; + struct pp_hwmgr *hwmgr; int ret = 0; struct pp_instance *pp_handle = (struct pp_instance *)handle; ret = pp_check(pp_handle); if (ret == 0 || ret == PP_DPM_DISABLED) { - smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->smu_fini == NULL) + if (hwmgr->smumgr_funcs->smu_fini == NULL) return -EINVAL; - ret = smumgr->smumgr_funcs->smu_fini(smumgr); + ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); } return ret; } static int pp_hw_init(void *handle) { - struct pp_smumgr *smumgr; - struct pp_eventmgr *eventmgr; int ret = 0; struct pp_instance *pp_handle = (struct pp_instance *)handle; + struct pp_hwmgr *hwmgr; ret = pp_check(pp_handle); if (ret == 0 || ret == PP_DPM_DISABLED) { - smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->start_smu == NULL) + if (hwmgr->smumgr_funcs->start_smu == NULL) return -EINVAL; - if(smumgr->smumgr_funcs->start_smu(smumgr)) { + if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) { pr_err("smc start failed\n"); - smumgr->smumgr_funcs->smu_fini(smumgr); + hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); return -EINVAL;; } if (ret == PP_DPM_DISABLED) @@ -146,38 +128,21 @@ static int pp_hw_init(void *handle) ret = hwmgr_hw_init(pp_handle); if (ret) goto err; - - eventmgr = pp_handle->eventmgr; - if (eventmgr->pp_eventmgr_init == NULL || - eventmgr->pp_eventmgr_init(eventmgr)) - goto err; - return 0; err: pp_handle->pm_en = 0; - kfree(pp_handle->eventmgr); - kfree(pp_handle->hwmgr); - pp_handle->hwmgr = NULL; - pp_handle->eventmgr = NULL; return PP_DPM_DISABLED; } static int pp_hw_fini(void *handle) { - struct pp_eventmgr *eventmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; ret = pp_check(pp_handle); - - if (ret == 0) { - eventmgr = pp_handle->eventmgr; - - if (eventmgr->pp_eventmgr_fini != NULL) - eventmgr->pp_eventmgr_fini(eventmgr); - + if (ret == 0) hwmgr_hw_fini(pp_handle); - } + return 0; } @@ -244,8 +209,6 @@ static int pp_set_powergating_state(void *handle, static int pp_suspend(void *handle) { - struct pp_eventmgr *eventmgr; - struct pem_event_data event_data = { {0} }; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; @@ -256,17 +219,12 @@ static int pp_suspend(void *handle) else if (ret != 0) return ret; - eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); - - return 0; + return hwmgr_hw_suspend(pp_handle); } static int pp_resume(void *handle) { - struct pp_eventmgr *eventmgr; - struct pem_event_data event_data = { {0} }; - struct pp_smumgr *smumgr; + struct pp_hwmgr *hwmgr; int ret, ret1; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -275,26 +233,22 @@ static int pp_resume(void *handle) if (ret1 != 0 && ret1 != PP_DPM_DISABLED) return ret1; - smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; - if (smumgr->smumgr_funcs->start_smu == NULL) + if (hwmgr->smumgr_funcs->start_smu == NULL) return -EINVAL; - ret = smumgr->smumgr_funcs->start_smu(smumgr); + ret = hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr); if (ret) { pr_err("smc start failed\n"); - smumgr->smumgr_funcs->smu_fini(smumgr); + hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); return ret; } if (ret1 == PP_DPM_DISABLED) return 0; - eventmgr = pp_handle->eventmgr; - - pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); - - return 0; + return hwmgr_hw_resume(pp_handle); } const struct amd_ip_funcs pp_ip_funcs = { @@ -324,6 +278,42 @@ static int pp_dpm_fw_loading_complete(void *handle) return 0; } +static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, + enum amd_dpm_forced_level *level) +{ + uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | + AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; + + if (!(hwmgr->dpm_level & profile_mode_mask)) { + /* enter umd pstate, save current level, disable gfx cg*/ + if (*level & profile_mode_mask) { + hwmgr->saved_dpm_level = hwmgr->dpm_level; + hwmgr->en_umd_pstate = true; + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_CG_STATE_UNGATE); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_PG_STATE_UNGATE); + } + } else { + /* exit umd pstate, restore level, enable gfx cg*/ + if (!(*level & profile_mode_mask)) { + if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) + *level = hwmgr->saved_dpm_level; + hwmgr->en_umd_pstate = false; + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_CG_STATE_GATE); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_PG_STATE_GATE); + } + } +} + static int pp_dpm_force_performance_level(void *handle, enum amd_dpm_forced_level level) { @@ -338,13 +328,22 @@ static int pp_dpm_force_performance_level(void *handle, hwmgr = pp_handle->hwmgr; + if (level == hwmgr->dpm_level) + return 0; + if (hwmgr->hwmgr_func->force_dpm_level == NULL) { pr_info("%s was not implemented.\n", __func__); return 0; } mutex_lock(&pp_handle->pp_lock); - hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); + pp_dpm_en_umd_pstate(hwmgr, &level); + hwmgr->request_dpm_level = level; + hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); + ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); + if (!ret) + hwmgr->dpm_level = hwmgr->request_dpm_level; + mutex_unlock(&pp_handle->pp_lock); return 0; } @@ -369,11 +368,12 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( return level; } -static int pp_dpm_get_sclk(void *handle, bool low) +static uint32_t pp_dpm_get_sclk(void *handle, bool low) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; + uint32_t clk = 0; ret = pp_check(pp_handle); @@ -387,16 +387,17 @@ static int pp_dpm_get_sclk(void *handle, bool low) return 0; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->get_sclk(hwmgr, low); + clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low); mutex_unlock(&pp_handle->pp_lock); - return ret; + return clk; } -static int pp_dpm_get_mclk(void *handle, bool low) +static uint32_t pp_dpm_get_mclk(void *handle, bool low) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; + uint32_t clk = 0; ret = pp_check(pp_handle); @@ -410,12 +411,12 @@ static int pp_dpm_get_mclk(void *handle, bool low) return 0; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->get_mclk(hwmgr, low); + clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low); mutex_unlock(&pp_handle->pp_lock); - return ret; + return clk; } -static int pp_dpm_powergate_vce(void *handle, bool gate) +static void pp_dpm_powergate_vce(void *handle, bool gate) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -424,21 +425,20 @@ static int pp_dpm_powergate_vce(void *handle, bool gate) ret = pp_check(pp_handle); if (ret != 0) - return ret; + return; hwmgr = pp_handle->hwmgr; if (hwmgr->hwmgr_func->powergate_vce == NULL) { pr_info("%s was not implemented.\n", __func__); - return 0; + return; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); + hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); mutex_unlock(&pp_handle->pp_lock); - return ret; } -static int pp_dpm_powergate_uvd(void *handle, bool gate) +static void pp_dpm_powergate_uvd(void *handle, bool gate) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -447,74 +447,34 @@ static int pp_dpm_powergate_uvd(void *handle, bool gate) ret = pp_check(pp_handle); if (ret != 0) - return ret; + return; hwmgr = pp_handle->hwmgr; if (hwmgr->hwmgr_func->powergate_uvd == NULL) { pr_info("%s was not implemented.\n", __func__); - return 0; + return; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); + hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); mutex_unlock(&pp_handle->pp_lock); - return ret; } -static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) -{ - switch (state) { - case POWER_STATE_TYPE_BATTERY: - return PP_StateUILabel_Battery; - case POWER_STATE_TYPE_BALANCED: - return PP_StateUILabel_Balanced; - case POWER_STATE_TYPE_PERFORMANCE: - return PP_StateUILabel_Performance; - default: - return PP_StateUILabel_None; - } -} - -static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, +static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, void *input, void *output) { int ret = 0; - struct pem_event_data data = { {0} }; struct pp_instance *pp_handle = (struct pp_instance *)handle; ret = pp_check(pp_handle); if (ret != 0) return ret; - mutex_lock(&pp_handle->pp_lock); - switch (event_id) { - case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - case AMD_PP_EVENT_ENABLE_USER_STATE: - { - enum amd_pm_state_type ps; - - if (input == NULL) { - ret = -EINVAL; - break; - } - ps = *(unsigned long *)input; - data.requested_ui_label = power_state_convert(ps); - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - } - case AMD_PP_EVENT_COMPLETE_INIT: - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - case AMD_PP_EVENT_READJUST_POWER_STATE: - ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); - break; - default: - break; - } + mutex_lock(&pp_handle->pp_lock); + ret = hwmgr_handle_task(pp_handle, task_id, input, output); mutex_unlock(&pp_handle->pp_lock); + return ret; } @@ -562,7 +522,7 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) return pm_type; } -static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) +static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -571,25 +531,25 @@ static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) ret = pp_check(pp_handle); if (ret != 0) - return ret; + return; hwmgr = pp_handle->hwmgr; if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { pr_info("%s was not implemented.\n", __func__); - return 0; + return; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); + hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); mutex_unlock(&pp_handle->pp_lock); - return ret; } -static int pp_dpm_get_fan_control_mode(void *handle) +static uint32_t pp_dpm_get_fan_control_mode(void *handle) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; int ret = 0; + uint32_t mode = 0; ret = pp_check(pp_handle); @@ -603,9 +563,9 @@ static int pp_dpm_get_fan_control_mode(void *handle) return 0; } mutex_lock(&pp_handle->pp_lock); - ret = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); + mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); mutex_unlock(&pp_handle->pp_lock); - return ret; + return mode; } static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent) @@ -1128,7 +1088,7 @@ static int pp_dpm_switch_power_profile(void *handle, return 0; } -const struct amd_powerplay_funcs pp_dpm_funcs = { +const struct amd_pm_funcs pp_dpm_funcs = { .get_temperature = pp_dpm_get_temperature, .load_firmware = pp_dpm_load_fw, .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, @@ -1189,15 +1149,9 @@ int amd_powerplay_destroy(void *handle) { struct pp_instance *instance = (struct pp_instance *)handle; - if (instance->pm_en) { - kfree(instance->eventmgr); - kfree(instance->hwmgr); - instance->hwmgr = NULL; - instance->eventmgr = NULL; - } + kfree(instance->hwmgr); + instance->hwmgr = NULL; - kfree(instance->smu_mgr); - instance->smu_mgr = NULL; kfree(instance); instance = NULL; return 0; @@ -1206,18 +1160,16 @@ int amd_powerplay_destroy(void *handle) int amd_powerplay_reset(void *handle) { struct pp_instance *instance = (struct pp_instance *)handle; - struct pp_eventmgr *eventmgr; - struct pem_event_data event_data = { {0} }; int ret; - if (cgs_is_virtualization_enabled(instance->smu_mgr->device)) + if (cgs_is_virtualization_enabled(instance->hwmgr->device)) return PP_DPM_DISABLED; ret = pp_check(instance); if (ret != 0) return ret; - ret = pp_hw_fini(handle); + ret = pp_hw_fini(instance); if (ret) return ret; @@ -1225,16 +1177,7 @@ int amd_powerplay_reset(void *handle) if (ret) return PP_DPM_DISABLED; - eventmgr = instance->eventmgr; - - if (eventmgr->pp_eventmgr_init == NULL) - return PP_DPM_DISABLED; - - ret = eventmgr->pp_eventmgr_init(eventmgr); - if (ret) - return ret; - - return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data); + return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); } /* export this function to DAL */ diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile b/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile deleted file mode 100644 index 7509e3850087..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the 'event manager' sub-component of powerplay. -# It provides the event management services for the driver. - -EVENT_MGR = eventmgr.o eventinit.o eventmanagement.o \ - eventactionchains.o eventsubchains.o eventtasks.o psm.o - -AMD_PP_EVENT = $(addprefix $(AMD_PP_PATH)/eventmgr/,$(EVENT_MGR)) - -AMD_POWERPLAY_FILES += $(AMD_PP_EVENT) - diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c deleted file mode 100644 index 8cee4e0f9fde..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "eventmgr.h" -#include "eventactionchains.h" -#include "eventsubchains.h" - -static const pem_event_action * const initialize_event[] = { - block_adjust_power_state_tasks, - power_budget_tasks, - system_config_tasks, - setup_asic_tasks, - enable_dynamic_state_management_tasks, - get_2d_performance_state_tasks, - set_performance_state_tasks, - initialize_thermal_controller_tasks, - conditionally_force_3d_performance_state_tasks, - process_vbios_eventinfo_tasks, - broadcast_power_policy_tasks, - NULL -}; - -const struct action_chain initialize_action_chain = { - "Initialize", - initialize_event -}; - -static const pem_event_action * const uninitialize_event[] = { - ungate_all_display_phys_tasks, - uninitialize_display_phy_access_tasks, - disable_gfx_voltage_island_power_gating_tasks, - disable_gfx_clock_gating_tasks, - uninitialize_thermal_controller_tasks, - set_boot_state_tasks, - adjust_power_state_tasks, - disable_dynamic_state_management_tasks, - disable_clock_power_gatings_tasks, - cleanup_asic_tasks, - prepare_for_pnp_stop_tasks, - NULL -}; - -const struct action_chain uninitialize_action_chain = { - "Uninitialize", - uninitialize_event -}; - -static const pem_event_action * const power_source_change_event_pp_enabled[] = { - set_power_source_tasks, - set_power_saving_state_tasks, - adjust_power_state_tasks, - enable_disable_fps_tasks, - set_nbmcu_state_tasks, - broadcast_power_policy_tasks, - NULL -}; - -const struct action_chain power_source_change_action_chain_pp_enabled = { - "Power source change - PowerPlay enabled", - power_source_change_event_pp_enabled -}; - -static const pem_event_action * const power_source_change_event_pp_disabled[] = { - set_power_source_tasks, - set_nbmcu_state_tasks, - NULL -}; - -const struct action_chain power_source_changes_action_chain_pp_disabled = { - "Power source change - PowerPlay disabled", - power_source_change_event_pp_disabled -}; - -static const pem_event_action * const power_source_change_event_hardware_dc[] = { - set_power_source_tasks, - set_power_saving_state_tasks, - adjust_power_state_tasks, - enable_disable_fps_tasks, - reset_hardware_dc_notification_tasks, - set_nbmcu_state_tasks, - broadcast_power_policy_tasks, - NULL -}; - -const struct action_chain power_source_change_action_chain_hardware_dc = { - "Power source change - with Hardware DC switching", - power_source_change_event_hardware_dc -}; - -static const pem_event_action * const suspend_event[] = { - reset_display_phy_access_tasks, - unregister_interrupt_tasks, - disable_gfx_voltage_island_power_gating_tasks, - disable_gfx_clock_gating_tasks, - notify_smu_suspend_tasks, - disable_smc_firmware_ctf_tasks, - set_boot_state_tasks, - adjust_power_state_tasks, - disable_fps_tasks, - vari_bright_suspend_tasks, - reset_fan_speed_to_default_tasks, - power_down_asic_tasks, - disable_stutter_mode_tasks, - set_connected_standby_tasks, - block_hw_access_tasks, - NULL -}; - -const struct action_chain suspend_action_chain = { - "Suspend", - suspend_event -}; - -static const pem_event_action * const resume_event[] = { - unblock_hw_access_tasks, - resume_connected_standby_tasks, - notify_smu_resume_tasks, - reset_display_configCounter_tasks, - update_dal_configuration_tasks, - vari_bright_resume_tasks, - setup_asic_tasks, - enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */ - enable_dynamic_state_management_tasks, - enable_disable_bapm_tasks, - initialize_thermal_controller_tasks, - get_2d_performance_state_tasks, - set_performance_state_tasks, - adjust_power_state_tasks, - enable_disable_fps_tasks, - notify_hw_power_source_tasks, - process_vbios_event_info_tasks, - enable_gfx_clock_gating_tasks, - enable_gfx_voltage_island_power_gating_tasks, - reset_clock_gating_tasks, - notify_smu_vpu_recovery_end_tasks, - disable_vpu_cap_tasks, - execute_escape_sequence_tasks, - NULL -}; - - -const struct action_chain resume_action_chain = { - "resume", - resume_event -}; - -static const pem_event_action * const complete_init_event[] = { - unblock_adjust_power_state_tasks, - adjust_power_state_tasks, - enable_gfx_clock_gating_tasks, - enable_gfx_voltage_island_power_gating_tasks, - notify_power_state_change_tasks, - NULL -}; - -const struct action_chain complete_init_action_chain = { - "complete init", - complete_init_event -}; - -static const pem_event_action * const enable_gfx_clock_gating_event[] = { - enable_gfx_clock_gating_tasks, - NULL -}; - -const struct action_chain enable_gfx_clock_gating_action_chain = { - "enable gfx clock gate", - enable_gfx_clock_gating_event -}; - -static const pem_event_action * const disable_gfx_clock_gating_event[] = { - disable_gfx_clock_gating_tasks, - NULL -}; - -const struct action_chain disable_gfx_clock_gating_action_chain = { - "disable gfx clock gate", - disable_gfx_clock_gating_event -}; - -static const pem_event_action * const enable_cgpg_event[] = { - enable_cgpg_tasks, - NULL -}; - -const struct action_chain enable_cgpg_action_chain = { - "eable cg pg", - enable_cgpg_event -}; - -static const pem_event_action * const disable_cgpg_event[] = { - disable_cgpg_tasks, - NULL -}; - -const struct action_chain disable_cgpg_action_chain = { - "disable cg pg", - disable_cgpg_event -}; - - -/* Enable user _2d performance and activate */ - -static const pem_event_action * const enable_user_state_event[] = { - create_new_user_performance_state_tasks, - adjust_power_state_tasks, - NULL -}; - -const struct action_chain enable_user_state_action_chain = { - "Enable user state", - enable_user_state_event -}; - -static const pem_event_action * const enable_user_2d_performance_event[] = { - enable_user_2d_performance_tasks, - add_user_2d_performance_state_tasks, - set_performance_state_tasks, - adjust_power_state_tasks, - delete_user_2d_performance_state_tasks, - NULL -}; - -const struct action_chain enable_user_2d_performance_action_chain = { - "enable_user_2d_performance_event_activate", - enable_user_2d_performance_event -}; - - -static const pem_event_action * const disable_user_2d_performance_event[] = { - disable_user_2d_performance_tasks, - delete_user_2d_performance_state_tasks, - NULL -}; - -const struct action_chain disable_user_2d_performance_action_chain = { - "disable_user_2d_performance_event", - disable_user_2d_performance_event -}; - - -static const pem_event_action * const display_config_change_event[] = { - /* countDisplayConfigurationChangeEventTasks, */ - unblock_adjust_power_state_tasks, - set_cpu_power_state, - notify_hw_power_source_tasks, - get_2d_performance_state_tasks, - set_performance_state_tasks, - /* updateDALConfigurationTasks, - variBrightDisplayConfigurationChangeTasks, */ - adjust_power_state_tasks, - /*enableDisableFPSTasks, - setNBMCUStateTasks, - notifyPCIEDeviceReadyTasks,*/ - NULL -}; - -const struct action_chain display_config_change_action_chain = { - "Display configuration change", - display_config_change_event -}; - -static const pem_event_action * const readjust_power_state_event[] = { - adjust_power_state_tasks, - NULL -}; - -const struct action_chain readjust_power_state_action_chain = { - "re-adjust power state", - readjust_power_state_event -}; - diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h deleted file mode 100644 index f181e53cdcda..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _EVENT_ACTION_CHAINS_H_ -#define _EVENT_ACTION_CHAINS_H_ -#include "eventmgr.h" - -extern const struct action_chain initialize_action_chain; - -extern const struct action_chain uninitialize_action_chain; - -extern const struct action_chain power_source_change_action_chain_pp_enabled; - -extern const struct action_chain power_source_changes_action_chain_pp_disabled; - -extern const struct action_chain power_source_change_action_chain_hardware_dc; - -extern const struct action_chain suspend_action_chain; - -extern const struct action_chain resume_action_chain; - -extern const struct action_chain complete_init_action_chain; - -extern const struct action_chain enable_gfx_clock_gating_action_chain; - -extern const struct action_chain disable_gfx_clock_gating_action_chain; - -extern const struct action_chain enable_cgpg_action_chain; - -extern const struct action_chain disable_cgpg_action_chain; - -extern const struct action_chain enable_user_2d_performance_action_chain; - -extern const struct action_chain disable_user_2d_performance_action_chain; - -extern const struct action_chain enable_user_state_action_chain; - -extern const struct action_chain readjust_power_state_action_chain; - -extern const struct action_chain display_config_change_action_chain; - -#endif /*_EVENT_ACTION_CHAINS_H_*/ - diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c deleted file mode 100644 index a3cd230d636d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "eventmgr.h" -#include "eventinit.h" -#include "ppinterrupt.h" -#include "hardwaremanager.h" - -void pem_init_feature_info(struct pp_eventmgr *eventmgr) -{ - - /* PowerPlay info */ - eventmgr->ui_state_info[PP_PowerSource_AC].default_ui_lable = - PP_StateUILabel_Performance; - - eventmgr->ui_state_info[PP_PowerSource_AC].current_ui_label = - PP_StateUILabel_Performance; - - eventmgr->ui_state_info[PP_PowerSource_DC].default_ui_lable = - PP_StateUILabel_Battery; - - eventmgr->ui_state_info[PP_PowerSource_DC].current_ui_label = - PP_StateUILabel_Battery; - - if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_PowerPlaySupport)) { - eventmgr->features[PP_Feature_PowerPlay].supported = true; - eventmgr->features[PP_Feature_PowerPlay].version = PEM_CURRENT_POWERPLAY_FEATURE_VERSION; - eventmgr->features[PP_Feature_PowerPlay].enabled_default = true; - eventmgr->features[PP_Feature_PowerPlay].enabled = true; - } else { - eventmgr->features[PP_Feature_PowerPlay].supported = false; - eventmgr->features[PP_Feature_PowerPlay].enabled = false; - eventmgr->features[PP_Feature_PowerPlay].enabled_default = false; - } - - eventmgr->features[PP_Feature_Force3DClock].supported = true; - eventmgr->features[PP_Feature_Force3DClock].enabled = false; - eventmgr->features[PP_Feature_Force3DClock].enabled_default = false; - eventmgr->features[PP_Feature_Force3DClock].version = 1; - - /* over drive*/ - eventmgr->features[PP_Feature_User2DPerformance].version = 4; - eventmgr->features[PP_Feature_User3DPerformance].version = 4; - eventmgr->features[PP_Feature_OverdriveTest].version = 4; - - eventmgr->features[PP_Feature_OverDrive].version = 4; - eventmgr->features[PP_Feature_OverDrive].enabled = false; - eventmgr->features[PP_Feature_OverDrive].enabled_default = false; - - eventmgr->features[PP_Feature_User2DPerformance].supported = false; - eventmgr->features[PP_Feature_User2DPerformance].enabled = false; - eventmgr->features[PP_Feature_User2DPerformance].enabled_default = false; - - eventmgr->features[PP_Feature_User3DPerformance].supported = false; - eventmgr->features[PP_Feature_User3DPerformance].enabled = false; - eventmgr->features[PP_Feature_User3DPerformance].enabled_default = false; - - eventmgr->features[PP_Feature_OverdriveTest].supported = false; - eventmgr->features[PP_Feature_OverdriveTest].enabled = false; - eventmgr->features[PP_Feature_OverdriveTest].enabled_default = false; - - eventmgr->features[PP_Feature_OverDrive].supported = false; - - eventmgr->features[PP_Feature_PowerBudgetWaiver].enabled_default = false; - eventmgr->features[PP_Feature_PowerBudgetWaiver].version = 1; - eventmgr->features[PP_Feature_PowerBudgetWaiver].supported = false; - eventmgr->features[PP_Feature_PowerBudgetWaiver].enabled = false; - - /* Multi UVD States support */ - eventmgr->features[PP_Feature_MultiUVDState].supported = false; - eventmgr->features[PP_Feature_MultiUVDState].enabled = false; - eventmgr->features[PP_Feature_MultiUVDState].enabled_default = false; - - /* Dynamic UVD States support */ - eventmgr->features[PP_Feature_DynamicUVDState].supported = false; - eventmgr->features[PP_Feature_DynamicUVDState].enabled = false; - eventmgr->features[PP_Feature_DynamicUVDState].enabled_default = false; - - /* VCE DPM support */ - eventmgr->features[PP_Feature_VCEDPM].supported = false; - eventmgr->features[PP_Feature_VCEDPM].enabled = false; - eventmgr->features[PP_Feature_VCEDPM].enabled_default = false; - - /* ACP PowerGating support */ - eventmgr->features[PP_Feature_ACP_POWERGATING].supported = false; - eventmgr->features[PP_Feature_ACP_POWERGATING].enabled = false; - eventmgr->features[PP_Feature_ACP_POWERGATING].enabled_default = false; - - /* PPM support */ - eventmgr->features[PP_Feature_PPM].version = 1; - eventmgr->features[PP_Feature_PPM].supported = false; - eventmgr->features[PP_Feature_PPM].enabled = false; - - /* FFC support (enables fan and temp settings, Gemini needs temp settings) */ - if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_ODFuzzyFanControlSupport) || - phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_GeminiRegulatorFanControlSupport)) { - eventmgr->features[PP_Feature_FFC].version = 1; - eventmgr->features[PP_Feature_FFC].supported = true; - eventmgr->features[PP_Feature_FFC].enabled = true; - eventmgr->features[PP_Feature_FFC].enabled_default = true; - } else { - eventmgr->features[PP_Feature_FFC].supported = false; - eventmgr->features[PP_Feature_FFC].enabled = false; - eventmgr->features[PP_Feature_FFC].enabled_default = false; - } - - eventmgr->features[PP_Feature_VariBright].supported = false; - eventmgr->features[PP_Feature_VariBright].enabled = false; - eventmgr->features[PP_Feature_VariBright].enabled_default = false; - - eventmgr->features[PP_Feature_BACO].supported = false; - eventmgr->features[PP_Feature_BACO].supported = false; - eventmgr->features[PP_Feature_BACO].enabled_default = false; - - /* PowerDown feature support */ - eventmgr->features[PP_Feature_PowerDown].supported = false; - eventmgr->features[PP_Feature_PowerDown].enabled = false; - eventmgr->features[PP_Feature_PowerDown].enabled_default = false; - - eventmgr->features[PP_Feature_FPS].version = 1; - eventmgr->features[PP_Feature_FPS].supported = false; - eventmgr->features[PP_Feature_FPS].enabled_default = false; - eventmgr->features[PP_Feature_FPS].enabled = false; - - eventmgr->features[PP_Feature_ViPG].version = 1; - eventmgr->features[PP_Feature_ViPG].supported = false; - eventmgr->features[PP_Feature_ViPG].enabled_default = false; - eventmgr->features[PP_Feature_ViPG].enabled = false; -} - -static int thermal_interrupt_callback(void *private_data, - unsigned src_id, const uint32_t *iv_entry) -{ - /* TO DO hanle PEM_Event_ThermalNotification (struct pp_eventmgr *)private_data*/ - pr_info("current thermal is out of range \n"); - return 0; -} - -int pem_register_interrupts(struct pp_eventmgr *eventmgr) -{ - int result = 0; - struct pp_interrupt_registration_info info; - - info.call_back = thermal_interrupt_callback; - info.context = eventmgr; - - result = phm_register_thermal_interrupt(eventmgr->hwmgr, &info); - - /* TODO: - * 2. Register CTF event interrupt - * 3. Register for vbios events interrupt - * 4. Register External Throttle Interrupt - * 5. Register Smc To Host Interrupt - * */ - return result; -} - - -int pem_unregister_interrupts(struct pp_eventmgr *eventmgr) -{ - return 0; -} - - -void pem_uninit_featureInfo(struct pp_eventmgr *eventmgr) -{ - eventmgr->features[PP_Feature_MultiUVDState].supported = false; - eventmgr->features[PP_Feature_VariBright].supported = false; - eventmgr->features[PP_Feature_PowerBudgetWaiver].supported = false; - eventmgr->features[PP_Feature_OverDrive].supported = false; - eventmgr->features[PP_Feature_OverdriveTest].supported = false; - eventmgr->features[PP_Feature_User3DPerformance].supported = false; - eventmgr->features[PP_Feature_User2DPerformance].supported = false; - eventmgr->features[PP_Feature_PowerPlay].supported = false; - eventmgr->features[PP_Feature_Force3DClock].supported = false; -} diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c deleted file mode 100644 index cd1ca07ef7f7..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "eventmanagement.h" -#include "eventmgr.h" -#include "eventactionchains.h" - -int pem_init_event_action_chains(struct pp_eventmgr *eventmgr) -{ - int i; - - for (i = 0; i < AMD_PP_EVENT_MAX; i++) - eventmgr->event_chain[i] = NULL; - - eventmgr->event_chain[AMD_PP_EVENT_SUSPEND] = pem_get_suspend_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_INITIALIZE] = pem_get_initialize_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_UNINITIALIZE] = pem_get_uninitialize_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_POWER_SOURCE_CHANGE] = pem_get_power_source_change_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_HIBERNATE] = pem_get_hibernate_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_RESUME] = pem_get_resume_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_THERMAL_NOTIFICATION] = pem_get_thermal_notification_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_VBIOS_NOTIFICATION] = pem_get_vbios_notification_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_ENTER_THERMAL_STATE] = pem_get_enter_thermal_state_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_EXIT_THERMAL_STATE] = pem_get_exit_thermal_state_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_ENABLE_POWER_PLAY] = pem_get_enable_powerplay_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_DISABLE_POWER_PLAY] = pem_get_disable_powerplay_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST] = pem_get_enable_overdrive_test_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST] = pem_get_disable_overdrive_test_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING] = pem_get_enable_gfx_clock_gating_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING] = pem_get_disable_gfx_clock_gating_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_ENABLE_CGPG] = pem_get_enable_cgpg_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_DISABLE_CGPG] = pem_get_disable_cgpg_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_COMPLETE_INIT] = pem_get_complete_init_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_SCREEN_ON] = pem_get_screen_on_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_SCREEN_OFF] = pem_get_screen_off_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_PRE_SUSPEND] = pem_get_pre_suspend_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_PRE_RESUME] = pem_get_pre_resume_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_ENABLE_USER_STATE] = pem_enable_user_state_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_READJUST_POWER_STATE] = pem_readjust_power_state_action_chain(eventmgr); - eventmgr->event_chain[AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE] = pem_display_config_change_action_chain(eventmgr); - return 0; -} - -int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data) -{ - const pem_event_action * const *paction_chain; - const pem_event_action *psub_chain; - int tmp_result = 0; - int result = 0; - - if (eventmgr == NULL || event_chain == NULL || event_data == NULL) - return -EINVAL; - - for (paction_chain = event_chain->action_chain; NULL != *paction_chain; paction_chain++) { - if (0 != result) - return result; - - for (psub_chain = *paction_chain; NULL != *psub_chain; psub_chain++) { - tmp_result = (*psub_chain)(eventmgr, event_data); - if (0 == result) - result = tmp_result; - } - } - - return result; -} - -const struct action_chain *pem_get_suspend_action_chain(struct pp_eventmgr *eventmgr) -{ - return &suspend_action_chain; -} - -const struct action_chain *pem_get_initialize_action_chain(struct pp_eventmgr *eventmgr) -{ - return &initialize_action_chain; -} - -const struct action_chain *pem_get_uninitialize_action_chain(struct pp_eventmgr *eventmgr) -{ - return &uninitialize_action_chain; -} - -const struct action_chain *pem_get_power_source_change_action_chain(struct pp_eventmgr *eventmgr) -{ - return &power_source_change_action_chain_pp_enabled; /* other case base on feature info*/ -} - -const struct action_chain *pem_get_resume_action_chain(struct pp_eventmgr *eventmgr) -{ - return &resume_action_chain; -} - -const struct action_chain *pem_get_hibernate_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_thermal_notification_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_vbios_notification_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_enter_thermal_state_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_exit_thermal_state_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_enable_powerplay_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_disable_powerplay_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_enable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_disable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_enable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr) -{ - return &enable_gfx_clock_gating_action_chain; -} - -const struct action_chain *pem_get_disable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr) -{ - return &disable_gfx_clock_gating_action_chain; -} - -const struct action_chain *pem_get_enable_cgpg_action_chain(struct pp_eventmgr *eventmgr) -{ - return &enable_cgpg_action_chain; -} - -const struct action_chain *pem_get_disable_cgpg_action_chain(struct pp_eventmgr *eventmgr) -{ - return &disable_cgpg_action_chain; -} - -const struct action_chain *pem_get_complete_init_action_chain(struct pp_eventmgr *eventmgr) -{ - return &complete_init_action_chain; -} - -const struct action_chain *pem_get_screen_on_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_screen_off_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_pre_suspend_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_get_pre_resume_action_chain(struct pp_eventmgr *eventmgr) -{ - return NULL; -} - -const struct action_chain *pem_enable_user_state_action_chain(struct pp_eventmgr *eventmgr) -{ - return &enable_user_state_action_chain; -} - -const struct action_chain *pem_readjust_power_state_action_chain(struct pp_eventmgr *eventmgr) -{ - return &readjust_power_state_action_chain; -} - -const struct action_chain *pem_display_config_change_action_chain(struct pp_eventmgr *eventmgr) -{ - return &display_config_change_action_chain; -} diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h deleted file mode 100644 index 383d4b295aa9..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _EVENT_MANAGEMENT_H_ -#define _EVENT_MANAGEMENT_H_ - -#include "eventmgr.h" - -int pem_init_event_action_chains(struct pp_eventmgr *eventmgr); -int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data); -const struct action_chain *pem_get_suspend_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_initialize_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_uninitialize_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_power_source_change_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_resume_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_hibernate_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_thermal_notification_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_vbios_notification_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_enter_thermal_state_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_exit_thermal_state_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_enable_powerplay_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_disable_powerplay_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_enable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_disable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_enable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_disable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_enable_cgpg_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_disable_cgpg_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_complete_init_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_screen_on_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_screen_off_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_pre_suspend_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_get_pre_resume_action_chain(struct pp_eventmgr *eventmgr); - -extern const struct action_chain *pem_enable_user_state_action_chain(struct pp_eventmgr *eventmgr); -extern const struct action_chain *pem_readjust_power_state_action_chain(struct pp_eventmgr *eventmgr); -const struct action_chain *pem_display_config_change_action_chain(struct pp_eventmgr *eventmgr); - - -#endif /* _EVENT_MANAGEMENT_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c deleted file mode 100644 index 3e3ca03bd344..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include "eventmgr.h" -#include "hwmgr.h" -#include "eventinit.h" -#include "eventmanagement.h" - -static int pem_init(struct pp_eventmgr *eventmgr) -{ - int result = 0; - struct pem_event_data event_data = { {0} }; - - /* Initialize PowerPlay feature info */ - pem_init_feature_info(eventmgr); - - /* Initialize event action chains */ - pem_init_event_action_chains(eventmgr); - - /* Call initialization event */ - result = pem_handle_event(eventmgr, AMD_PP_EVENT_INITIALIZE, &event_data); - - /* if (0 != result) - return result; */ - - /* Register interrupt callback functions */ - result = pem_register_interrupts(eventmgr); - return 0; -} - -static void pem_fini(struct pp_eventmgr *eventmgr) -{ - struct pem_event_data event_data = { {0} }; - - pem_uninit_featureInfo(eventmgr); - pem_unregister_interrupts(eventmgr); - - pem_handle_event(eventmgr, AMD_PP_EVENT_UNINITIALIZE, &event_data); -} - -int eventmgr_early_init(struct pp_instance *handle) -{ - struct pp_eventmgr *eventmgr; - - if (handle == NULL) - return -EINVAL; - - eventmgr = kzalloc(sizeof(struct pp_eventmgr), GFP_KERNEL); - if (eventmgr == NULL) - return -ENOMEM; - - eventmgr->hwmgr = handle->hwmgr; - handle->eventmgr = eventmgr; - - eventmgr->platform_descriptor = &(eventmgr->hwmgr->platform_descriptor); - eventmgr->pp_eventmgr_init = pem_init; - eventmgr->pp_eventmgr_fini = pem_fini; - - return 0; -} - -static int pem_handle_event_unlocked(struct pp_eventmgr *eventmgr, enum amd_pp_event event, struct pem_event_data *data) -{ - if (eventmgr == NULL || event >= AMD_PP_EVENT_MAX || data == NULL) - return -EINVAL; - - return pem_excute_event_chain(eventmgr, eventmgr->event_chain[event], data); -} - -int pem_handle_event(struct pp_eventmgr *eventmgr, enum amd_pp_event event, struct pem_event_data *event_data) -{ - int r = 0; - - r = pem_handle_event_unlocked(eventmgr, event, event_data); - - return r; -} - -bool pem_is_hw_access_blocked(struct pp_eventmgr *eventmgr) -{ - return (eventmgr->block_adjust_power_state || phm_is_hw_access_blocked(eventmgr->hwmgr)); -} diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c deleted file mode 100644 index b82c43af59ab..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "eventmgr.h" -#include "eventsubchains.h" -#include "eventtasks.h" -#include "hardwaremanager.h" - -const pem_event_action reset_display_phy_access_tasks[] = { - pem_task_reset_display_phys_access, - NULL -}; - -const pem_event_action broadcast_power_policy_tasks[] = { - /* PEM_Task_BroadcastPowerPolicyChange, */ - NULL -}; - -const pem_event_action unregister_interrupt_tasks[] = { - pem_task_unregister_interrupts, - NULL -}; - -/* Disable GFX Voltage Islands Power Gating */ -const pem_event_action disable_gfx_voltage_island_powergating_tasks[] = { - pem_task_disable_voltage_island_power_gating, - NULL -}; - -const pem_event_action disable_gfx_clockgating_tasks[] = { - pem_task_disable_gfx_clock_gating, - NULL -}; - -const pem_event_action block_adjust_power_state_tasks[] = { - pem_task_block_adjust_power_state, - NULL -}; - - -const pem_event_action unblock_adjust_power_state_tasks[] = { - pem_task_unblock_adjust_power_state, - NULL -}; - -const pem_event_action set_performance_state_tasks[] = { - pem_task_set_performance_state, - NULL -}; - -const pem_event_action get_2d_performance_state_tasks[] = { - pem_task_get_2D_performance_state_id, - NULL -}; - -const pem_event_action conditionally_force3D_performance_state_tasks[] = { - pem_task_conditionally_force_3d_performance_state, - NULL -}; - -const pem_event_action process_vbios_eventinfo_tasks[] = { - /* PEM_Task_ProcessVbiosEventInfo,*/ - NULL -}; - -const pem_event_action enable_dynamic_state_management_tasks[] = { - /* PEM_Task_ResetBAPMPolicyChangedFlag,*/ - pem_task_get_boot_state_id, - pem_task_enable_dynamic_state_management, - pem_task_register_interrupts, - NULL -}; - -const pem_event_action enable_clock_power_gatings_tasks[] = { - pem_task_enable_clock_power_gatings_tasks, - pem_task_powerdown_uvd_tasks, - pem_task_powerdown_vce_tasks, - NULL -}; - -const pem_event_action setup_asic_tasks[] = { - pem_task_setup_asic, - NULL -}; - -const pem_event_action power_budget_tasks[] = { - /* TODO - * PEM_Task_PowerBudgetWaiverAvailable, - * PEM_Task_PowerBudgetWarningMessage, - * PEM_Task_PruneStatesBasedOnPowerBudget, - */ - NULL -}; - -const pem_event_action system_config_tasks[] = { - /* PEM_Task_PruneStatesBasedOnSystemConfig,*/ - NULL -}; - - -const pem_event_action conditionally_force_3d_performance_state_tasks[] = { - pem_task_conditionally_force_3d_performance_state, - NULL -}; - -const pem_event_action ungate_all_display_phys_tasks[] = { - /* PEM_Task_GetDisplayPhyAccessInfo */ - NULL -}; - -const pem_event_action uninitialize_display_phy_access_tasks[] = { - /* PEM_Task_UninitializeDisplayPhysAccess, */ - NULL -}; - -const pem_event_action disable_gfx_voltage_island_power_gating_tasks[] = { - /* PEM_Task_DisableVoltageIslandPowerGating, */ - NULL -}; - -const pem_event_action disable_gfx_clock_gating_tasks[] = { - pem_task_disable_gfx_clock_gating, - NULL -}; - -const pem_event_action set_boot_state_tasks[] = { - pem_task_get_boot_state_id, - pem_task_set_boot_state, - NULL -}; - -const pem_event_action adjust_power_state_tasks[] = { - pem_task_notify_hw_mgr_display_configuration_change, - pem_task_adjust_power_state, - pem_task_notify_smc_display_config_after_power_state_adjustment, - pem_task_update_allowed_performance_levels, - /* to do pem_task_Enable_disable_bapm, */ - NULL -}; - -const pem_event_action disable_dynamic_state_management_tasks[] = { - pem_task_unregister_interrupts, - pem_task_get_boot_state_id, - pem_task_disable_dynamic_state_management, - NULL -}; - -const pem_event_action disable_clock_power_gatings_tasks[] = { - pem_task_disable_clock_power_gatings_tasks, - NULL -}; - -const pem_event_action cleanup_asic_tasks[] = { - /* PEM_Task_DisableFPS,*/ - pem_task_cleanup_asic, - NULL -}; - -const pem_event_action prepare_for_pnp_stop_tasks[] = { - /* PEM_Task_PrepareForPnpStop,*/ - NULL -}; - -const pem_event_action set_power_source_tasks[] = { - pem_task_set_power_source, - pem_task_notify_hw_of_power_source, - NULL -}; - -const pem_event_action set_power_saving_state_tasks[] = { - pem_task_reset_power_saving_state, - pem_task_get_power_saving_state, - pem_task_set_power_saving_state, - /* PEM_Task_ResetODDCState, - * PEM_Task_GetODDCState, - * PEM_Task_SetODDCState,*/ - NULL -}; - -const pem_event_action enable_disable_fps_tasks[] = { - /* PEM_Task_EnableDisableFPS,*/ - NULL -}; - -const pem_event_action set_nbmcu_state_tasks[] = { - /* PEM_Task_NBMCUStateChange,*/ - NULL -}; - -const pem_event_action reset_hardware_dc_notification_tasks[] = { - /* PEM_Task_ResetHardwareDCNotification,*/ - NULL -}; - - -const pem_event_action notify_smu_suspend_tasks[] = { - /* PEM_Task_NotifySMUSuspend,*/ - NULL -}; - -const pem_event_action disable_smc_firmware_ctf_tasks[] = { - pem_task_disable_smc_firmware_ctf, - NULL -}; - -const pem_event_action disable_fps_tasks[] = { - /* PEM_Task_DisableFPS,*/ - NULL -}; - -const pem_event_action vari_bright_suspend_tasks[] = { - /* PEM_Task_VariBright_Suspend,*/ - NULL -}; - -const pem_event_action reset_fan_speed_to_default_tasks[] = { - /* PEM_Task_ResetFanSpeedToDefault,*/ - NULL -}; - -const pem_event_action power_down_asic_tasks[] = { - /* PEM_Task_DisableFPS,*/ - pem_task_power_down_asic, - NULL -}; - -const pem_event_action disable_stutter_mode_tasks[] = { - /* PEM_Task_DisableStutterMode,*/ - NULL -}; - -const pem_event_action set_connected_standby_tasks[] = { - /* PEM_Task_SetConnectedStandby,*/ - NULL -}; - -const pem_event_action block_hw_access_tasks[] = { - pem_task_block_hw_access, - NULL -}; - -const pem_event_action unblock_hw_access_tasks[] = { - pem_task_un_block_hw_access, - NULL -}; - -const pem_event_action resume_connected_standby_tasks[] = { - /* PEM_Task_ResumeConnectedStandby,*/ - NULL -}; - -const pem_event_action notify_smu_resume_tasks[] = { - /* PEM_Task_NotifySMUResume,*/ - NULL -}; - -const pem_event_action reset_display_configCounter_tasks[] = { - pem_task_reset_display_phys_access, - NULL -}; - -const pem_event_action update_dal_configuration_tasks[] = { - /* PEM_Task_CheckVBlankTime,*/ - NULL -}; - -const pem_event_action vari_bright_resume_tasks[] = { - /* PEM_Task_VariBright_Resume,*/ - NULL -}; - -const pem_event_action notify_hw_power_source_tasks[] = { - pem_task_notify_hw_of_power_source, - NULL -}; - -const pem_event_action process_vbios_event_info_tasks[] = { - /* PEM_Task_ProcessVbiosEventInfo,*/ - NULL -}; - -const pem_event_action enable_gfx_clock_gating_tasks[] = { - pem_task_enable_gfx_clock_gating, - NULL -}; - -const pem_event_action enable_gfx_voltage_island_power_gating_tasks[] = { - pem_task_enable_voltage_island_power_gating, - NULL -}; - -const pem_event_action reset_clock_gating_tasks[] = { - /* PEM_Task_ResetClockGating*/ - NULL -}; - -const pem_event_action notify_smu_vpu_recovery_end_tasks[] = { - /* PEM_Task_NotifySmuVPURecoveryEnd,*/ - NULL -}; - -const pem_event_action disable_vpu_cap_tasks[] = { - /* PEM_Task_DisableVPUCap,*/ - NULL -}; - -const pem_event_action execute_escape_sequence_tasks[] = { - /* PEM_Task_ExecuteEscapesequence,*/ - NULL -}; - -const pem_event_action notify_power_state_change_tasks[] = { - pem_task_notify_power_state_change, - NULL -}; - -const pem_event_action enable_cgpg_tasks[] = { - pem_task_enable_cgpg, - NULL -}; - -const pem_event_action disable_cgpg_tasks[] = { - pem_task_disable_cgpg, - NULL -}; - -const pem_event_action enable_user_2d_performance_tasks[] = { - /* PEM_Task_SetUser2DPerformanceFlag,*/ - /* PEM_Task_UpdateUser2DPerformanceEnableEvents,*/ - NULL -}; - -const pem_event_action add_user_2d_performance_state_tasks[] = { - /* PEM_Task_Get2DPerformanceTemplate,*/ - /* PEM_Task_AllocateNewPowerStateMemory,*/ - /* PEM_Task_CopyNewPowerStateInfo,*/ - /* PEM_Task_UpdateNewPowerStateClocks,*/ - /* PEM_Task_UpdateNewPowerStateUser2DPerformanceFlag,*/ - /* PEM_Task_AddPowerState,*/ - /* PEM_Task_ReleaseNewPowerStateMemory,*/ - NULL -}; - -const pem_event_action delete_user_2d_performance_state_tasks[] = { - /* PEM_Task_GetCurrentUser2DPerformanceStateID,*/ - /* PEM_Task_DeletePowerState,*/ - /* PEM_Task_SetCurrentUser2DPerformanceStateID,*/ - NULL -}; - -const pem_event_action disable_user_2d_performance_tasks[] = { - /* PEM_Task_ResetUser2DPerformanceFlag,*/ - /* PEM_Task_UpdateUser2DPerformanceDisableEvents,*/ - NULL -}; - -const pem_event_action enable_stutter_mode_tasks[] = { - pem_task_enable_stutter_mode, - NULL -}; - -const pem_event_action enable_disable_bapm_tasks[] = { - /*PEM_Task_EnableDisableBAPM,*/ - NULL -}; - -const pem_event_action reset_boot_state_tasks[] = { - pem_task_reset_boot_state, - NULL -}; - -const pem_event_action create_new_user_performance_state_tasks[] = { - pem_task_create_user_performance_state, - NULL -}; - -const pem_event_action initialize_thermal_controller_tasks[] = { - pem_task_initialize_thermal_controller, - NULL -}; - -const pem_event_action uninitialize_thermal_controller_tasks[] = { - pem_task_uninitialize_thermal_controller, - NULL -}; - -const pem_event_action set_cpu_power_state[] = { - pem_task_set_cpu_power_state, - NULL -};
\ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h deleted file mode 100644 index 7714cb927428..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _EVENT_SUB_CHAINS_H_ -#define _EVENT_SUB_CHAINS_H_ - -#include "eventmgr.h" - -extern const pem_event_action reset_display_phy_access_tasks[]; -extern const pem_event_action broadcast_power_policy_tasks[]; -extern const pem_event_action unregister_interrupt_tasks[]; -extern const pem_event_action disable_GFX_voltage_island_powergating_tasks[]; -extern const pem_event_action disable_GFX_clockgating_tasks[]; -extern const pem_event_action block_adjust_power_state_tasks[]; -extern const pem_event_action unblock_adjust_power_state_tasks[]; -extern const pem_event_action set_performance_state_tasks[]; -extern const pem_event_action get_2D_performance_state_tasks[]; -extern const pem_event_action conditionally_force3D_performance_state_tasks[]; -extern const pem_event_action process_vbios_eventinfo_tasks[]; -extern const pem_event_action enable_dynamic_state_management_tasks[]; -extern const pem_event_action enable_clock_power_gatings_tasks[]; -extern const pem_event_action conditionally_force3D_performance_state_tasks[]; -extern const pem_event_action setup_asic_tasks[]; -extern const pem_event_action power_budget_tasks[]; -extern const pem_event_action system_config_tasks[]; -extern const pem_event_action get_2d_performance_state_tasks[]; -extern const pem_event_action conditionally_force_3d_performance_state_tasks[]; -extern const pem_event_action ungate_all_display_phys_tasks[]; -extern const pem_event_action uninitialize_display_phy_access_tasks[]; -extern const pem_event_action disable_gfx_voltage_island_power_gating_tasks[]; -extern const pem_event_action disable_gfx_clock_gating_tasks[]; -extern const pem_event_action set_boot_state_tasks[]; -extern const pem_event_action adjust_power_state_tasks[]; -extern const pem_event_action disable_dynamic_state_management_tasks[]; -extern const pem_event_action disable_clock_power_gatings_tasks[]; -extern const pem_event_action cleanup_asic_tasks[]; -extern const pem_event_action prepare_for_pnp_stop_tasks[]; -extern const pem_event_action set_power_source_tasks[]; -extern const pem_event_action set_power_saving_state_tasks[]; -extern const pem_event_action enable_disable_fps_tasks[]; -extern const pem_event_action set_nbmcu_state_tasks[]; -extern const pem_event_action reset_hardware_dc_notification_tasks[]; -extern const pem_event_action notify_smu_suspend_tasks[]; -extern const pem_event_action disable_smc_firmware_ctf_tasks[]; -extern const pem_event_action disable_fps_tasks[]; -extern const pem_event_action vari_bright_suspend_tasks[]; -extern const pem_event_action reset_fan_speed_to_default_tasks[]; -extern const pem_event_action power_down_asic_tasks[]; -extern const pem_event_action disable_stutter_mode_tasks[]; -extern const pem_event_action set_connected_standby_tasks[]; -extern const pem_event_action block_hw_access_tasks[]; -extern const pem_event_action unblock_hw_access_tasks[]; -extern const pem_event_action resume_connected_standby_tasks[]; -extern const pem_event_action notify_smu_resume_tasks[]; -extern const pem_event_action reset_display_configCounter_tasks[]; -extern const pem_event_action update_dal_configuration_tasks[]; -extern const pem_event_action vari_bright_resume_tasks[]; -extern const pem_event_action notify_hw_power_source_tasks[]; -extern const pem_event_action process_vbios_event_info_tasks[]; -extern const pem_event_action enable_gfx_clock_gating_tasks[]; -extern const pem_event_action enable_gfx_voltage_island_power_gating_tasks[]; -extern const pem_event_action reset_clock_gating_tasks[]; -extern const pem_event_action notify_smu_vpu_recovery_end_tasks[]; -extern const pem_event_action disable_vpu_cap_tasks[]; -extern const pem_event_action execute_escape_sequence_tasks[]; -extern const pem_event_action notify_power_state_change_tasks[]; -extern const pem_event_action enable_cgpg_tasks[]; -extern const pem_event_action disable_cgpg_tasks[]; -extern const pem_event_action enable_user_2d_performance_tasks[]; -extern const pem_event_action add_user_2d_performance_state_tasks[]; -extern const pem_event_action delete_user_2d_performance_state_tasks[]; -extern const pem_event_action disable_user_2d_performance_tasks[]; -extern const pem_event_action enable_stutter_mode_tasks[]; -extern const pem_event_action enable_disable_bapm_tasks[]; -extern const pem_event_action reset_boot_state_tasks[]; -extern const pem_event_action create_new_user_performance_state_tasks[]; -extern const pem_event_action initialize_thermal_controller_tasks[]; -extern const pem_event_action uninitialize_thermal_controller_tasks[]; -extern const pem_event_action set_cpu_power_state[]; -#endif /* _EVENT_SUB_CHAINS_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c deleted file mode 100644 index 8c4ebaae1e0c..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "eventmgr.h" -#include "eventinit.h" -#include "eventmanagement.h" -#include "eventmanager.h" -#include "hardwaremanager.h" -#include "eventtasks.h" -#include "power_state.h" -#include "hwmgr.h" -#include "amd_powerplay.h" -#include "psm.h" - -#define TEMP_RANGE_MIN (90 * 1000) -#define TEMP_RANGE_MAX (120 * 1000) - -int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - - if (eventmgr == NULL || eventmgr->hwmgr == NULL) - return -EINVAL; - - if (pem_is_hw_access_blocked(eventmgr)) - return 0; - - phm_force_dpm_levels(eventmgr->hwmgr, eventmgr->hwmgr->dpm_level); - - return 0; -} - -/* eventtasks_generic.c */ -int pem_task_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - struct pp_hwmgr *hwmgr; - - if (pem_is_hw_access_blocked(eventmgr)) - return 0; - - hwmgr = eventmgr->hwmgr; - if (event_data->pnew_power_state != NULL) - hwmgr->request_ps = event_data->pnew_power_state; - - if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) - psm_adjust_power_state_dynamic(eventmgr, event_data->skip_state_adjust_rules); - else - psm_adjust_power_state_static(eventmgr, event_data->skip_state_adjust_rules); - - return 0; -} - -int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_power_down_asic(eventmgr->hwmgr); -} - -int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - if (pem_is_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID)) - return psm_set_states(eventmgr, &(event_data->requested_state_id)); - - return 0; -} - -int pem_task_reset_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_update_new_power_state_clocks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_system_shutdown(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_register_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_unregister_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return pem_unregister_interrupts(eventmgr); -} - -int pem_task_get_boot_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - int result; - - result = psm_get_state_by_classification(eventmgr, - PP_StateClassificationFlag_Boot, - &(event_data->requested_state_id) - ); - - if (0 == result) - pem_set_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID); - else - pem_unset_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID); - - return result; -} - -int pem_task_enable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_enable_dynamic_state_management(eventmgr->hwmgr); -} - -int pem_task_disable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_disable_dynamic_state_management(eventmgr->hwmgr); -} - -int pem_task_enable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_enable_clock_power_gatings(eventmgr->hwmgr); -} - -int pem_task_powerdown_uvd_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_powerdown_uvd(eventmgr->hwmgr); -} - -int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - phm_powergate_uvd(eventmgr->hwmgr, true); - phm_powergate_vce(eventmgr->hwmgr, true); - return 0; -} - -int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - phm_disable_clock_power_gatings(eventmgr->hwmgr); - return 0; -} - -int pem_task_start_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_stop_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_disable_smc_firmware_ctf(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_disable_smc_firmware_ctf(eventmgr->hwmgr); -} - -int pem_task_setup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_setup_asic(eventmgr->hwmgr); -} - -int pem_task_cleanup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_store_dal_configuration(struct pp_eventmgr *eventmgr, const struct amd_display_configuration *display_config) -{ - /* TODO */ - return 0; - /*phm_store_dal_configuration_data(eventmgr->hwmgr, display_config) */ -} - -int pem_task_notify_hw_mgr_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - if (pem_is_hw_access_blocked(eventmgr)) - return 0; - - return phm_display_configuration_changed(eventmgr->hwmgr); -} - -int pem_task_notify_hw_mgr_pre_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return 0; -} - -int pem_task_notify_smc_display_config_after_power_state_adjustment(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - if (pem_is_hw_access_blocked(eventmgr)) - return 0; - - return phm_notify_smc_display_config_after_ps_adjustment(eventmgr->hwmgr); -} - -int pem_task_block_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - eventmgr->block_adjust_power_state = true; - /* to do PHM_ResetIPSCounter(pEventMgr->pHwMgr);*/ - return 0; -} - -int pem_task_unblock_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - eventmgr->block_adjust_power_state = false; - return 0; -} - -int pem_task_notify_power_state_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_un_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_set_cpu_power_state(eventmgr->hwmgr); -} - -/*powersaving*/ - -int pem_task_set_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_notify_hw_of_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_get_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_reset_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_set_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_set_screen_state_on(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_set_screen_state_off(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_enable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_disable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_enable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_enable_clock_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - - -int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_disable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - - -/* performance */ -int pem_task_set_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - if (pem_is_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID)) - return psm_set_states(eventmgr, &(event_data->requested_state_id)); - - return 0; -} - -int pem_task_conditionally_force_3d_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_enable_stutter_mode(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - -int pem_task_get_2D_performance_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - int result; - - if (eventmgr->features[PP_Feature_PowerPlay].supported && - !(eventmgr->features[PP_Feature_PowerPlay].enabled)) - result = psm_get_state_by_classification(eventmgr, - PP_StateClassificationFlag_Boot, - &(event_data->requested_state_id)); - else if (eventmgr->features[PP_Feature_User2DPerformance].enabled) - result = psm_get_state_by_classification(eventmgr, - PP_StateClassificationFlag_User2DPerformance, - &(event_data->requested_state_id)); - else - result = psm_get_ui_state(eventmgr, PP_StateUILabel_Performance, - &(event_data->requested_state_id)); - - if (0 == result) - pem_set_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID); - else - pem_unset_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID); - - return result; -} - -int pem_task_create_user_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - struct pp_power_state *state; - int table_entries; - struct pp_hwmgr *hwmgr = eventmgr->hwmgr; - int i; - - table_entries = hwmgr->num_ps; - state = hwmgr->ps; - -restart_search: - for (i = 0; i < table_entries; i++) { - if (state->classification.ui_label & event_data->requested_ui_label) { - event_data->pnew_power_state = state; - return 0; - } - state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); - } - - switch (event_data->requested_ui_label) { - case PP_StateUILabel_Battery: - case PP_StateUILabel_Balanced: - event_data->requested_ui_label = PP_StateUILabel_Performance; - goto restart_search; - default: - break; - } - return -1; -} - -int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - struct PP_TemperatureRange range; - - range.max = TEMP_RANGE_MAX; - range.min = TEMP_RANGE_MIN; - - if (eventmgr == NULL || eventmgr->platform_descriptor == NULL) - return -EINVAL; - - if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_ThermalController)) - return phm_start_thermal_controller(eventmgr->hwmgr, &range); - - return 0; -} - -int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - return phm_stop_thermal_controller(eventmgr->hwmgr); -} diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h deleted file mode 100644 index 37e7ca5a58e0..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _EVENT_TASKS_H_ -#define _EVENT_TASKS_H_ -#include "eventmgr.h" - -struct amd_display_configuration; - -/* eventtasks_generic.c */ -int pem_task_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_get_boot_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_reset_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_update_new_power_state_clocks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_system_shutdown(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_register_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_unregister_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_enable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_disable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_enable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_powerdown_uvd_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_start_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_stop_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_setup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_cleanup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_store_dal_configuration (struct pp_eventmgr *eventmgr, const struct amd_display_configuration *display_config); -int pem_task_notify_hw_mgr_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_notify_hw_mgr_pre_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_block_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_unblock_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_notify_power_state_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_un_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_notify_smc_display_config_after_power_state_adjustment(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -/*powersaving*/ - -int pem_task_set_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_notify_hw_of_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_get_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_reset_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_set_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_set_screen_state_on(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_set_screen_state_off(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_enable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_disable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_enable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_disable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_enable_stutter_mode(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); - -/* performance */ -int pem_task_set_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_conditionally_force_3d_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_get_2D_performance_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_create_user_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -/*thermal */ -int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); -int pem_task_disable_smc_firmware_ctf(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data); - -#endif /* _EVENT_TASKS_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c deleted file mode 100644 index 489908887e9c..000000000000 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include "psm.h" - -int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label, unsigned long *state_id) -{ - struct pp_power_state *state; - int table_entries; - struct pp_hwmgr *hwmgr = eventmgr->hwmgr; - int i; - - table_entries = hwmgr->num_ps; - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - if (state->classification.ui_label & ui_label) { - *state_id = state->id; - return 0; - } - state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); - } - return -1; -} - -int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateClassificationFlag flag, unsigned long *state_id) -{ - struct pp_power_state *state; - int table_entries; - struct pp_hwmgr *hwmgr = eventmgr->hwmgr; - int i; - - table_entries = hwmgr->num_ps; - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - if (state->classification.flags & flag) { - *state_id = state->id; - return 0; - } - state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); - } - return -1; -} - -int psm_set_states(struct pp_eventmgr *eventmgr, unsigned long *state_id) -{ - struct pp_power_state *state; - int table_entries; - struct pp_hwmgr *hwmgr = eventmgr->hwmgr; - int i; - - table_entries = hwmgr->num_ps; - - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - if (state->id == *state_id) { - memcpy(hwmgr->request_ps, state, hwmgr->ps_size); - return 0; - } - state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); - } - return -1; -} - -int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip) -{ - - struct pp_power_state *pcurrent; - struct pp_power_state *requested; - struct pp_hwmgr *hwmgr; - bool equal; - - if (skip) - return 0; - - hwmgr = eventmgr->hwmgr; - pcurrent = hwmgr->current_ps; - requested = hwmgr->request_ps; - - if (requested == NULL) - return 0; - - phm_apply_state_adjust_rules(hwmgr, requested, pcurrent); - - if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr, &pcurrent->hardware, &requested->hardware, &equal))) - equal = false; - - if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) { - phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware); - memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size); - } - return 0; -} - -int psm_adjust_power_state_static(struct pp_eventmgr *eventmgr, bool skip) -{ - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index f0277c16c2bf..dc4bbcfe1243 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -2,14 +2,15 @@ # Makefile for the 'hw manager' sub-component of powerplay. # It provides the hardware management services for the driver. -HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ +HARDWARE_MGR = hwmgr.o processpptables.o \ hardwaremanager.o pp_acpi.o cz_hwmgr.o \ cz_clockpowergating.o pppcielanes.o\ process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \ smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ smu7_clockpowergating.o \ vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \ - vega10_thermal.o pp_overdriver.o rv_hwmgr.o + vega10_thermal.o rv_hwmgr.o pp_psm.o\ + pp_overdriver.o AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c index b33935fcf428..44de0874629f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c @@ -103,16 +103,6 @@ int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr) return 0; } -static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result) -{ - return 0; -} - -static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result) -{ - return 0; -} - int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -123,12 +113,12 @@ int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) PHM_PlatformCaps_UVDDPM)) { cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled; dpm_features |= UVD_DPM_MASK; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, dpm_features); } else { dpm_features |= UVD_DPM_MASK; cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, dpm_features); } return 0; @@ -144,12 +134,12 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) PHM_PlatformCaps_VCEDPM)) { cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled; dpm_features |= VCE_DPM_MASK; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, dpm_features); } else { dpm_features |= VCE_DPM_MASK; cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, dpm_features); } @@ -157,7 +147,7 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) } -int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) +void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -183,10 +173,9 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) cz_dpm_update_uvd_dpm(hwmgr, false); } - return 0; } -int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) +void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -215,29 +204,6 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) AMD_CG_STATE_UNGATE); cz_dpm_update_vce_dpm(hwmgr); cz_enable_disable_vce_dpm(hwmgr, true); - return 0; } - - return 0; } - -static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = { - /*we don't need an exit table here, because there is only D3 cold on Kv*/ - { - .isFunctionNeededInRuntimeTable = phm_cf_want_uvd_power_gating, - .tableFunction = cz_tf_uvd_power_gating_initialize - }, - { - .isFunctionNeededInRuntimeTable = phm_cf_want_vce_power_gating, - .tableFunction = cz_tf_vce_power_gating_initialize - }, - /* to do { NULL, cz_tf_xdma_power_gating_enable }, */ - { } -}; - -const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = { - 0, - PHM_MasterTableFlag_None, - cz_enable_clock_power_gatings_list -}; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h index 1954ceaed439..92f707bc46e7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h @@ -29,8 +29,8 @@ extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating); extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master; -extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); -extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); +extern void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); +extern void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); extern int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable); #endif /* _CZ_CLOCK_POWER_GATING_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index bc839ff0bdd0..73bb99d62a44 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -162,8 +162,8 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr) struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); if (cz_hwmgr->max_sclk_level == 0) { - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel); - cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1; + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel); + cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1; } return cz_hwmgr->max_sclk_level; @@ -440,14 +440,7 @@ static int cz_construct_boot_state(struct pp_hwmgr *hwmgr) return 0; } -static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) -{ - return 0; -} - -static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) { struct SMU8_Fusion_ClkTable *clock_table; int ret; @@ -469,7 +462,7 @@ static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input, if (!hwmgr->need_pp_table_upload) return 0; - ret = smum_download_powerplay_table(hwmgr->smumgr, &table); + ret = smum_download_powerplay_table(hwmgr, &table); PP_ASSERT_WITH_CODE((0 == ret && NULL != table), "Fail to get clock table from SMU!", return -EINVAL;); @@ -561,13 +554,12 @@ static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input, (uint8_t)dividers.pll_post_divider; } - ret = smum_upload_powerplay_table(hwmgr->smumgr); + ret = smum_upload_powerplay_table(hwmgr); return ret; } -static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct phm_clock_voltage_dependency_table *table = @@ -593,8 +585,7 @@ static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input, return 0; } -static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct phm_uvd_clock_voltage_dependency_table *table = @@ -607,8 +598,8 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input, cz_hwmgr->uvd_dpm.soft_min_clk = 0; cz_hwmgr->uvd_dpm.hard_min_clk = 0; - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel); - level = smum_get_argument(hwmgr->smumgr); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel); + level = smum_get_argument(hwmgr); if (level < table->count) clock = table->entries[level].vclk; @@ -621,8 +612,7 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input, return 0; } -static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int cz_init_vce_limit(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct phm_vce_clock_voltage_dependency_table *table = @@ -635,8 +625,8 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input, cz_hwmgr->vce_dpm.soft_min_clk = 0; cz_hwmgr->vce_dpm.hard_min_clk = 0; - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel); - level = smum_get_argument(hwmgr->smumgr); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel); + level = smum_get_argument(hwmgr); if (level < table->count) clock = table->entries[level].ecclk; @@ -649,8 +639,7 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input, return 0; } -static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int cz_init_acp_limit(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct phm_acp_clock_voltage_dependency_table *table = @@ -663,8 +652,8 @@ static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input, cz_hwmgr->acp_dpm.soft_min_clk = 0; cz_hwmgr->acp_dpm.hard_min_clk = 0; - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel); - level = smum_get_argument(hwmgr->smumgr); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel); + level = smum_get_argument(hwmgr); if (level < table->count) clock = table->entries[level].acpclk; @@ -676,8 +665,7 @@ static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input, return 0; } -static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -686,22 +674,16 @@ static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input, cz_hwmgr->samu_power_gated = false; cz_hwmgr->acp_power_gated = false; cz_hwmgr->pgacpinit = true; - - return 0; } -static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); cz_hwmgr->low_sclk_interrupt_threshold = 0; - - return 0; } -static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) + +static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct phm_clock_voltage_dependency_table *table = @@ -727,7 +709,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr, if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) { cz_hwmgr->sclk_dpm.hard_min_clk = clock; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkHardMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.hard_min_clk, @@ -753,7 +735,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr, if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) { cz_hwmgr->sclk_dpm.soft_min_clk = clock; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_min_clk, @@ -764,7 +746,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr, PHM_PlatformCaps_StablePState) && cz_hwmgr->sclk_dpm.soft_max_clk != clock) { cz_hwmgr->sclk_dpm.soft_max_clk = clock; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMax, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_max_clk, @@ -774,9 +756,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr, return 0; } -static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { @@ -786,7 +766,7 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr, PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetMinDeepSleepSclk, clks); } @@ -794,77 +774,84 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr, return 0; } -static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWatermarkFrequency, cz_hwmgr->sclk_dpm.soft_max_clk); return 0; } -static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock) { + struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend); + + if (hw_data->is_nb_dpm_enabled) { + if (enable) { + PP_DBG_LOG("enable Low Memory PState.\n"); + + return smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_EnableLowMemoryPstate, + (lock ? 1 : 0)); + } else { + PP_DBG_LOG("disable Low Memory PState.\n"); + + return smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_DisableLowMemoryPstate, + (lock ? 1 : 0)); + } + } + return 0; } - -static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr) { int ret = 0; struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); unsigned long dpm_features = 0; - if (!cz_hwmgr->is_nb_dpm_enabled) { - PP_DBG_LOG("enabling ALL SMU features.\n"); + if (cz_hwmgr->is_nb_dpm_enabled) { + cz_nbdpm_pstate_enable_disable(hwmgr, true, true); dpm_features |= NB_DPM_MASK; ret = smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, - PPSMC_MSG_EnableAllSmuFeatures, + hwmgr, + PPSMC_MSG_DisableAllSmuFeatures, dpm_features); if (ret == 0) - cz_hwmgr->is_nb_dpm_enabled = true; + cz_hwmgr->is_nb_dpm_enabled = false; } return ret; } -static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock) +static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr) { - struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend); - - if (hw_data->is_nb_dpm_enabled) { - if (enable) { - PP_DBG_LOG("enable Low Memory PState.\n"); + int ret = 0; - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_EnableLowMemoryPstate, - (lock ? 1 : 0)); - } else { - PP_DBG_LOG("disable Low Memory PState.\n"); + struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); + unsigned long dpm_features = 0; - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_DisableLowMemoryPstate, - (lock ? 1 : 0)); - } + if (!cz_hwmgr->is_nb_dpm_enabled) { + PP_DBG_LOG("enabling ALL SMU features.\n"); + dpm_features |= NB_DPM_MASK; + ret = smum_send_msg_to_smc_with_parameter( + hwmgr, + PPSMC_MSG_EnableAllSmuFeatures, + dpm_features); + if (ret == 0) + cz_hwmgr->is_nb_dpm_enabled = true; } - return 0; + return ret; } -static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int cz_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input) { bool disable_switch; bool enable_low_mem_state; @@ -886,64 +873,64 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr, return 0; } -static const struct phm_master_table_item cz_set_power_state_list[] = { - { .tableFunction = cz_tf_update_sclk_limit }, - { .tableFunction = cz_tf_set_deep_sleep_sclk_threshold }, - { .tableFunction = cz_tf_set_watermark_threshold }, - { .tableFunction = cz_tf_set_enabled_levels }, - { .tableFunction = cz_tf_enable_nb_dpm }, - { .tableFunction = cz_tf_update_low_mem_pstate }, - { } -}; +static int cz_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) +{ + int ret = 0; -static const struct phm_master_table_header cz_set_power_state_master = { - 0, - PHM_MasterTableFlag_None, - cz_set_power_state_list -}; + cz_update_sclk_limit(hwmgr); + cz_set_deep_sleep_sclk_threshold(hwmgr); + cz_set_watermark_threshold(hwmgr); + ret = cz_enable_nb_dpm(hwmgr); + if (ret) + return ret; + cz_update_low_mem_pstate(hwmgr, input); -static const struct phm_master_table_item cz_setup_asic_list[] = { - { .tableFunction = cz_tf_reset_active_process_mask }, - { .tableFunction = cz_tf_upload_pptable_to_smu }, - { .tableFunction = cz_tf_init_sclk_limit }, - { .tableFunction = cz_tf_init_uvd_limit }, - { .tableFunction = cz_tf_init_vce_limit }, - { .tableFunction = cz_tf_init_acp_limit }, - { .tableFunction = cz_tf_init_power_gate_state }, - { .tableFunction = cz_tf_init_sclk_threshold }, - { } + return 0; }; -static const struct phm_master_table_header cz_setup_asic_master = { - 0, - PHM_MasterTableFlag_None, - cz_setup_asic_list -}; -static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int cz_setup_asic_task(struct pp_hwmgr *hwmgr) +{ + int ret; + + ret = cz_upload_pptable_to_smu(hwmgr); + if (ret) + return ret; + ret = cz_init_sclk_limit(hwmgr); + if (ret) + return ret; + ret = cz_init_uvd_limit(hwmgr); + if (ret) + return ret; + ret = cz_init_vce_limit(hwmgr); + if (ret) + return ret; + ret = cz_init_acp_limit(hwmgr); + if (ret) + return ret; + + cz_init_power_gate_state(hwmgr); + cz_init_sclk_threshold(hwmgr); + + return 0; +} + +static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend); + hw_data->disp_clk_bypass_pending = false; hw_data->disp_clk_bypass = false; - - return 0; } -static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend); - hw_data->is_nb_dpm_enabled = false; - return 0; + hw_data->is_nb_dpm_enabled = false; } -static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend); @@ -951,63 +938,73 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr, hw_data->cc6_settings.cpu_pstate_separation_time = 0; hw_data->cc6_settings.cpu_cc6_disable = false; hw_data->cc6_settings.cpu_pstate_disable = false; - - return 0; } -static const struct phm_master_table_item cz_power_down_asic_list[] = { - { .tableFunction = cz_tf_power_up_display_clock_sys_pll }, - { .tableFunction = cz_tf_clear_nb_dpm_flag }, - { .tableFunction = cz_tf_reset_cc6_data }, - { } -}; - -static const struct phm_master_table_header cz_power_down_asic_master = { - 0, - PHM_MasterTableFlag_None, - cz_power_down_asic_list +static int cz_power_off_asic(struct pp_hwmgr *hwmgr) +{ + cz_power_up_display_clock_sys_pll(hwmgr); + cz_clear_nb_dpm_flag(hwmgr); + cz_reset_cc6_data(hwmgr); + return 0; }; -static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static void cz_program_voting_clients(struct pp_hwmgr *hwmgr) { PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0); - return 0; } -static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output, - void *storage, int result) +static void cz_clear_voting_clients(struct pp_hwmgr *hwmgr) +{ + PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, 0); +} + +static int cz_start_dpm(struct pp_hwmgr *hwmgr) { - int res = 0xff; + int ret = 0; struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); unsigned long dpm_features = 0; cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled; dpm_features |= SCLK_DPM_MASK; - res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, dpm_features); - return res; + return ret; } -static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int cz_stop_dpm(struct pp_hwmgr *hwmgr) +{ + int ret = 0; + struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); + unsigned long dpm_features = 0; + + if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) { + dpm_features |= SCLK_DPM_MASK; + cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled; + ret = smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_DisableAllSmuFeatures, + dpm_features); + } + return ret; +} + +static int cz_program_bootup_state(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock; cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_min_clk, PPSMC_MSG_SetSclkSoftMin)); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMax, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_max_clk, @@ -1016,13 +1013,11 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input, return 0; } -static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); cz_hwmgr->acp_boot_level = 0xff; - return 0; } static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr, @@ -1031,67 +1026,52 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr, int result; unsigned long features; - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0); + result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0); if (result == 0) { - features = smum_get_argument(hwmgr->smumgr); + features = smum_get_argument(hwmgr); if (features & check_feature) return true; } - return result; + return false; } -static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static bool cz_check_for_dpm_enabled(struct pp_hwmgr *hwmgr) { if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn)) - return PP_Result_TableImmediateExit; - return 0; + return true; + return false; } -static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int cz_disable_dpm_tasks(struct pp_hwmgr *hwmgr) { - /* TO DO */ - return 0; -} + if (!cz_check_for_dpm_enabled(hwmgr)) { + pr_info("dpm has been disabled\n"); + return 0; + } + cz_disable_nb_dpm(hwmgr); -static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) -{ - if (!cz_dpm_check_smu_features(hwmgr, - SMU_EnabledFeatureScoreboard_SclkDpmOn)) - return PP_Result_TableImmediateExit; - return 0; -} + cz_clear_voting_clients(hwmgr); + if (cz_stop_dpm(hwmgr)) + return -EINVAL; -static const struct phm_master_table_item cz_disable_dpm_list[] = { - { .tableFunction = cz_tf_check_for_dpm_enabled }, - { }, + return 0; }; +static int cz_enable_dpm_tasks(struct pp_hwmgr *hwmgr) +{ + if (cz_check_for_dpm_enabled(hwmgr)) { + pr_info("dpm has been enabled\n"); + return 0; + } -static const struct phm_master_table_header cz_disable_dpm_master = { - 0, - PHM_MasterTableFlag_None, - cz_disable_dpm_list -}; - -static const struct phm_master_table_item cz_enable_dpm_list[] = { - { .tableFunction = cz_tf_check_for_dpm_disabled }, - { .tableFunction = cz_tf_program_voting_clients }, - { .tableFunction = cz_tf_start_dpm }, - { .tableFunction = cz_tf_program_bootup_state }, - { .tableFunction = cz_tf_enable_didt }, - { .tableFunction = cz_tf_reset_acp_boot_level }, - { }, -}; + cz_program_voting_clients(hwmgr); + if (cz_start_dpm(hwmgr)) + return -EINVAL; + cz_program_bootup_state(hwmgr); + cz_reset_acp_boot_level(hwmgr); -static const struct phm_master_table_header cz_enable_dpm_master = { - 0, - PHM_MasterTableFlag_None, - cz_enable_dpm_list + return 0; }; static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, @@ -1138,7 +1118,11 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, cz_ps->action = cz_current_ps->action; - if (!force_high && (cz_ps->action == FORCE_HIGH)) + if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + cz_nbdpm_pstate_enable_disable(hwmgr, false, false); + else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) + cz_nbdpm_pstate_enable_disable(hwmgr, false, true); + else if (!force_high && (cz_ps->action == FORCE_HIGH)) cz_ps->action = CANCEL_FORCE_HIGH; else if (force_high && (cz_ps->action != FORCE_HIGH)) cz_ps->action = FORCE_HIGH; @@ -1173,62 +1157,16 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr) cz_construct_boot_state(hwmgr); - result = phm_construct_table(hwmgr, &cz_setup_asic_master, - &(hwmgr->setup_asic)); - if (result != 0) { - pr_err("Fail to construct setup ASIC\n"); - return result; - } - - result = phm_construct_table(hwmgr, &cz_power_down_asic_master, - &(hwmgr->power_down_asic)); - if (result != 0) { - pr_err("Fail to construct power down ASIC\n"); - return result; - } - - result = phm_construct_table(hwmgr, &cz_disable_dpm_master, - &(hwmgr->disable_dynamic_state_management)); - if (result != 0) { - pr_err("Fail to disable_dynamic_state\n"); - return result; - } - result = phm_construct_table(hwmgr, &cz_enable_dpm_master, - &(hwmgr->enable_dynamic_state_management)); - if (result != 0) { - pr_err("Fail to enable_dynamic_state\n"); - return result; - } - result = phm_construct_table(hwmgr, &cz_set_power_state_master, - &(hwmgr->set_power_state)); - if (result != 0) { - pr_err("Fail to construct set_power_state\n"); - return result; - } hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = CZ_MAX_HARDWARE_POWERLEVELS; - result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings)); - if (result != 0) { - pr_err("Fail to construct enable_clock_power_gatings\n"); - return result; - } return result; } static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { if (hwmgr != NULL) { - phm_destroy_table(hwmgr, &(hwmgr->enable_clock_power_gatings)); - phm_destroy_table(hwmgr, &(hwmgr->set_power_state)); - phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management)); - phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management)); - phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); - phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); - - if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - } + kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; kfree(hwmgr->backend); hwmgr->backend = NULL; @@ -1240,13 +1178,13 @@ static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_max_clk, PPSMC_MSG_SetSclkSoftMin)); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMax, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_max_clk, @@ -1278,13 +1216,13 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) cz_hwmgr->sclk_dpm.soft_max_clk = clock; cz_hwmgr->sclk_dpm.hard_max_clk = clock; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_min_clk, PPSMC_MSG_SetSclkSoftMin)); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMax, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_max_clk, @@ -1297,13 +1235,13 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMax, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_min_clk, PPSMC_MSG_SetSclkSoftMax)); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_min_clk, @@ -1312,106 +1250,25 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) return 0; } -static int cz_phm_force_dpm_sclk(struct pp_hwmgr *hwmgr, uint32_t sclk) -{ - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetSclkSoftMin, - cz_get_sclk_level(hwmgr, - sclk, - PPSMC_MSG_SetSclkSoftMin)); - - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetSclkSoftMax, - cz_get_sclk_level(hwmgr, - sclk, - PPSMC_MSG_SetSclkSoftMax)); - return 0; -} - -static int cz_get_profiling_clk(struct pp_hwmgr *hwmgr, uint32_t *sclk) -{ - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - int32_t tmp_sclk; - int32_t count; - - tmp_sclk = table->entries[table->count-1].clk * 70 / 100; - - for (count = table->count-1; count >= 0; count--) { - if (tmp_sclk >= table->entries[count].clk) { - tmp_sclk = table->entries[count].clk; - *sclk = tmp_sclk; - break; - } - } - if (count < 0) - *sclk = table->entries[0].clk; - - return 0; -} - static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) { - uint32_t sclk = 0; int ret = 0; - uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; - - if (level == hwmgr->dpm_level) - return ret; - - if (!(hwmgr->dpm_level & profile_mode_mask)) { - /* enter profile mode, save current level, disable gfx cg*/ - if (level & profile_mode_mask) { - hwmgr->saved_dpm_level = hwmgr->dpm_level; - cgs_set_clockgating_state(hwmgr->device, - AMD_IP_BLOCK_TYPE_GFX, - AMD_CG_STATE_UNGATE); - } - } else { - /* exit profile mode, restore level, enable gfx cg*/ - if (!(level & profile_mode_mask)) { - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) - level = hwmgr->saved_dpm_level; - cgs_set_clockgating_state(hwmgr->device, - AMD_IP_BLOCK_TYPE_GFX, - AMD_CG_STATE_GATE); - } - } switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: ret = cz_phm_force_dpm_highest(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_LOW: case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: ret = cz_phm_force_dpm_lowest(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_AUTO: ret = cz_phm_unforce_dpm_levels(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; - break; - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: - ret = cz_get_profiling_clk(hwmgr, &sclk); - if (ret) - return ret; - hwmgr->dpm_level = level; - cz_phm_force_dpm_sclk(hwmgr, sclk); break; case AMD_DPM_FORCED_LEVEL_MANUAL: - hwmgr->dpm_level = level; - break; case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: default: break; @@ -1424,7 +1281,7 @@ int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF); return 0; } @@ -1436,11 +1293,11 @@ int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDynamicPowerGating)) { return smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_UVDPowerON, 1); } else { return smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_UVDPowerON, 0); } } @@ -1457,11 +1314,12 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) if (!bgate) { /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { + PHM_PlatformCaps_StablePState) + || hwmgr->en_umd_pstate) { cz_hwmgr->uvd_dpm.hard_min_clk = ptable->entries[ptable->count - 1].vclk; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetUvdHardMin, cz_get_uvd_level(hwmgr, cz_hwmgr->uvd_dpm.hard_min_clk, @@ -1486,11 +1344,12 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { + PHM_PlatformCaps_StablePState) + || hwmgr->en_umd_pstate) { cz_hwmgr->vce_dpm.hard_min_clk = ptable->entries[ptable->count - 1].ecclk; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetEclkHardMin, cz_get_eclk_level(hwmgr, cz_hwmgr->vce_dpm.hard_min_clk, @@ -1498,15 +1357,15 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) } else { /*Program HardMin based on the vce_arbiter.ecclk */ if (hwmgr->vce_arbiter.ecclk == 0) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetEclkHardMin, 0); /* disable ECLK DPM 0. Otherwise VCE could hang if * switching SCLK from DPM 0 to 6/7 */ - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetEclkSoftMin, 1); } else { cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetEclkHardMin, cz_get_eclk_level(hwmgr, cz_hwmgr->vce_dpm.hard_min_clk, @@ -1520,7 +1379,7 @@ int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_VCEPowerOFF); return 0; } @@ -1529,19 +1388,19 @@ int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_VCEPowerON); return 0; } -static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); return cz_hwmgr->sys_info.bootup_uma_clock; } -static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { struct pp_power_state *ps; struct cz_power_state *cz_ps; @@ -1679,7 +1538,7 @@ static void cz_hw_print_display_cfg( PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n", data); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDisplaySizePowerParams, data); } @@ -1744,10 +1603,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr, switch (type) { case PP_SCLK: - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMin, mask); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMax, mask); break; @@ -1989,7 +1848,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, *((uint32_t *)value) = 0; return 0; case AMDGPU_PP_SENSOR_GPU_LOAD: - result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity); + result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity); if (0 == result) { activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0); activity_percent = activity_percent > 100 ? 100 : activity_percent; @@ -2015,7 +1874,6 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, static const struct pp_hwmgr_func cz_hwmgr_funcs = { .backend_init = cz_hwmgr_backend_init, .backend_fini = cz_hwmgr_backend_fini, - .asic_setup = NULL, .apply_state_adjust_rules = cz_apply_state_adjust_rules, .force_dpm_level = cz_dpm_force_dpm_level, .get_power_state_size = cz_get_power_state_size, @@ -2037,6 +1895,11 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = { .get_clock_by_type = cz_get_clock_by_type, .get_max_high_clocks = cz_get_max_high_clocks, .read_sensor = cz_read_sensor, + .power_off_asic = cz_power_off_asic, + .asic_setup = cz_setup_asic_task, + .dynamic_state_management_enable = cz_enable_dpm_tasks, + .power_state_set = cz_set_power_state_tasks, + .dynamic_state_management_disable = cz_disable_dpm_tasks, }; int cz_init_function_pointers(struct pp_hwmgr *hwmgr) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c deleted file mode 100644 index bc7d8bd7e7cb..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include "hwmgr.h" - -static int phm_run_table(struct pp_hwmgr *hwmgr, - struct phm_runtime_table_header *rt_table, - void *input, - void *output, - void *temp_storage) -{ - int result = 0; - phm_table_function *function; - - if (rt_table->function_list == NULL) { - pr_debug("this function not implement!\n"); - return 0; - } - - for (function = rt_table->function_list; NULL != *function; function++) { - int tmp = (*function)(hwmgr, input, output, temp_storage, result); - - if (tmp == PP_Result_TableImmediateExit) - break; - if (tmp) { - if (0 == result) - result = tmp; - if (rt_table->exit_error) - break; - } - } - - return result; -} - -int phm_dispatch_table(struct pp_hwmgr *hwmgr, - struct phm_runtime_table_header *rt_table, - void *input, void *output) -{ - int result; - void *temp_storage; - - if (hwmgr == NULL || rt_table == NULL) { - pr_err("Invalid Parameter!\n"); - return -EINVAL; - } - - if (0 != rt_table->storage_size) { - temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL); - if (temp_storage == NULL) { - pr_err("Could not allocate table temporary storage\n"); - return -ENOMEM; - } - } else { - temp_storage = NULL; - } - - result = phm_run_table(hwmgr, rt_table, input, output, temp_storage); - - kfree(temp_storage); - - return result; -} - -int phm_construct_table(struct pp_hwmgr *hwmgr, - const struct phm_master_table_header *master_table, - struct phm_runtime_table_header *rt_table) -{ - uint32_t function_count = 0; - const struct phm_master_table_item *table_item; - uint32_t size; - phm_table_function *run_time_list; - phm_table_function *rtf; - - if (hwmgr == NULL || master_table == NULL || rt_table == NULL) { - pr_err("Invalid Parameter!\n"); - return -EINVAL; - } - - for (table_item = master_table->master_list; - NULL != table_item->tableFunction; table_item++) { - if ((NULL == table_item->isFunctionNeededInRuntimeTable) || - (table_item->isFunctionNeededInRuntimeTable(hwmgr))) - function_count++; - } - - size = (function_count + 1) * sizeof(phm_table_function); - run_time_list = kzalloc(size, GFP_KERNEL); - - if (NULL == run_time_list) - return -ENOMEM; - - rtf = run_time_list; - for (table_item = master_table->master_list; - NULL != table_item->tableFunction; table_item++) { - if ((rtf - run_time_list) > function_count) { - pr_err("Check function results have changed\n"); - kfree(run_time_list); - return -EINVAL; - } - - if ((NULL == table_item->isFunctionNeededInRuntimeTable) || - (table_item->isFunctionNeededInRuntimeTable(hwmgr))) { - *(rtf++) = table_item->tableFunction; - } - } - - if ((rtf - run_time_list) > function_count) { - pr_err("Check function results have changed\n"); - kfree(run_time_list); - return -EINVAL; - } - - *rtf = NULL; - rt_table->function_list = run_time_list; - rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError)); - rt_table->storage_size = master_table->storage_size; - return 0; -} - -int phm_destroy_table(struct pp_hwmgr *hwmgr, - struct phm_runtime_table_header *rt_table) -{ - if (hwmgr == NULL || rt_table == NULL) { - pr_err("Invalid Parameter\n"); - return -EINVAL; - } - - if (NULL == rt_table->function_list) - return 0; - - kfree(rt_table->function_list); - - rt_table->function_list = NULL; - rt_table->storage_size = 0; - rt_table->exit_error = false; - - return 0; -} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c index fcc722ea7649..623cff90233d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c @@ -26,35 +26,22 @@ #include "hardwaremanager.h" #include "power_state.h" + +#define TEMP_RANGE_MIN (0) +#define TEMP_RANGE_MAX (80 * 1000) + #define PHM_FUNC_CHECK(hw) \ do { \ if ((hw) == NULL || (hw)->hwmgr_func == NULL) \ return -EINVAL; \ } while (0) -bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr) -{ - return hwmgr->block_hw_access; -} - -int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block) -{ - hwmgr->block_hw_access = block; - return 0; -} - int phm_setup_asic(struct pp_hwmgr *hwmgr) { PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (NULL != hwmgr->hwmgr_func->asic_setup) - return hwmgr->hwmgr_func->asic_setup(hwmgr); - } else { - return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic), - NULL, NULL); - } + if (NULL != hwmgr->hwmgr_func->asic_setup) + return hwmgr->hwmgr_func->asic_setup(hwmgr); return 0; } @@ -63,14 +50,8 @@ int phm_power_down_asic(struct pp_hwmgr *hwmgr) { PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (NULL != hwmgr->hwmgr_func->power_off_asic) - return hwmgr->hwmgr_func->power_off_asic(hwmgr); - } else { - return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic), - NULL, NULL); - } + if (NULL != hwmgr->hwmgr_func->power_off_asic) + return hwmgr->hwmgr_func->power_off_asic(hwmgr); return 0; } @@ -86,13 +67,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr, states.pcurrent_state = pcurrent_state; states.pnew_state = pnew_power_state; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (NULL != hwmgr->hwmgr_func->power_state_set) - return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); - } else { - return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL); - } + if (NULL != hwmgr->hwmgr_func->power_state_set) + return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); return 0; } @@ -103,15 +79,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) bool enabled; PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) - ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); - } else { - ret = phm_dispatch_table(hwmgr, - &(hwmgr->enable_dynamic_state_management), - NULL, NULL); - } + if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) + ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); enabled = ret == 0; @@ -127,15 +96,8 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (hwmgr->hwmgr_func->dynamic_state_management_disable) - ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); - } else { - ret = phm_dispatch_table(hwmgr, - &(hwmgr->disable_dynamic_state_management), - NULL, NULL); - } + if (hwmgr->hwmgr_func->dynamic_state_management_disable) + ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); enabled = ret == 0 ? false : true; @@ -193,35 +155,13 @@ int phm_powerdown_uvd(struct pp_hwmgr *hwmgr) return 0; } -int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->powergate_uvd != NULL) - return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); - return 0; -} - -int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate) -{ - PHM_FUNC_CHECK(hwmgr); - - if (hwmgr->hwmgr_func->powergate_vce != NULL) - return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); - return 0; -} - int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr) { PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) - return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); - } else { - return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL); - } + if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) + return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); + return 0; } @@ -229,11 +169,9 @@ int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr) { PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) - return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); - } + if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) + return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); + return 0; } @@ -242,12 +180,9 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) { PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) { - if (NULL != hwmgr->hwmgr_func->display_config_changed) - hwmgr->hwmgr_func->display_config_changed(hwmgr); - } else - return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL); + if (NULL != hwmgr->hwmgr_func->display_config_changed) + hwmgr->hwmgr_func->display_config_changed(hwmgr); + return 0; } @@ -255,9 +190,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) { PHM_FUNC_CHECK(hwmgr); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface)) - if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) + if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); return 0; @@ -277,10 +210,10 @@ int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info) { PHM_FUNC_CHECK(hwmgr); - if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL) - return -EINVAL; + if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL) + return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info); - return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info); + return 0; } /** @@ -292,7 +225,21 @@ int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info) */ int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range) { - return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL); + struct PP_TemperatureRange range; + + if (temperature_range == NULL) { + range.max = TEMP_RANGE_MAX; + range.min = TEMP_RANGE_MIN; + } else { + range.max = temperature_range->max; + range.min = temperature_range->min; + } + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ThermalController) + && hwmgr->hwmgr_func->start_thermal_controller != NULL) + return hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range); + + return 0; } @@ -323,6 +270,9 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr, int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, const struct amd_pp_display_configuration *display_config) { + int index = 0; + int number_of_active_display = 0; + PHM_FUNC_CHECK(hwmgr); if (display_config == NULL) @@ -330,6 +280,17 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, hwmgr->display_config = *display_config; + if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk) + hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk); + + for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) { + if (hwmgr->display_config.displays[index].controller_id != 0) + number_of_active_display++; + } + + if (NULL != hwmgr->hwmgr_func->set_active_display_count) + hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display); + if (hwmgr->hwmgr_func->store_cc6_data == NULL) return -EINVAL; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 9547f265a8bb..35e80c969737 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -26,8 +26,8 @@ #include <linux/kernel.h> #include <linux/slab.h> #include <linux/types.h> +#include <linux/pci.h> #include <drm/amdgpu_drm.h> -#include "cgs_common.h" #include "power_state.h" #include "hwmgr.h" #include "pppcielanes.h" @@ -35,21 +35,100 @@ #include "ppsmc.h" #include "pp_acpi.h" #include "amd_acpi.h" +#include "pp_psm.h" -extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr); +extern const struct pp_smumgr_func ci_smu_funcs; +extern const struct pp_smumgr_func cz_smu_funcs; +extern const struct pp_smumgr_func iceland_smu_funcs; +extern const struct pp_smumgr_func tonga_smu_funcs; +extern const struct pp_smumgr_func fiji_smu_funcs; +extern const struct pp_smumgr_func polaris10_smu_funcs; +extern const struct pp_smumgr_func vega10_smu_funcs; +extern const struct pp_smumgr_func rv_smu_funcs; +extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr); static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr); static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr); static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr); static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr); static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr); static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr); +static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr); uint8_t convert_to_vid(uint16_t vddc) { return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); } +static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr, + struct cgs_system_info *sys_info) +{ + sys_info->size = sizeof(struct cgs_system_info); + sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN; + + return cgs_query_system_info(hwmgr->device, sys_info); +} + +static int phm_thermal_l2h_irq(void *private_data, + unsigned src_id, const uint32_t *iv_entry) +{ + struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data; + struct cgs_system_info sys_info = {0}; + int result; + + result = phm_get_pci_bus_devfn(hwmgr, &sys_info); + if (result) + return -EINVAL; + + pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n", + PCI_BUS_NUM(sys_info.value), + PCI_SLOT(sys_info.value), + PCI_FUNC(sys_info.value)); + return 0; +} + +static int phm_thermal_h2l_irq(void *private_data, + unsigned src_id, const uint32_t *iv_entry) +{ + struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data; + struct cgs_system_info sys_info = {0}; + int result; + + result = phm_get_pci_bus_devfn(hwmgr, &sys_info); + if (result) + return -EINVAL; + + pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n", + PCI_BUS_NUM(sys_info.value), + PCI_SLOT(sys_info.value), + PCI_FUNC(sys_info.value)); + return 0; +} + +static int phm_ctf_irq(void *private_data, + unsigned src_id, const uint32_t *iv_entry) +{ + struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data; + struct cgs_system_info sys_info = {0}; + int result; + + result = phm_get_pci_bus_devfn(hwmgr, &sys_info); + if (result) + return -EINVAL; + + pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n", + PCI_BUS_NUM(sys_info.value), + PCI_SLOT(sys_info.value), + PCI_FUNC(sys_info.value)); + return 0; +} + +static const struct cgs_irq_src_funcs thermal_irq_src[3] = { + { .handler = phm_thermal_l2h_irq }, + { .handler = phm_thermal_h2l_irq }, + { .handler = phm_ctf_irq } +}; + int hwmgr_early_init(struct pp_instance *handle) { struct pp_hwmgr *hwmgr; @@ -62,7 +141,6 @@ int hwmgr_early_init(struct pp_instance *handle) return -ENOMEM; handle->hwmgr = hwmgr; - hwmgr->smumgr = handle->smu_mgr; hwmgr->device = handle->device; hwmgr->chip_family = handle->chip_family; hwmgr->chip_id = handle->chip_id; @@ -73,24 +151,38 @@ int hwmgr_early_init(struct pp_instance *handle) hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; hwmgr_init_default_caps(hwmgr); hwmgr_set_user_specify_caps(hwmgr); + hwmgr->fan_ctrl_is_in_default_mode = true; + hwmgr->reload_fw = 1; switch (hwmgr->chip_family) { + case AMDGPU_FAMILY_CI: + hwmgr->smumgr_funcs = &ci_smu_funcs; + ci_set_asic_special_caps(hwmgr); + hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | + PP_ENABLE_GFX_CG_THRU_SMU); + hwmgr->pp_table_version = PP_TABLE_V0; + smu7_init_function_pointers(hwmgr); + break; case AMDGPU_FAMILY_CZ: + hwmgr->smumgr_funcs = &cz_smu_funcs; cz_init_function_pointers(hwmgr); break; case AMDGPU_FAMILY_VI: switch (hwmgr->chip_id) { case CHIP_TOPAZ: + hwmgr->smumgr_funcs = &iceland_smu_funcs; topaz_set_asic_special_caps(hwmgr); hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); hwmgr->pp_table_version = PP_TABLE_V0; break; case CHIP_TONGA: + hwmgr->smumgr_funcs = &tonga_smu_funcs; tonga_set_asic_special_caps(hwmgr); hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; break; case CHIP_FIJI: + hwmgr->smumgr_funcs = &fiji_smu_funcs; fiji_set_asic_special_caps(hwmgr); hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); @@ -98,6 +190,7 @@ int hwmgr_early_init(struct pp_instance *handle) case CHIP_POLARIS11: case CHIP_POLARIS10: case CHIP_POLARIS12: + hwmgr->smumgr_funcs = &polaris10_smu_funcs; polaris_set_asic_special_caps(hwmgr); hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); break; @@ -109,6 +202,7 @@ int hwmgr_early_init(struct pp_instance *handle) case AMDGPU_FAMILY_AI: switch (hwmgr->chip_id) { case CHIP_VEGA10: + hwmgr->smumgr_funcs = &vega10_smu_funcs; vega10_hwmgr_init(hwmgr); break; default: @@ -118,6 +212,7 @@ int hwmgr_early_init(struct pp_instance *handle) case AMDGPU_FAMILY_RV: switch (hwmgr->chip_id) { case CHIP_RAVEN: + hwmgr->smumgr_funcs = &rv_smu_funcs; rv_init_function_pointers(hwmgr); break; default: @@ -131,80 +226,6 @@ int hwmgr_early_init(struct pp_instance *handle) return 0; } -static int hw_init_power_state_table(struct pp_hwmgr *hwmgr) -{ - int result; - unsigned int i; - unsigned int table_entries; - struct pp_power_state *state; - int size; - - if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL) - return -EINVAL; - - if (hwmgr->hwmgr_func->get_power_state_size == NULL) - return -EINVAL; - - hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr); - - hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) + - sizeof(struct pp_power_state); - - hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL); - if (hwmgr->ps == NULL) - return -ENOMEM; - - hwmgr->request_ps = kzalloc(size, GFP_KERNEL); - if (hwmgr->request_ps == NULL) { - kfree(hwmgr->ps); - hwmgr->ps = NULL; - return -ENOMEM; - } - - hwmgr->current_ps = kzalloc(size, GFP_KERNEL); - if (hwmgr->current_ps == NULL) { - kfree(hwmgr->request_ps); - kfree(hwmgr->ps); - hwmgr->request_ps = NULL; - hwmgr->ps = NULL; - return -ENOMEM; - } - - state = hwmgr->ps; - - for (i = 0; i < table_entries; i++) { - result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state); - - if (state->classification.flags & PP_StateClassificationFlag_Boot) { - hwmgr->boot_ps = state; - memcpy(hwmgr->current_ps, state, size); - memcpy(hwmgr->request_ps, state, size); - } - - state->id = i + 1; /* assigned unique num for every power state id */ - - if (state->classification.flags & PP_StateClassificationFlag_Uvd) - hwmgr->uvd_ps = state; - state = (struct pp_power_state *)((unsigned long)state + size); - } - - return 0; -} - -static int hw_fini_power_state_table(struct pp_hwmgr *hwmgr) -{ - if (hwmgr == NULL) - return -EINVAL; - - kfree(hwmgr->current_ps); - kfree(hwmgr->request_ps); - kfree(hwmgr->ps); - hwmgr->request_ps = NULL; - hwmgr->ps = NULL; - hwmgr->current_ps = NULL; - return 0; -} - int hwmgr_hw_init(struct pp_instance *handle) { struct pp_hwmgr *hwmgr; @@ -228,9 +249,26 @@ int hwmgr_hw_init(struct pp_instance *handle) if (ret) goto err1; - ret = hw_init_power_state_table(hwmgr); + ret = psm_init_power_state_table(hwmgr); + if (ret) + goto err2; + + ret = phm_setup_asic(hwmgr); if (ret) goto err2; + + ret = phm_enable_dynamic_state_management(hwmgr); + if (ret) + goto err2; + ret = phm_start_thermal_controller(hwmgr, NULL); + ret |= psm_set_performance_states(hwmgr); + if (ret) + goto err2; + + ret = phm_register_thermal_interrupt(hwmgr, &thermal_irq_src); + if (ret) + goto err2; + return 0; err2: if (hwmgr->hwmgr_func->backend_fini) @@ -247,19 +285,138 @@ int hwmgr_hw_fini(struct pp_instance *handle) { struct pp_hwmgr *hwmgr; - if (handle == NULL) + if (handle == NULL || handle->hwmgr == NULL) return -EINVAL; hwmgr = handle->hwmgr; + phm_stop_thermal_controller(hwmgr); + psm_set_boot_states(hwmgr); + phm_display_configuration_changed(hwmgr); + psm_adjust_power_state_dynamic(hwmgr, false, NULL); + phm_disable_dynamic_state_management(hwmgr); + phm_disable_clock_power_gatings(hwmgr); + if (hwmgr->hwmgr_func->backend_fini) hwmgr->hwmgr_func->backend_fini(hwmgr); if (hwmgr->pptable_func->pptable_fini) hwmgr->pptable_func->pptable_fini(hwmgr); - return hw_fini_power_state_table(hwmgr); + return psm_fini_power_state_table(hwmgr); } +int hwmgr_hw_suspend(struct pp_instance *handle) +{ + struct pp_hwmgr *hwmgr; + int ret = 0; + + if (handle == NULL || handle->hwmgr == NULL) + return -EINVAL; + + hwmgr = handle->hwmgr; + phm_disable_smc_firmware_ctf(hwmgr); + ret = psm_set_boot_states(hwmgr); + if (ret) + return ret; + ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); + if (ret) + return ret; + ret = phm_power_down_asic(hwmgr); + + return ret; +} +int hwmgr_hw_resume(struct pp_instance *handle) +{ + struct pp_hwmgr *hwmgr; + int ret = 0; + + if (handle == NULL || handle->hwmgr == NULL) + return -EINVAL; + + hwmgr = handle->hwmgr; + ret = phm_setup_asic(hwmgr); + if (ret) + return ret; + + ret = phm_enable_dynamic_state_management(hwmgr); + if (ret) + return ret; + ret = phm_start_thermal_controller(hwmgr, NULL); + if (ret) + return ret; + + ret |= psm_set_performance_states(hwmgr); + if (ret) + return ret; + + ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); + + return ret; +} + +static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) +{ + switch (state) { + case POWER_STATE_TYPE_BATTERY: + return PP_StateUILabel_Battery; + case POWER_STATE_TYPE_BALANCED: + return PP_StateUILabel_Balanced; + case POWER_STATE_TYPE_PERFORMANCE: + return PP_StateUILabel_Performance; + default: + return PP_StateUILabel_None; + } +} + +int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id, + void *input, void *output) +{ + int ret = 0; + struct pp_hwmgr *hwmgr; + + if (handle == NULL || handle->hwmgr == NULL) + return -EINVAL; + + hwmgr = handle->hwmgr; + + switch (task_id) { + case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: + ret = phm_set_cpu_power_state(hwmgr); + if (ret) + return ret; + ret = psm_set_performance_states(hwmgr); + if (ret) + return ret; + ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); + break; + case AMD_PP_TASK_ENABLE_USER_STATE: + { + enum amd_pm_state_type ps; + enum PP_StateUILabel requested_ui_label; + struct pp_power_state *requested_ps = NULL; + + if (input == NULL) { + ret = -EINVAL; + break; + } + ps = *(unsigned long *)input; + + requested_ui_label = power_state_convert(ps); + ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps); + if (ret) + return ret; + ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps); + break; + } + case AMD_PP_TASK_COMPLETE_INIT: + case AMD_PP_TASK_READJUST_POWER_STATE: + ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); + break; + default: + break; + } + return ret; +} /** * Returns once the part of the register indicated by the mask has * reached the given value. @@ -294,7 +451,7 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, * reached the given value.The indirect space is described by giving * the memory-mapped index of the indirect index register. */ -void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, +int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, uint32_t indirect_port, uint32_t index, uint32_t value, @@ -302,14 +459,50 @@ void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, { if (hwmgr == NULL || hwmgr->device == NULL) { pr_err("Invalid Hardware Manager!"); - return; + return -EINVAL; } cgs_write_register(hwmgr->device, indirect_port, index); - phm_wait_on_register(hwmgr, indirect_port + 1, mask, value); + return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value); +} + +int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, + uint32_t index, + uint32_t value, uint32_t mask) +{ + uint32_t i; + uint32_t cur_value; + + if (hwmgr == NULL || hwmgr->device == NULL) + return -EINVAL; + + for (i = 0; i < hwmgr->usec_timeout; i++) { + cur_value = cgs_read_register(hwmgr->device, + index); + if ((cur_value & mask) != (value & mask)) + break; + udelay(1); + } + + /* timeout means wrong logic */ + if (i == hwmgr->usec_timeout) + return -ETIME; + return 0; } +int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr, + uint32_t indirect_port, + uint32_t index, + uint32_t value, + uint32_t mask) +{ + if (hwmgr == NULL || hwmgr->device == NULL) + return -EINVAL; + cgs_write_register(hwmgr->device, indirect_port, index); + return phm_wait_for_register_unequal(hwmgr, indirect_port + 1, + value, mask); +} bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr) { @@ -678,7 +871,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) for (i = 0; i < vddc_table->count; i++) { if (req_vddc <= vddc_table->entries[i].vddc) { req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VddC_Request, req_volt); return; } @@ -689,28 +882,8 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) { - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM); phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM); @@ -735,7 +908,6 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_FanSpeedInTableIsRPM); - return; } @@ -784,7 +956,8 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) { - + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EVV); phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); phm_cap_set(hwmgr->platform_descriptor.platformCaps, @@ -793,10 +966,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_AutomaticDCTransition); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - - if (hwmgr->chip_id != CHIP_POLARIS10) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SPLLShutdownSupport); @@ -814,6 +983,8 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) { + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EVV); phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); phm_cap_unset(hwmgr->platform_descriptor.platformCaps, @@ -822,15 +993,13 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_TDRamping); phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - return 0; } int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) { + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EVV); phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); phm_cap_unset(hwmgr->platform_descriptor.platformCaps, @@ -844,14 +1013,25 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_UVDPowerGating); phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating); + return 0; +} +int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) +{ phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - + PHM_PlatformCaps_EVV); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SQRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DBRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TDRamping); + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TCPRamping); return 0; } -int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) +int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr) { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); @@ -862,8 +1042,8 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); + PHM_PlatformCaps_MemorySpreadSpectrumSupport); phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_EVV); + PHM_PlatformCaps_EngineSpreadSpectrumSupport); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c new file mode 100644 index 000000000000..167cdc321db2 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c @@ -0,0 +1,246 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include "pp_psm.h" + +int psm_init_power_state_table(struct pp_hwmgr *hwmgr) +{ + int result; + unsigned int i; + unsigned int table_entries; + struct pp_power_state *state; + int size; + + if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL) + return -EINVAL; + + if (hwmgr->hwmgr_func->get_power_state_size == NULL) + return -EINVAL; + + hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr); + + hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) + + sizeof(struct pp_power_state); + + hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL); + if (hwmgr->ps == NULL) + return -ENOMEM; + + hwmgr->request_ps = kzalloc(size, GFP_KERNEL); + if (hwmgr->request_ps == NULL) { + kfree(hwmgr->ps); + hwmgr->ps = NULL; + return -ENOMEM; + } + + hwmgr->current_ps = kzalloc(size, GFP_KERNEL); + if (hwmgr->current_ps == NULL) { + kfree(hwmgr->request_ps); + kfree(hwmgr->ps); + hwmgr->request_ps = NULL; + hwmgr->ps = NULL; + return -ENOMEM; + } + + state = hwmgr->ps; + + for (i = 0; i < table_entries; i++) { + result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state); + + if (state->classification.flags & PP_StateClassificationFlag_Boot) { + hwmgr->boot_ps = state; + memcpy(hwmgr->current_ps, state, size); + memcpy(hwmgr->request_ps, state, size); + } + + state->id = i + 1; /* assigned unique num for every power state id */ + + if (state->classification.flags & PP_StateClassificationFlag_Uvd) + hwmgr->uvd_ps = state; + state = (struct pp_power_state *)((unsigned long)state + size); + } + + return 0; +} + +int psm_fini_power_state_table(struct pp_hwmgr *hwmgr) +{ + if (hwmgr == NULL) + return -EINVAL; + + kfree(hwmgr->current_ps); + kfree(hwmgr->request_ps); + kfree(hwmgr->ps); + hwmgr->request_ps = NULL; + hwmgr->ps = NULL; + hwmgr->current_ps = NULL; + return 0; +} + +static int psm_get_ui_state(struct pp_hwmgr *hwmgr, + enum PP_StateUILabel ui_label, + unsigned long *state_id) +{ + struct pp_power_state *state; + int table_entries; + int i; + + table_entries = hwmgr->num_ps; + state = hwmgr->ps; + + for (i = 0; i < table_entries; i++) { + if (state->classification.ui_label & ui_label) { + *state_id = state->id; + return 0; + } + state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); + } + return -EINVAL; +} + +static int psm_get_state_by_classification(struct pp_hwmgr *hwmgr, + enum PP_StateClassificationFlag flag, + unsigned long *state_id) +{ + struct pp_power_state *state; + int table_entries; + int i; + + table_entries = hwmgr->num_ps; + state = hwmgr->ps; + + for (i = 0; i < table_entries; i++) { + if (state->classification.flags & flag) { + *state_id = state->id; + return 0; + } + state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); + } + return -EINVAL; +} + +static int psm_set_states(struct pp_hwmgr *hwmgr, unsigned long state_id) +{ + struct pp_power_state *state; + int table_entries; + int i; + + table_entries = hwmgr->num_ps; + + state = hwmgr->ps; + + for (i = 0; i < table_entries; i++) { + if (state->id == state_id) { + memcpy(hwmgr->request_ps, state, hwmgr->ps_size); + return 0; + } + state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); + } + return -EINVAL; +} + +int psm_set_boot_states(struct pp_hwmgr *hwmgr) +{ + unsigned long state_id; + int ret = -EINVAL; + + if (!psm_get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot, + &state_id)) + ret = psm_set_states(hwmgr, state_id); + + return ret; +} + +int psm_set_performance_states(struct pp_hwmgr *hwmgr) +{ + unsigned long state_id; + int ret = -EINVAL; + + if (!psm_get_ui_state(hwmgr, PP_StateUILabel_Performance, + &state_id)) + ret = psm_set_states(hwmgr, state_id); + + return ret; +} + +int psm_set_user_performance_state(struct pp_hwmgr *hwmgr, + enum PP_StateUILabel label_id, + struct pp_power_state **state) +{ + int table_entries; + int i; + + table_entries = hwmgr->num_ps; + *state = hwmgr->ps; + +restart_search: + for (i = 0; i < table_entries; i++) { + if ((*state)->classification.ui_label & label_id) + return 0; + *state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size); + } + + switch (label_id) { + case PP_StateUILabel_Battery: + case PP_StateUILabel_Balanced: + label_id = PP_StateUILabel_Performance; + goto restart_search; + default: + break; + } + return -EINVAL; +} + +int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip, + struct pp_power_state *new_ps) +{ + struct pp_power_state *pcurrent; + struct pp_power_state *requested; + bool equal; + + if (skip) + return 0; + + if (new_ps != NULL) + requested = new_ps; + else + requested = hwmgr->request_ps; + + pcurrent = hwmgr->current_ps; + + phm_apply_state_adjust_rules(hwmgr, requested, pcurrent); + + if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr, + &pcurrent->hardware, &requested->hardware, &equal))) + equal = false; + + if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) { + phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware); + memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size); + } + return 0; +} + diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h index fbdff3e02aa3..fa1b6825036a 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,19 +20,21 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "eventmgr.h" -#include "eventinit.h" -#include "eventmanagement.h" -#include "eventmanager.h" -#include "power_state.h" -#include "hardwaremanager.h" -int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label, unsigned long *state_id); +#ifndef PP_PSM_H +#define PP_PSM_H -int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateClassificationFlag flag, unsigned long *state_id); +#include "hwmgr.h" -int psm_set_states(struct pp_eventmgr *eventmgr, unsigned long *state_id); +int psm_init_power_state_table(struct pp_hwmgr *hwmgr); +int psm_fini_power_state_table(struct pp_hwmgr *hwmgr); +int psm_set_boot_states(struct pp_hwmgr *hwmgr); +int psm_set_performance_states(struct pp_hwmgr *hwmgr); +int psm_set_user_performance_state(struct pp_hwmgr *hwmgr, + enum PP_StateUILabel label_id, + struct pp_power_state **state); +int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, + bool skip, + struct pp_power_state *new_ps); -int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip); - -int psm_adjust_power_state_static(struct pp_eventmgr *eventmgr, bool skip); +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c index 953e0c9ad7cd..a129bc5b1844 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c @@ -470,7 +470,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr) * SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ. * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE */ -bool atomctrl_is_voltage_controled_by_gpio_v3( +bool atomctrl_is_voltage_controlled_by_gpio_v3( struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode) @@ -1100,10 +1100,10 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, } } - PP_ASSERT_WITH_CODE(entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count, - "Can't find requested voltage id in vddc_dependency_on_sclk table!", + if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { + pr_debug("Can't find requested voltage id in vddc_dependency_on_sclk table!\n"); return -EINVAL; - ); + } get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC; get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; @@ -1418,3 +1418,83 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, return 0; } + +int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id) +{ + int result; + SET_VOLTAGE_PS_ALLOCATION allocation; + SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters = + (SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage; + + voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID; + + result = cgs_atom_exec_cmd_table(hwmgr->device, + GetIndexIntoMasterTable(COMMAND, SetVoltage), + voltage_parameters); + + *virtual_voltage_id = voltage_parameters->usVoltageLevel; + + return result; +} + +int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, + uint16_t *vddc, uint16_t *vddci, + uint16_t virtual_voltage_id, + uint16_t efuse_voltage_id) +{ + int i, j; + int ix; + u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; + ATOM_ASIC_PROFILING_INFO_V2_1 *profile; + + *vddc = 0; + *vddci = 0; + + ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); + + profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) + cgs_atom_get_data_table(hwmgr->device, + ix, + NULL, NULL, NULL); + if (!profile) + return -EINVAL; + + if ((profile->asHeader.ucTableFormatRevision >= 2) && + (profile->asHeader.ucTableContentRevision >= 1) && + (profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) { + leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset); + vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset); + vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset); + if (profile->ucElbVDDC_Num > 0) { + for (i = 0; i < profile->ucElbVDDC_Num; i++) { + if (vddc_id_buf[i] == virtual_voltage_id) { + for (j = 0; j < profile->ucLeakageBinNum; j++) { + if (efuse_voltage_id <= leakage_bin[j]) { + *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; + break; + } + } + break; + } + } + } + + vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset); + vddci_buf = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset); + if (profile->ucElbVDDCI_Num > 0) { + for (i = 0; i < profile->ucElbVDDCI_Num; i++) { + if (vddci_id_buf[i] == virtual_voltage_id) { + for (j = 0; j < profile->ucLeakageBinNum; j++) { + if (efuse_voltage_id <= leakage_bin[j]) { + *vddci = vddci_buf[j * profile->ucElbVDDC_Num + i]; + break; + } + } + break; + } + } + } + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h index e9fe2e84006b..c44a92064cf1 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h @@ -291,7 +291,7 @@ extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr); extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); -extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode); +extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode); extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table); extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); @@ -314,5 +314,11 @@ extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t *svd_gpio_id, uint8_t *svc_gpio_id, uint16_t *load_line); + +extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, + uint16_t *vddc, uint16_t *vddci, + uint16_t virtual_voltage_id, + uint16_t efuse_voltage_id); +extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id); #endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c index 84f01fd33aff..d1af1483c69b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c @@ -173,8 +173,6 @@ static int get_vddc_lookup_table( if (NULL == table) return -ENOMEM; - memset(table, 0x00, table_size); - table->count = vddc_lookup_pp_tables->ucNumEntries; for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) { @@ -335,8 +333,6 @@ static int get_valid_clk( if (NULL == table) return -ENOMEM; - memset(table, 0x00, table_size); - table->count = (uint32_t)clk_volt_pp_table->count; for (i = 0; i < table->count; i++) { @@ -390,8 +386,6 @@ static int get_mclk_voltage_dependency_table( if (NULL == mclk_table) return -ENOMEM; - memset(mclk_table, 0x00, table_size); - mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; for (i = 0; i < mclk_dep_table->ucNumEntries; i++) { @@ -439,8 +433,6 @@ static int get_sclk_voltage_dependency_table( if (NULL == sclk_table) return -ENOMEM; - memset(sclk_table, 0x00, table_size); - sclk_table->count = (uint32_t)tonga_table->ucNumEntries; for (i = 0; i < tonga_table->ucNumEntries; i++) { @@ -473,8 +465,6 @@ static int get_sclk_voltage_dependency_table( if (NULL == sclk_table) return -ENOMEM; - memset(sclk_table, 0x00, table_size); - sclk_table->count = (uint32_t)polaris_table->ucNumEntries; for (i = 0; i < polaris_table->ucNumEntries; i++) { @@ -525,8 +515,6 @@ static int get_pcie_table( if (pcie_table == NULL) return -ENOMEM; - memset(pcie_table, 0x00, table_size); - /* * Make sure the number of pcie entries are less than or equal to sclk dpm levels. * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1. @@ -567,8 +555,6 @@ static int get_pcie_table( if (pcie_table == NULL) return -ENOMEM; - memset(pcie_table, 0x00, table_size); - /* * Make sure the number of pcie entries are less than or equal to sclk dpm levels. * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1. @@ -615,8 +601,6 @@ static int get_cac_tdp_table( if (NULL == tdp_table) return -ENOMEM; - memset(tdp_table, 0x00, table_size); - hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); if (NULL == hwmgr->dyn_state.cac_dtp_table) { @@ -624,8 +608,6 @@ static int get_cac_tdp_table( return -ENOMEM; } - memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size); - if (table->ucRevId < 3) { const ATOM_Tonga_PowerTune_Table *tonga_table = (ATOM_Tonga_PowerTune_Table *)table; @@ -725,8 +707,6 @@ static int get_mm_clock_voltage_table( if (NULL == mm_table) return -ENOMEM; - memset(mm_table, 0x00, table_size); - mm_table->count = mm_dependency_table->ucNumEntries; for (i = 0; i < mm_dependency_table->ucNumEntries; i++) { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index 2716721e5453..485f7ebdc754 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c @@ -24,7 +24,7 @@ #include <linux/types.h> #include <linux/kernel.h> #include <linux/slab.h> - +#include <drm/amdgpu_drm.h> #include "processpptables.h" #include <atom-types.h> #include <atombios.h> @@ -790,6 +790,39 @@ static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2( return pstate; } +static unsigned char soft_dummy_pp_table[] = { + 0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 0x00, 0x6c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, + 0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x18, 0x05, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1, 0x00, 0x43, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x8e, 0x01, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c, + 0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x70, 0x00, 0x91, 0xf4, 0x00, + 0x64, 0x00, 0x40, 0x19, 0x01, 0x5a, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a, + 0x00, 0x00, 0x09, 0x30, 0x75, 0x00, 0x30, 0x75, 0x00, 0x40, 0x9c, 0x00, 0x40, 0x9c, 0x00, 0x59, + 0xd8, 0x00, 0x59, 0xd8, 0x00, 0x91, 0xf4, 0x00, 0x91, 0xf4, 0x00, 0x0e, 0x28, 0x01, 0x0e, 0x28, + 0x01, 0x90, 0x5f, 0x01, 0x90, 0x5f, 0x01, 0x00, 0x77, 0x01, 0x00, 0x77, 0x01, 0xca, 0x91, 0x01, + 0xca, 0x91, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01, + 0x7c, 0x00, 0x02, 0x70, 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a, + 0x00, 0x07, 0x08, 0x08, 0x00, 0x08, 0x00, 0x01, 0x02, 0x02, 0x02, 0x01, 0x02, 0x02, 0x02, 0x03, + 0x02, 0x04, 0x02, 0x00, 0x08, 0x40, 0x9c, 0x00, 0x30, 0x75, 0x00, 0x74, 0xb5, 0x00, 0xa0, 0x8c, + 0x00, 0x60, 0xea, 0x00, 0x74, 0xb5, 0x00, 0x0e, 0x28, 0x01, 0x60, 0xea, 0x00, 0x90, 0x5f, 0x01, + 0x40, 0x19, 0x01, 0xb2, 0xb0, 0x01, 0x90, 0x5f, 0x01, 0xc0, 0xd4, 0x01, 0x00, 0x77, 0x01, 0x5e, + 0xff, 0x01, 0xca, 0x91, 0x01, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01, 0x7c, 0x00, 0x02, 0x70, + 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a, 0x00, 0x07, 0x00, 0x08, + 0x80, 0x00, 0x30, 0x75, 0x00, 0x7e, 0x00, 0x40, 0x9c, 0x00, 0x7c, 0x00, 0x59, 0xd8, 0x00, 0x70, + 0x00, 0xdc, 0x0b, 0x01, 0x64, 0x00, 0x80, 0x38, 0x01, 0x5a, 0x00, 0x80, 0x38, 0x01, 0x52, 0x00, + 0x80, 0x38, 0x01, 0x4a, 0x00, 0x80, 0x38, 0x01, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c, + 0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x74, 0x00, 0x91, 0xf4, 0x00, + 0x66, 0x00, 0x40, 0x19, 0x01, 0x58, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a, + 0x00 +}; static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( struct pp_hwmgr *hwmgr) @@ -799,12 +832,17 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( uint16_t size; if (!table_addr) { - table_addr = cgs_atom_get_data_table(hwmgr->device, - GetIndexIntoMasterTable(DATA, PowerPlayInfo), - &size, &frev, &crev); - - hwmgr->soft_pp_table = table_addr; - hwmgr->soft_pp_table_size = size; + if (hwmgr->chip_id == CHIP_RAVEN) { + table_addr = &soft_dummy_pp_table[0]; + hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; + hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); + } else { + table_addr = cgs_atom_get_data_table(hwmgr->device, + GetIndexIntoMasterTable(DATA, PowerPlayInfo), + &size, &frev, &crev); + hwmgr->soft_pp_table = table_addr; + hwmgr->soft_pp_table_size = size; + } } return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr; @@ -924,15 +962,14 @@ int pp_tables_get_entry(struct pp_hwmgr *hwmgr, } } - if ((0 == result) && - (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot))) - result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware)); + if ((0 == result) && (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot))) { + if (hwmgr->chip_family < AMDGPU_FAMILY_RV) + result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware)); + } return result; } - - static int init_powerplay_tables( struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table @@ -1615,85 +1652,53 @@ static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) if (hwmgr->chip_id == CHIP_RAVEN) return 0; - if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) { - kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); - hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; - } + kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); + hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; - if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { - kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); - hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; - } + kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); + hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; - if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) { - kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); - hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; - } + kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); + hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; - if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { - kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); - hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; - } + kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); + hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; - if (NULL != hwmgr->dyn_state.valid_mclk_values) { - kfree(hwmgr->dyn_state.valid_mclk_values); - hwmgr->dyn_state.valid_mclk_values = NULL; - } + kfree(hwmgr->dyn_state.valid_mclk_values); + hwmgr->dyn_state.valid_mclk_values = NULL; - if (NULL != hwmgr->dyn_state.valid_sclk_values) { - kfree(hwmgr->dyn_state.valid_sclk_values); - hwmgr->dyn_state.valid_sclk_values = NULL; - } + kfree(hwmgr->dyn_state.valid_sclk_values); + hwmgr->dyn_state.valid_sclk_values = NULL; - if (NULL != hwmgr->dyn_state.cac_leakage_table) { - kfree(hwmgr->dyn_state.cac_leakage_table); - hwmgr->dyn_state.cac_leakage_table = NULL; - } + kfree(hwmgr->dyn_state.cac_leakage_table); + hwmgr->dyn_state.cac_leakage_table = NULL; - if (NULL != hwmgr->dyn_state.vddc_phase_shed_limits_table) { - kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); - hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; - } + kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); + hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; - if (NULL != hwmgr->dyn_state.vce_clock_voltage_dependency_table) { - kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); - hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; - } + kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); + hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; - if (NULL != hwmgr->dyn_state.uvd_clock_voltage_dependency_table) { - kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); - hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; - } + kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); + hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; - if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) { - kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); - hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; - } + kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); + hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; - if (NULL != hwmgr->dyn_state.acp_clock_voltage_dependency_table) { - kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); - hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; - } + kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); + hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; - if (NULL != hwmgr->dyn_state.cac_dtp_table) { - kfree(hwmgr->dyn_state.cac_dtp_table); - hwmgr->dyn_state.cac_dtp_table = NULL; - } + kfree(hwmgr->dyn_state.cac_dtp_table); + hwmgr->dyn_state.cac_dtp_table = NULL; - if (NULL != hwmgr->dyn_state.ppm_parameter_table) { - kfree(hwmgr->dyn_state.ppm_parameter_table); - hwmgr->dyn_state.ppm_parameter_table = NULL; - } + kfree(hwmgr->dyn_state.ppm_parameter_table); + hwmgr->dyn_state.ppm_parameter_table = NULL; - if (NULL != hwmgr->dyn_state.vdd_gfx_dependency_on_sclk) { - kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); - hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; - } + kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); + hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; - if (NULL != hwmgr->dyn_state.vq_budgeting_table) { - kfree(hwmgr->dyn_state.vq_budgeting_table); - hwmgr->dyn_state.vq_budgeting_table = NULL; - } + kfree(hwmgr->dyn_state.vq_budgeting_table); + hwmgr->dyn_state.vq_budgeting_table = NULL; return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c index edc5fb6412d9..9186b0788fac 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c @@ -38,20 +38,17 @@ #include "pp_soc15.h" #define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5 -#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip +#define RAVEN_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */ #define SCLK_MIN_DIV_INTV_SHIFT 12 -#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz +#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */ #define SMC_RAM_END 0x40000 static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic; + + int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, struct pp_display_clock_request *clock_req); -struct phm_vq_budgeting_record rv_vqtable[] = { - /* _TBD - * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */ - { 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 }, -}; static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps) { @@ -70,101 +67,27 @@ static const struct rv_power_state *cast_const_rv_ps( return (struct rv_power_state *)hw_ps; } -static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr) -{ - uint32_t table_size, i; - struct phm_vq_budgeting_table *ptable; - uint32_t num_entries = ARRAY_SIZE(rv_vqtable); - - if (hwmgr->dyn_state.vq_budgeting_table != NULL) - return 0; - - table_size = sizeof(struct phm_vq_budgeting_table) + - sizeof(struct phm_vq_budgeting_record) * (num_entries - 1); - - ptable = kzalloc(table_size, GFP_KERNEL); - if (NULL == ptable) - return -ENOMEM; - - ptable->numEntries = (uint8_t) num_entries; - - for (i = 0; i < ptable->numEntries; i++) { - ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs; - ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow; - ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh; - ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow; - ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh; - ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig; - ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk; - ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk; - ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk; - ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs; - } - - hwmgr->dyn_state.vq_budgeting_table = ptable; - - return 0; -} - static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) { struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend); - struct cgs_system_info sys_info = {0}; - int result; - rv_hwmgr->ddi_power_gating_disabled = 0; - rv_hwmgr->bapm_enabled = 1; rv_hwmgr->dce_slow_sclk_threshold = 30000; - rv_hwmgr->disable_driver_thermal_policy = 1; rv_hwmgr->thermal_auto_throttling_treshold = 0; rv_hwmgr->is_nb_dpm_enabled = 1; rv_hwmgr->dpm_flags = 1; - rv_hwmgr->disable_smu_acp_s3_handshake = 1; - rv_hwmgr->disable_notify_smu_vpu_recovery = 0; rv_hwmgr->gfx_off_controled_by_driver = false; - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicM3Arbiter); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDPowerGating); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDynamicPowerGating); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEPowerGating); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SamuPowerGating); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ACP); + rv_hwmgr->need_min_deep_sleep_dcefclk = true; + rv_hwmgr->num_active_display = 0; + rv_hwmgr->deep_sleep_dcefclk = 0; phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_GFXDynamicMGPowerGating); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkThrottleLowNotification); - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DisableVoltageIsland); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DynamicUVDState); - - sys_info.size = sizeof(struct cgs_system_info); - sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; - result = cgs_query_system_info(hwmgr->device, &sys_info); - if (!result) { - if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG) - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_GFXDynamicMGPowerGating); - } - + PHM_PlatformCaps_PowerPlaySupport); return 0; } @@ -234,102 +157,88 @@ static int rv_construct_boot_state(struct pp_hwmgr *hwmgr) return 0; } -static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) { struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); struct PP_Clocks clocks = {0}; struct pp_display_clock_request clock_req; clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; - clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; clock_req.clock_type = amd_pp_dcf_clock; clock_req.clock_freq_in_khz = clocks.dcefClock * 10; - if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0) - clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq; - PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req), "Attempt to set DCF Clock Failed!", return -EINVAL); - if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetMinDeepSleepDcefclk, - clocks.dcefClockInSR / 100); - /* - if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) { - if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100); - rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq), - } - } */ - if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) || ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) { rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100; rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinVcn, (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min); } if((hwmgr->gfx_arbiter.sclk_hard_min != 0) && ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetHardMinSocclkByFreq, hwmgr->gfx_arbiter.sclk_hard_min / 100); - rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq); + rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq); } if ((hwmgr->gfx_arbiter.gfxclk != 0) && (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetMinVideoGfxclkFreq, hwmgr->gfx_arbiter.gfxclk / 100); - rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq); + rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq); } if ((hwmgr->gfx_arbiter.fclk != 0) && (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetMinVideoFclkFreq, hwmgr->gfx_arbiter.fclk / 100); - rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq); + rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq); } return 0; } -static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) { - uint32_t num_of_active_displays = 0; - struct cgs_display_info info = {0}; + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); - cgs_get_active_displays_info(hwmgr->device, &info); - num_of_active_displays = info.display_count; + if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) { + rv_data->deep_sleep_dcefclk = clock/100; + smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetMinDeepSleepDcefclk, + rv_data->deep_sleep_dcefclk); + } + return 0; +} - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, +static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) +{ + struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + + if (rv_data->num_active_display != count) { + rv_data->num_active_display = count; + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDisplayCount, - num_of_active_displays); + rv_data->num_active_display); + } + return 0; } -static const struct phm_master_table_item rv_set_power_state_list[] = { - { NULL, rv_tf_set_clock_limit }, - { NULL, rv_tf_set_num_active_display }, - { } -}; - -static const struct phm_master_table_header rv_set_power_state_master = { - 0, - PHM_MasterTableFlag_None, - rv_set_power_state_list -}; +static int rv_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) +{ + return rv_set_clock_limit(hwmgr, input); +} -static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) +static int rv_init_power_gate_state(struct pp_hwmgr *hwmgr) { struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); @@ -340,20 +249,13 @@ static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input, return 0; } -static const struct phm_master_table_item rv_setup_asic_list[] = { - { .tableFunction = rv_tf_init_power_gate_state }, - { } -}; -static const struct phm_master_table_header rv_setup_asic_master = { - 0, - PHM_MasterTableFlag_None, - rv_setup_asic_list -}; +static int rv_setup_asic_task(struct pp_hwmgr *hwmgr) +{ + return rv_init_power_gate_state(hwmgr); +} -static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int rv_reset_cc6_data(struct pp_hwmgr *hwmgr) { struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); @@ -365,66 +267,42 @@ static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr, return 0; } -static const struct phm_master_table_item rv_power_down_asic_list[] = { - { .tableFunction = rv_tf_reset_cc6_data }, - { } -}; - -static const struct phm_master_table_header rv_power_down_asic_master = { - 0, - PHM_MasterTableFlag_None, - rv_power_down_asic_list -}; - +static int rv_power_off_asic(struct pp_hwmgr *hwmgr) +{ + return rv_reset_cc6_data(hwmgr); +} -static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr) { struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); if (rv_data->gfx_off_controled_by_driver) - smum_send_msg_to_smc(hwmgr->smumgr, + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff); return 0; } -static const struct phm_master_table_item rv_disable_dpm_list[] = { - {NULL, rv_tf_disable_gfx_off}, - { }, -}; - - -static const struct phm_master_table_header rv_disable_dpm_master = { - 0, - PHM_MasterTableFlag_None, - rv_disable_dpm_list -}; +static int rv_disable_dpm_tasks(struct pp_hwmgr *hwmgr) +{ + return rv_disable_gfx_off(hwmgr); +} -static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr, - void *input, void *output, - void *storage, int result) +static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr) { struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); if (rv_data->gfx_off_controled_by_driver) - smum_send_msg_to_smc(hwmgr->smumgr, + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff); return 0; } -static const struct phm_master_table_item rv_enable_dpm_list[] = { - {NULL, rv_tf_enable_gfx_off}, - { }, -}; - -static const struct phm_master_table_header rv_enable_dpm_master = { - 0, - PHM_MasterTableFlag_None, - rv_enable_dpm_list -}; +static int rv_enable_dpm_tasks(struct pp_hwmgr *hwmgr) +{ + return rv_enable_gfx_off(hwmgr); +} static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, struct pp_power_state *prequest_ps, @@ -505,7 +383,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr) DpmClocks_t *table = &(rv_data->clock_table); struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); - result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE); + result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE); PP_ASSERT_WITH_CODE((0 == result), "Attempt to copy clock table from smc failed", @@ -563,9 +441,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) return result; } - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerPlaySupport); - rv_populate_clock_table(hwmgr); result = rv_get_system_info_data(hwmgr); @@ -576,40 +451,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) rv_construct_boot_state(hwmgr); - result = phm_construct_table(hwmgr, &rv_setup_asic_master, - &(hwmgr->setup_asic)); - if (result != 0) { - pr_err("Fail to construct setup ASIC\n"); - return result; - } - - result = phm_construct_table(hwmgr, &rv_power_down_asic_master, - &(hwmgr->power_down_asic)); - if (result != 0) { - pr_err("Fail to construct power down ASIC\n"); - return result; - } - - result = phm_construct_table(hwmgr, &rv_set_power_state_master, - &(hwmgr->set_power_state)); - if (result != 0) { - pr_err("Fail to construct set_power_state\n"); - return result; - } - - result = phm_construct_table(hwmgr, &rv_disable_dpm_master, - &(hwmgr->disable_dynamic_state_management)); - if (result != 0) { - pr_err("Fail to disable_dynamic_state\n"); - return result; - } - result = phm_construct_table(hwmgr, &rv_enable_dpm_master, - &(hwmgr->enable_dynamic_state_management)); - if (result != 0) { - pr_err("Fail to enable_dynamic_state\n"); - return result; - } - hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = RAVEN_MAX_HARDWARE_POWERLEVELS; @@ -624,8 +465,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - rv_init_vq_budget_table(hwmgr); - return result; } @@ -634,46 +473,21 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info); - phm_destroy_table(hwmgr, &(hwmgr->set_power_state)); - phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management)); - phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management)); - phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); - phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); - - if (pinfo->vdd_dep_on_dcefclk) { - kfree(pinfo->vdd_dep_on_dcefclk); - pinfo->vdd_dep_on_dcefclk = NULL; - } - if (pinfo->vdd_dep_on_socclk) { - kfree(pinfo->vdd_dep_on_socclk); - pinfo->vdd_dep_on_socclk = NULL; - } - if (pinfo->vdd_dep_on_fclk) { - kfree(pinfo->vdd_dep_on_fclk); - pinfo->vdd_dep_on_fclk = NULL; - } - if (pinfo->vdd_dep_on_dispclk) { - kfree(pinfo->vdd_dep_on_dispclk); - pinfo->vdd_dep_on_dispclk = NULL; - } - if (pinfo->vdd_dep_on_dppclk) { - kfree(pinfo->vdd_dep_on_dppclk); - pinfo->vdd_dep_on_dppclk = NULL; - } - if (pinfo->vdd_dep_on_phyclk) { - kfree(pinfo->vdd_dep_on_phyclk); - pinfo->vdd_dep_on_phyclk = NULL; - } - - if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - } - - if (NULL != hwmgr->dyn_state.vq_budgeting_table) { - kfree(hwmgr->dyn_state.vq_budgeting_table); - hwmgr->dyn_state.vq_budgeting_table = NULL; - } + kfree(pinfo->vdd_dep_on_dcefclk); + pinfo->vdd_dep_on_dcefclk = NULL; + kfree(pinfo->vdd_dep_on_socclk); + pinfo->vdd_dep_on_socclk = NULL; + kfree(pinfo->vdd_dep_on_fclk); + pinfo->vdd_dep_on_fclk = NULL; + kfree(pinfo->vdd_dep_on_dispclk); + pinfo->vdd_dep_on_dispclk = NULL; + kfree(pinfo->vdd_dep_on_dppclk); + pinfo->vdd_dep_on_dppclk = NULL; + kfree(pinfo->vdd_dep_on_phyclk); + pinfo->vdd_dep_on_phyclk = NULL; + + kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; kfree(hwmgr->backend); hwmgr->backend = NULL; @@ -687,12 +501,12 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, return 0; } -static int rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { return 0; } -static int rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { return 0; } @@ -711,18 +525,9 @@ static int rv_dpm_get_pp_table_entry_callback( { struct rv_power_state *rv_ps = cast_rv_ps(hw_ps); - const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info; - - struct phm_clock_voltage_dependency_table *table = - hwmgr->dyn_state.vddc_dependency_on_sclk; - uint8_t clock_info_index = rv_clock_info->index; - - if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) - clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); - - rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk; - rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v; + rv_ps->levels[index].engine_clock = 0; + rv_ps->levels[index].vddc_index = 0; rv_ps->level = index + 1; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { @@ -814,12 +619,12 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p ps = cast_const_rv_ps(state); level_index = index > ps->level - 1 ? ps->level - 1 : index; - level->coreClock = ps->levels[level_index].engine_clock; + level->coreClock = 30000; if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { for (i = 1; i < ps->level; i++) { if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) { - level->coreClock = ps->levels[i].engine_clock; + level->coreClock = 30000; break; } } @@ -829,8 +634,9 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1; level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk; - } else + } else { level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; + } level->nonLocalMemoryFreq = 0; level->nonLocalMemoryWidth = 0; @@ -993,7 +799,7 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, return -EINVAL; } - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, + result = smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq); return result; @@ -1001,7 +807,8 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) { - return -EINVAL; + clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */ + return 0; } static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr) @@ -1058,6 +865,13 @@ static const struct pp_hwmgr_func rv_hwmgr_funcs = { .get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage, .get_max_high_clocks = rv_get_max_high_clocks, .read_sensor = rv_read_sensor, + .set_active_display_count = rv_set_active_display_count, + .set_deep_sleep_dcefclk = rv_set_deep_sleep_dcefclk, + .dynamic_state_management_enable = rv_enable_dpm_tasks, + .power_off_asic = rv_power_off_asic, + .asic_setup = rv_setup_asic_task, + .power_state_set = rv_set_power_state_tasks, + .dynamic_state_management_disable = rv_disable_dpm_tasks, }; int rv_init_function_pointers(struct pp_hwmgr *hwmgr) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h index 2472b50e54cf..68d61bd95ca0 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h @@ -293,7 +293,9 @@ struct rv_hwmgr { DpmClocks_t clock_table; uint32_t active_process_mask; - bool need_min_deep_sleep_dcefclk; /* disabled by default */ + bool need_min_deep_sleep_dcefclk; + uint32_t deep_sleep_dcefclk; + uint32_t num_active_display; }; struct pp_hwmgr; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c index 261b828ad590..69a0678ace98 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c @@ -27,21 +27,21 @@ static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) { - return smum_send_msg_to_smc(hwmgr->smumgr, enable ? + return smum_send_msg_to_smc(hwmgr, enable ? PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); } static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) { - return smum_send_msg_to_smc(hwmgr->smumgr, enable ? + return smum_send_msg_to_smc(hwmgr, enable ? PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); } static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) { - return smum_send_msg_to_smc(hwmgr->smumgr, enable ? + return smum_send_msg_to_smc(hwmgr, enable ? PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); } @@ -70,7 +70,7 @@ static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr) { if (phm_cf_want_uvd_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF); return 0; } @@ -80,10 +80,10 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) if (phm_cf_want_uvd_power_gating(hwmgr)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDynamicPowerGating)) { - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDPowerON, 1); } else { - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDPowerON, 0); } } @@ -94,7 +94,7 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) { if (phm_cf_want_vce_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_VCEPowerOFF); return 0; } @@ -102,7 +102,7 @@ static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) static int smu7_powerup_vce(struct pp_hwmgr *hwmgr) { if (phm_cf_want_vce_power_gating(hwmgr)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_VCEPowerON); return 0; } @@ -111,7 +111,7 @@ static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SamuPowerGating)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SAMPowerOFF); return 0; } @@ -120,7 +120,7 @@ static int smu7_powerup_samu(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SamuPowerGating)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SAMPowerON); return 0; } @@ -140,7 +140,7 @@ int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr) return 0; } -int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) +void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -166,10 +166,9 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) smu7_update_uvd_dpm(hwmgr, false); } - return 0; } -int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) +void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -194,7 +193,6 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) AMD_PG_STATE_UNGATE); smu7_update_vce_dpm(hwmgr, false); } - return 0; } int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate) @@ -237,7 +235,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_GFX_CGCG_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } if (PP_STATE_SUPPORT_LS & *msg_id) { @@ -247,7 +245,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_GFX_CGLS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -260,7 +258,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_GFX_3DCG_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } @@ -271,7 +269,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_GFX_3DLS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -284,7 +282,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_GFX_RLC_LS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -297,7 +295,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_GFX_CP_LS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -311,7 +309,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, CG_GFX_OTHERS_MGCG_MASK); if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -331,7 +329,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_BIF_MGCG_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } if (PP_STATE_SUPPORT_LS & *msg_id) { @@ -341,7 +339,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_BIF_MGLS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -354,7 +352,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_MC_MGCG_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } @@ -365,7 +363,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_MC_MGLS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -378,7 +376,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_DRM_MGCG_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } if (PP_STATE_SUPPORT_LS & *msg_id) { @@ -388,7 +386,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_DRM_MGLS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -401,7 +399,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_HDP_MGCG_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } @@ -412,7 +410,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_HDP_MGLS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -425,7 +423,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_SDMA_MGCG_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } @@ -436,7 +434,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_SDMA_MGLS_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -449,7 +447,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, value = CG_SYS_ROM_MASK; if (smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, msg, value)) + hwmgr, msg, value)) return -EINVAL; } break; @@ -489,9 +487,9 @@ int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) active_cus = sys_info.value; if (enable) - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus); else - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GFX_CU_PG_DISABLE); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h index c96ed9ed7eaf..7b54d48b2ce2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h @@ -27,8 +27,8 @@ #include "smu7_hwmgr.h" #include "pp_asicblocks.h" -int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); -int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); +void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); +void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr); int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate); int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index c2743233ba10..8dbe9148aad3 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -26,6 +26,7 @@ #include <linux/module.h> #include <linux/slab.h> #include <asm/div64.h> +#include <drm/amdgpu_drm.h> #include "pp_acpi.h" #include "ppatomctrl.h" #include "atombios.h" @@ -163,7 +164,7 @@ static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) { if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable); return 0; } @@ -300,28 +301,28 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;); } - tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC); + tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC); PP_ASSERT_WITH_CODE( (data->vddc_voltage_table.count <= tmp), "Too many voltage values for VDDC. Trimming to fit state table.", phm_trim_voltage_table_to_fit_state_table(tmp, &(data->vddc_voltage_table))); - tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); + tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); PP_ASSERT_WITH_CODE( (data->vddgfx_voltage_table.count <= tmp), "Too many voltage values for VDDC. Trimming to fit state table.", phm_trim_voltage_table_to_fit_state_table(tmp, &(data->vddgfx_voltage_table))); - tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI); + tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI); PP_ASSERT_WITH_CODE( (data->vddci_voltage_table.count <= tmp), "Too many voltage values for VDDCI. Trimming to fit state table.", phm_trim_voltage_table_to_fit_state_table(tmp, &(data->vddci_voltage_table))); - tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD); + tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD); PP_ASSERT_WITH_CODE( (data->mvdd_voltage_table.count <= tmp), "Too many voltage values for MVDD. Trimming to fit state table.", @@ -387,6 +388,7 @@ static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + int i; /* Clear reset for voting clients before enabling DPM */ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -394,50 +396,26 @@ static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); - + for (i = 0; i < 8; i++) + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_0 + i * 4, + data->voting_rights_clients[i]); return 0; } static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) { + int i; + /* Reset voting clients before disabling DPM */ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_1, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_2, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_3, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_4, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_5, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_6, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_7, 0); + for (i = 0; i < 8; i++) + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0); return 0; } @@ -493,7 +471,7 @@ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) { - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults); + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults); } /** @@ -551,7 +529,7 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) data->pcie_gen_performance = data->pcie_gen_power_saving; data->pcie_lane_performance = data->pcie_lane_power_saving; } - tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK); + tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK); phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, tmp, MAX_REGULAR_DPM_NUMBER); @@ -607,13 +585,20 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) data->dpm_table.pcie_speed_table.count = 6; } /* Populate last level for boot PCIE level, but do not increment count. */ - phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, + if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { + for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i, + get_pcie_gen_support(data->pcie_gen_cap, + PP_Max_PCIEGen), + data->vbios_boot_state.pcie_lane_bootup_value); + } else { + phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, data->dpm_table.pcie_speed_table.count, get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen), get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane)); - + } return 0; } @@ -625,27 +610,27 @@ static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) phm_reset_single_dpm_table( &data->dpm_table.sclk_table, - smum_get_mac_definition(hwmgr->smumgr, + smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS), MAX_REGULAR_DPM_NUMBER); phm_reset_single_dpm_table( &data->dpm_table.mclk_table, - smum_get_mac_definition(hwmgr->smumgr, + smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); phm_reset_single_dpm_table( &data->dpm_table.vddc_table, - smum_get_mac_definition(hwmgr->smumgr, + smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC), MAX_REGULAR_DPM_NUMBER); phm_reset_single_dpm_table( &data->dpm_table.vddci_table, - smum_get_mac_definition(hwmgr->smumgr, + smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); phm_reset_single_dpm_table( &data->dpm_table.mvdd_table, - smum_get_mac_definition(hwmgr->smumgr, + smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD), MAX_REGULAR_DPM_NUMBER); return 0; @@ -689,7 +674,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) allowed_vdd_sclk_table->entries[i].clk) { data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = allowed_vdd_sclk_table->entries[i].clk; - data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */ + data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; data->dpm_table.sclk_table.count++; } } @@ -703,7 +688,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) allowed_vdd_mclk_table->entries[i].clk) { data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = allowed_vdd_mclk_table->entries[i].clk; - data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */ + data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; data->dpm_table.mclk_table.count++; } } @@ -855,7 +840,7 @@ static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)) - return smum_send_msg_to_smc(hwmgr->smumgr, + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableVRHotGPIOInterrupt); return 0; @@ -873,7 +858,7 @@ static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); if (data->ulv_supported) - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV); return 0; } @@ -883,7 +868,7 @@ static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); if (data->ulv_supported) - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV); + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV); return 0; } @@ -892,12 +877,12 @@ static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON)) PP_ASSERT_WITH_CODE(false, "Attempt to enable Master Deep Sleep switch failed!", return -EINVAL); } else { - if (smum_send_msg_to_smc(hwmgr->smumgr, + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_OFF)) { PP_ASSERT_WITH_CODE(false, "Attempt to disable Master Deep Sleep switch failed!", @@ -912,7 +897,7 @@ static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { - if (smum_send_msg_to_smc(hwmgr->smumgr, + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_OFF)) { PP_ASSERT_WITH_CODE(false, "Attempt to disable Master Deep Sleep switch failed!", @@ -928,12 +913,12 @@ static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); uint32_t soft_register_value = 0; uint32_t handshake_disables_offset = data->soft_regs_start - + smum_get_offsetof(hwmgr->smumgr, + + smum_get_offsetof(hwmgr, SMU_SoftRegisters, HandshakeDisables); soft_register_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, handshake_disables_offset); - soft_register_value |= smum_get_mac_definition(hwmgr->smumgr, + soft_register_value |= smum_get_mac_definition(hwmgr, SMU_UVD_MCLK_HANDSHAKE_DISABLE); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, handshake_disables_offset, soft_register_value); @@ -947,7 +932,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) /* enable SCLK dpm */ if (!data->sclk_dpm_key_disabled) PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), + (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)), "Failed to enable SCLK DPM during DPM Start Function!", return -EINVAL); @@ -956,20 +941,31 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) smu7_disable_handshake_uvd(hwmgr); PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, + (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Enable)), "Failed to enable MCLK DPM during DPM Start Function!", return -EINVAL); PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); - udelay(10); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); + + if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005); + udelay(10); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005); + } else { + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); + udelay(10); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); + } } return 0; @@ -993,11 +989,15 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + - smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters, + smum_get_offsetof(hwmgr, SMU_SoftRegisters, VoltageChangeTimeout), 0x1000); PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); + if (hwmgr->chip_family == AMDGPU_FAMILY_CI) + cgs_write_register(hwmgr->device, 0x1488, + (cgs_read_register(hwmgr->device, 0x1488) & ~0x1)); + if (smu7_enable_sclk_mclk_dpm(hwmgr)) { pr_err("Failed to enable Sclk DPM and Mclk DPM!"); return -EINVAL; @@ -1006,7 +1006,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) /* enable PCIE dpm */ if (0 == data->pcie_dpm_key_disabled) { PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, + (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_Enable)), "Failed to enable pcie DPM during DPM Start Function!", return -EINVAL); @@ -1014,7 +1014,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Falcon_QuickTransition)) { - PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableACDCGPIOInterrupt)), "Failed to enable AC DC GPIO Interrupt!", ); @@ -1032,7 +1032,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), "Trying to disable SCLK DPM when DPM is disabled", return 0); - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable); } /* disable MCLK dpm */ @@ -1040,7 +1040,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), "Trying to disable MCLK DPM when DPM is disabled", return 0); - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable); } return 0; @@ -1060,7 +1060,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) /* disable PCIE dpm */ if (!data->pcie_dpm_key_disabled) { PP_ASSERT_WITH_CODE( - (smum_send_msg_to_smc(hwmgr->smumgr, + (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_Disable) == 0), "Failed to disable pcie DPM during DPM Stop Function!", return -EINVAL); @@ -1072,7 +1072,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) "Trying to disable voltage DPM when DPM is disabled", return 0); - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable); return 0; } @@ -1226,7 +1226,7 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable VR hot GPIO interrupt!", result = tmp_result); - smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay); + smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay); tmp_result = smu7_enable_sclk_control(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), @@ -1361,14 +1361,14 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) data->vddc_vddgfx_delta = 300; data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; - data->voting_rights_clients0 = SMU7_VOTINGRIGHTSCLIENTS_DFLT0; - data->voting_rights_clients1 = SMU7_VOTINGRIGHTSCLIENTS_DFLT1; - data->voting_rights_clients2 = SMU7_VOTINGRIGHTSCLIENTS_DFLT2; - data->voting_rights_clients3 = SMU7_VOTINGRIGHTSCLIENTS_DFLT3; - data->voting_rights_clients4 = SMU7_VOTINGRIGHTSCLIENTS_DFLT4; - data->voting_rights_clients5 = SMU7_VOTINGRIGHTSCLIENTS_DFLT5; - data->voting_rights_clients6 = SMU7_VOTINGRIGHTSCLIENTS_DFLT6; - data->voting_rights_clients7 = SMU7_VOTINGRIGHTSCLIENTS_DFLT7; + data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0; + data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1; + data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2; + data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3; + data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4; + data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5; + data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6; + data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7; data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; @@ -1382,23 +1382,40 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) data->force_pcie_gen = PP_PCIEGenInvalid; data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; - if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) { + if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) { uint8_t tmp1, tmp2; uint16_t tmp3 = 0; atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, &tmp3); tmp3 = (tmp3 >> 5) & 0x3; data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3; + } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { + data->vddc_phase_shed_control = 1; + } else { + data->vddc_phase_shed_control = 0; + } + + if (hwmgr->chip_id == CHIP_HAWAII) { + data->thermal_temp_setting.temperature_low = 94500; + data->thermal_temp_setting.temperature_high = 95000; + data->thermal_temp_setting.temperature_shutdown = 104000; + } else { + data->thermal_temp_setting.temperature_low = 99500; + data->thermal_temp_setting.temperature_high = 100000; + data->thermal_temp_setting.temperature_shutdown = 104000; } data->fast_watermark_threshold = 100; - if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; + else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, + VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) + data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDGFX)) { - if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; } @@ -1406,25 +1423,24 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EnableMVDDControl)) { - if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; - else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; } - if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) { + if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDGFX); - } if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDCI)) { - if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; - else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, + else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; } @@ -1543,7 +1559,7 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) if (vddc >= 2000 || vddc == 0) return -EINVAL; } else { - pr_warn("failed to retrieving EVV voltage!\n"); + pr_debug("failed to retrieving EVV voltage!\n"); continue; } @@ -1676,7 +1692,7 @@ static int phm_add_voltage(struct pp_hwmgr *hwmgr, PP_ASSERT_WITH_CODE((0 != look_up_table->count), "Lookup Table empty.", return -EINVAL); - i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); + i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); PP_ASSERT_WITH_CODE((i >= look_up_table->count), "Lookup Table is full.", return -EINVAL); @@ -2274,7 +2290,7 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; } - if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count > 1) + if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1) hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; return 0; @@ -2282,40 +2298,65 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - } - pp_smu7_thermal_fini(hwmgr); - if (NULL != hwmgr->backend) { - kfree(hwmgr->backend); - hwmgr->backend = NULL; - } + kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); + hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; + kfree(hwmgr->backend); + hwmgr->backend = NULL; + + return 0; +} + +static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr) +{ + uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + int i; + if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) { + for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { + virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; + if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci, + virtual_voltage_id, + efuse_voltage_id) == 0) { + if (vddc != 0 && vddc != virtual_voltage_id) { + data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; + data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; + data->vddc_leakage.count++; + } + if (vddci != 0 && vddci != virtual_voltage_id) { + data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci; + data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id; + data->vddci_leakage.count++; + } + } + } + } return 0; } static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data; - int result; + int result = 0; data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL); if (data == NULL) return -ENOMEM; hwmgr->backend = data; - pp_smu7_thermal_initialize(hwmgr); - smu7_patch_voltage_workaround(hwmgr); smu7_init_dpm_defaults(hwmgr); /* Get leakage voltage based on leakage ID. */ - result = smu7_get_evv_voltages(hwmgr); - - if (result) { - pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); - return -EINVAL; + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EVV)) { + result = smu7_get_evv_voltages(hwmgr); + if (result) { + pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); + return -EINVAL; + } + } else { + smu7_get_elb_voltages(hwmgr); } if (hwmgr->pp_table_version == PP_TABLE_V1) { @@ -2382,7 +2423,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) level++; if (level) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PCIeDPM_ForceLevel, level); } } @@ -2395,7 +2436,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) level++; if (level) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, (1 << level)); } @@ -2409,7 +2450,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) level++; if (level) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, (1 << level)); } @@ -2428,14 +2469,14 @@ static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) if (!data->sclk_dpm_key_disabled) { if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, data->dpm_level_enable_mask.sclk_dpm_enable_mask); } if (!data->mclk_dpm_key_disabled) { if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, data->dpm_level_enable_mask.mclk_dpm_enable_mask); } @@ -2451,7 +2492,7 @@ static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) return -EINVAL; if (!data->pcie_dpm_key_disabled) { - smum_send_msg_to_smc(hwmgr->smumgr, + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel); } @@ -2468,7 +2509,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { level = phm_get_lowest_enabled_level(hwmgr, data->dpm_level_enable_mask.sclk_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, (1 << level)); @@ -2478,7 +2519,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { level = phm_get_lowest_enabled_level(hwmgr, data->dpm_level_enable_mask.mclk_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, (1 << level)); } @@ -2488,7 +2529,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { level = phm_get_lowest_enabled_level(hwmgr, data->dpm_level_enable_mask.pcie_dpm_enable_mask); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PCIeDPM_ForceLevel, (level)); } @@ -2572,51 +2613,16 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, uint32_t sclk_mask = 0; uint32_t mclk_mask = 0; uint32_t pcie_mask = 0; - uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; - - if (level == hwmgr->dpm_level) - return ret; - - if (!(hwmgr->dpm_level & profile_mode_mask)) { - /* enter profile mode, save current level, disable gfx cg*/ - if (level & profile_mode_mask) { - hwmgr->saved_dpm_level = hwmgr->dpm_level; - cgs_set_clockgating_state(hwmgr->device, - AMD_IP_BLOCK_TYPE_GFX, - AMD_CG_STATE_UNGATE); - } - } else { - /* exit profile mode, restore level, enable gfx cg*/ - if (!(level & profile_mode_mask)) { - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) - level = hwmgr->saved_dpm_level; - cgs_set_clockgating_state(hwmgr->device, - AMD_IP_BLOCK_TYPE_GFX, - AMD_CG_STATE_GATE); - } - } switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: ret = smu7_force_dpm_highest(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_LOW: ret = smu7_force_dpm_lowest(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_AUTO: ret = smu7_unforce_dpm_levels(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: @@ -2625,26 +2631,23 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); if (ret) return ret; - hwmgr->dpm_level = level; smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); - break; case AMD_DPM_FORCED_LEVEL_MANUAL: - hwmgr->dpm_level = level; - break; case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: default: break; } - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); - else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); - - return 0; + if (!ret) { + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); + else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); + } + return ret; } static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) @@ -2843,7 +2846,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, } -static int smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { struct pp_power_state *ps; struct smu7_power_state *smu7_ps; @@ -2865,7 +2868,7 @@ static int smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) [smu7_ps->performance_level_count-1].memory_clock; } -static int smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { struct pp_power_state *ps; struct smu7_power_state *smu7_ps; @@ -3002,7 +3005,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, [smu7_power_state->performance_level_count++]); PP_ASSERT_WITH_CODE( - (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), + (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), "Performance levels exceeds SMC limit!", return -EINVAL); @@ -3071,11 +3074,11 @@ static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { if (dep_mclk_table->entries[0].clk != data->vbios_boot_state.mclk_bootup_value) - pr_err("Single MCLK entry VDDCI/MCLK dependency table " + pr_debug("Single MCLK entry VDDCI/MCLK dependency table " "does not match VBIOS boot MCLK level"); if (dep_mclk_table->entries[0].vddci != data->vbios_boot_state.vddci_bootup_value) - pr_err("Single VDDCI entry VDDCI/MCLK dependency table " + pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " "does not match VBIOS boot VDDCI level"); } @@ -3166,7 +3169,7 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, data->highest_mclk = memory_clock; PP_ASSERT_WITH_CODE( - (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), + (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), "Performance levels exceeds SMC limit!", return -EINVAL); @@ -3219,11 +3222,11 @@ static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { if (dep_mclk_table->entries[0].clk != data->vbios_boot_state.mclk_bootup_value) - pr_err("Single MCLK entry VDDCI/MCLK dependency table " + pr_debug("Single MCLK entry VDDCI/MCLK dependency table " "does not match VBIOS boot MCLK level"); if (dep_mclk_table->entries[0].v != data->vbios_boot_state.vddci_bootup_value) - pr_err("Single VDDCI entry VDDCI/MCLK dependency table " + pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " "does not match VBIOS boot VDDCI level"); } @@ -3312,14 +3315,14 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, struct pp_gpu_power *query) { - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart), "Failed to start pm status log!", return -1); msleep_interruptible(20); - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample), "Failed to sample pm status log!", return -1); @@ -3353,19 +3356,19 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, switch (idx) { case AMDGPU_PP_SENSOR_GFX_SCLK: - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency); sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); *((uint32_t *)value) = sclk; *size = 4; return 0; case AMDGPU_PP_SENSOR_GFX_MCLK: - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency); mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); *((uint32_t *)value) = mclk; *size = 4; return 0; case AMDGPU_PP_SENSOR_GPU_LOAD: - offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, + offset = data->soft_regs_start + smum_get_offsetof(hwmgr, SMU_SoftRegisters, AverageGraphicsActivity); @@ -3532,7 +3535,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), "Trying to freeze SCLK DPM when DPM is disabled", ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel), "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", return -EINVAL); @@ -3544,7 +3547,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), "Trying to freeze MCLK DPM when DPM is disabled", ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel), "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", return -EINVAL); @@ -3762,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), "Trying to Unfreeze SCLK DPM when DPM is disabled", ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel), "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", return -EINVAL); @@ -3774,7 +3777,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), "Trying to Unfreeze MCLK DPM when DPM is disabled", ); - PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel), "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", return -EINVAL); @@ -3822,11 +3825,14 @@ static int smu7_notify_link_speed_change_after_state_change( static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + int ret = 0; - if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { + smum_send_msg_to_smc_with_parameter(hwmgr, (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2); - return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL; + ret = (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL; + } + return ret; } static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) @@ -3899,10 +3905,7 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f hwmgr->thermal_controller. advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; - if (phm_is_hw_access_blocked(hwmgr)) - return 0; - - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); } @@ -3911,7 +3914,7 @@ smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) { PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; - return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; + return (smum_send_msg_to_smc(hwmgr, msg) == 0) ? 0 : -1; } static int @@ -3974,12 +3977,12 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, + data->soft_regs_start + smum_get_offsetof(hwmgr, SMU_SoftRegisters, PreVBlankGap), 0x64); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, + data->soft_regs_start + smum_get_offsetof(hwmgr, SMU_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); @@ -4004,10 +4007,7 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f hwmgr->thermal_controller. advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; - if (phm_is_hw_access_blocked(hwmgr)) - return 0; - - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); } @@ -4249,21 +4249,21 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - if (hwmgr->dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO | - AMD_DPM_FORCED_LEVEL_LOW | - AMD_DPM_FORCED_LEVEL_HIGH)) + if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO | + AMD_DPM_FORCED_LEVEL_LOW | + AMD_DPM_FORCED_LEVEL_HIGH)) return -EINVAL; switch (type) { case PP_SCLK: if (!data->sclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); break; case PP_MCLK: if (!data->mclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); break; @@ -4276,7 +4276,7 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, level++; if (!data->pcie_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PCIeDPM_ForceLevel, level); break; @@ -4300,7 +4300,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, switch (type) { case PP_SCLK: - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency); clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); for (i = 0; i < sclk_table->count; i++) { @@ -4316,7 +4316,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, (i == now) ? "*" : ""); break; case PP_MCLK: - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency); clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); for (i = 0; i < mclk_table->count; i++) { @@ -4353,31 +4353,27 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, return size; } -static int smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) +static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) { - int result = 0; - switch (mode) { case AMD_FAN_CTRL_NONE: - result = smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); + smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); break; case AMD_FAN_CTRL_MANUAL: if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) - result = smu7_fan_ctrl_stop_smc_fan_control(hwmgr); + smu7_fan_ctrl_stop_smc_fan_control(hwmgr); break; case AMD_FAN_CTRL_AUTO: - result = smu7_fan_ctrl_set_static_mode(hwmgr, mode); - if (!result) - result = smu7_fan_ctrl_start_smc_fan_control(hwmgr); + if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode)) + smu7_fan_ctrl_start_smc_fan_control(hwmgr); break; default: break; } - return result; } -static int smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) +static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) { return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL; } @@ -4606,7 +4602,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, if (sclk_mask) { if (!data->sclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, data->dpm_level_enable_mask. sclk_dpm_enable_mask & @@ -4615,7 +4611,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, if (mclk_mask) { if (!data->mclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, data->dpm_level_enable_mask. mclk_dpm_enable_mask & @@ -4627,8 +4623,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr, static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) { - struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); if (smu_data == NULL) return -EINVAL; @@ -4640,13 +4635,13 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( - hwmgr->smumgr, PPSMC_MSG_EnableAvfs), + hwmgr, PPSMC_MSG_EnableAvfs), "Failed to enable AVFS!", return -EINVAL); } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( - hwmgr->smumgr, PPSMC_MSG_DisableAvfs), + hwmgr, PPSMC_MSG_DisableAvfs), "Failed to disable AVFS!", return -EINVAL); @@ -4703,6 +4698,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = { .set_power_profile_state = smu7_set_power_profile_state, .avfs_control = smu7_avfs_control, .disable_smc_firmware_ctf = smu7_thermal_disable_alert, + .start_thermal_controller = smu7_start_thermal_controller, }; uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h index f221e17b67e7..e021154aedbd 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h @@ -182,14 +182,7 @@ struct smu7_hwmgr { struct smu7_dpm_table dpm_table; struct smu7_dpm_table golden_dpm_table; - uint32_t voting_rights_clients0; - uint32_t voting_rights_clients1; - uint32_t voting_rights_clients2; - uint32_t voting_rights_clients3; - uint32_t voting_rights_clients4; - uint32_t voting_rights_clients5; - uint32_t voting_rights_clients6; - uint32_t voting_rights_clients7; + uint32_t voting_rights_clients[8]; uint32_t static_screen_threshold_unit; uint32_t static_screen_threshold; uint32_t voltage_control; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c index 1dc31aa72781..85ca16abb626 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c @@ -629,51 +629,38 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) uint32_t block_en = 0; int32_t result = 0; uint32_t didt_block; - uint32_t data; if (hwmgr->chip_id == CHIP_POLARIS11) didt_block = Polaris11_DIDTBlock_Info; else didt_block = DIDTBlock_Info; - block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ? en : 0; - - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0); - data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data); + block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0; + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_SQ_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~SQ_Enable_MASK; didt_block |= block_en << SQ_Enable_SHIFT; - block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ? en : 0; - - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0); - data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data); + block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0; + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_DB_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~DB_Enable_MASK; didt_block |= block_en << DB_Enable_SHIFT; - block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ? en : 0; - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0); - data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data); + block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0; + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_TD_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~TD_Enable_MASK; didt_block |= block_en << TD_Enable_SHIFT; - block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping) ? en : 0; - - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0); - data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((block_en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data); + block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0; + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_TCP_CTRL0, DIDT_CTRL_EN, block_en); didt_block &= ~TCP_Enable_MASK; didt_block |= block_en << TCP_Enable_SHIFT; - if (enable) - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block); + result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block); return result; } @@ -753,12 +740,13 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) if (result == 0) num_se = sys_info.value; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { + if (PP_CAP(PHM_PlatformCaps_SQRamping) || + PP_CAP(PHM_PlatformCaps_DBRamping) || + PP_CAP(PHM_PlatformCaps_TDRamping) || + PP_CAP(PHM_PlatformCaps_TCPRamping)) { cgs_enter_safe_mode(hwmgr->device, true); + cgs_lock_grbm_idx(hwmgr->device, true); value = 0; value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); for (count = 0; count < num_se; count++) { @@ -775,7 +763,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) } else if (hwmgr->chip_id == CHIP_POLARIS11) { result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11); PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result); - if (hwmgr->smumgr->is_kicker) + if (hwmgr->is_kicker) result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker); else result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11); @@ -793,11 +781,12 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result); if (hwmgr->chip_id == CHIP_POLARIS11) { - result = smum_send_msg_to_smc(hwmgr->smumgr, + result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_EnableDpmDidt)); PP_ASSERT_WITH_CODE((0 == result), "Failed to enable DPM DIDT.", return result); } + cgs_lock_grbm_idx(hwmgr->device, false); cgs_enter_safe_mode(hwmgr->device, false); } @@ -808,10 +797,10 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) { int result; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { + if (PP_CAP(PHM_PlatformCaps_SQRamping) || + PP_CAP(PHM_PlatformCaps_DBRamping) || + PP_CAP(PHM_PlatformCaps_TDRamping) || + PP_CAP(PHM_PlatformCaps_TCPRamping)) { cgs_enter_safe_mode(hwmgr->device, true); @@ -820,7 +809,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) "Post DIDT enable clock gating failed.", return result); if (hwmgr->chip_id == CHIP_POLARIS11) { - result = smum_send_msg_to_smc(hwmgr->smumgr, + result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_DisableDpmDidt)); PP_ASSERT_WITH_CODE((0 == result), "Failed to disable DPM DIDT.", return result); @@ -836,10 +825,9 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr) struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); int result = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC)) { + if (PP_CAP(PHM_PlatformCaps_CAC)) { int smc_result; - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + smc_result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_EnableCac)); PP_ASSERT_WITH_CODE((0 == smc_result), "Failed to enable CAC in SMC.", result = -1); @@ -854,9 +842,8 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr) struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); int result = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC) && data->cac_enabled) { - int smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) { + int smc_result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_DisableCac)); PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable CAC in SMC.", result = -1); @@ -872,7 +859,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) if (data->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PkgPwrSetLimit, n); return 0; } @@ -880,7 +867,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, uint32_t target_tdp) { - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); } @@ -899,11 +886,9 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) else cac_table = hwmgr->dyn_state.cac_dtp_table; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { - + if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { if (data->enable_tdc_limit_feature) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + smc_result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_TDCLimitEnable)); PP_ASSERT_WITH_CODE((0 == smc_result), "Failed to enable TDCLimit in SMC.", result = -1;); @@ -913,14 +898,13 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) } if (data->enable_pkg_pwr_tracking_feature) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + smc_result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable)); PP_ASSERT_WITH_CODE((0 == smc_result), "Failed to enable PkgPwrTracking in SMC.", result = -1;); if (0 == smc_result) { uint32_t default_limit = (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256); - data->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; @@ -937,14 +921,13 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); int result = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment) && - data->power_containment_features) { + if (PP_CAP(PHM_PlatformCaps_PowerContainment) && + data->power_containment_features) { int smc_result; if (data->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + smc_result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_TDCLimitDisable)); PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable TDCLimit in SMC.", @@ -953,7 +936,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) if (data->power_containment_features & POWERCONTAINMENT_FEATURE_DTE) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + smc_result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_DisableDTE)); PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable DTE in SMC.", @@ -962,7 +945,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) if (data->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, + smc_result = smum_send_msg_to_smc(hwmgr, (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable)); PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable PkgPwrTracking in SMC.", @@ -987,16 +970,17 @@ int smu7_power_control_set_level(struct pp_hwmgr *hwmgr) cac_table = table_info->cac_dtp_table; else cac_table = hwmgr->dyn_state.cac_dtp_table; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { + if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { /* adjustment percentage has already been validated */ adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? hwmgr->platform_descriptor.TDPAdjustment : (-1 * hwmgr->platform_descriptor.TDPAdjustment); - /* SMC requested that target_tdp to be 7 bit fraction in DPM table - * but message to be 8 bit fraction for messages - */ - target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100; + + if (hwmgr->chip_id > CHIP_TONGA) + target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100; + else + target_tdp = ((100 + adjust_percent) * (int)(cac_table->usConfigurableTDP * 256)) / 100; + result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c index baddb569a8b8..d7aa643cdb51 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c @@ -37,9 +37,8 @@ int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, fan_speed_info->min_percent = 0; fan_speed_info->max_percent = 100; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM) && - hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { + if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && + hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { fan_speed_info->supports_rpm_read = true; fan_speed_info->supports_rpm_write = true; fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; @@ -87,8 +86,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) uint32_t crystal_clock_freq; if (hwmgr->thermal_controller.fanInfo.bNoFan || - (hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution == 0)) + !hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) return -ENODEV; tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -152,13 +150,11 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) { int result; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport)) { + if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) { cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY); - result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); + result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM)) + if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM)) hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, hwmgr->thermal_controller. advanceFanControlParameters.usMaxFanRPM); @@ -169,12 +165,12 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) } else { cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE); - result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); + result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl); } if (!result && hwmgr->thermal_controller. advanceFanControlParameters.ucTargetTemperature) - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanTemperatureTarget, hwmgr->thermal_controller. advanceFanControlParameters.ucTargetTemperature); @@ -187,7 +183,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) { hwmgr->fan_ctrl_enabled = false; - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); + return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl); } /** @@ -209,8 +205,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, if (speed > 100) speed = 100; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr); duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -241,8 +236,7 @@ int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); if (!result) result = smu7_fan_ctrl_start_smc_fan_control(hwmgr); @@ -270,8 +264,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) return 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr); crystal_clock_freq = smu7_get_xclk(hwmgr); @@ -367,7 +360,7 @@ static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr) * * @param hwmgr The address of the hardware manager. */ -int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr) +static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr) { uint32_t alert; @@ -378,7 +371,7 @@ int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr) CG_THERMAL_INT, THERM_INT_MASK, alert); /* send message to SMU to enable internal thermal interrupts */ - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable); } /** @@ -396,7 +389,7 @@ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr) CG_THERMAL_INT, THERM_INT_MASK, alert); /* send message to SMU to disable internal thermal interrupts */ - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable); + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable); } /** @@ -423,16 +416,14 @@ int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) * @param Result the last failure code * @return result from set temperature range routine */ -static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) +static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) { /* If the fantable setup has failed we could have disabled * PHM_PlatformCaps_MicrocodeFanControl even after * this function was included in the table. * Make sure that we still think controlling the fan is OK. */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { smu7_fan_ctrl_start_smc_fan_control(hwmgr); smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } @@ -440,108 +431,34 @@ static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, return 0; } -/** -* Set temperature range for high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -static int tf_smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) +int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr, + struct PP_TemperatureRange *range) { - struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input; + int ret = 0; if (range == NULL) return -EINVAL; - return smu7_thermal_set_temperature_range(hwmgr, range->min, range->max); -} - -/** -* Programs one-time setting registers -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from initialize thermal controller routine -*/ -static int tf_smu7_thermal_initialize(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return smu7_thermal_initialize(hwmgr); -} - -/** -* Enable high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from enable alert routine -*/ -static int tf_smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return smu7_thermal_enable_alert(hwmgr); -} - -/** -* Disable high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from disable alert routine -*/ -static int tf_smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return smu7_thermal_disable_alert(hwmgr); -} + smu7_thermal_initialize(hwmgr); + ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max); + if (ret) + return -EINVAL; + smu7_thermal_enable_alert(hwmgr); + ret = smum_thermal_avfs_enable(hwmgr); + if (ret) + return -EINVAL; -static const struct phm_master_table_item -phm_thermal_start_thermal_controller_master_list[] = { - { .tableFunction = tf_smu7_thermal_initialize }, - { .tableFunction = tf_smu7_thermal_set_temperature_range }, - { .tableFunction = tf_smu7_thermal_enable_alert }, - { .tableFunction = smum_thermal_avfs_enable }, /* We should restrict performance levels to low before we halt the SMC. * On the other hand we are still in boot state when we do this * so it would be pointless. * If this assumption changes we have to revisit this table. */ - { .tableFunction = smum_thermal_setup_fan_table }, - { .tableFunction = tf_smu7_thermal_start_smc_fan_control }, - { } -}; - -static const struct phm_master_table_header -phm_thermal_start_thermal_controller_master = { - 0, - PHM_MasterTableFlag_None, - phm_thermal_start_thermal_controller_master_list -}; - -static const struct phm_master_table_item -phm_thermal_set_temperature_range_master_list[] = { - { .tableFunction = tf_smu7_thermal_disable_alert }, - { .tableFunction = tf_smu7_thermal_set_temperature_range }, - { .tableFunction = tf_smu7_thermal_enable_alert }, - { } -}; - -static const struct phm_master_table_header -phm_thermal_set_temperature_range_master = { - 0, - PHM_MasterTableFlag_None, - phm_thermal_set_temperature_range_master_list -}; + smum_thermal_setup_fan_table(hwmgr); + smu7_thermal_start_smc_fan_control(hwmgr); + return 0; +} + + int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) { @@ -550,35 +467,3 @@ int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) return 0; } -/** -* Initializes the thermal controller related functions in the Hardware Manager structure. -* @param hwmgr The address of the hardware manager. -* @exception Any error code from the low-level communication. -*/ -int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr) -{ - int result; - - result = phm_construct_table(hwmgr, - &phm_thermal_set_temperature_range_master, - &(hwmgr->set_temperature_range)); - - if (!result) { - result = phm_construct_table(hwmgr, - &phm_thermal_start_thermal_controller_master, - &(hwmgr->start_thermal_controller)); - if (result) - phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range)); - } - - if (!result) - hwmgr->fan_ctrl_is_in_default_mode = true; - return result; -} - -void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr) -{ - phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range)); - phm_destroy_table(hwmgr, &(hwmgr->start_thermal_controller)); - return; -}
\ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h index ba71b608fa75..42c1ba0fad78 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h @@ -46,14 +46,13 @@ extern int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); -extern int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr); -extern void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr); extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr); extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); extern int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); -extern int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr); extern int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr); extern int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); +extern int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr, + struct PP_TemperatureRange *temperature_range); #endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 9d71a259d97d..a59d282797f5 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -201,9 +201,6 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_ControlVDDCI); phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_TablelessHardwareInterface); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EnableSMU7ThermalManagement); sys_info.size = sizeof(struct cgs_system_info); @@ -381,12 +378,10 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) if (!data->registry_data.socclk_dpm_key_disabled) data->smu_features[GNLD_DPM_SOCCLK].supported = true; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_UVDDPM)) + if (PP_CAP(PHM_PlatformCaps_UVDDPM)) data->smu_features[GNLD_DPM_UVD].supported = true; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_VCEDPM)) + if (PP_CAP(PHM_PlatformCaps_VCEDPM)) data->smu_features[GNLD_DPM_VCE].supported = true; if (!data->registry_data.pcie_dpm_key_disabled) @@ -395,9 +390,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) if (!data->registry_data.dcefclk_dpm_key_disabled) data->smu_features[GNLD_DPM_DCEFCLK].supported = true; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep) && - data->registry_data.sclk_deep_sleep_support) { + if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) && + data->registry_data.sclk_deep_sleep_support) { data->smu_features[GNLD_DS_GFXCLK].supported = true; data->smu_features[GNLD_DS_SOCCLK].supported = true; data->smu_features[GNLD_DS_LCLK].supported = true; @@ -431,8 +425,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) if (data->registry_data.vr0hot_enabled) data->smu_features[GNLD_VR0HOT].supported = true; - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetSmuVersion); - vega10_read_arg_from_smc(hwmgr->smumgr, &(data->smu_version)); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion); + vega10_read_arg_from_smc(hwmgr, &(data->smu_version)); /* ACG firmware has major version 5 */ if ((data->smu_version & 0xff000000) == 0x5000000) data->smu_features[GNLD_ACG].supported = true; @@ -497,8 +491,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) if (!vega10_get_socclk_for_voltage_evv(hwmgr, table_info->vddc_lookup_table, vv_id, &sclk)) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ClockStretcher)) { + if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) { for (j = 1; j < socclk_table->count; j++) { if (socclk_table->entries[j].clk == sclk && socclk_table->entries[j].cks_enable == 0) { @@ -591,61 +584,37 @@ static int vega10_patch_clock_voltage_limits_with_vddc_leakage( static int vega10_patch_voltage_dependency_tables_with_lookup_table( struct pp_hwmgr *hwmgr) { - uint8_t entry_id; - uint8_t voltage_id; + uint8_t entry_id, voltage_id; + unsigned i; struct phm_ppt_v2_information *table_info = (struct phm_ppt_v2_information *)(hwmgr->pptable); - struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = - table_info->vdd_dep_on_socclk; - struct phm_ppt_v1_clock_voltage_dependency_table *gfxclk_table = - table_info->vdd_dep_on_sclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dcefclk_table = - table_info->vdd_dep_on_dcefclk; - struct phm_ppt_v1_clock_voltage_dependency_table *pixclk_table = - table_info->vdd_dep_on_pixclk; - struct phm_ppt_v1_clock_voltage_dependency_table *dspclk_table = - table_info->vdd_dep_on_dispclk; - struct phm_ppt_v1_clock_voltage_dependency_table *phyclk_table = - table_info->vdd_dep_on_phyclk; - struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = - table_info->vdd_dep_on_mclk; struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = table_info->mm_dep_table; + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = + table_info->vdd_dep_on_mclk; - for (entry_id = 0; entry_id < socclk_table->count; entry_id++) { - voltage_id = socclk_table->entries[entry_id].vddInd; - socclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - - for (entry_id = 0; entry_id < gfxclk_table->count; entry_id++) { - voltage_id = gfxclk_table->entries[entry_id].vddInd; - gfxclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - - for (entry_id = 0; entry_id < dcefclk_table->count; entry_id++) { - voltage_id = dcefclk_table->entries[entry_id].vddInd; - dcefclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } - - for (entry_id = 0; entry_id < pixclk_table->count; entry_id++) { - voltage_id = pixclk_table->entries[entry_id].vddInd; - pixclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } + for (i = 0; i < 6; i++) { + struct phm_ppt_v1_clock_voltage_dependency_table *vdt; + switch (i) { + case 0: vdt = table_info->vdd_dep_on_socclk; break; + case 1: vdt = table_info->vdd_dep_on_sclk; break; + case 2: vdt = table_info->vdd_dep_on_dcefclk; break; + case 3: vdt = table_info->vdd_dep_on_pixclk; break; + case 4: vdt = table_info->vdd_dep_on_dispclk; break; + case 5: vdt = table_info->vdd_dep_on_phyclk; break; + } - for (entry_id = 0; entry_id < dspclk_table->count; entry_id++) { - voltage_id = dspclk_table->entries[entry_id].vddInd; - dspclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; + for (entry_id = 0; entry_id < vdt->count; entry_id++) { + voltage_id = vdt->entries[entry_id].vddInd; + vdt->entries[entry_id].vddc = + table_info->vddc_lookup_table->entries[voltage_id].us_vdd; + } } - for (entry_id = 0; entry_id < phyclk_table->count; entry_id++) { - voltage_id = phyclk_table->entries[entry_id].vddInd; - phyclk_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; + for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { + voltage_id = mm_table->entries[entry_id].vddcInd; + mm_table->entries[entry_id].vddc = + table_info->vddc_lookup_table->entries[voltage_id].us_vdd; } for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { @@ -660,11 +629,6 @@ static int vega10_patch_voltage_dependency_tables_with_lookup_table( table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; } - for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { - voltage_id = mm_table->entries[entry_id].vddcInd; - mm_table->entries[entry_id].vddc = - table_info->vddc_lookup_table->entries[voltage_id].us_vdd; - } return 0; @@ -838,8 +802,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) } /* VDDCI_MEM */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ControlVDDCI)) { + if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) { if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO; @@ -959,7 +922,7 @@ static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr) { uint32_t features_enabled; - if (!vega10_get_smc_features(hwmgr->smumgr, &features_enabled)) { + if (!vega10_get_smc_features(hwmgr, &features_enabled)) { if (features_enabled & SMC_DPM_FEATURES) return true; } @@ -1411,10 +1374,8 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct vega10_dpm_table)); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinACSupport) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinDCSupport)) { + if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) || + PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) { data->odn_dpm_table.odn_core_clock_dpm_levels. number_of_performance_levels = data->dpm_table.gfx_table.count; for (i = 0; i < data->dpm_table.gfx_table.count; i++) { @@ -1558,7 +1519,8 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) */ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, - uint32_t gfx_clock, PllSetting_t *current_gfxclk_level) + uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, + uint32_t *acg_freq) { struct phm_ppt_v2_information *table_info = (struct phm_ppt_v2_information *)(hwmgr->pptable); @@ -1609,6 +1571,8 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, cpu_to_le16(dividers.usPll_ss_slew_frac); current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); + *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */ + return 0; } @@ -1689,7 +1653,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) for (i = 0; i < dpm_table->count; i++) { result = vega10_populate_single_gfx_level(hwmgr, dpm_table->dpm_levels[i].value, - &(pp_table->GfxclkLevel[i])); + &(pp_table->GfxclkLevel[i]), + &(pp_table->AcgFreqTable[i])); if (result) return result; } @@ -1698,7 +1663,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) while (i < NUM_GFXCLK_DPM_LEVELS) { result = vega10_populate_single_gfx_level(hwmgr, dpm_table->dpm_levels[j].value, - &(pp_table->GfxclkLevel[i])); + &(pp_table->GfxclkLevel[i]), + &(pp_table->AcgFreqTable[i])); if (result) return result; i++; @@ -2306,21 +2272,21 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr) uint32_t agc_btc_response; if (data->smu_features[GNLD_ACG].supported) { - if (0 == vega10_enable_smc_features(hwmgr->smumgr, true, + if (0 == vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_InitializeAcg); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg); - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgBtc); - vega10_read_arg_from_smc(hwmgr->smumgr, &agc_btc_response); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc); + vega10_read_arg_from_smc(hwmgr, &agc_btc_response); if (1 == agc_btc_response) { if (1 == data->acg_loop_state) - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInClosedLoop); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop); else if (2 == data->acg_loop_state) - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInOpenLoop); - if (0 == vega10_enable_smc_features(hwmgr->smumgr, true, + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop); + if (0 == vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_ACG].smu_feature_bitmap)) data->smu_features[GNLD_ACG].enabled = true; } else { @@ -2337,13 +2303,11 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr) struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - if (data->smu_features[GNLD_ACG].supported) { - if (data->smu_features[GNLD_ACG].enabled) { - if (0 == vega10_enable_smc_features(hwmgr->smumgr, false, - data->smu_features[GNLD_ACG].smu_feature_bitmap)) + if (data->smu_features[GNLD_ACG].supported && + data->smu_features[GNLD_ACG].enabled) + if (!vega10_enable_smc_features(hwmgr, false, + data->smu_features[GNLD_ACG].smu_feature_bitmap)) data->smu_features[GNLD_ACG].enabled = false; - } - } return 0; } @@ -2358,9 +2322,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); if (!result) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot) && - (data->registry_data.regulator_hot_gpio_support)) { + if (PP_CAP(PHM_PlatformCaps_RegulatorHot) && + data->registry_data.regulator_hot_gpio_support) { pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio; @@ -2372,9 +2335,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) pp_table->VR1HotPolarity = 0; } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_AutomaticDCTransition) && - (data->registry_data.ac_dc_switch_gpio_support)) { + if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) && + data->registry_data.ac_dc_switch_gpio_support) { pp_table->AcDcGpio = gpio_params.ucAcDcGpio; pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; } else { @@ -2393,14 +2355,14 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) if (data->smu_features[GNLD_AVFS].supported) { if (enable) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_AVFS].smu_feature_bitmap), "[avfs_control] Attempt to Enable AVFS feature Failed!", return -1); data->smu_features[GNLD_AVFS].enabled = true; } else { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_AVFS].smu_feature_id), "[avfs_control] Attempt to Disable AVFS feature Failed!", @@ -2423,11 +2385,11 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumTop32); - vega10_read_arg_from_smc(hwmgr->smumgr, &top32); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32); + vega10_read_arg_from_smc(hwmgr, &top32); - smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumBottom32); - vega10_read_arg_from_smc(hwmgr->smumgr, &bottom32); + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32); + vega10_read_arg_from_smc(hwmgr, &bottom32); serial_number = ((uint64_t)bottom32 << 32) | top32; @@ -2441,7 +2403,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) avfs_fuse_table->VFT2_b = fuse.VFT2_b; avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; - result = vega10_copy_table_to_smc(hwmgr->smumgr, + result = vega10_copy_table_to_smc(hwmgr, (uint8_t *)avfs_fuse_table, AVFSFUSETABLE); PP_ASSERT_WITH_CODE(!result, "Failed to upload FuseOVerride!", @@ -2580,14 +2542,14 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; if (0 != boot_up_values.usVddc) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFloorSocVoltage, (boot_up_values.usVddc * 4)); data->vbios_boot_state.bsoc_vddc_lock = true; } else { data->vbios_boot_state.bsoc_vddc_lock = false; } - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, (uint32_t)(data->vbios_boot_state.dcef_clock / 100)); } @@ -2613,7 +2575,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) vega10_populate_and_upload_avfs_fuse_override(hwmgr); - result = vega10_copy_table_to_smc(hwmgr->smumgr, + result = vega10_copy_table_to_smc(hwmgr, (uint8_t *)pp_table, PPTABLE); PP_ASSERT_WITH_CODE(!result, "Failed to upload PPtable!", return result); @@ -2636,7 +2598,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) pr_info("THERMAL Feature Already enabled!"); PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr->smumgr, + !vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_THERMAL].smu_feature_bitmap), "Enable THERMAL Feature Failed!", @@ -2656,7 +2618,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) pr_info("THERMAL Feature Already disabled!"); PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr->smumgr, + !vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_THERMAL].smu_feature_bitmap), "disable THERMAL Feature Failed!", @@ -2672,11 +2634,10 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_RegulatorHot)) { + if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { if (data->smu_features[GNLD_VR0HOT].supported) { PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr->smumgr, + !vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), "Attempt to Enable VR0 Hot feature Failed!", @@ -2685,7 +2646,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) } else { if (data->smu_features[GNLD_VR1HOT].supported) { PP_ASSERT_WITH_CODE( - !vega10_enable_smc_features(hwmgr->smumgr, + !vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), "Attempt to Enable VR0 Hot feature Failed!", @@ -2703,7 +2664,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) (struct vega10_hwmgr *)(hwmgr->backend); if (data->registry_data.ulv_support) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_ULV].smu_feature_bitmap), "Enable ULV Feature Failed!", return -1); @@ -2719,7 +2680,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) (struct vega10_hwmgr *)(hwmgr->backend); if (data->registry_data.ulv_support) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_ULV].smu_feature_bitmap), "disable ULV Feature Failed!", return -EINVAL); @@ -2735,7 +2696,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) (struct vega10_hwmgr *)(hwmgr->backend); if (data->smu_features[GNLD_DS_GFXCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), "Attempt to Enable DS_GFXCLK Feature Failed!", return -EINVAL); @@ -2743,7 +2704,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) } if (data->smu_features[GNLD_DS_SOCCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), "Attempt to Enable DS_SOCCLK Feature Failed!", return -EINVAL); @@ -2751,7 +2712,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) } if (data->smu_features[GNLD_DS_LCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), "Attempt to Enable DS_LCLK Feature Failed!", return -EINVAL); @@ -2759,7 +2720,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) } if (data->smu_features[GNLD_DS_DCEFCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), "Attempt to Enable DS_DCEFCLK Feature Failed!", return -EINVAL); @@ -2775,7 +2736,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) (struct vega10_hwmgr *)(hwmgr->backend); if (data->smu_features[GNLD_DS_GFXCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), "Attempt to disable DS_GFXCLK Feature Failed!", return -EINVAL); @@ -2783,7 +2744,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) } if (data->smu_features[GNLD_DS_SOCCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), "Attempt to disable DS_ Feature Failed!", return -EINVAL); @@ -2791,7 +2752,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) } if (data->smu_features[GNLD_DS_LCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), "Attempt to disable DS_LCLK Feature Failed!", return -EINVAL); @@ -2799,7 +2760,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) } if (data->smu_features[GNLD_DS_DCEFCLK].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), "Attempt to disable DS_DCEFCLK Feature Failed!", return -EINVAL); @@ -2817,7 +2778,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), "Attempt to disable LED DPM feature failed!", return -EINVAL); data->smu_features[GNLD_LED_DISPLAY].enabled = false; @@ -2835,7 +2796,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) } } - vega10_enable_smc_features(hwmgr->smumgr, false, feature_mask); + vega10_enable_smc_features(hwmgr, false, feature_mask); return 0; } @@ -2865,7 +2826,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) } } - if (vega10_enable_smc_features(hwmgr->smumgr, + if (vega10_enable_smc_features(hwmgr, true, feature_mask)) { for (i = 0; i < GNLD_DPM_MAX; i++) { if (data->smu_features[i].smu_feature_bitmap & @@ -2875,22 +2836,21 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) } if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), "Attempt to Enable LED DPM feature Failed!", return -EINVAL); data->smu_features[GNLD_LED_DISPLAY].enabled = true; } if (data->vbios_boot_state.bsoc_vddc_lock) { - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFloorSocVoltage, 0); data->vbios_boot_state.bsoc_vddc_lock = false; } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_Falcon_QuickTransition)) { + if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { if (data->smu_features[GNLD_ACDC].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), "Attempt to Enable DS_GFXCLK Feature Failed!", return -1); @@ -2907,13 +2867,13 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) (struct vega10_hwmgr *)(hwmgr->backend); int tmp_result, result = 0; - tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureTelemetry, data->config_telemetry); PP_ASSERT_WITH_CODE(!tmp_result, "Failed to configure telemetry!", return tmp_result); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0); tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1; @@ -2931,8 +2891,7 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to initialize SMC table!", result = tmp_result); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) { + if (PP_CAP(PHM_PlatformCaps_ThermalController)) { tmp_result = vega10_enable_thermal_protection(hwmgr); PP_ASSERT_WITH_CODE(!tmp_result, "Failed to enable thermal protection!", @@ -3167,8 +3126,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { + if (PP_CAP(PHM_PlatformCaps_StablePState)) { PP_ASSERT_WITH_CODE( data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, @@ -3233,10 +3191,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, disable_mclk_switching_for_frame_lock = phm_cap_enabled( hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); - disable_mclk_switching_for_vr = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_DisableMclkSwitchForVR); - force_mclk_high = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ForceMclkHigh); + disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); + force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); disable_mclk_switching = (info.display_count > 1) || disable_mclk_switching_for_frame_lock || @@ -3287,8 +3243,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, vega10_ps->performance_levels[1].mem_clock; } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_StablePState)) { + if (PP_CAP(PHM_PlatformCaps_StablePState)) { for (i = 0; i < vega10_ps->performance_level_count; i++) { vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk; @@ -3320,10 +3275,8 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co data->need_update_dpm_table = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinACSupport) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinDCSupport)) { + if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) || + PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) { for (i = 0; i < sclk_table->count; i++) { if (sclk == sclk_table->dpm_levels[i].value) break; @@ -3407,10 +3360,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( uint32_t dpm_count, clock_percent; uint32_t i; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinACSupport) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODNinDCSupport)) { + if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) || + PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) { if (!data->need_update_dpm_table && !data->apply_optimized_settings && @@ -3475,10 +3426,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( dpm_table-> gfx_table.dpm_levels[dpm_table->gfx_table.count - 1]. value = sclk; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinACSupport) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinDCSupport)) { + if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) || + PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) { /* Need to do calculation based on the golden DPM table * as the Heatmap GPU Clock axis is also based on * the default values @@ -3532,10 +3481,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( mem_table.dpm_levels[dpm_table->mem_table.count - 1]. value = mclk; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinACSupport) || - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_OD6PlusinDCSupport)) { + if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) || + PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) { PP_ASSERT_WITH_CODE( golden_dpm_table->mem_table.dpm_levels @@ -3727,7 +3674,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) if (data->smc_state_table.gfx_boot_level != data->dpm_table.gfx_table.dpm_state.soft_min_level) { PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_SetSoftMinGfxclkByIndex, data->smc_state_table.gfx_boot_level), "Failed to set soft min sclk index!", @@ -3743,14 +3690,14 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) { socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_SetSoftMinSocclkByIndex, socclk_idx), "Failed to set soft min uclk index!", return -EINVAL); } else { PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, data->smc_state_table.mem_boot_level), "Failed to set soft min uclk index!", @@ -3775,7 +3722,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) if (data->smc_state_table.gfx_max_level != data->dpm_table.gfx_table.dpm_state.soft_max_level) { PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_SetSoftMaxGfxclkByIndex, data->smc_state_table.gfx_max_level), "Failed to set soft max sclk index!", @@ -3789,7 +3736,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) if (data->smc_state_table.mem_max_level != data->dpm_table.mem_table.dpm_state.soft_max_level) { PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_SetSoftMaxUclkByIndex, data->smc_state_table.mem_max_level), "Failed to set soft max mclk index!", @@ -3848,7 +3795,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) (struct vega10_hwmgr *)(hwmgr->backend); if (data->smu_features[GNLD_DPM_VCE].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, enable, data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), "Attempt to Enable/Disable DPM VCE Failed!", @@ -3866,9 +3813,8 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) int result = 0; uint32_t low_sclk_interrupt_threshold = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification) - && (hwmgr->gfx_arbiter.sclk_threshold != + if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && + (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) { data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold; @@ -3879,7 +3825,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) cpu_to_le32(low_sclk_interrupt_threshold); /* This message will also enable SmcToHost Interrupt */ - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetLowGfxclkInterruptThreshold, (uint32_t)low_sclk_interrupt_threshold); } @@ -3915,7 +3861,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, "Failed to update SCLK threshold!", result = tmp_result); - result = vega10_copy_table_to_smc(hwmgr->smumgr, + result = vega10_copy_table_to_smc(hwmgr, (uint8_t *)pp_table, PPTABLE); PP_ASSERT_WITH_CODE(!result, "Failed to upload PPtable!", return result); @@ -3926,7 +3872,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, return 0; } -static int vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { struct pp_power_state *ps; struct vega10_power_state *vega10_ps; @@ -3948,7 +3894,7 @@ static int vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) [vega10_ps->performance_level_count - 1].gfx_clock; } -static int vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { struct pp_power_state *ps; struct vega10_power_state *vega10_ps; @@ -3975,12 +3921,12 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, { uint32_t value; - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr), "Failed to get current package power!", return -EINVAL); - vega10_read_arg_from_smc(hwmgr->smumgr, &value); + vega10_read_arg_from_smc(hwmgr, &value); /* power value is an integer */ query->average_gpu_power = value << 8; @@ -3997,25 +3943,25 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, switch (idx) { case AMDGPU_PP_SENSOR_GFX_SCLK: - ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentGfxclkIndex); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex); if (!ret) { - vega10_read_arg_from_smc(hwmgr->smumgr, &sclk_idx); + vega10_read_arg_from_smc(hwmgr, &sclk_idx); *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value; *size = 4; } break; case AMDGPU_PP_SENSOR_GFX_MCLK: - ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentUclkIndex); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex); if (!ret) { - vega10_read_arg_from_smc(hwmgr->smumgr, &mclk_idx); + vega10_read_arg_from_smc(hwmgr, &mclk_idx); *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; *size = 4; } break; case AMDGPU_PP_SENSOR_GPU_LOAD: - ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetAverageGfxActivity, 0); + ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0); if (!ret) { - vega10_read_arg_from_smc(hwmgr->smumgr, &activity_percent); + vega10_read_arg_from_smc(hwmgr, &activity_percent); *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; *size = 4; } @@ -4050,7 +3996,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_disp) { - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetUclkFastSwitch, has_disp ? 0 : 1); } @@ -4085,7 +4031,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, if (!result) { clk_request = (clk_freq << 16) | clk_select; - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_RequestDisplayClockByFreq, clk_request); } @@ -4155,7 +4101,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value; if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk, + hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, min_clocks.dcefClockInSR /100), "Attempt to set divider for DCEFCLK Failed!",); } else { @@ -4167,7 +4113,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( if (min_clocks.memoryClock != 0) { idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx); + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx); data->dpm_table.mem_table.dpm_state.soft_min_level= idx; } @@ -4270,28 +4216,23 @@ static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_fo return 0; } -static int vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) +static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) { - int result = 0; - switch (mode) { case AMD_FAN_CTRL_NONE: - result = vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100); + vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100); break; case AMD_FAN_CTRL_MANUAL: - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) - result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr); + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) + vega10_fan_ctrl_stop_smc_fan_control(hwmgr); break; case AMD_FAN_CTRL_AUTO: - result = vega10_fan_ctrl_set_static_mode(hwmgr, mode); - if (!result) - result = vega10_fan_ctrl_start_smc_fan_control(hwmgr); + if (!vega10_fan_ctrl_set_static_mode(hwmgr, mode)) + vega10_fan_ctrl_start_smc_fan_control(hwmgr); break; default: break; } - return result; } static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, @@ -4301,51 +4242,16 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, uint32_t sclk_mask = 0; uint32_t mclk_mask = 0; uint32_t soc_mask = 0; - uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; - - if (level == hwmgr->dpm_level) - return ret; - - if (!(hwmgr->dpm_level & profile_mode_mask)) { - /* enter profile mode, save current level, disable gfx cg*/ - if (level & profile_mode_mask) { - hwmgr->saved_dpm_level = hwmgr->dpm_level; - cgs_set_clockgating_state(hwmgr->device, - AMD_IP_BLOCK_TYPE_GFX, - AMD_CG_STATE_UNGATE); - } - } else { - /* exit profile mode, restore level, enable gfx cg*/ - if (!(level & profile_mode_mask)) { - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) - level = hwmgr->saved_dpm_level; - cgs_set_clockgating_state(hwmgr->device, - AMD_IP_BLOCK_TYPE_GFX, - AMD_CG_STATE_GATE); - } - } switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: ret = vega10_force_dpm_highest(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_LOW: ret = vega10_force_dpm_lowest(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_AUTO: ret = vega10_unforce_dpm_levels(hwmgr); - if (ret) - return ret; - hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: @@ -4354,27 +4260,25 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); if (ret) return ret; - hwmgr->dpm_level = level; vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); break; case AMD_DPM_FORCED_LEVEL_MANUAL: - hwmgr->dpm_level = level; - break; case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: default: break; } - if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); - else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) - vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); - - return 0; + if (!ret) { + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); + else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); + } + return ret; } -static int vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) +static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); @@ -4619,7 +4523,7 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); int i; - if (hwmgr->dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO | + if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO | AMD_DPM_FORCED_LEVEL_LOW | AMD_DPM_FORCED_LEVEL_HIGH)) return -EINVAL; @@ -4692,11 +4596,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, if (data->registry_data.sclk_dpm_key_disabled) break; - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex), "Attempt to get current sclk index Failed!", return -1); - PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr, &now), "Attempt to read sclk index Failed!", return -1); @@ -4710,11 +4614,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, if (data->registry_data.mclk_dpm_key_disabled) break; - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex), "Attempt to get current mclk index Failed!", return -1); - PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr, &now), "Attempt to read mclk index Failed!", return -1); @@ -4725,11 +4629,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, (i == now) ? "*" : ""); break; case PP_PCIE: - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex), "Attempt to get current mclk index Failed!", return -1); - PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr, &now), "Attempt to read mclk index Failed!", return -1); @@ -4757,7 +4661,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) if ((data->water_marks_bitmap & WaterMarksExist) && !(data->water_marks_bitmap & WaterMarksLoaded)) { - result = vega10_copy_table_to_smc(hwmgr->smumgr, + result = vega10_copy_table_to_smc(hwmgr, (uint8_t *)wm_table, WMTABLE); PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); data->water_marks_bitmap |= WaterMarksLoaded; @@ -4766,7 +4670,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) if (data->water_marks_bitmap & WaterMarksLoaded) { cgs_get_active_displays_info(hwmgr->device, &info); num_turned_on_displays = info.display_count; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, num_turned_on_displays); } @@ -4779,7 +4683,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) (struct vega10_hwmgr *)(hwmgr->backend); if (data->smu_features[GNLD_DPM_UVD].supported) { - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, enable, data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), "Attempt to Enable/Disable DPM UVD Failed!", @@ -4789,20 +4693,20 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) return 0; } -static int vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) +static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) { struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); data->vce_power_gated = bgate; - return vega10_enable_disable_vce_dpm(hwmgr, !bgate); + vega10_enable_disable_vce_dpm(hwmgr, !bgate); } -static int vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) +static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) { struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); data->uvd_power_gated = bgate; - return vega10_enable_disable_uvd_dpm(hwmgr, !bgate); + vega10_enable_disable_uvd_dpm(hwmgr, !bgate); } static inline bool vega10_are_power_levels_equal( @@ -4861,7 +4765,7 @@ vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmg if (data->display_timing.num_existing_displays != info.display_count) is_update_required = true; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { + if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr) is_update_required = true; } @@ -4878,8 +4782,7 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) "DPM is not running right now, no need to disable DPM!", return 0); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) + if (PP_CAP(PHM_PlatformCaps_ThermalController)) vega10_disable_thermal_protection(hwmgr); tmp_result = vega10_disable_power_containment(hwmgr); @@ -4967,7 +4870,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, if (!data->registry_data.sclk_dpm_key_disabled) PP_ASSERT_WITH_CODE( !smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_SetSoftMinGfxclkByIndex, sclk_idx), "Failed to set soft min sclk index!", @@ -4978,7 +4881,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr, if (!data->registry_data.mclk_dpm_key_disabled) PP_ASSERT_WITH_CODE( !smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, + hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, mclk_idx), "Failed to set soft min mclk index!", @@ -5091,6 +4994,38 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) return 0; } +static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr, + const void *info) +{ + struct cgs_irq_src_funcs *irq_src = + (struct cgs_irq_src_funcs *)info; + + if (hwmgr->thermal_controller.ucType == + ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 || + hwmgr->thermal_controller.ucType == + ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { + PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device, + 0xf, /* AMDGPU_IH_CLIENTID_THM */ + 0, 0, irq_src[0].set, irq_src[0].handler, hwmgr), + "Failed to register high thermal interrupt!", + return -EINVAL); + PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device, + 0xf, /* AMDGPU_IH_CLIENTID_THM */ + 1, 0, irq_src[1].set, irq_src[1].handler, hwmgr), + "Failed to register low thermal interrupt!", + return -EINVAL); + } + + /* Register CTF(GPIO_19) interrupt */ + PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device, + 0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */ + 83, 0, irq_src[2].set, irq_src[2].handler, hwmgr), + "Failed to register CTF thermal interrupt!", + return -EINVAL); + + return 0; +} + static const struct pp_hwmgr_func vega10_hwmgr_funcs = { .backend_init = vega10_hwmgr_backend_init, .backend_fini = vega10_hwmgr_backend_fini, @@ -5144,12 +5079,13 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = { .get_mclk_od = vega10_get_mclk_od, .set_mclk_od = vega10_set_mclk_od, .avfs_control = vega10_avfs_enable, + .register_internal_thermal_interrupt = vega10_register_thermal_interrupt, }; int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) { hwmgr->hwmgr_func = &vega10_hwmgr_funcs; hwmgr->pptable_func = &vega10_pptable_funcs; - pp_vega10_thermal_initialize(hwmgr); + return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c index e7fa67063cdc..d2f695692f77 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c @@ -854,99 +854,79 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) uint32_t en = (enable ? 1 : 0); uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0); - data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data); + if (PP_CAP(PHM_PlatformCaps_SQRamping)) { + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_SQ_CTRL0, DIDT_CTRL_EN, en); didt_block_info &= ~SQ_Enable_MASK; didt_block_info |= en << SQ_Enable_SHIFT; } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0); - data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data); + if (PP_CAP(PHM_PlatformCaps_DBRamping)) { + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_DB_CTRL0, DIDT_CTRL_EN, en); didt_block_info &= ~DB_Enable_MASK; didt_block_info |= en << DB_Enable_SHIFT; } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0); - data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data); + if (PP_CAP(PHM_PlatformCaps_TDRamping)) { + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_TD_CTRL0, DIDT_CTRL_EN, en); didt_block_info &= ~TD_Enable_MASK; didt_block_info |= en << TD_Enable_SHIFT; } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0); - data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data); + if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_TCP_CTRL0, DIDT_CTRL_EN, en); didt_block_info &= ~TCP_Enable_MASK; didt_block_info |= en << TCP_Enable_SHIFT; } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { - data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0); - data &= ~DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK; - data |= ((en << DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0, data); + if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { + CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, + DIDT_DBR_CTRL0, DIDT_CTRL_EN, en); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable)) { - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { + if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) { + if (PP_CAP(PHM_PlatformCaps_SQRamping)) { data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); - data &= ~DIDT_SQ_EDC_CTRL__EDC_EN_MASK; - data |= ((en << DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT) & DIDT_SQ_EDC_CTRL__EDC_EN_MASK); - data &= ~DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK; - data |= ((~en << DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK); + data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en); + data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { + if (PP_CAP(PHM_PlatformCaps_DBRamping)) { data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); - data &= ~DIDT_DB_EDC_CTRL__EDC_EN_MASK; - data |= ((en << DIDT_DB_EDC_CTRL__EDC_EN__SHIFT) & DIDT_DB_EDC_CTRL__EDC_EN_MASK); - data &= ~DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK; - data |= ((~en << DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK); + data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en); + data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { + if (PP_CAP(PHM_PlatformCaps_TDRamping)) { data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); - data &= ~DIDT_TD_EDC_CTRL__EDC_EN_MASK; - data |= ((en << DIDT_TD_EDC_CTRL__EDC_EN__SHIFT) & DIDT_TD_EDC_CTRL__EDC_EN_MASK); - data &= ~DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK; - data |= ((~en << DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK); + data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en); + data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) { + if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); - data &= ~DIDT_TCP_EDC_CTRL__EDC_EN_MASK; - data |= ((en << DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT) & DIDT_TCP_EDC_CTRL__EDC_EN_MASK); - data &= ~DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK; - data |= ((~en << DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK); + data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en); + data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { + if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); - data &= ~DIDT_DBR_EDC_CTRL__EDC_EN_MASK; - data |= ((en << DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT) & DIDT_DBR_EDC_CTRL__EDC_EN_MASK); - data &= ~DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK; - data |= ((~en << DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK); + data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en); + data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data); } } if (enable) { /* For Vega10, SMC does not support any mask yet. */ - result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); + result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!"); } } @@ -1040,10 +1020,10 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) cgs_enter_safe_mode(hwmgr->device, false); vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) + if (PP_CAP(PHM_PlatformCaps_GCEDC)) vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) + if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); return 0; @@ -1059,12 +1039,12 @@ static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) cgs_enter_safe_mode(hwmgr->device, false); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) { + if (PP_CAP(PHM_PlatformCaps_GCEDC)) { data = 0x00000000; cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) + if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); return 0; @@ -1159,12 +1139,12 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) { + if (PP_CAP(PHM_PlatformCaps_GCEDC)) { vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10); vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) + if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); return 0; @@ -1180,12 +1160,12 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) cgs_enter_safe_mode(hwmgr->device, false); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) { + if (PP_CAP(PHM_PlatformCaps_GCEDC)) { data = 0x00000000; cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data); } - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) + if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); return 0; @@ -1263,7 +1243,7 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) } if (0 == result) { - PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), + PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result); data->smu_features[GNLD_DIDT].enabled = true; } @@ -1310,7 +1290,7 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) } if (0 == result) { - PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), + PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result); data->smu_features[GNLD_DIDT].enabled = false; } @@ -1364,7 +1344,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) (struct vega10_hwmgr *)(hwmgr->backend); if (data->registry_data.enable_pkg_pwr_tracking_feature) - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetPptLimit, n); return 0; @@ -1381,16 +1361,15 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit); int result = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { + if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { if (data->smu_features[GNLD_PPT].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_PPT].smu_feature_bitmap), "Attempt to enable PPT feature Failed!", data->smu_features[GNLD_PPT].supported = false); if (data->smu_features[GNLD_TDC].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_TDC].smu_feature_bitmap), "Attempt to enable PPT feature Failed!", data->smu_features[GNLD_TDC].supported = false); @@ -1409,16 +1388,15 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { + if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { if (data->smu_features[GNLD_PPT].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_PPT].smu_feature_bitmap), "Attempt to disable PPT feature Failed!", data->smu_features[GNLD_PPT].supported = false); if (data->smu_features[GNLD_TDC].supported) - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_TDC].smu_feature_bitmap), "Attempt to disable PPT feature Failed!", data->smu_features[GNLD_TDC].supported = false); @@ -1430,7 +1408,7 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, uint32_t adjust_percent) { - return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_OverDriveSetPercentage, adjust_percent); } @@ -1438,8 +1416,7 @@ int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) { int adjust_percent, result = 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment)) { + if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? hwmgr->platform_descriptor.TDPAdjustment : diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c index d44243441d28..1feefac49ea9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c @@ -31,11 +31,11 @@ static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) { - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm), "Attempt to get current RPM from SMC Failed!", return -1); - PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr, current_rpm), "Attempt to read current RPM from SMC Failed!", return -1); @@ -54,8 +54,7 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, fan_speed_info->min_percent = 0; fan_speed_info->max_percent = 100; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_FanSpeedInTableIsRPM) && + if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && hwmgr->thermal_controller.fanInfo. ucTachometerPulsesPerRevolution) { fan_speed_info->supports_rpm_read = true; @@ -105,14 +104,15 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) if (hwmgr->thermal_controller.fanInfo.bNoFan) return -1; - if (data->smu_features[GNLD_FAN_CONTROL].supported) + if (data->smu_features[GNLD_FAN_CONTROL].supported) { result = vega10_get_current_rpm(hwmgr, speed); - else { + } else { uint32_t reg = soc15_get_register_offset(THM_HWID, 0, mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS); - tach_period = (cgs_read_register(hwmgr->device, - reg) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> - CG_TACH_STATUS__TACH_PERIOD__SHIFT; + tach_period = + CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_TACH_STATUS, + TACH_PERIOD); if (tach_period == 0) return -EINVAL; @@ -141,23 +141,20 @@ int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) if (hwmgr->fan_ctrl_is_in_default_mode) { hwmgr->fan_ctrl_default_mode = - (cgs_read_register(hwmgr->device, reg) & - CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> - CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; - hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) & - CG_FDO_CTRL2__TMIN_MASK) >> - CG_FDO_CTRL2__TMIN__SHIFT; + CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, FDO_PWM_MODE); + hwmgr->tmin = + CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, TMIN); hwmgr->fan_ctrl_is_in_default_mode = false; } cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_FDO_CTRL2__TMIN_MASK) | - (0 << CG_FDO_CTRL2__TMIN__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, TMIN, 0)); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) | - (mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, FDO_PWM_MODE, mode)); return 0; } @@ -176,14 +173,13 @@ int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) if (!hwmgr->fan_ctrl_is_in_default_mode) { cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) | - (hwmgr->fan_ctrl_default_mode << - CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, FDO_PWM_MODE, + hwmgr->fan_ctrl_default_mode)); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_FDO_CTRL2__TMIN_MASK) | - (hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, TMIN, + hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT)); hwmgr->fan_ctrl_is_in_default_mode = true; } @@ -203,7 +199,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr) if (data->smu_features[GNLD_FAN_CONTROL].supported) { PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( - hwmgr->smumgr, true, + hwmgr, true, data->smu_features[GNLD_FAN_CONTROL]. smu_feature_bitmap), "Attempt to Enable FAN CONTROL feature Failed!", @@ -220,7 +216,7 @@ static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr) if (data->smu_features[GNLD_FAN_CONTROL].supported) { PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( - hwmgr->smumgr, false, + hwmgr, false, data->smu_features[GNLD_FAN_CONTROL]. smu_feature_bitmap), "Attempt to Enable FAN CONTROL feature Failed!", @@ -279,16 +275,14 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, if (speed > 100) speed = 100; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) vega10_fan_ctrl_stop_smc_fan_control(hwmgr); reg = soc15_get_register_offset(THM_HWID, 0, mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1); - duty100 = (cgs_read_register(hwmgr->device, reg) & - CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> - CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; + duty100 = CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL1, FMAX_DUTY100); if (duty100 == 0) return -EINVAL; @@ -300,9 +294,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, reg = soc15_get_register_offset(THM_HWID, 0, mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) | - (duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } @@ -314,18 +307,13 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, */ int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) { - int result; - if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { - result = vega10_fan_ctrl_start_smc_fan_control(hwmgr); - } else - result = vega10_fan_ctrl_set_default_mode(hwmgr); - - return result; + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) + return vega10_fan_ctrl_start_smc_fan_control(hwmgr); + else + return vega10_fan_ctrl_set_default_mode(hwmgr); } /** @@ -342,12 +330,11 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) uint32_t reg; if (hwmgr->thermal_controller.fanInfo.bNoFan || - (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || - (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) + (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || + (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) return -1; - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr); if (!result) { @@ -356,9 +343,9 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) reg = soc15_get_register_offset(THM_HWID, 0, mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_TACH_STATUS__TACH_PERIOD_MASK) | - (tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_TACH_STATUS, TACH_PERIOD, + tach_period)); } return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM); } @@ -374,7 +361,7 @@ int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr) uint32_t reg; reg = soc15_get_register_offset(THM_HWID, 0, - mmCG_TACH_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS); + mmCG_MULT_THERMAL_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS); temp = cgs_read_register(hwmgr->device, reg); @@ -418,20 +405,10 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, val = cgs_read_register(hwmgr->device, reg); - val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK); - val |= (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT); - - val &= (~THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK); - val |= (1 << THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT); - - val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK); - val |= ((high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) - << THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT); - - val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK); - val |= ((low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) - << THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT); - + val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); + val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); + val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); + val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); cgs_write_register(hwmgr->device, reg, val); @@ -452,19 +429,16 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) reg = soc15_get_register_offset(THM_HWID, 0, mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_TACH_CTRL__EDGE_PER_REV_MASK) | - ((hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution - 1) << - CG_TACH_CTRL__EDGE_PER_REV__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_TACH_CTRL, EDGE_PER_REV, + hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1)); } reg = soc15_get_register_offset(THM_HWID, 0, mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) | - (0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28)); return 0; } @@ -484,7 +458,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) if (data->smu_features[GNLD_FW_CTF].enabled) printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n"); - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), "Attempt to Enable FW CTF feature Failed!", @@ -516,7 +490,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) printk("[Thermal_EnableAlert] FW CTF Already disabled!\n"); - PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), "Attempt to disable FW CTF feature Failed!", @@ -554,8 +528,7 @@ int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) * @param Result the last failure code * @return result from set temperature range routine */ -int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) +int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) { int ret; struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); @@ -573,7 +546,7 @@ int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, table->FanTargetTemperature = hwmgr->thermal_controller. advanceFanControlParameters.usTMax; - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanTemperatureTarget, (uint32_t)table->FanTargetTemperature); @@ -602,7 +575,7 @@ int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, table->FanStartTemp = hwmgr->thermal_controller. advanceFanControlParameters.usZeroRPMStartTemperature; - ret = vega10_copy_table_to_smc(hwmgr->smumgr, + ret = vega10_copy_table_to_smc(hwmgr, (uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE); if (ret) pr_info("Failed to update Fan Control Table in PPTable!"); @@ -619,123 +592,50 @@ int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, * @param Result the last failure code * @return result from set temperature range routine */ -int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) +int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) { /* If the fantable setup has failed we could have disabled * PHM_PlatformCaps_MicrocodeFanControl even after * this function was included in the table. * Make sure that we still think controlling the fan is OK. */ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_MicrocodeFanControl)) { + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) vega10_fan_ctrl_start_smc_fan_control(hwmgr); - } return 0; } -/** -* Set temperature range for high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from set temperature range routine -*/ -int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) + +int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr, + struct PP_TemperatureRange *range) { - struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input; + int ret = 0; if (range == NULL) return -EINVAL; - return vega10_thermal_set_temperature_range(hwmgr, range); -} - -/** -* Programs one-time setting registers -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from initialize thermal controller routine -*/ -int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return vega10_thermal_initialize(hwmgr); -} - -/** -* Enable high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from enable alert routine -*/ -int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return vega10_thermal_enable_alert(hwmgr); -} - -/** -* Disable high and low alerts -* @param hwmgr the address of the powerplay hardware manager. -* @param pInput the pointer to input data -* @param pOutput the pointer to output data -* @param pStorage the pointer to temporary storage -* @param Result the last failure code -* @return result from disable alert routine -*/ -static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - return vega10_thermal_disable_alert(hwmgr); -} + vega10_thermal_initialize(hwmgr); + ret = vega10_thermal_set_temperature_range(hwmgr, range); + if (ret) + return -EINVAL; -static struct phm_master_table_item -vega10_thermal_start_thermal_controller_master_list[] = { - { .tableFunction = tf_vega10_thermal_initialize }, - { .tableFunction = tf_vega10_thermal_set_temperature_range }, - { .tableFunction = tf_vega10_thermal_enable_alert }, + vega10_thermal_enable_alert(hwmgr); /* We should restrict performance levels to low before we halt the SMC. * On the other hand we are still in boot state when we do this * so it would be pointless. * If this assumption changes we have to revisit this table. */ - { .tableFunction = tf_vega10_thermal_setup_fan_table }, - { .tableFunction = tf_vega10_thermal_start_smc_fan_control }, - { } -}; + ret = vega10_thermal_setup_fan_table(hwmgr); + if (ret) + return -EINVAL; -static struct phm_master_table_header -vega10_thermal_start_thermal_controller_master = { - 0, - PHM_MasterTableFlag_None, - vega10_thermal_start_thermal_controller_master_list -}; + vega10_thermal_start_smc_fan_control(hwmgr); -static struct phm_master_table_item -vega10_thermal_set_temperature_range_master_list[] = { - { .tableFunction = tf_vega10_thermal_disable_alert }, - { .tableFunction = tf_vega10_thermal_set_temperature_range }, - { .tableFunction = tf_vega10_thermal_enable_alert }, - { } + return 0; }; -struct phm_master_table_header -vega10_thermal_set_temperature_range_master = { - 0, - PHM_MasterTableFlag_None, - vega10_thermal_set_temperature_range_master_list -}; + + int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) { @@ -745,32 +645,3 @@ int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) } return 0; } - -/** -* Initializes the thermal controller related functions -* in the Hardware Manager structure. -* @param hwmgr The address of the hardware manager. -* @exception Any error code from the low-level communication. -*/ -int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr) -{ - int result; - - result = phm_construct_table(hwmgr, - &vega10_thermal_set_temperature_range_master, - &(hwmgr->set_temperature_range)); - - if (!result) { - result = phm_construct_table(hwmgr, - &vega10_thermal_start_thermal_controller_master, - &(hwmgr->start_thermal_controller)); - if (result) - phm_destroy_table(hwmgr, - &(hwmgr->set_temperature_range)); - } - - if (!result) - hwmgr->fan_ctrl_is_in_default_mode = true; - return result; -} - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h index 776f3a2effc0..f34ce04cfd89 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h @@ -50,13 +50,6 @@ struct vega10_temperature { #define FDO_PWM_MODE_STATIC_RPM 5 -extern int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result); -extern int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result); -extern int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result); - extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr); extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, @@ -69,7 +62,6 @@ extern int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, extern int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); -extern int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr); extern int vega10_thermal_ctrl_uninitialize_thermal_controller( struct pp_hwmgr *hwmgr); extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, @@ -77,9 +69,10 @@ extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, extern int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); -extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr); extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr); -int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); +extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); + +extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr); #endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 07e9c0b5915d..435da2647727 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -31,7 +31,7 @@ #include "dm_pp_interface.h" extern const struct amd_ip_funcs pp_ip_funcs; -extern const struct amd_powerplay_funcs pp_dpm_funcs; +extern const struct amd_pm_funcs pp_dpm_funcs; #define PP_DPM_DISABLED 0xCCCC @@ -50,94 +50,12 @@ enum amd_pp_sensors { AMDGPU_PP_SENSOR_GPU_POWER, }; -enum amd_pp_event { - AMD_PP_EVENT_INITIALIZE = 0, - AMD_PP_EVENT_UNINITIALIZE, - AMD_PP_EVENT_POWER_SOURCE_CHANGE, - AMD_PP_EVENT_SUSPEND, - AMD_PP_EVENT_RESUME, - AMD_PP_EVENT_ENTER_REST_STATE, - AMD_PP_EVENT_EXIT_REST_STATE, - AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, - AMD_PP_EVENT_THERMAL_NOTIFICATION, - AMD_PP_EVENT_VBIOS_NOTIFICATION, - AMD_PP_EVENT_ENTER_THERMAL_STATE, - AMD_PP_EVENT_EXIT_THERMAL_STATE, - AMD_PP_EVENT_ENTER_FORCED_STATE, - AMD_PP_EVENT_EXIT_FORCED_STATE, - AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE, - AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE, - AMD_PP_EVENT_ENTER_SCREEN_SAVER, - AMD_PP_EVENT_EXIT_SCREEN_SAVER, - AMD_PP_EVENT_VPU_RECOVERY_BEGIN, - AMD_PP_EVENT_VPU_RECOVERY_END, - AMD_PP_EVENT_ENABLE_POWER_PLAY, - AMD_PP_EVENT_DISABLE_POWER_PLAY, - AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL, - AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE, - AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE, - AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE, - AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE, - AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST, - AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST, - AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE, - AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE, - AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING, - AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING, - AMD_PP_EVENT_ENABLE_CGPG, - AMD_PP_EVENT_DISABLE_CGPG, - AMD_PP_EVENT_ENTER_TEXT_MODE, - AMD_PP_EVENT_EXIT_TEXT_MODE, - AMD_PP_EVENT_VIDEO_START, - AMD_PP_EVENT_VIDEO_STOP, - AMD_PP_EVENT_ENABLE_USER_STATE, - AMD_PP_EVENT_DISABLE_USER_STATE, - AMD_PP_EVENT_READJUST_POWER_STATE, - AMD_PP_EVENT_START_INACTIVITY, - AMD_PP_EVENT_STOP_INACTIVITY, - AMD_PP_EVENT_LINKED_ADAPTERS_READY, - AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE, - AMD_PP_EVENT_COMPLETE_INIT, - AMD_PP_EVENT_CRITICAL_THERMAL_FAULT, - AMD_PP_EVENT_BACKLIGHT_CHANGED, - AMD_PP_EVENT_ENABLE_VARI_BRIGHT, - AMD_PP_EVENT_DISABLE_VARI_BRIGHT, - AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS, - AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS, - AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL, - AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT, - AMD_PP_EVENT_SCREEN_ON, - AMD_PP_EVENT_SCREEN_OFF, - AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE, - AMD_PP_EVENT_ENTER_ULP_STATE, - AMD_PP_EVENT_EXIT_ULP_STATE, - AMD_PP_EVENT_REGISTER_IP_STATE, - AMD_PP_EVENT_UNREGISTER_IP_STATE, - AMD_PP_EVENT_ENTER_MGPU_MODE, - AMD_PP_EVENT_EXIT_MGPU_MODE, - AMD_PP_EVENT_ENTER_MULTI_GPU_MODE, - AMD_PP_EVENT_PRE_SUSPEND, - AMD_PP_EVENT_PRE_RESUME, - AMD_PP_EVENT_ENTER_BACOS, - AMD_PP_EVENT_EXIT_BACOS, - AMD_PP_EVENT_RESUME_BACO, - AMD_PP_EVENT_RESET_BACO, - AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS, - AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS, - AMD_PP_EVENT_START_COMPUTE_APPLICATION, - AMD_PP_EVENT_STOP_COMPUTE_APPLICATION, - AMD_PP_EVENT_REDUCE_POWER_LIMIT, - AMD_PP_EVENT_ENTER_FRAME_LOCK, - AMD_PP_EVENT_EXIT_FRAME_LOOCK, - AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO, - AMD_PP_EVENT_LONG_IDLE_ENTER_BACO, - AMD_PP_EVENT_LONG_IDLE_EXIT_BACO, - AMD_PP_EVENT_HIBERNATE, - AMD_PP_EVENT_CONNECTED_STANDBY, - AMD_PP_EVENT_ENTER_SELF_REFRESH, - AMD_PP_EVENT_EXIT_SELF_REFRESH, - AMD_PP_EVENT_START_AVFS_BTC, - AMD_PP_EVENT_MAX +enum amd_pp_task { + AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, + AMD_PP_TASK_ENABLE_USER_STATE, + AMD_PP_TASK_READJUST_POWER_STATE, + AMD_PP_TASK_COMPLETE_INIT, + AMD_PP_TASK_MAX }; struct amd_pp_init { @@ -295,12 +213,6 @@ enum { PP_GROUP_MAX }; -enum pp_clock_type { - PP_SCLK, - PP_MCLK, - PP_PCIE, -}; - struct pp_states_info { uint32_t nums; uint32_t states[16]; @@ -355,49 +267,10 @@ struct pp_display_clock_request { support << PP_STATE_SUPPORT_SHIFT |\ state << PP_STATE_SHIFT) -struct amd_powerplay_funcs { - int (*get_temperature)(void *handle); - int (*load_firmware)(void *handle); - int (*wait_for_fw_loading_complete)(void *handle); - int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); - enum amd_dpm_forced_level (*get_performance_level)(void *handle); - enum amd_pm_state_type (*get_current_power_state)(void *handle); - int (*get_sclk)(void *handle, bool low); - int (*get_mclk)(void *handle, bool low); - int (*powergate_vce)(void *handle, bool gate); - int (*powergate_uvd)(void *handle, bool gate); - int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id, - void *input, void *output); - int (*set_fan_control_mode)(void *handle, uint32_t mode); - int (*get_fan_control_mode)(void *handle); - int (*set_fan_speed_percent)(void *handle, uint32_t percent); - int (*get_fan_speed_percent)(void *handle, uint32_t *speed); - int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); - int (*get_pp_num_states)(void *handle, struct pp_states_info *data); - int (*get_pp_table)(void *handle, char **table); - int (*set_pp_table)(void *handle, const char *buf, size_t size); - int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); - int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); - int (*get_sclk_od)(void *handle); - int (*set_sclk_od)(void *handle, uint32_t value); - int (*get_mclk_od)(void *handle); - int (*set_mclk_od)(void *handle, uint32_t value); - int (*read_sensor)(void *handle, int idx, void *value, int *size); - struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx); - int (*reset_power_profile_state)(void *handle, - struct amd_pp_profile *request); - int (*get_power_profile_state)(void *handle, - struct amd_pp_profile *query); - int (*set_power_profile_state)(void *handle, - struct amd_pp_profile *request); - int (*switch_power_profile)(void *handle, - enum amd_pp_profile_type type); -}; - struct amd_powerplay { void *pp_handle; const struct amd_ip_funcs *ip_funcs; - const struct amd_powerplay_funcs *pp_funcs; + const struct amd_pm_funcs *pp_funcs; }; int amd_powerplay_create(struct amd_pp_init *pp_init, diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h b/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h deleted file mode 100644 index b9d84de8a44d..000000000000 --- a/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _EVENT_MANAGER_H_ -#define _EVENT_MANAGER_H_ - -#include "power_state.h" -#include "pp_power_source.h" -#include "hardwaremanager.h" -#include "pp_asicblocks.h" - -struct pp_eventmgr; -enum amd_pp_event; - -enum PEM_EventDataValid { - PEM_EventDataValid_RequestedStateID = 0, - PEM_EventDataValid_RequestedUILabel, - PEM_EventDataValid_NewPowerState, - PEM_EventDataValid_RequestedPowerSource, - PEM_EventDataValid_RequestedClocks, - PEM_EventDataValid_CurrentTemperature, - PEM_EventDataValid_AsicBlocks, - PEM_EventDataValid_ODParameters, - PEM_EventDataValid_PXAdapterPrefs, - PEM_EventDataValid_PXUserPrefs, - PEM_EventDataValid_PXSwitchReason, - PEM_EventDataValid_PXSwitchPhase, - PEM_EventDataValid_HdVideo, - PEM_EventDataValid_BacklightLevel, - PEM_EventDatavalid_VariBrightParams, - PEM_EventDataValid_VariBrightLevel, - PEM_EventDataValid_VariBrightImmediateChange, - PEM_EventDataValid_PercentWhite, - PEM_EventDataValid_SdVideo, - PEM_EventDataValid_HTLinkChangeReason, - PEM_EventDataValid_HWBlocks, - PEM_EventDataValid_RequestedThermalState, - PEM_EventDataValid_MvcVideo, - PEM_EventDataValid_Max -}; - -typedef enum PEM_EventDataValid PEM_EventDataValid; - -/* Number of bits in ULONG variable */ -#define PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD (sizeof(unsigned long)*8) - -/* Number of ULONG entries used by event data valid bits */ -#define PEM_MAX_NUM_EVENTDATAVALID_ULONG_ENTRIES \ - ((PEM_EventDataValid_Max + PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD - 1) / \ - PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD) - -static inline void pem_set_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field) -{ - fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] |= - (1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)); -} - -static inline void pem_unset_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field) -{ - fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] &= - ~(1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)); -} - -static inline unsigned long pem_is_event_data_valid(const unsigned long *fields, PEM_EventDataValid valid_field) -{ - return fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] & - (1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)); -} - -struct pem_event_data { - unsigned long valid_fields[100]; - unsigned long requested_state_id; - enum PP_StateUILabel requested_ui_label; - struct pp_power_state *pnew_power_state; - enum pp_power_source requested_power_source; - struct PP_Clocks requested_clocks; - bool skip_state_adjust_rules; - struct phm_asic_blocks asic_blocks; - /* to doPP_ThermalState requestedThermalState; - enum ThermalStateRequestSrc requestThermalStateSrc; - PP_Temperature currentTemperature;*/ - -}; - -int pem_handle_event(struct pp_eventmgr *eventmgr, enum amd_pp_event event, - struct pem_event_data *event_data); - -bool pem_is_hw_access_blocked(struct pp_eventmgr *eventmgr); - -#endif /* _EVENT_MANAGER_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h deleted file mode 100644 index 7bd8a7e57080..000000000000 --- a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _EVENTMGR_H_ -#define _EVENTMGR_H_ - -#include <linux/mutex.h> -#include "pp_instance.h" -#include "hardwaremanager.h" -#include "eventmanager.h" -#include "pp_feature.h" -#include "pp_power_source.h" -#include "power_state.h" - -typedef int (*pem_event_action)(struct pp_eventmgr *eventmgr, - struct pem_event_data *event_data); - -struct action_chain { - const char *description; /* action chain description for debugging purpose */ - const pem_event_action * const *action_chain; /* pointer to chain of event actions */ -}; - -struct pem_power_source_ui_state_info { - enum PP_StateUILabel current_ui_label; - enum PP_StateUILabel default_ui_lable; - unsigned long configurable_ui_mapping; -}; - -struct pp_clock_range { - uint32_t min_sclk_khz; - uint32_t max_sclk_khz; - - uint32_t min_mclk_khz; - uint32_t max_mclk_khz; - - uint32_t min_vclk_khz; - uint32_t max_vclk_khz; - - uint32_t min_dclk_khz; - uint32_t max_dclk_khz; - - uint32_t min_aclk_khz; - uint32_t max_aclk_khz; - - uint32_t min_eclk_khz; - uint32_t max_eclk_khz; -}; - -enum pp_state { - UNINITIALIZED, - INACTIVE, - ACTIVE -}; - -enum pp_ring_index { - PP_RING_TYPE_GFX_INDEX = 0, - PP_RING_TYPE_DMA_INDEX, - PP_RING_TYPE_DMA1_INDEX, - PP_RING_TYPE_UVD_INDEX, - PP_RING_TYPE_VCE0_INDEX, - PP_RING_TYPE_VCE1_INDEX, - PP_RING_TYPE_CP1_INDEX, - PP_RING_TYPE_CP2_INDEX, - PP_NUM_RINGS, -}; - -struct pp_request { - uint32_t flags; - uint32_t sclk; - uint32_t sclk_throttle; - uint32_t mclk; - uint32_t vclk; - uint32_t dclk; - uint32_t eclk; - uint32_t aclk; - uint32_t iclk; - uint32_t vp8clk; - uint32_t rsv[32]; -}; - -struct pp_eventmgr { - struct pp_hwmgr *hwmgr; - struct pp_smumgr *smumgr; - - struct pp_feature_info features[PP_Feature_Max]; - const struct action_chain *event_chain[AMD_PP_EVENT_MAX]; - struct phm_platform_descriptor *platform_descriptor; - struct pp_clock_range clock_range; - enum pp_power_source current_power_source; - struct pem_power_source_ui_state_info ui_state_info[PP_PowerSource_Max]; - enum pp_state states[PP_NUM_RINGS]; - struct pp_request hi_req; - struct list_head context_list; - struct mutex lock; - bool block_adjust_power_state; - bool enable_cg; - bool enable_gfx_cgpg; - int (*pp_eventmgr_init)(struct pp_eventmgr *eventmgr); - void (*pp_eventmgr_fini)(struct pp_eventmgr *eventmgr); -}; - -int eventmgr_early_init(struct pp_instance *handle); - -#endif /* _EVENTMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h index a4c8b09b6f14..57a0467b7267 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h @@ -283,6 +283,8 @@ static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); } +#define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c)) + #define PP_PCIEGenInvalid 0xffff enum PP_PCIEGen { PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */ @@ -295,7 +297,7 @@ typedef enum PP_PCIEGen PP_PCIEGen; #define PP_Min_PCIEGen PP_PCIEGen1 #define PP_Max_PCIEGen PP_PCIEGen3 #define PP_Min_PCIELane 1 -#define PP_Max_PCIELane 32 +#define PP_Max_PCIELane 16 enum phm_clock_Type { PHM_DispClock = 1, @@ -373,8 +375,6 @@ struct phm_odn_clock_levels { extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr); extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr); -extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate); -extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate); extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr); extern int phm_setup_asic(struct pp_hwmgr *hwmgr); extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr); diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 91b0105e8240..126b44d47a99 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -32,6 +32,7 @@ #include "ppatomctrl.h" #include "hwmgr_ppt.h" #include "power_state.h" +#include "cgs_linux.h" struct pp_instance; struct pp_hwmgr; @@ -61,10 +62,6 @@ struct vi_dpm_table { struct vi_dpm_level dpm_level[1]; }; -enum PP_Result { - PP_Result_TableImmediateExit = 0x13, -}; - #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 #define PCIE_PERF_REQ_GEN1 2 @@ -103,17 +100,6 @@ enum PHM_BackEnd_Magic { PHM_Rv_Magic = 0x20161121 }; - -#define PHM_PCIE_POWERGATING_TARGET_GFX 0 -#define PHM_PCIE_POWERGATING_TARGET_DDI 1 -#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2 -#define PHM_PCIE_POWERGATING_TARGET_PHY 3 - -typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result); - -typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr); - struct phm_set_power_state_input { const struct pp_hw_power_state *pcurrent_state; const struct pp_hw_power_state *pnew_state; @@ -149,30 +135,6 @@ struct phm_gfx_arbiter { uint32_t fclk; }; -/* Entries in the master tables */ -struct phm_master_table_item { - phm_check_function isFunctionNeededInRuntimeTable; - phm_table_function tableFunction; -}; - -enum phm_master_table_flag { - PHM_MasterTableFlag_None = 0, - PHM_MasterTableFlag_ExitOnError = 1, -}; - -/* The header of the master tables */ -struct phm_master_table_header { - uint32_t storage_size; - uint32_t flags; - const struct phm_master_table_item *master_list; -}; - -struct phm_runtime_table_header { - uint32_t storage_size; - bool exit_error; - phm_table_function *function_list; -}; - struct phm_clock_array { uint32_t count; uint32_t values[1]; @@ -216,19 +178,6 @@ struct phm_phase_shedding_limits_record { uint32_t Mclk; }; - -extern int phm_dispatch_table(struct pp_hwmgr *hwmgr, - struct phm_runtime_table_header *rt_table, - void *input, void *output); - -extern int phm_construct_table(struct pp_hwmgr *hwmgr, - const struct phm_master_table_header *master_table, - struct phm_runtime_table_header *rt_table); - -extern int phm_destroy_table(struct pp_hwmgr *hwmgr, - struct phm_runtime_table_header *rt_table); - - struct phm_uvd_clock_voltage_dependency_record { uint32_t vclk; uint32_t dclk; @@ -286,6 +235,39 @@ struct phm_vce_clock_voltage_dependency_table { struct phm_vce_clock_voltage_dependency_record entries[1]; }; +struct pp_smumgr_func { + int (*smu_init)(struct pp_hwmgr *hwmgr); + int (*smu_fini)(struct pp_hwmgr *hwmgr); + int (*start_smu)(struct pp_hwmgr *hwmgr); + int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr, + uint32_t firmware); + int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr); + int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr, + uint32_t firmware); + int (*get_argument)(struct pp_hwmgr *hwmgr); + int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg); + int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr, + uint16_t msg, uint32_t parameter); + int (*download_pptable_settings)(struct pp_hwmgr *hwmgr, + void **table); + int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr); + int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); + int (*process_firmware_header)(struct pp_hwmgr *hwmgr); + int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); + int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); + int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); + int (*init_smc_table)(struct pp_hwmgr *hwmgr); + int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); + int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); + int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); + uint32_t (*get_offsetof)(uint32_t type, uint32_t member); + uint32_t (*get_mac_definition)(uint32_t value); + bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); + int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request); + bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); +}; + struct pp_hwmgr_func { int (*backend_init)(struct pp_hwmgr *hw_mgr); int (*backend_fini)(struct pp_hwmgr *hw_mgr); @@ -311,10 +293,10 @@ struct pp_hwmgr_func { unsigned long, struct pp_power_state *); int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); int (*powerdown_uvd)(struct pp_hwmgr *hwmgr); - int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); - int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); - int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); - int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); + void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); + void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); + uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); + uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); int (*power_state_set)(struct pp_hwmgr *hwmgr, const void *state); int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr); @@ -328,8 +310,8 @@ struct pp_hwmgr_func { int (*get_temperature)(struct pp_hwmgr *hwmgr); int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); - int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); - int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); + void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); + uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); @@ -378,6 +360,9 @@ struct pp_hwmgr_func { struct amd_pp_profile *request); int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable); int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr); + int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count); + int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock); + int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range); }; struct pp_table_func { @@ -745,7 +730,7 @@ struct pp_hwmgr { enum amd_dpm_forced_level dpm_level; enum amd_dpm_forced_level saved_dpm_level; - bool block_hw_access; + enum amd_dpm_forced_level request_dpm_level; struct phm_gfx_arbiter gfx_arbiter; struct phm_acp_arbiter acp_arbiter; struct phm_uvd_arbiter uvd_arbiter; @@ -754,19 +739,17 @@ struct pp_hwmgr { void *pptable; struct phm_platform_descriptor platform_descriptor; void *backend; + + void *smu_backend; + const struct pp_smumgr_func *smumgr_funcs; + bool is_kicker; + bool reload_fw; + enum PP_DAL_POWERLEVEL dal_power_level; struct phm_dynamic_state_info dyn_state; - struct phm_runtime_table_header setup_asic; - struct phm_runtime_table_header power_down_asic; - struct phm_runtime_table_header disable_dynamic_state_management; - struct phm_runtime_table_header enable_dynamic_state_management; - struct phm_runtime_table_header set_power_state; - struct phm_runtime_table_header enable_clock_power_gatings; - struct phm_runtime_table_header display_configuration_changed; - struct phm_runtime_table_header start_thermal_controller; - struct phm_runtime_table_header set_temperature_range; const struct pp_hwmgr_func *hwmgr_func; const struct pp_table_func *pptable_func; + struct pp_power_state *ps; enum pp_power_source power_source; uint32_t num_ps; @@ -784,26 +767,44 @@ struct pp_hwmgr { struct amd_pp_display_configuration display_config; uint32_t feature_mask; - /* power profile */ + /* UMD Pstate */ struct amd_pp_profile gfx_power_profile; struct amd_pp_profile compute_power_profile; struct amd_pp_profile default_gfx_power_profile; struct amd_pp_profile default_compute_power_profile; enum amd_pp_profile_type current_power_profile; + bool en_umd_pstate; +}; + +struct cgs_irq_src_funcs { + cgs_irq_source_set_func_t set; + cgs_irq_handler_func_t handler; }; extern int hwmgr_early_init(struct pp_instance *handle); extern int hwmgr_hw_init(struct pp_instance *handle); extern int hwmgr_hw_fini(struct pp_instance *handle); +extern int hwmgr_hw_suspend(struct pp_instance *handle); +extern int hwmgr_hw_resume(struct pp_instance *handle); +extern int hwmgr_handle_task(struct pp_instance *handle, + enum amd_pp_task task_id, + void *input, void *output); extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, uint32_t value, uint32_t mask); -extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, +extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, uint32_t indirect_port, uint32_t index, uint32_t value, uint32_t mask); +extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, + uint32_t index, + uint32_t value, uint32_t mask); +extern int phm_wait_for_indirect_register_unequal( + struct pp_hwmgr *hwmgr, + uint32_t indirect_port, uint32_t index, + uint32_t value, uint32_t mask); extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr); @@ -888,5 +889,58 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) +#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ + phm_wait_for_indirect_register_unequal(hwmgr, \ + mm##port##_INDEX, index, value, mask) + +#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ + PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) + +#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ + PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ + (fieldval) << PHM_FIELD_SHIFT(reg, field), \ + PHM_FIELD_MASK(reg, field) ) + + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ + port, index, value, mask) \ + phm_wait_for_indirect_register_unequal(hwmgr, \ + mm##port##_INDEX_11, index, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ + (fieldval) << PHM_FIELD_SHIFT(reg, field), \ + PHM_FIELD_MASK(reg, field)) + + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \ + port, index, value, mask) \ + phm_wait_on_indirect_register(hwmgr, \ + mm##port##_INDEX_11, index, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \ + (fieldval) << PHM_FIELD_SHIFT(reg, field), \ + PHM_FIELD_MASK(reg, field)) + +#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ + index, value, mask) \ + phm_wait_for_register_unequal(hwmgr, \ + index, value, mask) + +#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ + PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \ + mm##reg, value, mask) + +#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ + PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \ + (fieldval) << PHM_FIELD_SHIFT(reg, field), \ + PHM_FIELD_MASK(reg, field)) #endif /* _HWMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h index 4c3b537a714f..25fb1460a194 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h @@ -23,9 +23,7 @@ #ifndef _PP_INSTANCE_H_ #define _PP_INSTANCE_H_ -#include "smumgr.h" #include "hwmgr.h" -#include "eventmgr.h" #define PP_VALID 0x1F1F1F1F @@ -36,9 +34,7 @@ struct pp_instance { bool pm_en; uint32_t feature_mask; void *device; - struct pp_smumgr *smu_mgr; struct pp_hwmgr *hwmgr; - struct pp_eventmgr *eventmgr; struct mutex pp_lock; }; diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h index f6d6c61f796a..2818c98ff5ca 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h @@ -315,10 +315,12 @@ typedef struct { uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS]; GbVdroopTable_t AcgBtcGbVdroopTable; QuadraticInt_t AcgAvfsGb; - uint32_t Reserved[4]; + + /* ACG Frequency Table, in Mhz */ + uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS]; /* Padding - ignore */ - uint32_t MmHubPadding[7]; /* SMU internal use */ + uint32_t MmHubPadding[3]; /* SMU internal use */ } PPTable_t; diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h index 5d61cc9d4554..7c9aba81cd6a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h @@ -23,23 +23,13 @@ #ifndef _SMUMGR_H_ #define _SMUMGR_H_ #include <linux/types.h> -#include "pp_instance.h" #include "amd_powerplay.h" - -struct pp_smumgr; -struct pp_instance; -struct pp_hwmgr; +#include "hwmgr.h" #define smu_lower_32_bits(n) ((uint32_t)(n)) #define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16)) -extern const struct pp_smumgr_func cz_smu_funcs; -extern const struct pp_smumgr_func iceland_smu_funcs; -extern const struct pp_smumgr_func tonga_smu_funcs; -extern const struct pp_smumgr_func fiji_smu_funcs; -extern const struct pp_smumgr_func polaris10_smu_funcs; -extern const struct pp_smumgr_func vega10_smu_funcs; -extern const struct pp_smumgr_func rv_smu_funcs; + enum AVFS_BTC_STATUS { AVFS_BTC_BOOT = 0, @@ -100,216 +90,44 @@ enum SMU_MAC_DEFINITION { SMU_UVD_MCLK_HANDSHAKE_DISABLE, }; +extern int smum_get_argument(struct pp_hwmgr *hwmgr); -struct pp_smumgr_func { - int (*smu_init)(struct pp_smumgr *smumgr); - int (*smu_fini)(struct pp_smumgr *smumgr); - int (*start_smu)(struct pp_smumgr *smumgr); - int (*check_fw_load_finish)(struct pp_smumgr *smumgr, - uint32_t firmware); - int (*request_smu_load_fw)(struct pp_smumgr *smumgr); - int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr, - uint32_t firmware); - int (*get_argument)(struct pp_smumgr *smumgr); - int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg); - int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr, - uint16_t msg, uint32_t parameter); - int (*download_pptable_settings)(struct pp_smumgr *smumgr, - void **table); - int (*upload_pptable_settings)(struct pp_smumgr *smumgr); - int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); - int (*process_firmware_header)(struct pp_hwmgr *hwmgr); - int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); - int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); - int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); - int (*init_smc_table)(struct pp_hwmgr *hwmgr); - int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); - int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); - int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); - uint32_t (*get_offsetof)(uint32_t type, uint32_t member); - uint32_t (*get_mac_definition)(uint32_t value); - bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); - int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr, - struct amd_pp_profile *request); - bool (*is_hw_avfs_present)(struct pp_smumgr *smumgr); -}; - -struct pp_smumgr { - uint32_t chip_family; - uint32_t chip_id; - void *device; - void *backend; - uint32_t usec_timeout; - bool reload_fw; - const struct pp_smumgr_func *smumgr_funcs; - bool is_kicker; -}; - -extern int smum_early_init(struct pp_instance *handle); +extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table); -extern int smum_get_argument(struct pp_smumgr *smumgr); +extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr); -extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table); +extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg); -extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr); - -extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); - -extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, +extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter); -extern int smum_wait_on_register(struct pp_smumgr *smumgr, - uint32_t index, uint32_t value, uint32_t mask); - -extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, - uint32_t index, uint32_t value, uint32_t mask); - -extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr, - uint32_t indirect_port, uint32_t index, - uint32_t value, uint32_t mask); - - -extern void smum_wait_for_indirect_register_unequal( - struct pp_smumgr *smumgr, - uint32_t indirect_port, uint32_t index, - uint32_t value, uint32_t mask); - extern int smu_allocate_memory(void *device, uint32_t size, enum cgs_gpu_mem_type type, uint32_t byte_align, uint64_t *mc_addr, void **kptr, void *handle); extern int smu_free_memory(void *device, void *handle); -extern int vega10_smum_init(struct pp_smumgr *smumgr); extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr); extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type); extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr); -extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result); -extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result); +extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr); +extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr); extern int smum_init_smc_table(struct pp_hwmgr *hwmgr); extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr); extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr); -extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, +extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member); -extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value); +extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value); extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr); extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, struct amd_pp_profile *request); -extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr); - -#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT - -#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK - -#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ - port, index, value, mask) \ - smum_wait_on_indirect_register(smumgr, \ - mm##port##_INDEX, index, value, mask) - -#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \ - SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) - -#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ - SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ - SMUM_FIELD_MASK(reg, field) ) - -#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ - index, value, mask) \ - smum_wait_for_register_unequal(smumgr, \ - index, value, mask) - -#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \ - SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ - mm##reg, value, mask) - -#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \ - SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \ - (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ - SMUM_FIELD_MASK(reg, field)) - -#define SMUM_GET_FIELD(value, reg, field) \ - (((value) & SMUM_FIELD_MASK(reg, field)) \ - >> SMUM_FIELD_SHIFT(reg, field)) - -#define SMUM_READ_FIELD(device, reg, field) \ - SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) - -#define SMUM_SET_FIELD(value, reg, field, field_val) \ - (((value) & ~SMUM_FIELD_MASK(reg, field)) | \ - (SMUM_FIELD_MASK(reg, field) & ((field_val) << \ - SMUM_FIELD_SHIFT(reg, field)))) - -#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \ - SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field) - -#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ - port, index, value, mask) \ - smum_wait_on_indirect_register(smumgr, \ - mm##port##_INDEX_0, index, value, mask) - -#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ - port, index, value, mask) \ - smum_wait_for_indirect_register_unequal(smumgr, \ - mm##port##_INDEX_0, index, value, mask) - - -#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \ - SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) - -#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \ - SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) - - -/*Operations on named fields.*/ - -#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ - SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field) - -#define SMUM_WRITE_FIELD(device, reg, field, fieldval) \ - cgs_write_register(device, mm##reg, \ - SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval)) - -#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ - cgs_write_ind_register(device, port, ix##reg, \ - SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field, fieldval)) - - -#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ - cgs_write_ind_register(device, port, ix##reg, \ - SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ - reg, field, fieldval)) - - -#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ - SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \ - (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ - SMUM_FIELD_MASK(reg, field)) - -#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \ - SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \ - (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ - SMUM_FIELD_MASK(reg, field)) - -#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \ - smum_wait_for_indirect_register_unequal(smumgr, \ - mm##port##_INDEX, index, value, mask) - -#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \ - SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) +extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); -#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \ - SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ - SMUM_FIELD_MASK(reg, field) ) #endif diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 1703bbefbfd5..a423c0a85129 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -4,7 +4,7 @@ SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \ polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \ - smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o + smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o ci_smc.o ci_smumgr.o AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c new file mode 100644 index 000000000000..9ee14315dce7 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c @@ -0,0 +1,2753 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/fb.h> +#include "linux/delay.h" +#include <linux/types.h> + +#include "smumgr.h" +#include "pp_debug.h" +#include "ci_smc.h" +#include "ci_smumgr.h" +#include "ppsmc.h" +#include "smu7_hwmgr.h" +#include "hardwaremanager.h" +#include "ppatomctrl.h" +#include "cgs_common.h" +#include "atombios.h" +#include "pppcielanes.h" + +#include "smu/smu_7_0_1_d.h" +#include "smu/smu_7_0_1_sh_mask.h" + +#include "dce/dce_8_0_d.h" +#include "dce/dce_8_0_sh_mask.h" + +#include "bif/bif_4_1_d.h" +#include "bif/bif_4_1_sh_mask.h" + +#include "gca/gfx_7_2_d.h" +#include "gca/gfx_7_2_sh_mask.h" + +#include "gmc/gmc_7_1_d.h" +#include "gmc/gmc_7_1_sh_mask.h" + +#include "processpptables.h" + +#define MC_CG_ARB_FREQ_F0 0x0a +#define MC_CG_ARB_FREQ_F1 0x0b +#define MC_CG_ARB_FREQ_F2 0x0c +#define MC_CG_ARB_FREQ_F3 0x0d + +#define SMC_RAM_END 0x40000 + +#define VOLTAGE_SCALE 4 +#define VOLTAGE_VID_OFFSET_SCALE1 625 +#define VOLTAGE_VID_OFFSET_SCALE2 100 +#define CISLAND_MINIMUM_ENGINE_CLOCK 800 +#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5 + +static const struct ci_pt_defaults defaults_hawaii_xt = { + 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, + { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, + { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } +}; + +static const struct ci_pt_defaults defaults_hawaii_pro = { + 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, + { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, + { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } +}; + +static const struct ci_pt_defaults defaults_bonaire_xt = { + 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, + { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, + { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } +}; + + +static const struct ci_pt_defaults defaults_saturn_xt = { + 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, + { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, + { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } +}; + + +static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr, + uint32_t smc_addr, uint32_t limit) +{ + if ((0 != (3 & smc_addr)) + || ((smc_addr + 3) >= limit)) { + pr_err("smc_addr invalid \n"); + return -EINVAL; + } + + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + return 0; +} + +static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, + const uint8_t *src, uint32_t byte_count, uint32_t limit) +{ + int result; + uint32_t data = 0; + uint32_t original_data; + uint32_t addr = 0; + uint32_t extra_shift; + + if ((3 & smc_start_address) + || ((smc_start_address + byte_count) >= limit)) { + pr_err("smc_start_address invalid \n"); + return -EINVAL; + } + + addr = smc_start_address; + + while (byte_count >= 4) { + /* Bytes are written into the SMC address space with the MSB first. */ + data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; + + result = ci_set_smc_sram_address(hwmgr, addr, limit); + + if (0 != result) + return result; + + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); + + src += 4; + byte_count -= 4; + addr += 4; + } + + if (0 != byte_count) { + + data = 0; + + result = ci_set_smc_sram_address(hwmgr, addr, limit); + + if (0 != result) + return result; + + + original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); + + extra_shift = 8 * (4 - byte_count); + + while (byte_count > 0) { + /* Bytes are written into the SMC addres space with the MSB first. */ + data = (0x100 * data) + *src++; + byte_count--; + } + + data <<= extra_shift; + + data |= (original_data & ~((~0UL) << extra_shift)); + + result = ci_set_smc_sram_address(hwmgr, addr, limit); + + if (0 != result) + return result; + + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); + } + + return 0; +} + + +static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr) +{ + static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; + + ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1); + + return 0; +} + +bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr) +{ + return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, + CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) + && (0x20100 <= cgs_read_ind_register(hwmgr->device, + CGS_IND_REG__SMC, ixSMC_PC_C))); +} + +static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, + uint32_t *value, uint32_t limit) +{ + int result; + + result = ci_set_smc_sram_address(hwmgr, smc_addr, limit); + + if (result) + return result; + + *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); + return 0; +} + +int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) +{ + int ret; + + if (!ci_is_smc_ram_running(hwmgr)) + return -EINVAL; + + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg); + + PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); + + ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); + + if (ret != 1) + pr_info("\n failed to send message %x ret is %d\n", msg, ret); + + return 0; +} + +int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, + uint16_t msg, uint32_t parameter) +{ + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter); + return ci_send_msg_to_smc(hwmgr, msg); +} + +static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct cgs_system_info sys_info = {0}; + uint32_t dev_id; + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; + cgs_query_system_info(hwmgr->device, &sys_info); + dev_id = (uint32_t)sys_info.value; + + switch (dev_id) { + case 0x67BA: + case 0x66B1: + smu_data->power_tune_defaults = &defaults_hawaii_pro; + break; + case 0x67B8: + case 0x66B0: + smu_data->power_tune_defaults = &defaults_hawaii_xt; + break; + case 0x6640: + case 0x6641: + case 0x6646: + case 0x6647: + smu_data->power_tune_defaults = &defaults_saturn_xt; + break; + case 0x6649: + case 0x6650: + case 0x6651: + case 0x6658: + case 0x665C: + case 0x665D: + case 0x67A0: + case 0x67A1: + case 0x67A2: + case 0x67A8: + case 0x67A9: + case 0x67AA: + case 0x67B9: + case 0x67BE: + default: + smu_data->power_tune_defaults = &defaults_bonaire_xt; + break; + } +} + +static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, + struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table, + uint32_t clock, uint32_t *vol) +{ + uint32_t i = 0; + + if (allowed_clock_voltage_table->count == 0) + return -EINVAL; + + for (i = 0; i < allowed_clock_voltage_table->count; i++) { + if (allowed_clock_voltage_table->entries[i].clk >= clock) { + *vol = allowed_clock_voltage_table->entries[i].v; + return 0; + } + } + + *vol = allowed_clock_voltage_table->entries[i - 1].v; + return 0; +} + +static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr, + uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk) +{ + const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct pp_atomctrl_clock_dividers_vi dividers; + uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; + uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; + uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; + uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; + uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; + uint32_t ref_clock; + uint32_t ref_divider; + uint32_t fbdiv; + int result; + + /* get the engine clock dividers for this clock value */ + result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); + + PP_ASSERT_WITH_CODE(result == 0, + "Error retrieving Engine Clock dividers from VBIOS.", + return result); + + /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */ + ref_clock = atomctrl_get_reference_clock(hwmgr); + ref_divider = 1 + dividers.uc_pll_ref_div; + + /* low 14 bits is fraction and high 12 bits is divider */ + fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; + + /* SPLL_FUNC_CNTL setup */ + spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, + SPLL_REF_DIV, dividers.uc_pll_ref_div); + spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, + SPLL_PDIV_A, dividers.uc_pll_post_div); + + /* SPLL_FUNC_CNTL_3 setup*/ + spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, + SPLL_FB_DIV, fbdiv); + + /* set to use fractional accumulation*/ + spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, + SPLL_DITHEN, 1); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { + struct pp_atomctrl_internal_ss_info ss_info; + uint32_t vco_freq = clock * dividers.uc_pll_post_div; + + if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr, + vco_freq, &ss_info)) { + uint32_t clk_s = ref_clock * 5 / + (ref_divider * ss_info.speed_spectrum_rate); + uint32_t clk_v = 4 * ss_info.speed_spectrum_percentage * + fbdiv / (clk_s * 10000); + + cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum, + CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s); + cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum, + CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); + cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2, + CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v); + } + } + + sclk->SclkFrequency = clock; + sclk->CgSpllFuncCntl3 = spll_func_cntl_3; + sclk->CgSpllFuncCntl4 = spll_func_cntl_4; + sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; + sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; + sclk->SclkDid = (uint8_t)dividers.pll_post_divider; + + return 0; +} + +static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, + const struct phm_phase_shedding_limits_table *pl, + uint32_t sclk, uint32_t *p_shed) +{ + unsigned int i; + + /* use the minimum phase shedding */ + *p_shed = 1; + + for (i = 0; i < pl->count; i++) { + if (sclk < pl->entries[i].Sclk) { + *p_shed = i; + break; + } + } +} + +static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock, + uint32_t clock_insr) +{ + uint8_t i; + uint32_t temp; + uint32_t min = min_t(uint32_t, clock_insr, CISLAND_MINIMUM_ENGINE_CLOCK); + + if (clock < min) { + pr_info("Engine clock can't satisfy stutter requirement!\n"); + return 0; + } + for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { + temp = clock >> i; + + if (temp >= min || i == 0) + break; + } + return i; +} + +static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr, + uint32_t clock, uint16_t sclk_al_threshold, + struct SMU7_Discrete_GraphicsLevel *level) +{ + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + + result = ci_calculate_sclk_params(hwmgr, clock, level); + + /* populate graphics levels */ + result = ci_get_dependency_volt_by_clk(hwmgr, + hwmgr->dyn_state.vddc_dependency_on_sclk, clock, + (uint32_t *)(&level->MinVddc)); + if (result) { + pr_err("vdd_dep_on_sclk table is NULL\n"); + return result; + } + + level->SclkFrequency = clock; + level->MinVddcPhases = 1; + + if (data->vddc_phase_shed_control) + ci_populate_phase_value_based_on_sclk(hwmgr, + hwmgr->dyn_state.vddc_phase_shed_limits_table, + clock, + &level->MinVddcPhases); + + level->ActivityLevel = sclk_al_threshold; + level->CcPwrDynRm = 0; + level->CcPwrDynRm1 = 0; + level->EnabledForActivity = 0; + /* this level can be used for throttling.*/ + level->EnabledForThrottle = 1; + level->UpH = 0; + level->DownH = 0; + level->VoltageDownH = 0; + level->PowerThrottle = 0; + + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkDeepSleep)) + level->DeepSleepDivId = + ci_get_sleep_divider_id_from_clock(clock, + CISLAND_MINIMUM_ENGINE_CLOCK); + + /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ + level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + + if (0 == result) { + level->MinVddc = PP_HOST_TO_SMC_UL(level->MinVddc * VOLTAGE_SCALE); + CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases); + CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel); + CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3); + CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4); + CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum); + CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2); + CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1); + } + + return result; +} + +int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int result = 0; + uint32_t array = smu_data->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); + uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) * + SMU7_MAX_LEVELS_GRAPHICS; + struct SMU7_Discrete_GraphicsLevel *levels = + smu_data->smc_state_table.GraphicsLevel; + uint32_t i; + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + result = ci_populate_single_graphic_level(hwmgr, + dpm_table->sclk_table.dpm_levels[i].value, + (uint16_t)smu_data->activity_target[i], + &levels[i]); + if (result) + return result; + if (i > 1) + smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; + if (i == (dpm_table->sclk_table.count - 1)) + smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = + PPSMC_DISPLAY_WATERMARK_HIGH; + } + + smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; + + smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; + data->dpm_level_enable_mask.sclk_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); + + result = ci_copy_bytes_to_smc(hwmgr, array, + (u8 *)levels, array_size, + SMC_RAM_END); + + return result; + +} + +static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + + smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; + smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc; + smu_data->power_tune_table.SviLoadLineTrimVddC = 3; + smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; + + return 0; +} + +static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr) +{ + uint16_t tdc_limit; + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + + tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); + smu_data->power_tune_table.TDC_VDDC_PkgLimit = + CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); + smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = + defaults->tdc_vddc_throttle_release_limit_perc; + smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt; + + return 0; +} + +static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + uint32_t temp; + + if (ci_read_smc_sram_dword(hwmgr, + fuse_table_offset + + offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), + (uint32_t *)&temp, SMC_RAM_END)) + PP_ASSERT_WITH_CODE(false, + "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!", + return -EINVAL); + else + smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl; + + return 0; +} + +static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) +{ + uint16_t tmp; + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) + || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) + tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity; + else + tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; + + smu_data->power_tune_table.FuzzyFan_PwmSetDelta = CONVERT_FROM_HOST_TO_SMC_US(tmp); + + return 0; +} + +static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) +{ + int i; + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; + uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; + uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2; + + PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, + "The CAC Leakage table does not exist!", return -EINVAL); + PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, + "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL); + PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, + "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL); + + for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) { + lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); + hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); + hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3); + } else { + lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc); + hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage); + } + } + + return 0; +} + +static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr) +{ + int i; + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint8_t *vid = smu_data->power_tune_table.VddCVid; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, + "There should never be more than 8 entries for VddcVid!!!", + return -EINVAL); + + for (i = 0; i < (int)data->vddc_voltage_table.count; i++) + vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value); + + return 0; +} + +static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; + u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; + int i, min, max; + + min = max = hi_vid[0]; + for (i = 0; i < 8; i++) { + if (0 != hi_vid[i]) { + if (min > hi_vid[i]) + min = hi_vid[i]; + if (max < hi_vid[i]) + max = hi_vid[i]; + } + + if (0 != lo_vid[i]) { + if (min > lo_vid[i]) + min = lo_vid[i]; + if (max < lo_vid[i]) + max = lo_vid[i]; + } + } + + if ((min == 0) || (max == 0)) + return -EINVAL; + smu_data->power_tune_table.GnbLPMLMaxVid = (u8)max; + smu_data->power_tune_table.GnbLPMLMinVid = (u8)min; + + return 0; +} + +static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; + uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; + struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; + + HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); + LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); + + smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd = + CONVERT_FROM_HOST_TO_SMC_US(HiSidd); + smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd = + CONVERT_FROM_HOST_TO_SMC_US(LoSidd); + + return 0; +} + +static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint32_t pm_fuse_table_offset; + int ret = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_PowerContainment)) { + if (ci_read_smc_sram_dword(hwmgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, PmFuseTable), + &pm_fuse_table_offset, SMC_RAM_END)) { + pr_err("Attempt to get pm_fuse_table_offset Failed!\n"); + return -EINVAL; + } + + /* DW0 - DW3 */ + ret = ci_populate_bapm_vddc_vid_sidd(hwmgr); + /* DW4 - DW5 */ + ret |= ci_populate_vddc_vid(hwmgr); + /* DW6 */ + ret |= ci_populate_svi_load_line(hwmgr); + /* DW7 */ + ret |= ci_populate_tdc_limit(hwmgr); + /* DW8 */ + ret |= ci_populate_dw8(hwmgr, pm_fuse_table_offset); + + ret |= ci_populate_fuzzy_fan(hwmgr, pm_fuse_table_offset); + + ret |= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(hwmgr); + + ret |= ci_populate_bapm_vddc_base_leakage_sidd(hwmgr); + if (ret) + return ret; + + ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, + (uint8_t *)&smu_data->power_tune_table, + sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END); + } + return ret; +} + +static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; + SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); + struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; + struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; + const uint16_t *def1, *def2; + int i, j, k; + + dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); + dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); + + dpm_table->DTETjOffset = 0; + dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES); + dpm_table->GpuTjHyst = 8; + + dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base; + + if (ppm) { + dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000; + dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256; + } else { + dpm_table->PPM_PkgPwrLimit = 0; + dpm_table->PPM_TemperatureLimit = 0; + } + + CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit); + CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit); + + dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); + def1 = defaults->bapmti_r; + def2 = defaults->bapmti_rc; + + for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { + for (j = 0; j < SMU7_DTE_SOURCES; j++) { + for (k = 0; k < SMU7_DTE_SINKS; k++) { + dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1); + dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2); + def1++; + def2++; + } + } + } + + return 0; +} + +static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr, + pp_atomctrl_voltage_table_entry *tab, uint16_t *hi, + uint16_t *lo) +{ + uint16_t v_index; + bool vol_found = false; + *hi = tab->value * VOLTAGE_SCALE; + *lo = tab->value * VOLTAGE_SCALE; + + PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, + "The SCLK/VDDC Dependency Table does not exist.\n", + return -EINVAL); + + if (NULL == hwmgr->dyn_state.cac_leakage_table) { + pr_warn("CAC Leakage Table does not exist, using vddc.\n"); + return 0; + } + + for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { + if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { + vol_found = true; + if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { + *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; + *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE); + } else { + pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n"); + *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; + *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); + } + break; + } + } + + if (!vol_found) { + for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { + if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { + vol_found = true; + if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { + *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; + *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE; + } else { + pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table."); + *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; + *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); + } + break; + } + } + + if (!vol_found) + pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n"); + } + + return 0; +} + +static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr, + pp_atomctrl_voltage_table_entry *tab, + SMU7_Discrete_VoltageLevel *smc_voltage_tab) +{ + int result; + + result = ci_get_std_voltage_value_sidd(hwmgr, tab, + &smc_voltage_tab->StdVoltageHiSidd, + &smc_voltage_tab->StdVoltageLoSidd); + if (result) { + smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE; + smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE; + } + + smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE); + CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd); + CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageLoSidd); + + return 0; +} + +static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + unsigned int count; + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + table->VddcLevelCount = data->vddc_voltage_table.count; + for (count = 0; count < table->VddcLevelCount; count++) { + result = ci_populate_smc_voltage_table(hwmgr, + &(data->vddc_voltage_table.entries[count]), + &(table->VddcLevel[count])); + PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); + + /* GPIO voltage control */ + if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) + table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low; + else + table->VddcLevel[count].Smio = 0; + } + + CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); + + return 0; +} + +static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t count; + int result; + + table->VddciLevelCount = data->vddci_voltage_table.count; + + for (count = 0; count < table->VddciLevelCount; count++) { + result = ci_populate_smc_voltage_table(hwmgr, + &(data->vddci_voltage_table.entries[count]), + &(table->VddciLevel[count])); + PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); + if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) + table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low; + else + table->VddciLevel[count].Smio |= 0; + } + + CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); + + return 0; +} + +static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t count; + int result; + + table->MvddLevelCount = data->mvdd_voltage_table.count; + + for (count = 0; count < table->MvddLevelCount; count++) { + result = ci_populate_smc_voltage_table(hwmgr, + &(data->mvdd_voltage_table.entries[count]), + &table->MvddLevel[count]); + PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); + if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) + table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low; + else + table->MvddLevel[count].Smio |= 0; + } + + CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); + + return 0; +} + + +static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + int result; + + result = ci_populate_smc_vddc_table(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "can not populate VDDC voltage table to SMC", return -EINVAL); + + result = ci_populate_smc_vdd_ci_table(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "can not populate VDDCI voltage table to SMC", return -EINVAL); + + result = ci_populate_smc_mvdd_table(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "can not populate MVDD voltage table to SMC", return -EINVAL); + + return 0; +} + +static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr, + struct SMU7_Discrete_Ulv *state) +{ + uint32_t voltage_response_time, ulv_voltage; + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + state->CcPwrDynRm = 0; + state->CcPwrDynRm1 = 0; + + result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage); + PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;); + + if (ulv_voltage == 0) { + data->ulv_supported = false; + return 0; + } + + if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) { + /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */ + if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) + state->VddcOffset = 0; + else + /* used in SMIO Mode. not implemented for now. this is backup only for CI. */ + state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage); + } else { + /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */ + if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) + state->VddcOffsetVid = 0; + else /* used in SVI2 Mode */ + state->VddcOffsetVid = (uint8_t)( + (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) + * VOLTAGE_VID_OFFSET_SCALE2 + / VOLTAGE_VID_OFFSET_SCALE1); + } + state->VddcPhase = 1; + + CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); + CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); + + return 0; +} + +static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr, + SMU7_Discrete_Ulv *ulv_level) +{ + return ci_populate_ulv_level(hwmgr, ulv_level); +} + +static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint32_t i; + +/* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/ + for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { + table->LinkLevel[i].PcieGenSpeed = + (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; + table->LinkLevel[i].PcieLaneCount = + (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); + table->LinkLevel[i].EnabledForActivity = 1; + table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5); + table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30); + } + + smu_data->smc_state_table.LinkLevelCount = + (uint8_t)dpm_table->pcie_speed_table.count; + data->dpm_level_enable_mask.pcie_dpm_enable_mask = + phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); + + return 0; +} + +static int ci_calculate_mclk_params( + struct pp_hwmgr *hwmgr, + uint32_t memory_clock, + SMU7_Discrete_MemoryLevel *mclk, + bool strobe_mode, + bool dllStateOn + ) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; + uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; + uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; + uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; + uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; + uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; + uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; + uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; + uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; + + pp_atomctrl_memory_clock_param mpll_param; + int result; + + result = atomctrl_get_memory_pll_dividers_si(hwmgr, + memory_clock, &mpll_param, strobe_mode); + PP_ASSERT_WITH_CODE(0 == result, + "Error retrieving Memory Clock Parameters from VBIOS.", return result); + + mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); + + mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, + MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); + mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, + MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); + mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, + MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); + + mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl, + MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); + + if (data->is_memory_gddr5) { + mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, + MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); + mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, + MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); + } + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MemorySpreadSpectrumSupport)) { + pp_atomctrl_internal_ss_info ss_info; + uint32_t freq_nom; + uint32_t tmp; + uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); + + /* for GDDR5 for all modes and DDR3 */ + if (1 == mpll_param.qdr) + freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); + else + freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); + + /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/ + tmp = (freq_nom / reference_clock); + tmp = tmp * tmp; + + if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { + uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; + uint32_t clkv = + (uint32_t)((((131 * ss_info.speed_spectrum_percentage * + ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom); + + mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); + mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); + } + } + + mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, + MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); + mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, + MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); + mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, + MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); + + + mclk->MclkFrequency = memory_clock; + mclk->MpllFuncCntl = mpll_func_cntl; + mclk->MpllFuncCntl_1 = mpll_func_cntl_1; + mclk->MpllFuncCntl_2 = mpll_func_cntl_2; + mclk->MpllAdFuncCntl = mpll_ad_func_cntl; + mclk->MpllDqFuncCntl = mpll_dq_func_cntl; + mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; + mclk->DllCntl = dll_cntl; + mclk->MpllSs1 = mpll_ss1; + mclk->MpllSs2 = mpll_ss2; + + return 0; +} + +static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, + bool strobe_mode) +{ + uint8_t mc_para_index; + + if (strobe_mode) { + if (memory_clock < 12500) + mc_para_index = 0x00; + else if (memory_clock > 47500) + mc_para_index = 0x0f; + else + mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); + } else { + if (memory_clock < 65000) + mc_para_index = 0x00; + else if (memory_clock > 135000) + mc_para_index = 0x0f; + else + mc_para_index = (uint8_t)((memory_clock - 60000) / 5000); + } + + return mc_para_index; +} + +static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) +{ + uint8_t mc_para_index; + + if (memory_clock < 10000) + mc_para_index = 0; + else if (memory_clock >= 80000) + mc_para_index = 0x0f; + else + mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1); + + return mc_para_index; +} + +static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, + uint32_t memory_clock, uint32_t *p_shed) +{ + unsigned int i; + + *p_shed = 1; + + for (i = 0; i < pl->count; i++) { + if (memory_clock < pl->entries[i].Mclk) { + *p_shed = i; + break; + } + } + + return 0; +} + +static int ci_populate_single_memory_level( + struct pp_hwmgr *hwmgr, + uint32_t memory_clock, + SMU7_Discrete_MemoryLevel *memory_level + ) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + int result = 0; + bool dll_state_on; + struct cgs_display_info info = {0}; + uint32_t mclk_edc_wr_enable_threshold = 40000; + uint32_t mclk_edc_enable_threshold = 40000; + uint32_t mclk_strobe_mode_threshold = 40000; + + if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { + result = ci_get_dependency_volt_by_clk(hwmgr, + hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); + PP_ASSERT_WITH_CODE((0 == result), + "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); + } + + if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { + result = ci_get_dependency_volt_by_clk(hwmgr, + hwmgr->dyn_state.vddci_dependency_on_mclk, + memory_clock, + &memory_level->MinVddci); + PP_ASSERT_WITH_CODE((0 == result), + "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result); + } + + if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { + result = ci_get_dependency_volt_by_clk(hwmgr, + hwmgr->dyn_state.mvdd_dependency_on_mclk, + memory_clock, + &memory_level->MinMvdd); + PP_ASSERT_WITH_CODE((0 == result), + "can not find MinVddci voltage value from memory MVDD voltage dependency table", return result); + } + + memory_level->MinVddcPhases = 1; + + if (data->vddc_phase_shed_control) { + ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table, + memory_clock, &memory_level->MinVddcPhases); + } + + memory_level->EnabledForThrottle = 1; + memory_level->EnabledForActivity = 1; + memory_level->UpH = 0; + memory_level->DownH = 100; + memory_level->VoltageDownH = 0; + + /* Indicates maximum activity level for this performance level.*/ + memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target; + memory_level->StutterEnable = 0; + memory_level->StrobeEnable = 0; + memory_level->EdcReadEnable = 0; + memory_level->EdcWriteEnable = 0; + memory_level->RttEnable = 0; + + /* default set to low watermark. Highest level will be set to high later.*/ + memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + + cgs_get_active_displays_info(hwmgr->device, &info); + data->display_timing.num_existing_displays = info.display_count; + + /* stutter mode not support on ci */ + + /* decide strobe mode*/ + memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && + (memory_clock <= mclk_strobe_mode_threshold); + + /* decide EDC mode and memory clock ratio*/ + if (data->is_memory_gddr5) { + memory_level->StrobeRatio = ci_get_mclk_frequency_ratio(memory_clock, + memory_level->StrobeEnable); + + if ((mclk_edc_enable_threshold != 0) && + (memory_clock > mclk_edc_enable_threshold)) { + memory_level->EdcReadEnable = 1; + } + + if ((mclk_edc_wr_enable_threshold != 0) && + (memory_clock > mclk_edc_wr_enable_threshold)) { + memory_level->EdcWriteEnable = 1; + } + + if (memory_level->StrobeEnable) { + if (ci_get_mclk_frequency_ratio(memory_clock, 1) >= + ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) + dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; + else + dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; + } else + dll_state_on = data->dll_default_on; + } else { + memory_level->StrobeRatio = + ci_get_ddr3_mclk_frequency_ratio(memory_clock); + dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; + } + + result = ci_calculate_mclk_params(hwmgr, + memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); + + if (0 == result) { + memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); + memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE); + memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE); + /* MCLK frequency in units of 10KHz*/ + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); + /* Indicates maximum activity level for this performance level.*/ + CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); + CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); + } + + return result; +} + +int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_dpm_table *dpm_table = &data->dpm_table; + int result; + struct cgs_system_info sys_info = {0}; + uint32_t dev_id; + + uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel); + uint32_t level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * SMU7_MAX_LEVELS_MEMORY; + SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; + uint32_t i; + + memset(levels, 0x00, level_array_size); + + for (i = 0; i < dpm_table->mclk_table.count; i++) { + PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), + "can not populate memory level as memory clock is zero", return -EINVAL); + result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, + &(smu_data->smc_state_table.MemoryLevel[i])); + if (0 != result) + return result; + } + + smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; + cgs_query_system_info(hwmgr->device, &sys_info); + dev_id = (uint32_t)sys_info.value; + + if ((dpm_table->mclk_table.count >= 2) + && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) { + smu_data->smc_state_table.MemoryLevel[1].MinVddci = + smu_data->smc_state_table.MemoryLevel[0].MinVddci; + smu_data->smc_state_table.MemoryLevel[1].MinMvdd = + smu_data->smc_state_table.MemoryLevel[0].MinMvdd; + } + smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; + CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); + + smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; + data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); + smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; + + result = ci_copy_bytes_to_smc(hwmgr, + level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, + SMC_RAM_END); + + return result; +} + +static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, + SMU7_Discrete_VoltageLevel *voltage) +{ + const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + uint32_t i = 0; + + if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { + /* find mvdd value which clock is more than request */ + for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { + if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { + /* Always round to higher voltage. */ + voltage->Voltage = data->mvdd_voltage_table.entries[i].value; + break; + } + } + + PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, + "MVDD Voltage is outside the supported range.", return -EINVAL); + + } else { + return -EINVAL; + } + + return 0; +} + +static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + int result = 0; + const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct pp_atomctrl_clock_dividers_vi dividers; + + SMU7_Discrete_VoltageLevel voltage_level; + uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; + uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; + uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; + uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; + + + /* The ACPI state should not do DPM on DC (or ever).*/ + table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; + + if (data->acpi_vddc) + table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); + else + table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); + + table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; + /* assign zero for now*/ + table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); + + /* get the engine clock dividers for this clock value*/ + result = atomctrl_get_engine_pll_dividers_vi(hwmgr, + table->ACPILevel.SclkFrequency, ÷rs); + + PP_ASSERT_WITH_CODE(result == 0, + "Error retrieving Engine Clock dividers from VBIOS.", return result); + + /* divider ID for required SCLK*/ + table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; + table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + table->ACPILevel.DeepSleepDivId = 0; + + spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, + CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); + spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, + CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); + spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, + CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); + + table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; + table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; + table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; + table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; + table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; + table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; + table->ACPILevel.CcPwrDynRm = 0; + table->ACPILevel.CcPwrDynRm1 = 0; + + /* For various features to be enabled/disabled while this level is active.*/ + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); + /* SCLK frequency in units of 10KHz*/ + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); + CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); + + + /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ + table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; + table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; + + if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control) + table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc; + else { + if (data->acpi_vddci != 0) + table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE); + else + table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE); + } + + if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level)) + table->MemoryACPILevel.MinMvdd = + PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); + else + table->MemoryACPILevel.MinMvdd = 0; + + /* Force reset on DLL*/ + mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, + MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); + mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, + MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); + + /* Disable DLL in ACPIState*/ + mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, + MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); + mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, + MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); + + /* Enable DLL bypass signal*/ + dll_cntl = PHM_SET_FIELD(dll_cntl, + DLL_CNTL, MRDCK0_BYPASS, 0); + dll_cntl = PHM_SET_FIELD(dll_cntl, + DLL_CNTL, MRDCK1_BYPASS, 0); + + table->MemoryACPILevel.DllCntl = + PP_HOST_TO_SMC_UL(dll_cntl); + table->MemoryACPILevel.MclkPwrmgtCntl = + PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); + table->MemoryACPILevel.MpllAdFuncCntl = + PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); + table->MemoryACPILevel.MpllDqFuncCntl = + PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); + table->MemoryACPILevel.MpllFuncCntl = + PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); + table->MemoryACPILevel.MpllFuncCntl_1 = + PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); + table->MemoryACPILevel.MpllFuncCntl_2 = + PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); + table->MemoryACPILevel.MpllSs1 = + PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); + table->MemoryACPILevel.MpllSs2 = + PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); + + table->MemoryACPILevel.EnabledForThrottle = 0; + table->MemoryACPILevel.EnabledForActivity = 0; + table->MemoryACPILevel.UpH = 0; + table->MemoryACPILevel.DownH = 100; + table->MemoryACPILevel.VoltageDownH = 0; + /* Indicates maximum activity level for this performance level.*/ + table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); + + table->MemoryACPILevel.StutterEnable = 0; + table->MemoryACPILevel.StrobeEnable = 0; + table->MemoryACPILevel.EdcReadEnable = 0; + table->MemoryACPILevel.EdcWriteEnable = 0; + table->MemoryACPILevel.RttEnable = 0; + + return result; +} + +static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + int result = 0; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_uvd_clock_voltage_dependency_table *uvd_table = + hwmgr->dyn_state.uvd_clock_voltage_dependency_table; + + table->UvdLevelCount = (uint8_t)(uvd_table->count); + + for (count = 0; count < table->UvdLevelCount; count++) { + table->UvdLevel[count].VclkFrequency = + uvd_table->entries[count].vclk; + table->UvdLevel[count].DclkFrequency = + uvd_table->entries[count].dclk; + table->UvdLevel[count].MinVddc = + uvd_table->entries[count].v * VOLTAGE_SCALE; + table->UvdLevel[count].MinVddcPhases = 1; + + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->UvdLevel[count].VclkFrequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for Vclk clock", return result); + + table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; + + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->UvdLevel[count].DclkFrequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for Dclk clock", return result); + + table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); + CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); + CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc); + } + + return result; +} + +static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_vce_clock_voltage_dependency_table *vce_table = + hwmgr->dyn_state.vce_clock_voltage_dependency_table; + + table->VceLevelCount = (uint8_t)(vce_table->count); + table->VceBootLevel = 0; + + for (count = 0; count < table->VceLevelCount; count++) { + table->VceLevel[count].Frequency = vce_table->entries[count].evclk; + table->VceLevel[count].MinVoltage = + vce_table->entries[count].v * VOLTAGE_SCALE; + table->VceLevel[count].MinPhases = 1; + + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->VceLevel[count].Frequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for VCE engine clock", + return result); + + table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); + CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage); + } + return result; +} + +static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_acp_clock_voltage_dependency_table *acp_table = + hwmgr->dyn_state.acp_clock_voltage_dependency_table; + + table->AcpLevelCount = (uint8_t)(acp_table->count); + table->AcpBootLevel = 0; + + for (count = 0; count < table->AcpLevelCount; count++) { + table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk; + table->AcpLevel[count].MinVoltage = acp_table->entries[count].v; + table->AcpLevel[count].MinPhases = 1; + + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->AcpLevel[count].Frequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for engine clock", return result); + + table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); + CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage); + } + return result; +} + +static int ci_populate_smc_samu_level(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + int result = -EINVAL; + uint8_t count; + struct pp_atomctrl_clock_dividers_vi dividers; + struct phm_samu_clock_voltage_dependency_table *samu_table = + hwmgr->dyn_state.samu_clock_voltage_dependency_table; + + table->SamuBootLevel = 0; + table->SamuLevelCount = (uint8_t)(samu_table->count); + + for (count = 0; count < table->SamuLevelCount; count++) { + table->SamuLevel[count].Frequency = samu_table->entries[count].samclk; + table->SamuLevel[count].MinVoltage = samu_table->entries[count].v * VOLTAGE_SCALE; + table->SamuLevel[count].MinPhases = 1; + + /* retrieve divider value for VBIOS */ + result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, + table->SamuLevel[count].Frequency, ÷rs); + PP_ASSERT_WITH_CODE((0 == result), + "can not find divide id for samu clock", return result); + + table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + + CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); + CONVERT_FROM_HOST_TO_SMC_US(table->SamuLevel[count].MinVoltage); + } + return result; +} + +static int ci_populate_memory_timing_parameters( + struct pp_hwmgr *hwmgr, + uint32_t engine_clock, + uint32_t memory_clock, + struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs + ) +{ + uint32_t dramTiming; + uint32_t dramTiming2; + uint32_t burstTime; + int result; + + result = atomctrl_set_engine_dram_timings_rv770(hwmgr, + engine_clock, memory_clock); + + PP_ASSERT_WITH_CODE(result == 0, + "Error calling VBIOS to set DRAM_TIMING.", return result); + + dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); + dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); + burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); + + arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); + arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); + arb_regs->McArbBurstTime = (uint8_t)burstTime; + + return 0; +} + +static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + int result = 0; + SMU7_Discrete_MCArbDramTimingTable arb_regs; + uint32_t i, j; + + memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable)); + + for (i = 0; i < data->dpm_table.sclk_table.count; i++) { + for (j = 0; j < data->dpm_table.mclk_table.count; j++) { + result = ci_populate_memory_timing_parameters + (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, + data->dpm_table.mclk_table.dpm_levels[j].value, + &arb_regs.entries[i][j]); + + if (0 != result) + break; + } + } + + if (0 == result) { + result = ci_copy_bytes_to_smc( + hwmgr, + smu_data->arb_table_start, + (uint8_t *)&arb_regs, + sizeof(SMU7_Discrete_MCArbDramTimingTable), + SMC_RAM_END + ); + } + + return result; +} + +static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + int result = 0; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; + + /* find boot level from dpm table*/ + result = phm_find_boot_level(&(data->dpm_table.sclk_table), + data->vbios_boot_state.sclk_bootup_value, + (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); + + if (0 != result) { + smu_data->smc_state_table.GraphicsBootLevel = 0; + pr_err("VBIOS did not find boot engine clock value \ + in dependency table. Using Graphics DPM level 0!"); + result = 0; + } + + result = phm_find_boot_level(&(data->dpm_table.mclk_table), + data->vbios_boot_state.mclk_bootup_value, + (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); + + if (0 != result) { + smu_data->smc_state_table.MemoryBootLevel = 0; + pr_err("VBIOS did not find boot engine clock value \ + in dependency table. Using Memory DPM level 0!"); + result = 0; + } + + table->BootVddc = data->vbios_boot_state.vddc_bootup_value; + table->BootVddci = data->vbios_boot_state.vddci_bootup_value; + table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; + + return result; +} + +static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr, + SMU7_Discrete_MCRegisters *mc_reg_table) +{ + const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend; + + uint32_t i, j; + + for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { + if (smu_data->mc_reg_table.validflag & 1<<j) { + PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE, + "Index of mc_reg_table->address[] array out of boundary", return -EINVAL); + mc_reg_table->address[i].s0 = + PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); + mc_reg_table->address[i].s1 = + PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); + i++; + } + } + + mc_reg_table->last = (uint8_t)i; + + return 0; +} + +static void ci_convert_mc_registers( + const struct ci_mc_reg_entry *entry, + SMU7_Discrete_MCRegisterSet *data, + uint32_t num_entries, uint32_t valid_flag) +{ + uint32_t i, j; + + for (i = 0, j = 0; j < num_entries; j++) { + if (valid_flag & 1<<j) { + data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]); + i++; + } + } +} + +static int ci_convert_mc_reg_table_entry_to_smc( + struct pp_hwmgr *hwmgr, + const uint32_t memory_clock, + SMU7_Discrete_MCRegisterSet *mc_reg_table_data + ) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint32_t i = 0; + + for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { + if (memory_clock <= + smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) { + break; + } + } + + if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) + --i; + + ci_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i], + mc_reg_table_data, smu_data->mc_reg_table.last, + smu_data->mc_reg_table.validflag); + + return 0; +} + +static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, + SMU7_Discrete_MCRegisters *mc_regs) +{ + int result = 0; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + int res; + uint32_t i; + + for (i = 0; i < data->dpm_table.mclk_table.count; i++) { + res = ci_convert_mc_reg_table_entry_to_smc( + hwmgr, + data->dpm_table.mclk_table.dpm_levels[i].value, + &mc_regs->data[i] + ); + + if (0 != res) + result = res; + } + + return result; +} + +static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t address; + int32_t result; + + if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) + return 0; + + + memset(&smu_data->mc_regs, 0, sizeof(SMU7_Discrete_MCRegisters)); + + result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs)); + + if (result != 0) + return result; + + address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]); + + return ci_copy_bytes_to_smc(hwmgr, address, + (uint8_t *)&smu_data->mc_regs.data[0], + sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, + SMC_RAM_END); +} + +static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) +{ + int result; + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters)); + result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize MCRegTable for the MC register addresses!", return result;); + + result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize MCRegTable for driver state!", return result;); + + return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start, + (uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END); +} + +static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + uint8_t count, level; + + count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); + + for (level = 0; level < count; level++) { + if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk + >= data->vbios_boot_state.sclk_bootup_value) { + smu_data->smc_state_table.GraphicsBootLevel = level; + break; + } + } + + count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); + + for (level = 0; level < count; level++) { + if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk + >= data->vbios_boot_state.mclk_bootup_value) { + smu_data->smc_state_table.MemoryBootLevel = level; + break; + } + } + + return 0; +} + +static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr, + SMU7_Discrete_DpmTable *table) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) + table->SVI2Enable = 1; + else + table->SVI2Enable = 0; + return 0; +} + +static int ci_start_smc(struct pp_hwmgr *hwmgr) +{ + /* set smc instruct start point at 0x0 */ + ci_program_jump_on_start(hwmgr); + + /* enable smc clock */ + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); + + PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, + INTERRUPTS_ENABLED, 1); + + return 0; +} + +int ci_init_smc_table(struct pp_hwmgr *hwmgr) +{ + int result; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table); + struct pp_atomctrl_gpio_pin_assignment gpio_pin; + u32 i; + + ci_initialize_power_tune_defaults(hwmgr); + memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); + + if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) + ci_populate_smc_voltage_tables(hwmgr, table); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition)) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; + + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_StepVddc)) + table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; + + if (data->is_memory_gddr5) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; + + if (data->ulv_supported) { + result = ci_populate_ulv_state(hwmgr, &(table->Ulv)); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize ULV state!", return result); + + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + ixCG_ULV_PARAMETER, 0x40035); + } + + result = ci_populate_all_graphic_levels(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Graphics Level!", return result); + + result = ci_populate_all_memory_levels(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Memory Level!", return result); + + result = ci_populate_smc_link_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Link Level!", return result); + + result = ci_populate_smc_acpi_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize ACPI Level!", return result); + + result = ci_populate_smc_vce_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize VCE Level!", return result); + + result = ci_populate_smc_acp_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize ACP Level!", return result); + + result = ci_populate_smc_samu_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize SAMU Level!", return result); + + /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */ + /* need to populate the ARB settings for the initial state. */ + result = ci_program_memory_timing_parameters(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to Write ARB settings for the initial state.", return result); + + result = ci_populate_smc_uvd_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize UVD Level!", return result); + + table->UvdBootLevel = 0; + table->VceBootLevel = 0; + table->AcpBootLevel = 0; + table->SamuBootLevel = 0; + + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; + + result = ci_populate_smc_boot_level(hwmgr, table); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to initialize Boot Level!", return result); + + result = ci_populate_smc_initial_state(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); + + result = ci_populate_bapm_parameters_in_dpm_table(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); + + table->UVDInterval = 1; + table->VCEInterval = 1; + table->ACPInterval = 1; + table->SAMUInterval = 1; + table->GraphicsVoltageChangeEnable = 1; + table->GraphicsThermThrottleEnable = 1; + table->GraphicsInterval = 1; + table->VoltageInterval = 1; + table->ThermalInterval = 1; + + table->TemperatureLimitHigh = + (data->thermal_temp_setting.temperature_high * + SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + table->TemperatureLimitLow = + (data->thermal_temp_setting.temperature_low * + SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + table->MemoryVoltageChangeEnable = 1; + table->MemoryInterval = 1; + table->VoltageResponseTime = 0; + table->VddcVddciDelta = 4000; + table->PhaseResponseTime = 0; + table->MemoryThermThrottleEnable = 1; + + PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), + "There must be 1 or more PCIE levels defined in PPTable.", + return -EINVAL); + + table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count; + table->PCIeGenInterval = 1; + + ci_populate_smc_svi2_config(hwmgr, table); + + for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++) + CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]); + + table->ThermGpio = 17; + table->SclkStepSize = 0x4000; + if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { + table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_RegulatorHot); + } else { + table->VRHotGpio = SMU7_UNUSED_GPIO_PIN; + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_RegulatorHot); + } + + table->AcDcGpio = SMU7_UNUSED_GPIO_PIN; + + CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid); + CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid); + CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); + CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); + CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); + table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta); + CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); + CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); + + table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE); + table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE); + table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); + + /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ + result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, SystemFlags), + (uint8_t *)&(table->SystemFlags), + sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController), + SMC_RAM_END); + + PP_ASSERT_WITH_CODE(0 == result, + "Failed to upload dpm data to SMC memory!", return result;); + + result = ci_populate_initial_mc_reg_table(hwmgr); + PP_ASSERT_WITH_CODE((0 == result), + "Failed to populate initialize MC Reg table!", return result); + + result = ci_populate_pm_fuses(hwmgr); + PP_ASSERT_WITH_CODE(0 == result, + "Failed to populate PM fuses to SMC memory!", return result); + + ci_start_smc(hwmgr); + + return 0; +} + +int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) +{ + struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); + SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + uint32_t duty100; + uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; + uint16_t fdo_min, slope1, slope2; + uint32_t reference_clock; + int res; + uint64_t tmp64; + + if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) + return 0; + + if (hwmgr->thermal_controller.fanInfo.bNoFan) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + + if (0 == ci_data->fan_table_start) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + + duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100); + + if (0 == duty100) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + + tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100; + do_div(tmp64, 10000); + fdo_min = (uint16_t)tmp64; + + t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin; + t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed; + + pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin; + pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed; + + slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); + slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); + + fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100); + fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100); + fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100); + + fan_table.Slope1 = cpu_to_be16(slope1); + fan_table.Slope2 = cpu_to_be16(slope2); + + fan_table.FdoMin = cpu_to_be16(fdo_min); + + fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst); + + fan_table.HystUp = cpu_to_be16(1); + + fan_table.HystSlope = cpu_to_be16(1); + + fan_table.TempRespLim = cpu_to_be16(5); + + reference_clock = smu7_get_xclk(hwmgr); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600); + + fan_table.FdoMax = cpu_to_be16((uint16_t)duty100); + + fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); + + res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); + + return 0; +} + +static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + if (data->need_update_smu7_dpm_table & + (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) + return ci_program_memory_timing_parameters(hwmgr); + + return 0; +} + +int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) + && (hwmgr->gfx_arbiter.sclk_threshold != + data->low_sclk_interrupt_threshold)) { + data->low_sclk_interrupt_threshold = + hwmgr->gfx_arbiter.sclk_threshold; + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + + CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); + + result = ci_copy_bytes_to_smc( + hwmgr, + smu_data->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, + LowSclkInterruptT), + (uint8_t *)&low_sclk_interrupt_threshold, + sizeof(uint32_t), + SMC_RAM_END); + } + + result = ci_update_and_upload_mc_reg_table(hwmgr); + + PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); + + result = ci_program_mem_timing_parameters(hwmgr); + PP_ASSERT_WITH_CODE((result == 0), + "Failed to program memory timing parameters!", + ); + + return result; +} + +uint32_t ci_get_offsetof(uint32_t type, uint32_t member) +{ + switch (type) { + case SMU_SoftRegisters: + switch (member) { + case HandshakeDisables: + return offsetof(SMU7_SoftRegisters, HandshakeDisables); + case VoltageChangeTimeout: + return offsetof(SMU7_SoftRegisters, VoltageChangeTimeout); + case AverageGraphicsActivity: + return offsetof(SMU7_SoftRegisters, AverageGraphicsA); + case PreVBlankGap: + return offsetof(SMU7_SoftRegisters, PreVBlankGap); + case VBlankTimeout: + return offsetof(SMU7_SoftRegisters, VBlankTimeout); + } + case SMU_Discrete_DpmTable: + switch (member) { + case LowSclkInterruptThreshold: + return offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT); + } + } + pr_debug("can't get the offset of type %x member %x\n", type, member); + return 0; +} + +uint32_t ci_get_mac_definition(uint32_t value) +{ + switch (value) { + case SMU_MAX_LEVELS_GRAPHICS: + return SMU7_MAX_LEVELS_GRAPHICS; + case SMU_MAX_LEVELS_MEMORY: + return SMU7_MAX_LEVELS_MEMORY; + case SMU_MAX_LEVELS_LINK: + return SMU7_MAX_LEVELS_LINK; + case SMU_MAX_ENTRIES_SMIO: + return SMU7_MAX_ENTRIES_SMIO; + case SMU_MAX_LEVELS_VDDC: + return SMU7_MAX_LEVELS_VDDC; + case SMU_MAX_LEVELS_VDDCI: + return SMU7_MAX_LEVELS_VDDCI; + case SMU_MAX_LEVELS_MVDD: + return SMU7_MAX_LEVELS_MVDD; + } + + pr_debug("can't get the mac of %x\n", value); + return 0; +} + +static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr) +{ + uint32_t byte_count, start_addr; + uint8_t *src; + uint32_t data; + + struct cgs_firmware_info info = {0}; + + cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); + + hwmgr->is_kicker = info.is_kicker; + byte_count = info.image_size; + src = (uint8_t *)info.kptr; + start_addr = info.ucode_start_address; + + if (byte_count > SMC_RAM_END) { + pr_err("SMC address is beyond the SMC RAM area.\n"); + return -EINVAL; + } + + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); + + for (; byte_count >= 4; byte_count -= 4) { + data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); + src += 4; + } + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + + if (0 != byte_count) { + pr_err("SMC size must be dividable by 4\n"); + return -EINVAL; + } + + return 0; +} + +static int ci_upload_firmware(struct pp_hwmgr *hwmgr) +{ + if (ci_is_smc_ram_running(hwmgr)) { + pr_info("smc is running, no need to load smc firmware\n"); + return 0; + } + PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, + boot_seq_done, 1); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL, + pre_fetcher_en, 1); + + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); + return ci_load_smc_ucode(hwmgr); +} + +int ci_process_firmware_header(struct pp_hwmgr *hwmgr) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend); + + uint32_t tmp = 0; + int result; + bool error = false; + + if (ci_upload_firmware(hwmgr)) + return -EINVAL; + + result = ci_read_smc_sram_dword(hwmgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, DpmTable), + &tmp, SMC_RAM_END); + + if (0 == result) + ci_data->dpm_table_start = tmp; + + error |= (0 != result); + + result = ci_read_smc_sram_dword(hwmgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, SoftRegisters), + &tmp, SMC_RAM_END); + + if (0 == result) { + data->soft_regs_start = tmp; + ci_data->soft_regs_start = tmp; + } + + error |= (0 != result); + + result = ci_read_smc_sram_dword(hwmgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, mcRegisterTable), + &tmp, SMC_RAM_END); + + if (0 == result) + ci_data->mc_reg_table_start = tmp; + + result = ci_read_smc_sram_dword(hwmgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, FanTable), + &tmp, SMC_RAM_END); + + if (0 == result) + ci_data->fan_table_start = tmp; + + error |= (0 != result); + + result = ci_read_smc_sram_dword(hwmgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), + &tmp, SMC_RAM_END); + + if (0 == result) + ci_data->arb_table_start = tmp; + + error |= (0 != result); + + result = ci_read_smc_sram_dword(hwmgr, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, Version), + &tmp, SMC_RAM_END); + + if (0 == result) + hwmgr->microcode_version_info.SMC = tmp; + + error |= (0 != result); + + return error ? 1 : 0; +} + +static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr) +{ + return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); +} + +static bool ci_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg) +{ + bool result = true; + + switch (in_reg) { + case mmMC_SEQ_RAS_TIMING: + *out_reg = mmMC_SEQ_RAS_TIMING_LP; + break; + + case mmMC_SEQ_DLL_STBY: + *out_reg = mmMC_SEQ_DLL_STBY_LP; + break; + + case mmMC_SEQ_G5PDX_CMD0: + *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; + break; + + case mmMC_SEQ_G5PDX_CMD1: + *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; + break; + + case mmMC_SEQ_G5PDX_CTRL: + *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; + break; + + case mmMC_SEQ_CAS_TIMING: + *out_reg = mmMC_SEQ_CAS_TIMING_LP; + break; + + case mmMC_SEQ_MISC_TIMING: + *out_reg = mmMC_SEQ_MISC_TIMING_LP; + break; + + case mmMC_SEQ_MISC_TIMING2: + *out_reg = mmMC_SEQ_MISC_TIMING2_LP; + break; + + case mmMC_SEQ_PMG_DVS_CMD: + *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP; + break; + + case mmMC_SEQ_PMG_DVS_CTL: + *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP; + break; + + case mmMC_SEQ_RD_CTL_D0: + *out_reg = mmMC_SEQ_RD_CTL_D0_LP; + break; + + case mmMC_SEQ_RD_CTL_D1: + *out_reg = mmMC_SEQ_RD_CTL_D1_LP; + break; + + case mmMC_SEQ_WR_CTL_D0: + *out_reg = mmMC_SEQ_WR_CTL_D0_LP; + break; + + case mmMC_SEQ_WR_CTL_D1: + *out_reg = mmMC_SEQ_WR_CTL_D1_LP; + break; + + case mmMC_PMG_CMD_EMRS: + *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP; + break; + + case mmMC_PMG_CMD_MRS: + *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP; + break; + + case mmMC_PMG_CMD_MRS1: + *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP; + break; + + case mmMC_SEQ_PMG_TIMING: + *out_reg = mmMC_SEQ_PMG_TIMING_LP; + break; + + case mmMC_PMG_CMD_MRS2: + *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP; + break; + + case mmMC_SEQ_WR_CTL_2: + *out_reg = mmMC_SEQ_WR_CTL_2_LP; + break; + + default: + result = false; + break; + } + + return result; +} + +static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) +{ + uint32_t i; + uint16_t address; + + for (i = 0; i < table->last; i++) { + table->mc_reg_address[i].s0 = + ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) + ? address : table->mc_reg_address[i].s1; + } + return 0; +} + +static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, + struct ci_mc_reg_table *ni_table) +{ + uint8_t i, j; + + PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); + PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), + "Invalid VramInfo table.", return -EINVAL); + + for (i = 0; i < table->last; i++) + ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; + + ni_table->last = table->last; + + for (i = 0; i < table->num_entries; i++) { + ni_table->mc_reg_table_entry[i].mclk_max = + table->mc_reg_table_entry[i].mclk_max; + for (j = 0; j < table->last; j++) { + ni_table->mc_reg_table_entry[i].mc_data[j] = + table->mc_reg_table_entry[i].mc_data[j]; + } + } + + ni_table->num_entries = table->num_entries; + + return 0; +} + +static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, + struct ci_mc_reg_table *table) +{ + uint8_t i, j, k; + uint32_t temp_reg; + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + + for (i = 0, j = table->last; i < table->last; i++) { + PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); + + switch (table->mc_reg_address[i].s1) { + + case mmMC_SEQ_MISC1: + temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS); + table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; + table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + ((temp_reg & 0xffff0000)) | + ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); + } + j++; + PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); + + temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); + table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; + table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + (temp_reg & 0xffff0000) | + (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); + + if (!data->is_memory_gddr5) + table->mc_reg_table_entry[k].mc_data[j] |= 0x100; + } + j++; + PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); + + if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) { + table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; + table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; + } + j++; + PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); + } + + break; + + case mmMC_SEQ_RESERVE_M: + temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); + table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; + table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + (temp_reg & 0xffff0000) | + (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); + } + j++; + PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); + break; + + default: + break; + } + + } + + table->last = j; + + return 0; +} + +static int ci_set_valid_flag(struct ci_mc_reg_table *table) +{ + uint8_t i, j; + + for (i = 0; i < table->last; i++) { + for (j = 1; j < table->num_entries; j++) { + if (table->mc_reg_table_entry[j-1].mc_data[i] != + table->mc_reg_table_entry[j].mc_data[i]) { + table->validflag |= (1 << i); + break; + } + } + } + + return 0; +} + +int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) +{ + int result; + struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend); + pp_atomctrl_mc_reg_table *table; + struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table; + uint8_t module_index = ci_get_memory_modile_index(hwmgr); + + table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); + + if (NULL == table) + return -ENOMEM; + + /* Program additional LP registers that are no longer programmed by VBIOS */ + cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); + cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); + cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); + cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0)); + cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1)); + cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL)); + cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD)); + cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL)); + cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING)); + cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); + cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); + cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); + cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); + cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); + cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); + cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); + cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); + cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); + cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); + cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); + + memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); + + result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); + + if (0 == result) + result = ci_copy_vbios_smc_reg_table(table, ni_table); + + if (0 == result) { + ci_set_s0_mc_reg_index(ni_table); + result = ci_set_mc_special_registers(hwmgr, ni_table); + } + + if (0 == result) + ci_set_valid_flag(ni_table); + + kfree(table); + + return result; +} + +bool ci_is_dpm_running(struct pp_hwmgr *hwmgr) +{ + return ci_is_smc_ram_running(hwmgr); +} + +int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request) +{ + struct ci_smumgr *smu_data = (struct ci_smumgr *) + (hwmgr->smu_backend); + struct SMU7_Discrete_GraphicsLevel *levels = + smu_data->smc_state_table.GraphicsLevel; + uint32_t array = smu_data->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); + uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) * + SMU7_MAX_LEVELS_GRAPHICS; + uint32_t i; + + for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { + levels[i].ActivityLevel = + cpu_to_be16(request->activity_threshold); + levels[i].EnabledForActivity = 1; + levels[i].UpH = request->up_hyst; + levels[i].DownH = request->down_hyst; + } + + return ci_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, + array_size, SMC_RAM_END); +} diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h new file mode 100644 index 000000000000..cc4176d2d25f --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h @@ -0,0 +1,52 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef CI_SMC_H +#define CI_SMC_H + +#include <linux/types.h> + + +struct pp_smumgr; +struct pp_hwmgr; +struct amd_pp_profile; + +int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, + uint16_t msg, uint32_t parameter); +int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg); +int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); +int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr); +int ci_init_smc_table(struct pp_hwmgr *hwmgr); +int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr); +int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type); +int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr); +uint32_t ci_get_offsetof(uint32_t type, uint32_t member); +uint32_t ci_get_mac_definition(uint32_t value); +int ci_process_firmware_header(struct pp_hwmgr *hwmgr); +int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr); +bool ci_is_dpm_running(struct pp_hwmgr *hwmgr); +int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, + struct amd_pp_profile *request); + + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c new file mode 100644 index 000000000000..f265f42a7ed3 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c @@ -0,0 +1,86 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/fb.h> +#include "linux/delay.h" + +#include "smumgr.h" +#include "ci_smumgr.h" +#include "cgs_common.h" +#include "ci_smc.h" + +static int ci_smu_init(struct pp_hwmgr *hwmgr) +{ + int i; + struct ci_smumgr *ci_priv = NULL; + + ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL); + + if (ci_priv == NULL) + return -ENOMEM; + + for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) + ci_priv->activity_target[i] = 30; + + hwmgr->smu_backend = ci_priv; + + return 0; +} + +static int ci_smu_fini(struct pp_hwmgr *hwmgr) +{ + kfree(hwmgr->smu_backend); + hwmgr->smu_backend = NULL; + cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU); + return 0; +} + +static int ci_start_smu(struct pp_hwmgr *hwmgr) +{ + return 0; +} + +const struct pp_smumgr_func ci_smu_funcs = { + .smu_init = ci_smu_init, + .smu_fini = ci_smu_fini, + .start_smu = ci_start_smu, + .check_fw_load_finish = NULL, + .request_smu_load_fw = NULL, + .request_smu_load_specific_fw = NULL, + .send_msg_to_smc = ci_send_msg_to_smc, + .send_msg_to_smc_with_parameter = ci_send_msg_to_smc_with_parameter, + .download_pptable_settings = NULL, + .upload_pptable_settings = NULL, + .get_offsetof = ci_get_offsetof, + .process_firmware_header = ci_process_firmware_header, + .init_smc_table = ci_init_smc_table, + .update_sclk_threshold = ci_update_sclk_threshold, + .thermal_setup_fan_table = ci_thermal_setup_fan_table, + .populate_all_graphic_levels = ci_populate_all_graphic_levels, + .populate_all_memory_levels = ci_populate_all_memory_levels, + .get_mac_definition = ci_get_mac_definition, + .initialize_mc_reg_table = ci_initialize_mc_reg_table, + .is_dpm_running = ci_is_dpm_running, + .populate_requested_graphic_levels = ci_populate_requested_graphic_levels, +}; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h new file mode 100644 index 000000000000..8189cfa17c46 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h @@ -0,0 +1,78 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _CI_SMUMANAGER_H_ +#define _CI_SMUMANAGER_H_ + +#define SMU__NUM_SCLK_DPM_STATE 8 +#define SMU__NUM_MCLK_DPM_LEVELS 6 +#define SMU__NUM_LCLK_DPM_LEVELS 8 +#define SMU__NUM_PCIE_DPM_LEVELS 8 + +#include "smu7_discrete.h" +#include <pp_endian.h> +#include "ppatomctrl.h" + +struct ci_pt_defaults { + u8 svi_load_line_en; + u8 svi_load_line_vddc; + u8 tdc_vddc_throttle_release_limit_perc; + u8 tdc_mawt; + u8 tdc_waterfall_ctl; + u8 dte_ambient_temp_base; + u32 display_cac; + u32 bapm_temp_gradient; + u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; + u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; +}; + +struct ci_mc_reg_entry { + uint32_t mclk_max; + uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; +}; + +struct ci_mc_reg_table { + uint8_t last; + uint8_t num_entries; + uint16_t validflag; + struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; + SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; +}; + +struct ci_smumgr { + uint32_t soft_regs_start; + uint32_t dpm_table_start; + uint32_t mc_reg_table_start; + uint32_t fan_table_start; + uint32_t arb_table_start; + uint32_t ulv_setting_starts; + struct SMU7_Discrete_DpmTable smc_state_table; + struct SMU7_Discrete_PmFuses power_tune_table; + const struct ci_pt_defaults *power_tune_defaults; + SMU7_Discrete_MCRegisters mc_regs; + struct ci_mc_reg_table mc_reg_table; + uint32_t activity_target[SMU7_MAX_LEVELS_GRAPHICS]; + +}; + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c index 652aaa43e95c..78ab0556e48f 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c @@ -52,53 +52,52 @@ static const enum cz_scratch_entry firmware_list[] = { CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, }; -static int cz_smum_get_argument(struct pp_smumgr *smumgr) +static int cz_smum_get_argument(struct pp_hwmgr *hwmgr) { - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; - return cgs_read_register(smumgr->device, + return cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0); } -static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr, - uint16_t msg) +static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg) { int result = 0; - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; - result = SMUM_WAIT_FIELD_UNEQUAL(smumgr, + result = PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); if (result != 0) { pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg); return result; } - cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0); - cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg); + cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0); + cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg); return 0; } /* Send a message to the SMC, and wait for its response.*/ -static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) { int result = 0; - result = cz_send_msg_to_smc_async(smumgr, msg); + result = cz_send_msg_to_smc_async(hwmgr, msg); if (result != 0) return result; - return SMUM_WAIT_FIELD_UNEQUAL(smumgr, + return PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); } -static int cz_set_smc_sram_address(struct pp_smumgr *smumgr, +static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_address, uint32_t limit) { - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; if (0 != (3 & smc_address)) { @@ -111,39 +110,39 @@ static int cz_set_smc_sram_address(struct pp_smumgr *smumgr, return -EINVAL; } - cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX_0, + cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0, SMN_MP1_SRAM_START_ADDR + smc_address); return 0; } -static int cz_write_smc_sram_dword(struct pp_smumgr *smumgr, +static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_address, uint32_t value, uint32_t limit) { int result; - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; - result = cz_set_smc_sram_address(smumgr, smc_address, limit); + result = cz_set_smc_sram_address(hwmgr, smc_address, limit); if (!result) - cgs_write_register(smumgr->device, mmMP0PUB_IND_DATA_0, value); + cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value); return result; } -static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, +static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) { - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; - cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter); + cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter); - return cz_send_msg_to_smc(smumgr, msg); + return cz_send_msg_to_smc(hwmgr, msg); } -static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, +static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t firmware) { int i; @@ -151,19 +150,19 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, SMU8_FIRMWARE_HEADER_LOCATION + offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; - cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX, index); + cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index); - for (i = 0; i < smumgr->usec_timeout; i++) { + for (i = 0; i < hwmgr->usec_timeout; i++) { if (firmware == - (cgs_read_register(smumgr->device, mmMP0PUB_IND_DATA) & firmware)) + (cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware)) break; udelay(1); } - if (i >= smumgr->usec_timeout) { + if (i >= hwmgr->usec_timeout) { pr_err("SMU check loaded firmware failed.\n"); return -EINVAL; } @@ -171,7 +170,7 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, return 0; } -static int cz_load_mec_firmware(struct pp_smumgr *smumgr) +static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr) { uint32_t reg_data; uint32_t tmp; @@ -179,44 +178,44 @@ static int cz_load_mec_firmware(struct pp_smumgr *smumgr) struct cgs_firmware_info info = {0}; struct cz_smumgr *cz_smu; - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; - cz_smu = (struct cz_smumgr *)smumgr->backend; - ret = cgs_get_firmware_info(smumgr->device, + cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; + ret = cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_CP_MEC, &info); if (ret) return -EINVAL; /* Disable MEC parsing/prefetching */ - tmp = cgs_read_register(smumgr->device, + tmp = cgs_read_register(hwmgr->device, mmCP_MEC_CNTL); - tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); - tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); - cgs_write_register(smumgr->device, mmCP_MEC_CNTL, tmp); + tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); + tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); + cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp); - tmp = cgs_read_register(smumgr->device, + tmp = cgs_read_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); - cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); + cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); reg_data = smu_lower_32_bits(info.mc_addr) & - SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO); - cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_LO, reg_data); + PHM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO); + cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data); reg_data = smu_upper_32_bits(info.mc_addr) & - SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI); - cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_HI, reg_data); + PHM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI); + cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data); return 0; } -static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, +static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr, enum cz_scratch_entry firmware_enum) { uint8_t ret = 0; @@ -226,7 +225,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, ret = UCODE_ID_SDMA0; break; case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1: - if (smumgr->chip_id == CHIP_STONEY) + if (hwmgr->chip_id == CHIP_STONEY) ret = UCODE_ID_SDMA0; else ret = UCODE_ID_SDMA1; @@ -244,7 +243,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, ret = UCODE_ID_CP_MEC_JT1; break; case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2: - if (smumgr->chip_id == CHIP_STONEY) + if (hwmgr->chip_id == CHIP_STONEY) ret = UCODE_ID_CP_MEC_JT1; else ret = UCODE_ID_CP_MEC_JT2; @@ -326,17 +325,17 @@ static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type) } static int cz_smu_populate_single_scratch_task( - struct pp_smumgr *smumgr, + struct pp_hwmgr *hwmgr, enum cz_scratch_entry fw_enum, uint8_t type, bool is_last) { uint8_t i; - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; task->type = type; - task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum); + task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum); task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count; for (i = 0; i < cz_smu->scratch_buffer_length; i++) @@ -363,17 +362,17 @@ static int cz_smu_populate_single_scratch_task( } static int cz_smu_populate_single_ucode_load_task( - struct pp_smumgr *smumgr, + struct pp_hwmgr *hwmgr, enum cz_scratch_entry fw_enum, bool is_last) { uint8_t i; - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; task->type = TASK_TYPE_UCODE_LOAD; - task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum); + task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum); task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count; for (i = 0; i < cz_smu->driver_buffer_length; i++) @@ -392,22 +391,22 @@ static int cz_smu_populate_single_ucode_load_task( return 0; } -static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_smumgr *smumgr) +static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count; - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, TASK_TYPE_UCODE_SAVE, true); return 0; } -static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr) +static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr) { int i; - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; for (i = 0; i < NUM_JOBLIST_ENTRIES; i++) @@ -416,17 +415,17 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr) return 0; } -static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr) +static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count; - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, TASK_TYPE_UCODE_SAVE, false); - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, TASK_TYPE_UCODE_SAVE, true); @@ -434,121 +433,120 @@ static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr) } -static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr) +static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count; - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); - if (smumgr->chip_id == CHIP_STONEY) - cz_smu_populate_single_ucode_load_task(smumgr, + if (hwmgr->chip_id == CHIP_STONEY) + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); else - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false); /* populate scratch */ - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, TASK_TYPE_UCODE_LOAD, false); - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, TASK_TYPE_UCODE_LOAD, false); - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, TASK_TYPE_UCODE_LOAD, true); return 0; } -static int cz_smu_construct_toc_for_power_profiling( - struct pp_smumgr *smumgr) +static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count; - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, TASK_TYPE_INITIALIZE, true); return 0; } -static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr) +static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count; - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); - if (smumgr->chip_id != CHIP_STONEY) - cz_smu_populate_single_ucode_load_task(smumgr, + if (hwmgr->chip_id != CHIP_STONEY) + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); - if (smumgr->chip_id != CHIP_STONEY) - cz_smu_populate_single_ucode_load_task(smumgr, + if (hwmgr->chip_id != CHIP_STONEY) + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); - cz_smu_populate_single_ucode_load_task(smumgr, + cz_smu_populate_single_ucode_load_task(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true); return 0; } -static int cz_smu_construct_toc_for_clock_table(struct pp_smumgr *smumgr) +static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count; - cz_smu_populate_single_scratch_task(smumgr, + cz_smu_populate_single_scratch_task(hwmgr, CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, TASK_TYPE_INITIALIZE, true); return 0; } -static int cz_smu_construct_toc(struct pp_smumgr *smumgr) +static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; cz_smu->toc_entry_used_count = 0; - cz_smu_initialize_toc_empty_job_list(smumgr); - cz_smu_construct_toc_for_rlc_aram_save(smumgr); - cz_smu_construct_toc_for_vddgfx_enter(smumgr); - cz_smu_construct_toc_for_vddgfx_exit(smumgr); - cz_smu_construct_toc_for_power_profiling(smumgr); - cz_smu_construct_toc_for_bootup(smumgr); - cz_smu_construct_toc_for_clock_table(smumgr); + cz_smu_initialize_toc_empty_job_list(hwmgr); + cz_smu_construct_toc_for_rlc_aram_save(hwmgr); + cz_smu_construct_toc_for_vddgfx_enter(hwmgr); + cz_smu_construct_toc_for_vddgfx_exit(hwmgr); + cz_smu_construct_toc_for_power_profiling(hwmgr); + cz_smu_construct_toc_for_bootup(hwmgr); + cz_smu_construct_toc_for_clock_table(hwmgr); return 0; } -static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr) +static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; uint32_t firmware_type; uint32_t i; int ret; @@ -559,12 +557,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr) for (i = 0; i < ARRAY_SIZE(firmware_list); i++) { - firmware_type = cz_translate_firmware_enum_to_arg(smumgr, + firmware_type = cz_translate_firmware_enum_to_arg(hwmgr, firmware_list[i]); ucode_id = cz_convert_fw_type_to_cgs(firmware_type); - ret = cgs_get_firmware_info(smumgr->device, + ret = cgs_get_firmware_info(hwmgr->device, ucode_id, &info); if (ret == 0) { @@ -585,12 +583,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr) } static int cz_smu_populate_single_scratch_entry( - struct pp_smumgr *smumgr, + struct pp_hwmgr *hwmgr, enum cz_scratch_entry scratch_type, uint32_t ulsize_byte, struct cz_buffer_entry *entry) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; long long mc_addr = ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32) | cz_smu->smu_buffer.mc_addr_low; @@ -611,9 +609,9 @@ static int cz_smu_populate_single_scratch_entry( return 0; } -static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table) +static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; unsigned long i; for (i = 0; i < cz_smu->scratch_buffer_length; i++) { @@ -624,25 +622,25 @@ static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table) *table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr; - cz_send_msg_to_smc_with_parameter(smumgr, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetClkTableAddrHi, cz_smu->scratch_buffer[i].mc_addr_high); - cz_send_msg_to_smc_with_parameter(smumgr, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetClkTableAddrLo, cz_smu->scratch_buffer[i].mc_addr_low); - cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob, cz_smu->toc_entry_clock_table); - cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToDram); + cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram); return 0; } -static int cz_upload_pptable_settings(struct pp_smumgr *smumgr) +static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; + struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; unsigned long i; for (i = 0; i < cz_smu->scratch_buffer_length; i++) { @@ -651,63 +649,63 @@ static int cz_upload_pptable_settings(struct pp_smumgr *smumgr) break; } - cz_send_msg_to_smc_with_parameter(smumgr, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetClkTableAddrHi, cz_smu->scratch_buffer[i].mc_addr_high); - cz_send_msg_to_smc_with_parameter(smumgr, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetClkTableAddrLo, cz_smu->scratch_buffer[i].mc_addr_low); - cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob, cz_smu->toc_entry_clock_table); - cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToSmu); + cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu); return 0; } -static int cz_request_smu_load_fw(struct pp_smumgr *smumgr) +static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr) { - struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend); + struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smu_backend); uint32_t smc_address; - if (!smumgr->reload_fw) { + if (!hwmgr->reload_fw) { pr_info("skip reloading...\n"); return 0; } - cz_smu_populate_firmware_entries(smumgr); + cz_smu_populate_firmware_entries(hwmgr); - cz_smu_construct_toc(smumgr); + cz_smu_construct_toc(hwmgr); smc_address = SMU8_FIRMWARE_HEADER_LOCATION + offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); - cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4); + cz_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4); - cz_send_msg_to_smc_with_parameter(smumgr, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DriverDramAddrHi, cz_smu->toc_buffer.mc_addr_high); - cz_send_msg_to_smc_with_parameter(smumgr, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DriverDramAddrLo, cz_smu->toc_buffer.mc_addr_low); - cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs); + cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs); - cz_send_msg_to_smc_with_parameter(smumgr, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob, cz_smu->toc_entry_aram); - cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, + cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob, cz_smu->toc_entry_power_profiling_index); - return cz_send_msg_to_smc_with_parameter(smumgr, + return cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob, cz_smu->toc_entry_initialize_index); } -static int cz_start_smu(struct pp_smumgr *smumgr) +static int cz_start_smu(struct pp_hwmgr *hwmgr) { int ret = 0; uint32_t fw_to_check = 0; @@ -721,23 +719,23 @@ static int cz_start_smu(struct pp_smumgr *smumgr) UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK; - if (smumgr->chip_id == CHIP_STONEY) + if (hwmgr->chip_id == CHIP_STONEY) fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK); - ret = cz_request_smu_load_fw(smumgr); + ret = cz_request_smu_load_fw(hwmgr); if (ret) pr_err("SMU firmware load failed\n"); - cz_check_fw_load_finish(smumgr, fw_to_check); + cz_check_fw_load_finish(hwmgr, fw_to_check); - ret = cz_load_mec_firmware(smumgr); + ret = cz_load_mec_firmware(hwmgr); if (ret) pr_err("Mec Firmware load failed\n"); return ret; } -static int cz_smu_init(struct pp_smumgr *smumgr) +static int cz_smu_init(struct pp_hwmgr *hwmgr) { uint64_t mc_addr = 0; int ret = 0; @@ -747,7 +745,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) if (cz_smu == NULL) return -ENOMEM; - smumgr->backend = cz_smu; + hwmgr->smu_backend = cz_smu; cz_smu->toc_buffer.data_size = 4096; cz_smu->smu_buffer.data_size = @@ -757,7 +755,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) + ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32); - ret = smu_allocate_memory(smumgr->device, + ret = smu_allocate_memory(hwmgr->device, cz_smu->toc_buffer.data_size, CGS_GPU_MEM_TYPE__GART_CACHEABLE, PAGE_SIZE, @@ -770,7 +768,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); - ret = smu_allocate_memory(smumgr->device, + ret = smu_allocate_memory(hwmgr->device, cz_smu->smu_buffer.data_size, CGS_GPU_MEM_TYPE__GART_CACHEABLE, PAGE_SIZE, @@ -783,7 +781,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); - if (0 != cz_smu_populate_single_scratch_entry(smumgr, + if (0 != cz_smu_populate_single_scratch_entry(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, UCODE_ID_RLC_SCRATCH_SIZE_BYTE, &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { @@ -791,14 +789,14 @@ static int cz_smu_init(struct pp_smumgr *smumgr) return -1; } - if (0 != cz_smu_populate_single_scratch_entry(smumgr, + if (0 != cz_smu_populate_single_scratch_entry(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { pr_err("Error when Populate Firmware Entry.\n"); return -1; } - if (0 != cz_smu_populate_single_scratch_entry(smumgr, + if (0 != cz_smu_populate_single_scratch_entry(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { @@ -806,7 +804,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) return -1; } - if (0 != cz_smu_populate_single_scratch_entry(smumgr, + if (0 != cz_smu_populate_single_scratch_entry(hwmgr, CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, sizeof(struct SMU8_MultimediaPowerLogData), &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { @@ -814,7 +812,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr) return -1; } - if (0 != cz_smu_populate_single_scratch_entry(smumgr, + if (0 != cz_smu_populate_single_scratch_entry(hwmgr, CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, sizeof(struct SMU8_Fusion_ClkTable), &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { @@ -825,18 +823,18 @@ static int cz_smu_init(struct pp_smumgr *smumgr) return 0; } -static int cz_smu_fini(struct pp_smumgr *smumgr) +static int cz_smu_fini(struct pp_hwmgr *hwmgr) { struct cz_smumgr *cz_smu; - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; - cz_smu = (struct cz_smumgr *)smumgr->backend; + cz_smu = (struct cz_smumgr *)hwmgr->smu_backend; if (cz_smu) { - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, cz_smu->toc_buffer.handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, cz_smu->smu_buffer.handle); kfree(cz_smu); } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c index 8712f093d6d9..b1a66b5ada4a 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c @@ -198,7 +198,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda) static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -216,7 +216,7 @@ static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); @@ -299,7 +299,7 @@ static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; @@ -314,7 +314,7 @@ static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) { uint16_t tdc_limit; - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; @@ -334,11 +334,11 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; uint32_t temp; - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, fuse_table_offset + offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl), (uint32_t *)&temp, SMC_RAM_END)) @@ -359,7 +359,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr) { int i; - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -370,7 +370,7 @@ static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr) static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); if ((hwmgr->thermal_controller.advanceFanControlParameters. usFanOutputSensitivity & (1 << 15)) || @@ -389,7 +389,7 @@ static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr) { int i; - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -398,14 +398,9 @@ static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr) return 0; } -static int fiji_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) -{ - return 0; -} - static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; @@ -426,11 +421,11 @@ static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr) { uint32_t pm_fuse_table_offset; - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, PmFuseTable), &pm_fuse_table_offset, SMC_RAM_END)) @@ -472,19 +467,13 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr) "Attempt to populate GnbLPML Failed!", return -EINVAL); - /* DW19 */ - if (fiji_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate GnbLPML Min and Max Vid Failed!", - return -EINVAL); - /* DW20 */ if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate BapmVddCBaseLeakage Hi and Lo " "Sidd Failed!", return -EINVAL); - if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, + if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, (uint8_t *)&smu_data->power_tune_table, sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END)) PP_ASSERT_WITH_CODE(false, @@ -586,7 +575,7 @@ static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr, { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); int i; /* Index (dpm_table->pcie_speed_table.count) @@ -774,7 +763,7 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; struct phm_ppt_v1_information *table_info = @@ -859,7 +848,7 @@ int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) levels[1].pcieDpmLevel = mid_pcie_level_enabled; } /* level count will send to smc once at init smc table and never change */ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, (uint32_t)array_size, SMC_RAM_END); return result; @@ -1000,7 +989,7 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr, int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; int result; /* populate MCLK dpm table to SMU7 */ @@ -1043,7 +1032,7 @@ int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr) PPSMC_DISPLAY_WATERMARK_HIGH; /* level count will send to smc once at init smc table and never change */ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, (uint32_t)array_size, SMC_RAM_END); return result; @@ -1352,7 +1341,7 @@ static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct SMU73_Discrete_MCArbDramTimingTable arb_regs; uint32_t i, j; int result = 0; @@ -1370,7 +1359,7 @@ static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) if (!result) result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.arb_table_start, (uint8_t *)&arb_regs, sizeof(SMU73_Discrete_MCArbDramTimingTable), @@ -1460,7 +1449,7 @@ static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr, static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint8_t count, level; @@ -1491,7 +1480,7 @@ static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, volt_with_cks, value; uint16_t clock_freq_u16; - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, volt_offset = 0; struct phm_ppt_v1_information *table_info = @@ -1694,9 +1683,9 @@ static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr, return 0; } -static int fiji_init_arb_table_index(struct pp_smumgr *smumgr) +static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); uint32_t tmp; int result; @@ -1708,7 +1697,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr) * In reality this field should not be in that structure * but in a soft register. */ - result = smu7_read_smc_sram_dword(smumgr, + result = smu7_read_smc_sram_dword(hwmgr, smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); if (result) @@ -1717,13 +1706,13 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr) tmp &= 0x00FFFFFF; tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; - return smu7_write_smc_sram_dword(smumgr, + return smu7_write_smc_sram_dword(hwmgr, smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); } static int fiji_save_default_power_profile(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct SMU73_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel; unsigned min_level = 1; @@ -1782,7 +1771,7 @@ static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr) } } if (mask) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LedConfig, mask); return 0; @@ -1799,7 +1788,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) { int result; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table); @@ -1985,7 +1974,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, + result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable, SystemFlags), (uint8_t *)&(table->SystemFlags), @@ -1994,7 +1983,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(0 == result, "Failed to upload dpm data to SMC memory!", return result); - result = fiji_init_arb_table_index(hwmgr->smumgr); + result = fiji_init_arb_table_index(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to upload arb data to SMC memory!", return result); @@ -2022,7 +2011,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr) */ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; uint32_t duty100; @@ -2104,20 +2093,20 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); - res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start, + res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); if (!res && hwmgr->thermal_controller. advanceFanControlParameters.ucMinimumPWMLimit) - res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + res = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanMinPwm, hwmgr->thermal_controller. advanceFanControlParameters.ucMinimumPWMLimit); if (!res && hwmgr->thermal_controller. advanceFanControlParameters.ulMinFanSCLKAcousticLimit) - res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + res = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanSclkTarget, hwmgr->thermal_controller. advanceFanControlParameters.ulMinFanSCLKAcousticLimit); @@ -2133,13 +2122,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr) { int ret; - struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) return 0; - ret = smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs); if (!ret) /* If this param is not changed, this function could fire unnecessarily */ @@ -2162,7 +2150,7 @@ static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); int result = 0; uint32_t low_sclk_interrupt_threshold = 0; @@ -2179,7 +2167,7 @@ int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold), @@ -2256,7 +2244,7 @@ uint32_t fiji_get_mac_definition(uint32_t value) static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2280,7 +2268,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_UVDDPM) || phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDDPM_SetEnabledMask, (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); return 0; @@ -2288,7 +2276,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2312,7 +2300,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VCEDPM_SetEnabledMask, (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); return 0; @@ -2320,7 +2308,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr) { - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; @@ -2339,7 +2327,7 @@ static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SAMUDPM_SetEnabledMask, (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); return 0; @@ -2373,12 +2361,12 @@ int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); + struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend); uint32_t tmp; int result; bool error = false; - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, DpmTable), &tmp, SMC_RAM_END); @@ -2388,7 +2376,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, SoftRegisters), &tmp, SMC_RAM_END); @@ -2400,7 +2388,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, mcRegisterTable), &tmp, SMC_RAM_END); @@ -2408,7 +2396,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) if (!result) smu_data->smu7_data.mc_reg_table_start = tmp; - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, FanTable), &tmp, SMC_RAM_END); @@ -2418,7 +2406,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, mcArbDramTimingTable), &tmp, SMC_RAM_END); @@ -2428,7 +2416,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, Version), &tmp, SMC_RAM_END); @@ -2476,7 +2464,7 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, struct amd_pp_profile *request) { struct fiji_smumgr *smu_data = (struct fiji_smumgr *) - (hwmgr->smumgr->backend); + (hwmgr->smu_backend); struct SMU73_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; uint32_t array = smu_data->smu7_data.dpm_table_start + @@ -2493,6 +2481,6 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, levels[i].DownHyst = request->down_hyst; } - return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, array_size, SMC_RAM_END); } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c index 6ae948fc524f..5b25e067b2f1 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c @@ -58,122 +58,122 @@ static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = { { 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 } }; -static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr) +static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) { int result = 0; /* Wait for smc boot up */ - /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, + /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = smu7_upload_smu_firmware_image(smumgr); + result = smu7_upload_smu_firmware_image(hwmgr); if (result) return result; /* Clear status */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); /* De-assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); /* Wait for ROM firmware to initialize interrupt hendler */ - /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND, + /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND, SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */ /* Set SMU Auto Start */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_INPUT_DATA, AUTO_START, 1); /* Clear firmware interrupt enable flag */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); - cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); - cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000); + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); + PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); /* Wait for done bit to be set */ - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); /* Check pass/failed indicator */ - if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS) != 1) { PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); } /* Wait for firmware to initialize */ - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); return result; } -static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) +static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) { int result = 0; /* wait for smc boot up */ - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); /* Clear firmware interrupt enable flag */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); /* Assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = smu7_upload_smu_firmware_image(smumgr); + result = smu7_upload_smu_firmware_image(hwmgr); if (result) return result; /* Set smc instruct start point at 0x0 */ - smu7_program_jump_on_start(smumgr); + smu7_program_jump_on_start(hwmgr); /* Enable clock */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); /* De-assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); /* Wait for firmware to initialize */ - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); return result; } -static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) +static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr) { int i; int result = -EINVAL; uint32_t reg, data; const PWR_Command_Table *pvirus = PwrVirusTable; - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { switch (pvirus->command) { case PwrCmdWrite: reg = pvirus->reg; data = pvirus->data; - cgs_write_register(smumgr->device, reg, data); + cgs_write_register(hwmgr->device, reg, data); break; case PwrCmdEnd: @@ -192,13 +192,13 @@ static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) return result; } -static int fiji_start_avfs_btc(struct pp_smumgr *smumgr) +static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr) { int result = 0; - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); if (0 != smu_data->avfs.avfs_btc_param) { - if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, + if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed"); result = -EINVAL; @@ -206,23 +206,23 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr) } /* Soft-Reset to reset the engine before loading uCode */ /* halt */ - cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); + cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); /* reset everything */ - cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); + cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); /* clear reset */ - cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); + cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); return result; } -static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) +static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) { int32_t vr_config; uint32_t table_start; uint32_t level_addr, vr_config_addr; uint32_t level_size = sizeof(avfs_graphics_level); - PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, DpmTable), &table_start, 0x40000), @@ -237,7 +237,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) vr_config_addr = table_start + offsetof(SMU73_Discrete_DpmTable, VRConfig); - PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr, + PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr, (uint8_t *)&vr_config, sizeof(int32_t), 0x40000), "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying " "vr_config value over to SMC", @@ -245,7 +245,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); - PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr, + PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr, (uint8_t *)(&avfs_graphics_level), level_size, 0x40000), "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!", return -1;); @@ -253,9 +253,9 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) return 0; } -static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) +static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started) { - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); switch (smu_data->avfs.avfs_btc_status) { case AVFS_BTC_COMPLETED_PREVIOUSLY: @@ -265,17 +265,17 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) if (!smu_started) break; smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; - PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr), + PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr), "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level" " table over to SMU", return -EINVAL;); smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; - PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr), + PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(hwmgr), "[AVFS][fiji_avfs_event_mgr] Could not setup " "Pwr Virus for AVFS ", return -EINVAL;); smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; - PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr), + PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr), "[AVFS][fiji_avfs_event_mgr] Failure at " "fiji_start_avfs_btc. AVFS Disabled", return -EINVAL;); @@ -293,64 +293,64 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) return 0; } -static int fiji_start_smu(struct pp_smumgr *smumgr) +static int fiji_start_smu(struct pp_hwmgr *hwmgr) { int result = 0; - struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); + struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend); /* Only start SMC if SMC RAM is not running */ - if (!(smu7_is_smc_ram_running(smumgr) - || cgs_is_virtualization_enabled(smumgr->device))) { - fiji_avfs_event_mgr(smumgr, false); + if (!(smu7_is_smc_ram_running(hwmgr) + || cgs_is_virtualization_enabled(hwmgr->device))) { + fiji_avfs_event_mgr(hwmgr, false); /* Check if SMU is running in protected mode */ - if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, + if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)) { - result = fiji_start_smu_in_non_protection_mode(smumgr); + result = fiji_start_smu_in_non_protection_mode(hwmgr); if (result) return result; } else { - result = fiji_start_smu_in_protection_mode(smumgr); + result = fiji_start_smu_in_protection_mode(hwmgr); if (result) return result; } - fiji_avfs_event_mgr(smumgr, true); + fiji_avfs_event_mgr(hwmgr, true); } /* To initialize all clock gating before RLC loaded and running.*/ - cgs_set_clockgating_state(smumgr->device, + cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE); - cgs_set_clockgating_state(smumgr->device, + cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE); - cgs_set_clockgating_state(smumgr->device, + cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE); - cgs_set_clockgating_state(smumgr->device, + cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE); /* Setup SoftRegsStart here for register lookup in case * DummyBackEnd is used and ProcessFirmwareHeader is not executed */ - smu7_read_smc_sram_dword(smumgr, + smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header, SoftRegisters), &(priv->smu7_data.soft_regs_start), 0x40000); - result = smu7_request_smu_load_fw(smumgr); + result = smu7_request_smu_load_fw(hwmgr); return result; } -static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) +static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr) { uint32_t efuse = 0; uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; - if (cgs_is_virtualization_enabled(smumgr->device)) + if (cgs_is_virtualization_enabled(hwmgr->device)) return 0; - if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB, + if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB, mask, &efuse)) { if (efuse) return true; @@ -365,7 +365,7 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) * @param smc_addr the address in the SMC RAM to access. * @param value to write to the SMC SRAM. */ -static int fiji_smu_init(struct pp_smumgr *smumgr) +static int fiji_smu_init(struct pp_hwmgr *hwmgr) { int i; struct fiji_smumgr *fiji_priv = NULL; @@ -375,9 +375,9 @@ static int fiji_smu_init(struct pp_smumgr *smumgr) if (fiji_priv == NULL) return -ENOMEM; - smumgr->backend = fiji_priv; + hwmgr->smu_backend = fiji_priv; - if (smu7_init(smumgr)) + if (smu7_init(hwmgr)) return -EINVAL; for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c index 51adf04ab4b3..efb0fc033274 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c @@ -101,7 +101,7 @@ static const struct iceland_pt_defaults defaults_icelandpro = { static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) { - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); struct cgs_system_info sys_info = {0}; uint32_t dev_id; @@ -130,7 +130,7 @@ static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr) { - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; @@ -144,7 +144,7 @@ static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr) static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr) { uint16_t tdc_limit; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); @@ -159,11 +159,11 @@ static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr) static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) { - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; uint32_t temp; - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, fuse_table_offset + offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl), (uint32_t *)&temp, SMC_RAM_END)) @@ -184,7 +184,7 @@ static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr) static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr) { int i; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 8; i++) @@ -193,14 +193,9 @@ static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr) return 0; } -static int iceland_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) -{ - return 0; -} - static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) { - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; @@ -219,7 +214,7 @@ static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) { int i; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; @@ -245,7 +240,7 @@ static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) { int i; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); uint8_t *vid = smu_data->power_tune_table.VddCVid; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -264,12 +259,12 @@ static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) { - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); uint32_t pm_fuse_table_offset; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, PmFuseTable), &pm_fuse_table_offset, SMC_RAM_END)) @@ -317,19 +312,13 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) "Attempt to populate GnbLPML Failed!", return -EINVAL); - /* DW17 */ - if (iceland_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate GnbLPML Min and Max Vid Failed!", - return -EINVAL); - /* DW18 */ if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!", return -EINVAL); - if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, + if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, (uint8_t *)&smu_data->power_tune_table, sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END)) PP_ASSERT_WITH_CODE(false, @@ -339,7 +328,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) return 0; } -static int iceland_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, +static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table, uint32_t clock, uint32_t *vol) { @@ -601,7 +590,7 @@ static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discret { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); uint32_t i; /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ @@ -749,7 +738,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); /* populate graphics levels*/ - result = iceland_get_dependecy_volt_by_clk(hwmgr, + result = iceland_get_dependency_volt_by_clk(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, &graphic_level->MinVddc); PP_ASSERT_WITH_CODE((0 == result), @@ -816,7 +805,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, GraphicsLevel); @@ -892,7 +881,7 @@ int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; /* level count will send to smc once at init smc table and never change*/ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, + result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, SMC_RAM_END); @@ -1104,7 +1093,7 @@ static int iceland_populate_single_memory_level( uint32_t mclk_strobe_mode_threshold = 40000; if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { - result = iceland_get_dependecy_volt_by_clk(hwmgr, + result = iceland_get_dependency_volt_by_clk(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); PP_ASSERT_WITH_CODE((0 == result), "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); @@ -1113,7 +1102,7 @@ static int iceland_populate_single_memory_level( if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) { memory_level->MinVddci = memory_level->MinVddc; } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { - result = iceland_get_dependecy_volt_by_clk(hwmgr, + result = iceland_get_dependency_volt_by_clk(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk, memory_clock, &memory_level->MinVddci); @@ -1218,7 +1207,7 @@ static int iceland_populate_single_memory_level( int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; int result; @@ -1257,7 +1246,7 @@ int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr) smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; /* level count will send to smc once at init smc table and never change*/ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, + result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, SMC_RAM_END); @@ -1496,7 +1485,7 @@ static int iceland_populate_memory_timing_parameters( static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); int result = 0; SMU71_Discrete_MCArbDramTimingTable arb_regs; uint32_t i, j; @@ -1518,7 +1507,7 @@ static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) if (0 == result) { result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.arb_table_start, (uint8_t *)&arb_regs, sizeof(SMU71_Discrete_MCArbDramTimingTable), @@ -1534,7 +1523,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, { int result = 0; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); table->GraphicsBootLevel = 0; table->MemoryBootLevel = 0; @@ -1572,10 +1561,10 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, return result; } -static int iceland_populate_mc_reg_address(struct pp_smumgr *smumgr, +static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCRegisters *mc_reg_table) { - const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)smumgr->backend; + const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend; uint32_t i, j; @@ -1612,13 +1601,12 @@ static void iceland_convert_mc_registers( } } -static int iceland_convert_mc_reg_table_entry_to_smc( - struct pp_smumgr *smumgr, +static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU71_Discrete_MCRegisterSet *mc_reg_table_data ) { - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); uint32_t i = 0; for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { @@ -1648,7 +1636,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, for (i = 0; i < data->dpm_table.mclk_table.count; i++) { res = iceland_convert_mc_reg_table_entry_to_smc( - hwmgr->smumgr, + hwmgr, data->dpm_table.mclk_table.dpm_levels[i].value, &mc_regs->data[i] ); @@ -1662,8 +1650,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) { - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); uint32_t address; int32_t result; @@ -1682,7 +1669,7 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]); - return smu7_copy_bytes_to_smc(hwmgr->smumgr, address, + return smu7_copy_bytes_to_smc(hwmgr, address, (uint8_t *)&smu_data->mc_regs.data[0], sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, SMC_RAM_END); @@ -1691,11 +1678,10 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) { int result; - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters)); - result = iceland_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); + result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize MCRegTable for the MC register addresses!", return result;); @@ -1703,14 +1689,14 @@ static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize MCRegTable for driver state!", return result;); - return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start, + return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start, (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END); } static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); uint8_t count, level; count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); @@ -1739,7 +1725,7 @@ static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; @@ -1776,7 +1762,7 @@ static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit); CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit); - dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient); + dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); def1 = defaults->bapmti_r; def2 = defaults->bapmti_rc; @@ -1827,7 +1813,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) { int result; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table); @@ -1955,7 +1941,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.dpm_table_start + + result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, SystemFlags), (uint8_t *)&(table->SystemFlags), sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController), @@ -1965,7 +1951,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) "Failed to upload dpm data to SMC memory!", return result;); /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, + result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.ulv_setting_starts, (uint8_t *)&(smu_data->ulv_setting), sizeof(SMU71_Discrete_Ulv), @@ -1994,7 +1980,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) */ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) { - struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); + struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; uint32_t duty100; uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; @@ -2064,7 +2050,7 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) /* fan_table.FanControl_GL_Flag = 1; */ - res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); + res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); return 0; } @@ -2084,7 +2070,7 @@ static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); int result = 0; uint32_t low_sclk_interrupt_threshold = 0; @@ -2101,7 +2087,7 @@ int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold), @@ -2182,13 +2168,13 @@ uint32_t iceland_get_mac_definition(uint32_t value) int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); + struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend); uint32_t tmp; int result; bool error = false; - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, DpmTable), &tmp, SMC_RAM_END); @@ -2199,7 +2185,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, SoftRegisters), &tmp, SMC_RAM_END); @@ -2212,7 +2198,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, mcRegisterTable), &tmp, SMC_RAM_END); @@ -2221,7 +2207,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) smu7_data->mc_reg_table_start = tmp; } - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, FanTable), &tmp, SMC_RAM_END); @@ -2232,7 +2218,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, mcArbDramTimingTable), &tmp, SMC_RAM_END); @@ -2244,7 +2230,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, Version), &tmp, SMC_RAM_END); @@ -2255,7 +2241,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU71_FIRMWARE_HEADER_LOCATION + offsetof(SMU71_Firmware_Header, UlvSettings), &tmp, SMC_RAM_END); @@ -2522,7 +2508,7 @@ static int iceland_set_valid_flag(struct iceland_mc_reg_table *table) int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) { int result; - struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); + struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend); pp_atomctrl_mc_reg_table *table; struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table; uint8_t module_index = iceland_get_memory_modile_index(hwmgr); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c index 0bf2def3b659..78aa1122eacc 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c @@ -39,55 +39,55 @@ #define ICELAND_SMC_SIZE 0x20000 -static int iceland_start_smc(struct pp_smumgr *smumgr) +static int iceland_start_smc(struct pp_hwmgr *hwmgr) { - SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); return 0; } -static void iceland_reset_smc(struct pp_smumgr *smumgr) +static void iceland_reset_smc(struct pp_hwmgr *hwmgr) { - SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); } -static void iceland_stop_smc_clock(struct pp_smumgr *smumgr) +static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr) { - SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); } -static void iceland_start_smc_clock(struct pp_smumgr *smumgr) +static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr) { - SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); } -static int iceland_smu_start_smc(struct pp_smumgr *smumgr) +static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr) { /* set smc instruct start point at 0x0 */ - smu7_program_jump_on_start(smumgr); + smu7_program_jump_on_start(hwmgr); /* enable smc clock */ - iceland_start_smc_clock(smumgr); + iceland_start_smc_clock(hwmgr); /* de-assert reset */ - iceland_start_smc(smumgr); + iceland_start_smc(hwmgr); - SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, + PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); return 0; } -static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr, +static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, const uint8_t *src, uint32_t limit, uint32_t start_addr) { @@ -96,17 +96,17 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr, PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); - cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr); - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); while (byte_count >= 4) { data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; - cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data); + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); src += 4; byte_count -= 4; } - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); @@ -114,16 +114,16 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr, } -static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr) +static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr) { uint32_t val; struct cgs_firmware_info info = {0}; - if (smumgr == NULL || smumgr->device == NULL) + if (hwmgr == NULL || hwmgr->device == NULL) return -EINVAL; /* load SMC firmware */ - cgs_get_firmware_info(smumgr->device, + cgs_get_firmware_info(hwmgr->device, smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); if (info.image_size & 3) { @@ -137,56 +137,56 @@ static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr) } /* wait for smc boot up */ - SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, + PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); /* clear firmware interrupt enable flag */ - val = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, + val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_SYSCON_MISC_CNTL); - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_SYSCON_MISC_CNTL, val | 1); /* stop smc clock */ - iceland_stop_smc_clock(smumgr); + iceland_stop_smc_clock(hwmgr); /* reset smc */ - iceland_reset_smc(smumgr); - iceland_upload_smc_firmware_data(smumgr, info.image_size, + iceland_reset_smc(hwmgr); + iceland_upload_smc_firmware_data(hwmgr, info.image_size, (uint8_t *)info.kptr, ICELAND_SMC_SIZE, info.ucode_start_address); return 0; } -static int iceland_request_smu_load_specific_fw(struct pp_smumgr *smumgr, +static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr, uint32_t firmwareType) { return 0; } -static int iceland_start_smu(struct pp_smumgr *smumgr) +static int iceland_start_smu(struct pp_hwmgr *hwmgr) { int result; - result = iceland_smu_upload_firmware_image(smumgr); + result = iceland_smu_upload_firmware_image(hwmgr); if (result) return result; - result = iceland_smu_start_smc(smumgr); + result = iceland_smu_start_smc(hwmgr); if (result) return result; - if (!smu7_is_smc_ram_running(smumgr)) { + if (!smu7_is_smc_ram_running(hwmgr)) { pr_info("smu not running, upload firmware again \n"); - result = iceland_smu_upload_firmware_image(smumgr); + result = iceland_smu_upload_firmware_image(hwmgr); if (result) return result; - result = iceland_smu_start_smc(smumgr); + result = iceland_smu_start_smc(hwmgr); if (result) return result; } - result = smu7_request_smu_load_fw(smumgr); + result = smu7_request_smu_load_fw(hwmgr); return result; } @@ -198,7 +198,7 @@ static int iceland_start_smu(struct pp_smumgr *smumgr) * @param smcAddress the address in the SMC RAM to access. * @param value to write to the SMC SRAM. */ -static int iceland_smu_init(struct pp_smumgr *smumgr) +static int iceland_smu_init(struct pp_hwmgr *hwmgr) { int i; struct iceland_smumgr *iceland_priv = NULL; @@ -208,9 +208,9 @@ static int iceland_smu_init(struct pp_smumgr *smumgr) if (iceland_priv == NULL) return -ENOMEM; - smumgr->backend = iceland_priv; + hwmgr->smu_backend = iceland_priv; - if (smu7_init(smumgr)) + if (smu7_init(hwmgr)) return -EINVAL; for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h index 8eae01b37c40..802472530d34 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h @@ -39,7 +39,7 @@ struct iceland_pt_defaults { uint8_t tdc_waterfall_ctl; uint8_t dte_ambient_temp_base; uint32_t display_cac; - uint32_t bamp_temp_gradient; + uint32_t bapm_temp_gradient; uint16_t bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS]; uint16_t bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS]; }; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c index 99a00bd39256..c92ea38d2e15 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c @@ -148,7 +148,7 @@ static uint16_t scale_fan_gain_settings(uint16_t raw_setting) static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); @@ -196,7 +196,7 @@ static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmg static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; @@ -210,7 +210,7 @@ static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) { uint16_t tdc_limit; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; @@ -227,11 +227,11 @@ static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; uint32_t temp; - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, fuse_table_offset + offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), (uint32_t *)&temp, SMC_RAM_END)) @@ -252,7 +252,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) { int i; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -263,7 +263,7 @@ static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); /* TO DO move to hwmgr */ if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) @@ -279,7 +279,7 @@ static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) { int i; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -288,14 +288,9 @@ static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) return 0; } -static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) -{ - return 0; -} - static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; @@ -315,12 +310,12 @@ static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint32_t pm_fuse_table_offset; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, PmFuseTable), &pm_fuse_table_offset, SMC_RAM_END)) @@ -358,17 +353,12 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) "Attempt to populate GnbLPML Failed!", return -EINVAL); - if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate GnbLPML Min and Max Vid Failed!", - return -EINVAL); - if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate BapmVddCBaseLeakage Hi and Lo " "Sidd Failed!", return -EINVAL); - if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, + if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, (uint8_t *)&smu_data->power_tune_table, (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END)) PP_ASSERT_WITH_CODE(false, @@ -494,7 +484,6 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct pp_smumgr *smumgr = hwmgr->smumgr; state->CcPwrDynRm = 0; state->CcPwrDynRm1 = 0; @@ -503,7 +492,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); - if (smumgr->chip_id == CHIP_POLARIS12 || smumgr->is_kicker) + if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; else state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; @@ -525,7 +514,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; int i; @@ -556,8 +545,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, SMU74_Discrete_DpmTable *table) { - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint32_t i, ref_clk; struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; @@ -607,8 +595,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, SMU_SclkSetting *sclk_setting) { - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); struct pp_atomctrl_clock_dividers_ai dividers; uint32_t ref_clock; @@ -751,9 +738,8 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, */ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) { - struct pp_smumgr *smumgr = hwmgr->smumgr; struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -838,7 +824,7 @@ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) levels[1].pcieDpmLevel = mid_pcie_level_enabled; } /* level count will send to smc once at init smc table and never change */ - result = smu7_copy_bytes_to_smc(smumgr, array, (uint8_t *)levels, + result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, (uint32_t)array_size, SMC_RAM_END); return result; @@ -880,7 +866,7 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, if (mclk_stutter_mode_threshold && (clock <= mclk_stutter_mode_threshold) && - (SMUM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, + (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)) mem_level->StutterEnable = true; @@ -900,9 +886,8 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, */ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) { - struct pp_smumgr *smumgr = hwmgr->smumgr; struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; int result; /* populate MCLK dpm table to SMU7 */ @@ -943,7 +928,7 @@ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); /* level count will send to smc once at init smc table and never change */ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, (uint32_t)array_size, SMC_RAM_END); return result; @@ -1201,9 +1186,8 @@ static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { - struct pp_smumgr *smumgr = hwmgr->smumgr; struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct SMU74_Discrete_MCArbDramTimingTable arb_regs; uint32_t i, j; int result = 0; @@ -1222,7 +1206,7 @@ static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) } result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.arb_table_start, (uint8_t *)&arb_regs, sizeof(SMU74_Discrete_MCArbDramTimingTable), @@ -1321,9 +1305,8 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr, static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) { - struct pp_smumgr *smumgr = hwmgr->smumgr; struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint8_t count, level; @@ -1354,8 +1337,7 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) { uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0; struct phm_ppt_v1_information *table_info = @@ -1438,7 +1420,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint16_t config; config = VR_MERGED_WITH_VDDC; @@ -1482,8 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); int result = 0; @@ -1534,20 +1515,20 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100); } - result = smu7_read_smc_sram_dword(smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma), &tmp, SMC_RAM_END); - smu7_copy_bytes_to_smc(smumgr, + smu7_copy_bytes_to_smc(hwmgr, tmp, (uint8_t *)&AVFS_meanNsigma, sizeof(AVFS_meanNsigma_t), SMC_RAM_END); - result = smu7_read_smc_sram_dword(smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable), &tmp, SMC_RAM_END); - smu7_copy_bytes_to_smc(smumgr, + smu7_copy_bytes_to_smc(hwmgr, tmp, (uint8_t *)&AVFS_SclkOffset, sizeof(AVFS_Sclk_Offset_t), @@ -1569,9 +1550,9 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr) +static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint32_t tmp; int result; @@ -1583,7 +1564,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr) * In reality this field should not be in that structure * but in a soft register. */ - result = smu7_read_smc_sram_dword(smumgr, + result = smu7_read_smc_sram_dword(hwmgr, smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); if (result) @@ -1592,13 +1573,13 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr) tmp &= 0x00FFFFFF; tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; - return smu7_write_smc_sram_dword(smumgr, + return smu7_write_smc_sram_dword(hwmgr, smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); } static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -1615,7 +1596,7 @@ static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct SMU74_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel; unsigned min_level = 1; @@ -1658,9 +1639,9 @@ static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr) int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) { int result; - struct pp_smumgr *smumgr = hwmgr->smumgr; struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); + struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); @@ -1852,7 +1833,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, + result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, SystemFlags), (uint8_t *)&(table->SystemFlags), @@ -1861,7 +1842,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(0 == result, "Failed to upload dpm data to SMC memory!", return result); - result = polaris10_init_arb_table_index(hwmgr->smumgr); + result = polaris10_init_arb_table_index(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to upload arb data to SMC memory!", return result); @@ -1888,17 +1869,16 @@ static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) { int ret; - struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED) return 0; - ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting); - ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ? + ret = (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs) == 0) ? 0 : -1; if (!ret) @@ -1919,7 +1899,7 @@ int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) */ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; uint32_t duty100; uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; @@ -2000,20 +1980,20 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); - res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start, + res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END); if (!res && hwmgr->thermal_controller. advanceFanControlParameters.ucMinimumPWMLimit) - res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + res = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanMinPwm, hwmgr->thermal_controller. advanceFanControlParameters.ucMinimumPWMLimit); if (!res && hwmgr->thermal_controller. advanceFanControlParameters.ulMinFanSCLKAcousticLimit) - res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + res = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanSclkTarget, hwmgr->thermal_controller. advanceFanControlParameters.ulMinFanSCLKAcousticLimit); @@ -2027,7 +2007,7 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2051,7 +2031,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_UVDDPM) || phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDDPM_SetEnabledMask, (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); return 0; @@ -2059,7 +2039,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2083,7 +2063,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VCEDPM_SetEnabledMask, (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); return 0; @@ -2091,7 +2071,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; @@ -2110,7 +2090,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SAMUDPM_SetEnabledMask, (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); return 0; @@ -2119,7 +2099,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr) static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; @@ -2157,7 +2137,7 @@ int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); int result = 0; uint32_t low_sclk_interrupt_threshold = 0; @@ -2174,7 +2154,7 @@ int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold), @@ -2262,13 +2242,13 @@ uint32_t polaris10_get_mac_definition(uint32_t value) */ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) { - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); uint32_t tmp; int result; bool error = false; - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), &tmp, SMC_RAM_END); @@ -2278,7 +2258,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), &tmp, SMC_RAM_END); @@ -2290,7 +2270,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, mcRegisterTable), &tmp, SMC_RAM_END); @@ -2298,7 +2278,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) if (!result) smu_data->smu7_data.mc_reg_table_start = tmp; - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, FanTable), &tmp, SMC_RAM_END); @@ -2308,7 +2288,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), &tmp, SMC_RAM_END); @@ -2318,7 +2298,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, Version), &tmp, SMC_RAM_END); @@ -2342,7 +2322,7 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, struct amd_pp_profile *request) { struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *) - (hwmgr->smumgr->backend); + (hwmgr->smu_backend); struct SMU74_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; uint32_t array = smu_data->smu7_data.dpm_table_start + @@ -2359,6 +2339,6 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, levels[i].DownHyst = request->down_hyst; } - return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, array_size, SMC_RAM_END); } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c index 75f43dadc56b..22b8ecbf7fce 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -60,21 +60,21 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = { 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00}; -static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) +static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr) { int i; int result = -EINVAL; uint32_t reg, data; const PWR_Command_Table *pvirus = pwr_virus_table; - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { switch (pvirus->command) { case PwrCmdWrite: reg = pvirus->reg; data = pvirus->data; - cgs_write_register(smumgr->device, reg, data); + cgs_write_register(hwmgr->device, reg, data); break; case PwrCmdEnd: @@ -93,13 +93,13 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) return result; } -static int polaris10_perform_btc(struct pp_smumgr *smumgr) +static int polaris10_perform_btc(struct pp_hwmgr *hwmgr) { int result = 0; - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); if (0 != smu_data->avfs.avfs_btc_param) { - if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { + if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); result = -1; } @@ -107,16 +107,16 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr) if (smu_data->avfs.avfs_btc_param > 1) { /* Soft-Reset to reset the engine before loading uCode */ /* halt */ - cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); + cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); /* reset everything */ - cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); - cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); + cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); + cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); } return result; } -static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) +static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) { uint32_t vr_config; uint32_t dpm_table_start; @@ -127,7 +127,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) graphics_level_size = sizeof(avfs_graphics_level_polaris10); u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); - PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), &dpm_table_start, 0x40000), "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", @@ -138,14 +138,14 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); - PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address, + PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", return -1); graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); - PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, + PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, (uint8_t *)(&avfs_graphics_level_polaris10), graphics_level_size, 0x40000), "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", @@ -153,7 +153,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); - PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, + PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", return -1); @@ -162,7 +162,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); - PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address, + PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!", return -1); @@ -172,9 +172,9 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) static int -polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) +polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT) { - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); switch (smu_data->avfs.avfs_btc_status) { case AVFS_BTC_COMPLETED_PREVIOUSLY: @@ -183,20 +183,20 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */ smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED; - PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr), + PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr), "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", return -EINVAL); if (smu_data->avfs.avfs_btc_param > 1) { pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; - PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(smumgr), + PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(hwmgr), "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", return -EINVAL); } smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; - PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr), + PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr), "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled", return -EINVAL); smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS; @@ -215,146 +215,146 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) return 0; } -static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr) +static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) { int result = 0; /* Wait for smc boot up */ - /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ + /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ /* Assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = smu7_upload_smu_firmware_image(smumgr); + result = smu7_upload_smu_firmware_image(hwmgr); if (result != 0) return result; /* Clear status */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); /* De-assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); /* Call Test SMU message with 0x20000 offset to trigger SMU start */ - smu7_send_msg_to_smc_offset(smumgr); + smu7_send_msg_to_smc_offset(hwmgr); /* Wait done bit to be set */ /* Check pass/failed indicator */ - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); + PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); - if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); /* Wait for firmware to initialize */ - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); return result; } -static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) +static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) { int result = 0; /* wait for smc boot up */ - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); + PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); /* Clear firmware interrupt enable flag */ - /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = smu7_upload_smu_firmware_image(smumgr); + result = smu7_upload_smu_firmware_image(hwmgr); if (result != 0) return result; /* Set smc instruct start point at 0x0 */ - smu7_program_jump_on_start(smumgr); + smu7_program_jump_on_start(hwmgr); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); /* Wait for firmware to initialize */ - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); return result; } -static int polaris10_start_smu(struct pp_smumgr *smumgr) +static int polaris10_start_smu(struct pp_hwmgr *hwmgr) { int result = 0; - struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); bool SMU_VFT_INTACT; /* Only start SMC if SMC RAM is not running */ - if (!smu7_is_smc_ram_running(smumgr)) { + if (!smu7_is_smc_ram_running(hwmgr)) { SMU_VFT_INTACT = false; - smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); - smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); + smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); + smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); /* Check if SMU is running in protected mode */ if (smu_data->protected_mode == 0) { - result = polaris10_start_smu_in_non_protection_mode(smumgr); + result = polaris10_start_smu_in_non_protection_mode(hwmgr); } else { - result = polaris10_start_smu_in_protection_mode(smumgr); + result = polaris10_start_smu_in_protection_mode(hwmgr); /* If failed, try with different security Key. */ if (result != 0) { smu_data->smu7_data.security_hard_key ^= 1; - cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); - result = polaris10_start_smu_in_protection_mode(smumgr); + cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU); + result = polaris10_start_smu_in_protection_mode(hwmgr); } } if (result != 0) PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); - polaris10_avfs_event_mgr(smumgr, true); + polaris10_avfs_event_mgr(hwmgr, true); } else SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */ - polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT); + polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT); /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ - smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), + smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), &(smu_data->smu7_data.soft_regs_start), 0x40000); - result = smu7_request_smu_load_fw(smumgr); + result = smu7_request_smu_load_fw(hwmgr); return result; } -static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr) +static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr) { uint32_t efuse; - efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4)); + efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4)); efuse &= 0x00000001; if (efuse) return true; @@ -362,7 +362,7 @@ static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr) return false; } -static int polaris10_smu_init(struct pp_smumgr *smumgr) +static int polaris10_smu_init(struct pp_hwmgr *hwmgr) { struct polaris10_smumgr *smu_data; int i; @@ -371,9 +371,9 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr) if (smu_data == NULL) return -ENOMEM; - smumgr->backend = smu_data; + hwmgr->smu_backend = smu_data; - if (smu7_init(smumgr)) + if (smu7_init(hwmgr)) return -EINVAL; for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c index ce0a30388ea1..b98ade676d12 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c @@ -48,20 +48,20 @@ #define smnMP1_FIRMWARE_FLAGS 0x3010028 -bool rv_is_smc_ram_running(struct pp_smumgr *smumgr) +bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr) { uint32_t mp1_fw_flags, reg; reg = soc15_get_register_offset(NBIF_HWID, 0, mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); - cgs_write_register(smumgr->device, reg, + cgs_write_register(hwmgr->device, reg, (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); reg = soc15_get_register_offset(NBIF_HWID, 0, mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); - mp1_fw_flags = cgs_read_register(smumgr->device, reg); + mp1_fw_flags = cgs_read_register(hwmgr->device, reg); if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) return true; @@ -69,97 +69,97 @@ bool rv_is_smc_ram_running(struct pp_smumgr *smumgr) return false; } -static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr) +static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr) { uint32_t reg; - if (!rv_is_smc_ram_running(smumgr)) + if (!rv_is_smc_ram_running(hwmgr)) return -EINVAL; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); - smum_wait_for_register_unequal(smumgr, reg, + phm_wait_for_register_unequal(hwmgr, reg, 0, MP1_C2PMSG_90__CONTENT_MASK); - return cgs_read_register(smumgr->device, reg); + return cgs_read_register(hwmgr->device, reg); } -int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, +int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg) { uint32_t reg; - if (!rv_is_smc_ram_running(smumgr)) + if (!rv_is_smc_ram_running(hwmgr)) return -EINVAL; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); - cgs_write_register(smumgr->device, reg, msg); + cgs_write_register(hwmgr->device, reg, msg); return 0; } -int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) +int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg) { uint32_t reg; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); - *arg = cgs_read_register(smumgr->device, reg); + *arg = cgs_read_register(hwmgr->device, reg); return 0; } -int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) { uint32_t reg; - rv_wait_for_response(smumgr); + rv_wait_for_response(hwmgr); reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); - cgs_write_register(smumgr->device, reg, 0); + cgs_write_register(hwmgr->device, reg, 0); - rv_send_msg_to_smc_without_waiting(smumgr, msg); + rv_send_msg_to_smc_without_waiting(hwmgr, msg); - if (rv_wait_for_response(smumgr) == 0) + if (rv_wait_for_response(hwmgr) == 0) printk("Failed to send Message %x.\n", msg); return 0; } -int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, +int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) { uint32_t reg; - rv_wait_for_response(smumgr); + rv_wait_for_response(hwmgr); reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); - cgs_write_register(smumgr->device, reg, 0); + cgs_write_register(hwmgr->device, reg, 0); reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); - cgs_write_register(smumgr->device, reg, parameter); + cgs_write_register(hwmgr->device, reg, parameter); - rv_send_msg_to_smc_without_waiting(smumgr, msg); + rv_send_msg_to_smc_without_waiting(hwmgr, msg); - if (rv_wait_for_response(smumgr) == 0) + if (rv_wait_for_response(hwmgr) == 0) printk("Failed to send Message %x.\n", msg); return 0; } -int rv_copy_table_from_smc(struct pp_smumgr *smumgr, +int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id) { struct rv_smumgr *priv = - (struct rv_smumgr *)(smumgr->backend); + (struct rv_smumgr *)(hwmgr->smu_backend); PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, "Invalid SMU Table ID!", return -EINVAL;); @@ -167,16 +167,16 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr, "Invalid SMU Table version!", return -EINVAL;); PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, "Invalid SMU Table Length!", return -EINVAL;); - PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, priv->smu_tables.entry[table_id].table_addr_high) == 0, "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;); - PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrLow, priv->smu_tables.entry[table_id].table_addr_low) == 0, "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", return -EINVAL;); - PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_TransferTableSmu2Dram, priv->smu_tables.entry[table_id].table_id) == 0, "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", @@ -188,11 +188,11 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr, return 0; } -int rv_copy_table_to_smc(struct pp_smumgr *smumgr, +int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id) { struct rv_smumgr *priv = - (struct rv_smumgr *)(smumgr->backend); + (struct rv_smumgr *)(hwmgr->smu_backend); PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, "Invalid SMU Table ID!", return -EINVAL;); @@ -204,17 +204,17 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr, memcpy(priv->smu_tables.entry[table_id].table, table, priv->smu_tables.entry[table_id].size); - PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, priv->smu_tables.entry[table_id].table_addr_high) == 0, "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;); - PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrLow, priv->smu_tables.entry[table_id].table_addr_low) == 0, "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", return -EINVAL;); - PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_TransferTableDram2Smu, priv->smu_tables.entry[table_id].table_id) == 0, "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", @@ -223,15 +223,15 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr, return 0; } -static int rv_verify_smc_interface(struct pp_smumgr *smumgr) +static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr) { uint32_t smc_driver_if_version; - PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr, PPSMC_MSG_GetDriverIfVersion), "Attempt to get SMC IF Version Number Failed!", return -EINVAL); - PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr, + PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr, &smc_driver_if_version), "Attempt to read SMC IF Version Number Failed!", return -EINVAL); @@ -243,9 +243,9 @@ static int rv_verify_smc_interface(struct pp_smumgr *smumgr) } /* sdma is disabled by default in vbios, need to re-enable in driver */ -static int rv_smc_enable_sdma(struct pp_smumgr *smumgr) +static int rv_smc_enable_sdma(struct pp_hwmgr *hwmgr) { - PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma), "Attempt to power up sdma Failed!", return -EINVAL); @@ -253,9 +253,9 @@ static int rv_smc_enable_sdma(struct pp_smumgr *smumgr) return 0; } -static int rv_smc_disable_sdma(struct pp_smumgr *smumgr) +static int rv_smc_disable_sdma(struct pp_hwmgr *hwmgr) { - PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr, + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma), "Attempt to power down sdma Failed!", return -EINVAL); @@ -264,9 +264,9 @@ static int rv_smc_disable_sdma(struct pp_smumgr *smumgr) } /* vcn is disabled by default in vbios, need to re-enable in driver */ -static int rv_smc_enable_vcn(struct pp_smumgr *smumgr) +static int rv_smc_enable_vcn(struct pp_hwmgr *hwmgr) { - PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PowerUpVcn, 0), "Attempt to power up vcn Failed!", return -EINVAL); @@ -274,9 +274,9 @@ static int rv_smc_enable_vcn(struct pp_smumgr *smumgr) return 0; } -static int rv_smc_disable_vcn(struct pp_smumgr *smumgr) +static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr) { - PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PowerDownVcn, 0), "Attempt to power down vcn Failed!", return -EINVAL); @@ -284,38 +284,38 @@ static int rv_smc_disable_vcn(struct pp_smumgr *smumgr) return 0; } -static int rv_smu_fini(struct pp_smumgr *smumgr) +static int rv_smu_fini(struct pp_hwmgr *hwmgr) { struct rv_smumgr *priv = - (struct rv_smumgr *)(smumgr->backend); + (struct rv_smumgr *)(hwmgr->smu_backend); if (priv) { - rv_smc_disable_sdma(smumgr); - rv_smc_disable_vcn(smumgr); - cgs_free_gpu_mem(smumgr->device, + rv_smc_disable_sdma(hwmgr); + rv_smc_disable_vcn(hwmgr); + cgs_free_gpu_mem(hwmgr->device, priv->smu_tables.entry[WMTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, priv->smu_tables.entry[CLOCKTABLE].handle); - kfree(smumgr->backend); - smumgr->backend = NULL; + kfree(hwmgr->smu_backend); + hwmgr->smu_backend = NULL; } return 0; } -static int rv_start_smu(struct pp_smumgr *smumgr) +static int rv_start_smu(struct pp_hwmgr *hwmgr) { - if (rv_verify_smc_interface(smumgr)) + if (rv_verify_smc_interface(hwmgr)) return -EINVAL; - if (rv_smc_enable_sdma(smumgr)) + if (rv_smc_enable_sdma(hwmgr)) return -EINVAL; - if (rv_smc_enable_vcn(smumgr)) + if (rv_smc_enable_vcn(hwmgr)) return -EINVAL; return 0; } -static int rv_smu_init(struct pp_smumgr *smumgr) +static int rv_smu_init(struct pp_hwmgr *hwmgr) { struct rv_smumgr *priv; uint64_t mc_addr; @@ -327,10 +327,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr) if (!priv) return -ENOMEM; - smumgr->backend = priv; + hwmgr->smu_backend = priv; /* allocate space for watermarks table */ - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, sizeof(Watermarks_t), CGS_GPU_MEM_TYPE__GART_CACHEABLE, PAGE_SIZE, @@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(kaddr, "[rv_smu_init] Out of memory for wmtable.", - kfree(smumgr->backend); - smumgr->backend = NULL; + kfree(hwmgr->smu_backend); + hwmgr->smu_backend = NULL; return -EINVAL); priv->smu_tables.entry[WMTABLE].version = 0x01; @@ -355,7 +355,7 @@ static int rv_smu_init(struct pp_smumgr *smumgr) priv->smu_tables.entry[WMTABLE].handle = handle; /* allocate space for watermarks table */ - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, sizeof(DpmClocks_t), CGS_GPU_MEM_TYPE__GART_CACHEABLE, PAGE_SIZE, @@ -365,10 +365,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(kaddr, "[rv_smu_init] Out of memory for CLOCKTABLE.", - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); - kfree(smumgr->backend); - smumgr->backend = NULL; + kfree(hwmgr->smu_backend); + hwmgr->smu_backend = NULL; return -EINVAL); priv->smu_tables.entry[CLOCKTABLE].version = 0x01; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h index 262c8ded87c0..58888400f1b8 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h @@ -51,11 +51,11 @@ struct rv_smumgr { struct smu_table_array smu_tables; }; -int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); -bool rv_is_smc_ram_running(struct pp_smumgr *smumgr); -int rv_copy_table_from_smc(struct pp_smumgr *smumgr, +int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg); +bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr); +int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id); -int rv_copy_table_to_smc(struct pp_smumgr *smumgr, +int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c index 76347ff6d655..2ae05bbdb974 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c @@ -34,18 +34,18 @@ #define SMU7_SMC_SIZE 0x20000 -static int smu7_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) +static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit) { PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); - cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr); - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ return 0; } -int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) +int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) { uint32_t data; uint32_t addr; @@ -59,7 +59,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres addr = smc_start_address; while (byte_count >= 4) { - smu7_read_smc_sram_dword(smumgr, addr, &data, limit); + smu7_read_smc_sram_dword(hwmgr, addr, &data, limit); *dest = PP_SMC_TO_HOST_UL(data); @@ -69,7 +69,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres } if (byte_count) { - smu7_read_smc_sram_dword(smumgr, addr, &data, limit); + smu7_read_smc_sram_dword(hwmgr, addr, &data, limit); *pdata = PP_SMC_TO_HOST_UL(data); /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */ dest_byte = (uint8_t *)dest; @@ -81,7 +81,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres } -int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, +int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit) { int result; @@ -99,12 +99,12 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, /* Bytes are written into the SMC addres space with the MSB first. */ data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; - result = smu7_set_smc_sram_address(smumgr, addr, limit); + result = smu7_set_smc_sram_address(hwmgr, addr, limit); if (0 != result) return result; - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data); src += 4; byte_count -= 4; @@ -115,13 +115,13 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, data = 0; - result = smu7_set_smc_sram_address(smumgr, addr, limit); + result = smu7_set_smc_sram_address(hwmgr, addr, limit); if (0 != result) return result; - original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); + original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11); extra_shift = 8 * (4 - byte_count); @@ -135,53 +135,53 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, data |= (original_data & ~((~0UL) << extra_shift)); - result = smu7_set_smc_sram_address(smumgr, addr, limit); + result = smu7_set_smc_sram_address(hwmgr, addr, limit); if (0 != result) return result; - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data); } return 0; } -int smu7_program_jump_on_start(struct pp_smumgr *smumgr) +int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr) { static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; - smu7_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); + smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1); return 0; } -bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr) +bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr) { - return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) - && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); + return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) + && (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); } -int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) { int ret; - if (!smu7_is_smc_ram_running(smumgr)) + if (!smu7_is_smc_ram_running(hwmgr)) return -EINVAL; - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); - ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); + ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); if (ret != 1) pr_info("\n failed to send pre message %x ret is %d \n", msg, ret); - cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg); - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); - ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); + ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP); if (ret != 1) pr_info("\n failed to send message %x ret is %d \n", msg, ret); @@ -189,53 +189,53 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) return 0; } -int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) +int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg) { - cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg); return 0; } -int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) { - if (!smu7_is_smc_ram_running(smumgr)) { + if (!smu7_is_smc_ram_running(hwmgr)) { return -EINVAL; } - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); - cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter); - return smu7_send_msg_to_smc(smumgr, msg); + return smu7_send_msg_to_smc(hwmgr, msg); } -int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) { - cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter); - return smu7_send_msg_to_smc_without_waiting(smumgr, msg); + return smu7_send_msg_to_smc_without_waiting(hwmgr, msg); } -int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr) +int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr) { - cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); + cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000); - cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); + cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test); - SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); + PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0); - if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) + if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP)) pr_info("Failed to send Message.\n"); return 0; } -int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr) +int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr) { - if (!smu7_is_smc_ram_running(smumgr)) + if (!smu7_is_smc_ram_running(hwmgr)) return -EINVAL; - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); return 0; } @@ -289,29 +289,29 @@ enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type) } -int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) +int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) { int result; - result = smu7_set_smc_sram_address(smumgr, smc_addr, limit); + result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit); if (result) return result; - *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11); + *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11); return 0; } -int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) +int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit) { int result; - result = smu7_set_smc_sram_address(smumgr, smc_addr, limit); + result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit); if (result) return result; - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value); + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value); return 0; } @@ -354,14 +354,14 @@ static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type) return result; } -static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, +static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr, uint32_t fw_type, struct SMU_Entry *entry) { int result = 0; struct cgs_firmware_info info = {0}; - result = cgs_get_firmware_info(smumgr->device, + result = cgs_get_firmware_info(hwmgr->device, smu7_convert_fw_type_to_cgs(fw_type), &info); @@ -374,13 +374,14 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, entry->meta_data_addr_low = 0; /* digest need be excluded out */ - if (cgs_is_virtualization_enabled(smumgr->device)) + if (cgs_is_virtualization_enabled(hwmgr->device)) info.image_size -= 20; entry->data_size_byte = info.image_size; entry->num_register_entries = 0; } - if (fw_type == UCODE_ID_RLC_G) + if ((fw_type == UCODE_ID_RLC_G) + || (fw_type == UCODE_ID_CP_MEC)) entry->flags = 1; else entry->flags = 0; @@ -388,30 +389,30 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, return 0; } -int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) +int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr) { - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); uint32_t fw_to_load; int result = 0; struct SMU_DRAMData_TOC *toc; - if (!smumgr->reload_fw) { + if (!hwmgr->reload_fw) { pr_info("skip reloading...\n"); return 0; } if (smu_data->soft_regs_start) - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, - smu_data->soft_regs_start + smum_get_offsetof(smumgr, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, + smu_data->soft_regs_start + smum_get_offsetof(hwmgr, SMU_SoftRegisters, UcodeLoadStatus), 0x0); - if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */ - if (!cgs_is_virtualization_enabled(smumgr->device)) { - smu7_send_msg_to_smc_with_parameter(smumgr, + if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */ + if (!cgs_is_virtualization_enabled(hwmgr->device)) { + smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); - smu7_send_msg_to_smc_with_parameter(smumgr, + smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); } @@ -438,80 +439,79 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) toc->num_entries = 0; toc->structure_version = 1; - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - if (cgs_is_virtualization_enabled(smumgr->device)) - PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + if (cgs_is_virtualization_enabled(hwmgr->device)) + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); - smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); - smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); + smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); + smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); - if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) + if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load)) pr_err("Fail to Request SMU Load uCode"); return result; } /* Check if the FW has been loaded, SMU will not return if loading has not finished. */ -int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) +int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) { - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type); uint32_t ret; - ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11, - smu_data->soft_regs_start + smum_get_offsetof(smumgr, + ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11, + smu_data->soft_regs_start + smum_get_offsetof(hwmgr, SMU_SoftRegisters, UcodeLoadStatus), fw_mask, fw_mask); - return ret; } -int smu7_reload_firmware(struct pp_smumgr *smumgr) +int smu7_reload_firmware(struct pp_hwmgr *hwmgr) { - return smumgr->smumgr_funcs->start_smu(smumgr); + return hwmgr->smumgr_funcs->start_smu(hwmgr); } -static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) +static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit) { uint32_t byte_count = length; PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); - cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000); - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); + cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); for (; byte_count >= 4; byte_count -= 4) - cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++); + cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++); - SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); @@ -519,41 +519,41 @@ static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t leng } -int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr) +int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr) { int result = 0; - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend); + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); struct cgs_firmware_info info = {0}; if (smu_data->security_hard_key == 1) - cgs_get_firmware_info(smumgr->device, + cgs_get_firmware_info(hwmgr->device, smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); else - cgs_get_firmware_info(smumgr->device, + cgs_get_firmware_info(hwmgr->device, smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); - smumgr->is_kicker = info.is_kicker; + hwmgr->is_kicker = info.is_kicker; - result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); + result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); return result; } -int smu7_init(struct pp_smumgr *smumgr) +int smu7_init(struct pp_hwmgr *hwmgr) { struct smu7_smumgr *smu_data; uint8_t *internal_buf; uint64_t mc_addr = 0; /* Allocate memory for backend private data */ - smu_data = (struct smu7_smumgr *)(smumgr->backend); + smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); smu_data->header_buffer.data_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; /* Allocate FW image data structure and header buffer and * send the header buffer address to SMU */ - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, smu_data->header_buffer.data_size, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, PAGE_SIZE, @@ -567,16 +567,16 @@ int smu7_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE((NULL != smu_data->header), "Out of memory.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, + kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)smu_data->header_buffer.handle); return -EINVAL); - if (cgs_is_virtualization_enabled(smumgr->device)) + if (cgs_is_virtualization_enabled(hwmgr->device)) return 0; smu_data->smu_buffer.data_size = 200*4096; - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, smu_data->smu_buffer.data_size, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, PAGE_SIZE, @@ -590,12 +590,12 @@ int smu7_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE((NULL != internal_buf), "Out of memory.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, + kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)smu_data->smu_buffer.handle); return -EINVAL); - if (smum_is_hw_avfs_present(smumgr)) + if (smum_is_hw_avfs_present(hwmgr)) smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT; else smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED; @@ -604,12 +604,10 @@ int smu7_init(struct pp_smumgr *smumgr) } -int smu7_smu_fini(struct pp_smumgr *smumgr) +int smu7_smu_fini(struct pp_hwmgr *hwmgr) { - if (smumgr->backend) { - kfree(smumgr->backend); - smumgr->backend = NULL; - } - cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); + kfree(hwmgr->smu_backend); + hwmgr->smu_backend = NULL; + cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h index ee5e32d2921e..0b63c5c1043c 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h @@ -60,32 +60,32 @@ struct smu7_smumgr { }; -int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, +int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit); -int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, +int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit); -int smu7_program_jump_on_start(struct pp_smumgr *smumgr); -bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr); -int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); -int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg); -int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, +int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr); +bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr); +int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg); +int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg); +int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter); -int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, +int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter); -int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr); -int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr); +int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr); +int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr); enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type); -int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, +int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit); -int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, +int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit); -int smu7_request_smu_load_fw(struct pp_smumgr *smumgr); -int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type); -int smu7_reload_firmware(struct pp_smumgr *smumgr); -int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr); -int smu7_init(struct pp_smumgr *smumgr); -int smu7_smu_fini(struct pp_smumgr *smumgr); +int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr); +int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type); +int smu7_reload_firmware(struct pp_hwmgr *hwmgr); +int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr); +int smu7_init(struct pp_hwmgr *hwmgr); +int smu7_smu_fini(struct pp_hwmgr *hwmgr); #endif
\ No newline at end of file diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c index 3bdf6478de7f..867388456530 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c @@ -27,7 +27,6 @@ #include <linux/slab.h> #include <linux/types.h> #include <drm/amdgpu_drm.h> -#include "pp_instance.h" #include "smumgr.h" #include "cgs_common.h" @@ -46,88 +45,18 @@ MODULE_FIRMWARE("amdgpu/polaris12_smc.bin"); MODULE_FIRMWARE("amdgpu/vega10_smc.bin"); MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin"); -int smum_early_init(struct pp_instance *handle) +int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr) { - struct pp_smumgr *smumgr; - - if (handle == NULL) - return -EINVAL; - - smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL); - if (smumgr == NULL) - return -ENOMEM; - - smumgr->device = handle->device; - smumgr->chip_family = handle->chip_family; - smumgr->chip_id = handle->chip_id; - smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; - smumgr->reload_fw = 1; - handle->smu_mgr = smumgr; - - switch (smumgr->chip_family) { - case AMDGPU_FAMILY_CZ: - smumgr->smumgr_funcs = &cz_smu_funcs; - break; - case AMDGPU_FAMILY_VI: - switch (smumgr->chip_id) { - case CHIP_TOPAZ: - smumgr->smumgr_funcs = &iceland_smu_funcs; - break; - case CHIP_TONGA: - smumgr->smumgr_funcs = &tonga_smu_funcs; - break; - case CHIP_FIJI: - smumgr->smumgr_funcs = &fiji_smu_funcs; - break; - case CHIP_POLARIS11: - case CHIP_POLARIS10: - case CHIP_POLARIS12: - smumgr->smumgr_funcs = &polaris10_smu_funcs; - break; - default: - return -EINVAL; - } - break; - case AMDGPU_FAMILY_AI: - switch (smumgr->chip_id) { - case CHIP_VEGA10: - smumgr->smumgr_funcs = &vega10_smu_funcs; - break; - default: - return -EINVAL; - } - break; - case AMDGPU_FAMILY_RV: - switch (smumgr->chip_id) { - case CHIP_RAVEN: - smumgr->smumgr_funcs = &rv_smu_funcs; - break; - default: - return -EINVAL; - } - break; - default: - kfree(smumgr); - return -EINVAL; - } - - return 0; -} - -int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) -{ - if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable) - return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr); + if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable) + return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr); return 0; } -int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, - void *input, void *output, void *storage, int result) +int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table) - return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); + if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table) + return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); return 0; } @@ -135,8 +64,8 @@ int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold) - return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr); + if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold) + return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr); return 0; } @@ -144,163 +73,75 @@ int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) { - if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table) - return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type); + if (NULL != hwmgr->smumgr_funcs->update_smc_table) + return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type); return 0; } -uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member) +uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member) { - if (NULL != smumgr->smumgr_funcs->get_offsetof) - return smumgr->smumgr_funcs->get_offsetof(type, member); + if (NULL != hwmgr->smumgr_funcs->get_offsetof) + return hwmgr->smumgr_funcs->get_offsetof(type, member); return 0; } int smum_process_firmware_header(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header) - return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr); + if (NULL != hwmgr->smumgr_funcs->process_firmware_header) + return hwmgr->smumgr_funcs->process_firmware_header(hwmgr); return 0; } -int smum_get_argument(struct pp_smumgr *smumgr) +int smum_get_argument(struct pp_hwmgr *hwmgr) { - if (NULL != smumgr->smumgr_funcs->get_argument) - return smumgr->smumgr_funcs->get_argument(smumgr); + if (NULL != hwmgr->smumgr_funcs->get_argument) + return hwmgr->smumgr_funcs->get_argument(hwmgr); return 0; } -uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value) +uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value) { - if (NULL != smumgr->smumgr_funcs->get_mac_definition) - return smumgr->smumgr_funcs->get_mac_definition(value); + if (NULL != hwmgr->smumgr_funcs->get_mac_definition) + return hwmgr->smumgr_funcs->get_mac_definition(value); return 0; } -int smum_download_powerplay_table(struct pp_smumgr *smumgr, - void **table) +int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table) { - if (NULL != smumgr->smumgr_funcs->download_pptable_settings) - return smumgr->smumgr_funcs->download_pptable_settings(smumgr, + if (NULL != hwmgr->smumgr_funcs->download_pptable_settings) + return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr, table); return 0; } -int smum_upload_powerplay_table(struct pp_smumgr *smumgr) +int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr) { - if (NULL != smumgr->smumgr_funcs->upload_pptable_settings) - return smumgr->smumgr_funcs->upload_pptable_settings(smumgr); + if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings) + return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr); return 0; } -int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) { - if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL) + if (hwmgr == NULL || hwmgr->smumgr_funcs->send_msg_to_smc == NULL) return -EINVAL; - return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg); + return hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg); } -int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, +int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) { - if (smumgr == NULL || - smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL) - return -EINVAL; - return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter( - smumgr, msg, parameter); -} - -/* - * Returns once the part of the register indicated by the mask has - * reached the given value. - */ -int smum_wait_on_register(struct pp_smumgr *smumgr, - uint32_t index, - uint32_t value, uint32_t mask) -{ - uint32_t i; - uint32_t cur_value; - - if (smumgr == NULL || smumgr->device == NULL) - return -EINVAL; - - for (i = 0; i < smumgr->usec_timeout; i++) { - cur_value = cgs_read_register(smumgr->device, index); - if ((cur_value & mask) == (value & mask)) - break; - udelay(1); - } - - /* timeout means wrong logic*/ - if (i == smumgr->usec_timeout) - return -1; - - return 0; -} - -int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, - uint32_t index, - uint32_t value, uint32_t mask) -{ - uint32_t i; - uint32_t cur_value; - - if (smumgr == NULL) + if (hwmgr == NULL || + hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL) return -EINVAL; - - for (i = 0; i < smumgr->usec_timeout; i++) { - cur_value = cgs_read_register(smumgr->device, - index); - if ((cur_value & mask) != (value & mask)) - break; - udelay(1); - } - - /* timeout means wrong logic */ - if (i == smumgr->usec_timeout) - return -1; - - return 0; -} - - -/* - * Returns once the part of the register indicated by the mask - * has reached the given value.The indirect space is described by - * giving the memory-mapped index of the indirect index register. - */ -int smum_wait_on_indirect_register(struct pp_smumgr *smumgr, - uint32_t indirect_port, - uint32_t index, - uint32_t value, - uint32_t mask) -{ - if (smumgr == NULL || smumgr->device == NULL) - return -EINVAL; - - cgs_write_register(smumgr->device, indirect_port, index); - return smum_wait_on_register(smumgr, indirect_port + 1, - mask, value); -} - -void smum_wait_for_indirect_register_unequal( - struct pp_smumgr *smumgr, - uint32_t indirect_port, - uint32_t index, - uint32_t value, - uint32_t mask) -{ - if (smumgr == NULL || smumgr->device == NULL) - return; - cgs_write_register(smumgr->device, indirect_port, index); - smum_wait_for_register_unequal(smumgr, indirect_port + 1, - value, mask); + return hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter( + hwmgr, msg, parameter); } int smu_allocate_memory(void *device, uint32_t size, @@ -316,7 +157,7 @@ int smu_allocate_memory(void *device, uint32_t size, return -EINVAL; ret = cgs_alloc_gpu_mem(device, type, size, byte_align, - 0, 0, (cgs_handle_t *)handle); + (cgs_handle_t *)handle); if (ret) return -ENOMEM; @@ -356,24 +197,24 @@ int smu_free_memory(void *device, void *handle) int smum_init_smc_table(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table) - return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr); + if (NULL != hwmgr->smumgr_funcs->init_smc_table) + return hwmgr->smumgr_funcs->init_smc_table(hwmgr); return 0; } int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels) - return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr); + if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels) + return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr); return 0; } int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels) - return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr); + if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels) + return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr); return 0; } @@ -381,16 +222,16 @@ int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr) /*this interface is needed by island ci/vi */ int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table) - return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr); + if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table) + return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr); return 0; } bool smum_is_dpm_running(struct pp_hwmgr *hwmgr) { - if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running) - return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr); + if (NULL != hwmgr->smumgr_funcs->is_dpm_running) + return hwmgr->smumgr_funcs->is_dpm_running(hwmgr); return true; } @@ -398,17 +239,17 @@ bool smum_is_dpm_running(struct pp_hwmgr *hwmgr) int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, struct amd_pp_profile *request) { - if (hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels) - return hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels( + if (hwmgr->smumgr_funcs->populate_requested_graphic_levels) + return hwmgr->smumgr_funcs->populate_requested_graphic_levels( hwmgr, request); return 0; } -bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr) +bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr) { - if (smumgr->smumgr_funcs->is_hw_avfs_present) - return smumgr->smumgr_funcs->is_hw_avfs_present(smumgr); + if (hwmgr->smumgr_funcs->is_hw_avfs_present) + return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr); return false; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c index 65d3a4893958..1f720ccdaf99 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c @@ -97,7 +97,7 @@ static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = { */ -static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, +static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table, uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) { @@ -406,7 +406,7 @@ static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_ { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t i; /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ @@ -539,7 +539,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); /* populate graphics levels*/ - result = tonga_get_dependecy_volt_by_clk(hwmgr, + result = tonga_get_dependency_volt_by_clk(hwmgr, pptable_info->vdd_dep_on_sclk, engine_clock, &graphic_level->MinVoltage, &mvdd); PP_ASSERT_WITH_CODE((!result), @@ -598,7 +598,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct smu7_dpm_table *dpm_table = &data->dpm_table; struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; @@ -690,7 +690,7 @@ int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; } /* level count will send to smc once at init smc table and never change*/ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_address, + result = smu7_copy_bytes_to_smc(hwmgr, level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, SMC_RAM_END); @@ -895,7 +895,7 @@ static int tonga_populate_single_memory_level( uint32_t mclk_strobe_mode_threshold = 40000; if (NULL != pptable_info->vdd_dep_on_mclk) { - result = tonga_get_dependecy_volt_by_clk(hwmgr, + result = tonga_get_dependency_volt_by_clk(hwmgr, pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &mvdd); @@ -1002,7 +1002,7 @@ int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); struct smu7_dpm_table *dpm_table = &data->dpm_table; int result; @@ -1048,7 +1048,7 @@ int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; /* level count will send to smc once at init smc table and never change*/ - result = smu7_copy_bytes_to_smc(hwmgr->smumgr, + result = smu7_copy_bytes_to_smc(hwmgr, level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, SMC_RAM_END); @@ -1090,7 +1090,7 @@ static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, { int result = 0; struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct pp_atomctrl_clock_dividers_vi dividers; @@ -1454,7 +1454,7 @@ static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); int result = 0; SMU72_Discrete_MCArbDramTimingTable arb_regs; uint32_t i, j; @@ -1475,7 +1475,7 @@ static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) if (!result) { result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.arb_table_start, (uint8_t *)&arb_regs, sizeof(SMU72_Discrete_MCArbDramTimingTable), @@ -1492,7 +1492,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr, int result = 0; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); table->GraphicsBootLevel = 0; table->MemoryBootLevel = 0; @@ -1543,7 +1543,7 @@ static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) volt_with_cks, value; uint16_t clock_freq_u16; struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, volt_offset = 0; struct phm_ppt_v1_information *table_info = @@ -1782,9 +1782,9 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr, * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) +static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) { - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t tmp; int result; @@ -1797,7 +1797,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) * In reality this field should not be in that structure * but in a soft register. */ - result = smu7_read_smc_sram_dword(smumgr, + result = smu7_read_smc_sram_dword(hwmgr, smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); if (result != 0) @@ -1806,7 +1806,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) tmp &= 0x00FFFFFF; tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; - return smu7_write_smc_sram_dword(smumgr, + return smu7_write_smc_sram_dword(hwmgr, smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); } @@ -1814,7 +1814,7 @@ static int tonga_init_arb_table_index(struct pp_smumgr *smumgr) static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); struct phm_ppt_v1_information *table_info = @@ -1838,7 +1838,7 @@ static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base; dpm_table->BAPM_TEMP_GRADIENT = - PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient); + PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); pdef1 = defaults->bapmti_r; pdef2 = defaults->bapmti_rc; @@ -1861,7 +1861,7 @@ static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; @@ -1876,7 +1876,7 @@ static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr) { uint16_t tdc_limit; struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -1897,11 +1897,11 @@ static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr) static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; uint32_t temp; - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, fuse_table_offset + offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl), (uint32_t *)&temp, SMC_RAM_END)) @@ -1919,7 +1919,7 @@ static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr) { int i; struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -1930,7 +1930,7 @@ static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr) static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) { - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); if ((hwmgr->thermal_controller.advanceFanControlParameters. usFanOutputSensitivity & (1 << 15)) || @@ -1949,7 +1949,7 @@ static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr) { int i; struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -1958,15 +1958,10 @@ static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr) return 0; } -static int tonga_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) -{ - return 0; -} - static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; @@ -1987,12 +1982,12 @@ static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t pm_fuse_table_offset; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { - if (smu7_read_smc_sram_dword(hwmgr->smumgr, + if (smu7_read_smc_sram_dword(hwmgr, SMU72_FIRMWARE_HEADER_LOCATION + offsetof(SMU72_Firmware_Header, PmFuseTable), &pm_fuse_table_offset, SMC_RAM_END)) @@ -2035,13 +2030,6 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) "Attempt to populate GnbLPML Failed !", return -EINVAL); - /* DW19 */ - if (tonga_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) - PP_ASSERT_WITH_CODE(false, - "Attempt to populate GnbLPML " - "Min and Max Vid Failed !", - return -EINVAL); - /* DW20 */ if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr)) PP_ASSERT_WITH_CODE( @@ -2050,7 +2038,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) "Hi and Lo Sidd Failed !", return -EINVAL); - if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, + if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, (uint8_t *)&smu_data->power_tune_table, sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END)) PP_ASSERT_WITH_CODE(false, @@ -2060,10 +2048,10 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) return 0; } -static int tonga_populate_mc_reg_address(struct pp_smumgr *smumgr, +static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table) { - const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)smumgr->backend; + const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend; uint32_t i, j; @@ -2104,12 +2092,12 @@ static void tonga_convert_mc_registers( } static int tonga_convert_mc_reg_table_entry_to_smc( - struct pp_smumgr *smumgr, + struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU72_Discrete_MCRegisterSet *mc_reg_table_data ) { - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t i = 0; for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { @@ -2139,7 +2127,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, for (i = 0; i < data->dpm_table.mclk_table.count; i++) { res = tonga_convert_mc_reg_table_entry_to_smc( - hwmgr->smumgr, + hwmgr, data->dpm_table.mclk_table.dpm_levels[i].value, &mc_regs->data[i] ); @@ -2153,8 +2141,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) { - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); uint32_t address; int32_t result; @@ -2175,7 +2162,7 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); return smu7_copy_bytes_to_smc( - hwmgr->smumgr, address, + hwmgr, address, (uint8_t *)&smu_data->mc_regs.data[0], sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, @@ -2185,11 +2172,10 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) { int result; - struct pp_smumgr *smumgr = hwmgr->smumgr; - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters)); - result = tonga_populate_mc_reg_address(smumgr, &(smu_data->mc_regs)); + result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); PP_ASSERT_WITH_CODE(!result, "Failed to initialize MCRegTable for the MC register addresses !", return result;); @@ -2199,13 +2185,13 @@ static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) "Failed to initialize MCRegTable for driver state !", return result;); - return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start, + return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start, (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END); } static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) { - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2221,7 +2207,7 @@ static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) static void tonga_save_default_power_profile(struct pp_hwmgr *hwmgr) { - struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smu_backend); struct SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel; unsigned min_level = 1; @@ -2267,7 +2253,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) int result; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2483,7 +2469,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags), (uint8_t *)&(table->SystemFlags), sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController), @@ -2492,7 +2478,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE(!result, "Failed to upload dpm data to SMC memory !", return result;); - result = tonga_init_arb_table_index(hwmgr->smumgr); + result = tonga_init_arb_table_index(hwmgr); PP_ASSERT_WITH_CODE(!result, "Failed to upload arb data to SMC memory !", return result); @@ -2521,7 +2507,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr) int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; uint32_t duty100; uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; @@ -2600,7 +2586,7 @@ int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) fan_table.FanControl_GL_Flag = 1; - res = smu7_copy_bytes_to_smc(hwmgr->smumgr, + res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), @@ -2625,7 +2611,7 @@ int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); int result = 0; uint32_t low_sclk_interrupt_threshold = 0; @@ -2642,7 +2628,7 @@ int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); result = smu7_copy_bytes_to_smc( - hwmgr->smumgr, + hwmgr, smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold), @@ -2728,7 +2714,7 @@ uint32_t tonga_get_mac_definition(uint32_t value) static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2753,7 +2739,7 @@ static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_UVDDPM) || phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDDPM_SetEnabledMask, (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); return 0; @@ -2762,7 +2748,7 @@ static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *smu_data = - (struct tonga_smumgr *)(hwmgr->smumgr->backend); + (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2784,7 +2770,7 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VCEDPM_SetEnabledMask, (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); return 0; @@ -2792,7 +2778,7 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr) { - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t mm_boot_level_offset, mm_boot_level_value; smu_data->smc_state_table.SamuBootLevel = 0; @@ -2810,7 +2796,7 @@ static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SAMUDPM_SetEnabledMask, (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel)); return 0; @@ -2844,13 +2830,13 @@ int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); uint32_t tmp; int result; bool error = false; - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU72_FIRMWARE_HEADER_LOCATION + offsetof(SMU72_Firmware_Header, DpmTable), &tmp, SMC_RAM_END); @@ -2860,7 +2846,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (result != 0); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU72_FIRMWARE_HEADER_LOCATION + offsetof(SMU72_Firmware_Header, SoftRegisters), &tmp, SMC_RAM_END); @@ -2873,7 +2859,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (result != 0); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU72_FIRMWARE_HEADER_LOCATION + offsetof(SMU72_Firmware_Header, mcRegisterTable), &tmp, SMC_RAM_END); @@ -2881,7 +2867,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) if (!result) smu_data->smu7_data.mc_reg_table_start = tmp; - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU72_FIRMWARE_HEADER_LOCATION + offsetof(SMU72_Firmware_Header, FanTable), &tmp, SMC_RAM_END); @@ -2891,7 +2877,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (result != 0); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU72_FIRMWARE_HEADER_LOCATION + offsetof(SMU72_Firmware_Header, mcArbDramTimingTable), &tmp, SMC_RAM_END); @@ -2901,7 +2887,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (result != 0); - result = smu7_read_smc_sram_dword(hwmgr->smumgr, + result = smu7_read_smc_sram_dword(hwmgr, SMU72_FIRMWARE_HEADER_LOCATION + offsetof(SMU72_Firmware_Header, Version), &tmp, SMC_RAM_END); @@ -3170,7 +3156,7 @@ static int tonga_set_valid_flag(struct tonga_mc_reg_table *table) int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) { int result; - struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); + struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); pp_atomctrl_mc_reg_table *table; struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table; uint8_t module_index = tonga_get_memory_modile_index(hwmgr); @@ -3253,7 +3239,7 @@ int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, struct amd_pp_profile *request) { struct tonga_smumgr *smu_data = (struct tonga_smumgr *) - (hwmgr->smumgr->backend); + (hwmgr->smu_backend); struct SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; uint32_t array = smu_data->smu7_data.dpm_table_start + @@ -3270,6 +3256,6 @@ int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, levels[i].DownHyst = request->down_hyst; } - return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, array_size, SMC_RAM_END); } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h index 962860f13f24..9d6a78a65976 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h @@ -40,7 +40,7 @@ struct tonga_pt_defaults { uint8_t tdc_waterfall_ctl; uint8_t dte_ambient_temp_base; uint32_t display_cac; - uint32_t bamp_temp_gradient; + uint32_t bapm_temp_gradient; uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS]; uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS]; }; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index c35f4c35c9ca..d22cf218cf18 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -37,125 +37,125 @@ #include "smu7_smumgr.h" -static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr) +static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr) { int result; /* Assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = smu7_upload_smu_firmware_image(smumgr); + result = smu7_upload_smu_firmware_image(hwmgr); if (result) return result; /* Clear status */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); /* Enable clock */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); /* De-assert reset */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); /* Set SMU Auto Start */ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_INPUT_DATA, AUTO_START, 1); /* Clear firmware interrupt enable flag */ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); /** * Call Test SMU message with 0x20000 offset to trigger SMU start */ - smu7_send_msg_to_smc_offset(smumgr); + smu7_send_msg_to_smc_offset(hwmgr); /* Wait for done bit to be set */ - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); /* Check pass/failed indicator */ - if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, + if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) { pr_err("SMU Firmware start failed\n"); return -EINVAL; } /* Wait for firmware to initialize */ - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); return 0; } -static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr) +static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr) { int result = 0; /* wait for smc boot up */ - SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); /*Clear firmware interrupt enable flag*/ - cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = smu7_upload_smu_firmware_image(smumgr); + result = smu7_upload_smu_firmware_image(hwmgr); if (result != 0) return result; /* Set smc instruct start point at 0x0 */ - smu7_program_jump_on_start(smumgr); + smu7_program_jump_on_start(hwmgr); - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); /*De-assert reset*/ - SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); /* Wait for firmware to initialize */ - SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, + PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); return result; } -static int tonga_start_smu(struct pp_smumgr *smumgr) +static int tonga_start_smu(struct pp_hwmgr *hwmgr) { int result; /* Only start SMC if SMC RAM is not running */ - if (!(smu7_is_smc_ram_running(smumgr) || - cgs_is_virtualization_enabled(smumgr->device))) { + if (!(smu7_is_smc_ram_running(hwmgr) || + cgs_is_virtualization_enabled(hwmgr->device))) { /*Check if SMU is running in protected mode*/ - if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, + if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)) { - result = tonga_start_in_non_protection_mode(smumgr); + result = tonga_start_in_non_protection_mode(hwmgr); if (result) return result; } else { - result = tonga_start_in_protection_mode(smumgr); + result = tonga_start_in_protection_mode(hwmgr); if (result) return result; } } - result = smu7_request_smu_load_fw(smumgr); + result = smu7_request_smu_load_fw(hwmgr); return result; } @@ -167,7 +167,7 @@ static int tonga_start_smu(struct pp_smumgr *smumgr) * @param smcAddress the address in the SMC RAM to access. * @param value to write to the SMC SRAM. */ -static int tonga_smu_init(struct pp_smumgr *smumgr) +static int tonga_smu_init(struct pp_hwmgr *hwmgr) { struct tonga_smumgr *tonga_priv = NULL; int i; @@ -176,9 +176,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr) if (tonga_priv == NULL) return -ENOMEM; - smumgr->backend = tonga_priv; + hwmgr->smu_backend = tonga_priv; - if (smu7_init(smumgr)) + if (smu7_init(hwmgr)) return -EINVAL; for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c index 408514c965a0..2f979fb86824 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c @@ -53,20 +53,20 @@ #define smnMP0_FW_INTF 0x3010104 #define smnMP1_PUB_CTRL 0x3010b14 -static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr) +static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr) { uint32_t mp1_fw_flags, reg; reg = soc15_get_register_offset(NBIF_HWID, 0, mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); - cgs_write_register(smumgr->device, reg, + cgs_write_register(hwmgr->device, reg, (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); reg = soc15_get_register_offset(NBIF_HWID, 0, mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); - mp1_fw_flags = cgs_read_register(smumgr->device, reg); + mp1_fw_flags = cgs_read_register(hwmgr->device, reg); if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) return true; @@ -80,20 +80,20 @@ static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr) * @param smumgr the address of the powerplay hardware manager. * @return TRUE SMC has responded, FALSE otherwise. */ -static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr) +static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr) { uint32_t reg; - if (!vega10_is_smc_ram_running(smumgr)) + if (!vega10_is_smc_ram_running(hwmgr)) return -EINVAL; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); - smum_wait_for_register_unequal(smumgr, reg, + phm_wait_for_register_unequal(hwmgr, reg, 0, MP1_C2PMSG_90__CONTENT_MASK); - return cgs_read_register(smumgr->device, reg); + return cgs_read_register(hwmgr->device, reg); } /* @@ -102,43 +102,43 @@ static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr) * @param msg the message to send. * @return Always return 0. */ -int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, +int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg) { uint32_t reg; - if (!vega10_is_smc_ram_running(smumgr)) + if (!vega10_is_smc_ram_running(hwmgr)) return -EINVAL; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); - cgs_write_register(smumgr->device, reg, msg); + cgs_write_register(hwmgr->device, reg, msg); return 0; } /* * Send a message to the SMC, and wait for its response. - * @param smumgr the address of the powerplay hardware manager. + * @param hwmgr the address of the powerplay hardware manager. * @param msg the message to send. * @return Always return 0. */ -int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) { uint32_t reg; - if (!vega10_is_smc_ram_running(smumgr)) + if (!vega10_is_smc_ram_running(hwmgr)) return -EINVAL; - vega10_wait_for_response(smumgr); + vega10_wait_for_response(hwmgr); reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); - cgs_write_register(smumgr->device, reg, 0); + cgs_write_register(hwmgr->device, reg, 0); - vega10_send_msg_to_smc_without_waiting(smumgr, msg); + vega10_send_msg_to_smc_without_waiting(hwmgr, msg); - if (vega10_wait_for_response(smumgr) != 1) + if (vega10_wait_for_response(hwmgr) != 1) pr_err("Failed to send message: 0x%x\n", msg); return 0; @@ -146,32 +146,32 @@ int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) /* * Send a message to the SMC with parameter - * @param smumgr: the address of the powerplay hardware manager. + * @param hwmgr: the address of the powerplay hardware manager. * @param msg: the message to send. * @param parameter: the parameter to send * @return Always return 0. */ -int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, +int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) { uint32_t reg; - if (!vega10_is_smc_ram_running(smumgr)) + if (!vega10_is_smc_ram_running(hwmgr)) return -EINVAL; - vega10_wait_for_response(smumgr); + vega10_wait_for_response(hwmgr); reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); - cgs_write_register(smumgr->device, reg, 0); + cgs_write_register(hwmgr->device, reg, 0); reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); - cgs_write_register(smumgr->device, reg, parameter); + cgs_write_register(hwmgr->device, reg, parameter); - vega10_send_msg_to_smc_without_waiting(smumgr, msg); + vega10_send_msg_to_smc_without_waiting(hwmgr, msg); - if (vega10_wait_for_response(smumgr) != 1) + if (vega10_wait_for_response(hwmgr) != 1) pr_err("Failed to send message: 0x%x\n", msg); return 0; @@ -180,51 +180,51 @@ int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, /* * Send a message to the SMC with parameter, do not wait for response - * @param smumgr: the address of the powerplay hardware manager. + * @param hwmgr: the address of the powerplay hardware manager. * @param msg: the message to send. * @param parameter: the parameter to send * @return The response that came from the SMC. */ int vega10_send_msg_to_smc_with_parameter_without_waiting( - struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) + struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) { uint32_t reg; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); - cgs_write_register(smumgr->device, reg, parameter); + cgs_write_register(hwmgr->device, reg, parameter); - return vega10_send_msg_to_smc_without_waiting(smumgr, msg); + return vega10_send_msg_to_smc_without_waiting(hwmgr, msg); } /* * Retrieve an argument from SMC. - * @param smumgr the address of the powerplay hardware manager. + * @param hwmgr the address of the powerplay hardware manager. * @param arg pointer to store the argument from SMC. * @return Always return 0. */ -int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg) +int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg) { uint32_t reg; reg = soc15_get_register_offset(MP1_HWID, 0, mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); - *arg = cgs_read_register(smumgr->device, reg); + *arg = cgs_read_register(hwmgr->device, reg); return 0; } /* * Copy table from SMC into driver FB - * @param smumgr the address of the SMC manager + * @param hwmgr the address of the HW manager * @param table_id the driver's table ID to copy from */ -int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, +int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id) { struct vega10_smumgr *priv = - (struct vega10_smumgr *)(smumgr->backend); + (struct vega10_smumgr *)(hwmgr->smu_backend); PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, "Invalid SMU Table ID!", return -EINVAL); @@ -232,16 +232,16 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, "Invalid SMU Table version!", return -EINVAL); PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, "Invalid SMU Table Length!", return -EINVAL); - PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, priv->smu_tables.entry[table_id].table_addr_high) == 0, "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL); - PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrLow, priv->smu_tables.entry[table_id].table_addr_low) == 0, "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", return -EINVAL); - PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_TransferTableSmu2Dram, priv->smu_tables.entry[table_id].table_id) == 0, "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", @@ -255,14 +255,14 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, /* * Copy table from Driver FB into SMC - * @param smumgr the address of the SMC manager + * @param hwmgr the address of the HW manager * @param table_id the table to copy from */ -int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, +int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id) { struct vega10_smumgr *priv = - (struct vega10_smumgr *)(smumgr->backend); + (struct vega10_smumgr *)(hwmgr->smu_backend); PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, "Invalid SMU Table ID!", return -EINVAL); @@ -274,17 +274,17 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, memcpy(priv->smu_tables.entry[table_id].table, table, priv->smu_tables.entry[table_id].size); - PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, priv->smu_tables.entry[table_id].table_addr_high) == 0, "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;); - PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrLow, priv->smu_tables.entry[table_id].table_addr_low) == 0, "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", return -EINVAL); - PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr, + PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_TransferTableDram2Smu, priv->smu_tables.entry[table_id].table_id) == 0, "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", @@ -293,87 +293,87 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, return 0; } -int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table) +int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table) { PP_ASSERT_WITH_CODE(avfs_table, "No access to SMC AVFS Table", return -EINVAL); - return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE); + return vega10_copy_table_from_smc(hwmgr, avfs_table, AVFSTABLE); } -int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table) +int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table) { PP_ASSERT_WITH_CODE(avfs_table, "No access to SMC AVFS Table", return -EINVAL); - return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE); + return vega10_copy_table_to_smc(hwmgr, avfs_table, AVFSTABLE); } -int vega10_enable_smc_features(struct pp_smumgr *smumgr, +int vega10_enable_smc_features(struct pp_hwmgr *hwmgr, bool enable, uint32_t feature_mask) { int msg = enable ? PPSMC_MSG_EnableSmuFeatures : PPSMC_MSG_DisableSmuFeatures; - return vega10_send_msg_to_smc_with_parameter(smumgr, + return vega10_send_msg_to_smc_with_parameter(hwmgr, msg, feature_mask); } -int vega10_get_smc_features(struct pp_smumgr *smumgr, +int vega10_get_smc_features(struct pp_hwmgr *hwmgr, uint32_t *features_enabled) { if (features_enabled == NULL) return -EINVAL; - if (!vega10_send_msg_to_smc(smumgr, + if (!vega10_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures)) { - vega10_read_arg_from_smc(smumgr, features_enabled); + vega10_read_arg_from_smc(hwmgr, features_enabled); return 0; } return -EINVAL; } -int vega10_set_tools_address(struct pp_smumgr *smumgr) +int vega10_set_tools_address(struct pp_hwmgr *hwmgr) { struct vega10_smumgr *priv = - (struct vega10_smumgr *)(smumgr->backend); + (struct vega10_smumgr *)(hwmgr->smu_backend); if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high || priv->smu_tables.entry[TOOLSTABLE].table_addr_low) { - if (!vega10_send_msg_to_smc_with_parameter(smumgr, + if (!vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetToolsDramAddrHigh, priv->smu_tables.entry[TOOLSTABLE].table_addr_high)) - vega10_send_msg_to_smc_with_parameter(smumgr, + vega10_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetToolsDramAddrLow, priv->smu_tables.entry[TOOLSTABLE].table_addr_low); } return 0; } -static int vega10_verify_smc_interface(struct pp_smumgr *smumgr) +static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) { uint32_t smc_driver_if_version; struct cgs_system_info sys_info = {0}; uint32_t dev_id; uint32_t rev_id; - PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr, + PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(hwmgr, PPSMC_MSG_GetDriverIfVersion), "Attempt to get SMC IF Version Number Failed!", return -EINVAL); - vega10_read_arg_from_smc(smumgr, &smc_driver_if_version); + vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version); sys_info.size = sizeof(struct cgs_system_info); sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; - cgs_query_system_info(smumgr->device, &sys_info); + cgs_query_system_info(hwmgr->device, &sys_info); dev_id = (uint32_t)sys_info.value; sys_info.size = sizeof(struct cgs_system_info); sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; - cgs_query_system_info(smumgr->device, &sys_info); + cgs_query_system_info(hwmgr->device, &sys_info); rev_id = (uint32_t)sys_info.value; if (!((dev_id == 0x687f) && @@ -392,7 +392,7 @@ static int vega10_verify_smc_interface(struct pp_smumgr *smumgr) return 0; } -static int vega10_smu_init(struct pp_smumgr *smumgr) +static int vega10_smu_init(struct pp_hwmgr *hwmgr) { struct vega10_smumgr *priv; uint64_t mc_addr; @@ -401,7 +401,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) int ret; struct cgs_firmware_info info = {0}; - ret = cgs_get_firmware_info(smumgr->device, + ret = cgs_get_firmware_info(hwmgr->device, smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); if (ret || !info.kptr) @@ -412,10 +412,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) if (!priv) return -ENOMEM; - smumgr->backend = priv; + hwmgr->smu_backend = priv; /* allocate space for pptable */ - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, sizeof(PPTable_t), CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, PAGE_SIZE, @@ -425,8 +425,8 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(kaddr, "[vega10_smu_init] Out of memory for pptable.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, + kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)handle); return -EINVAL); @@ -441,7 +441,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) priv->smu_tables.entry[PPTABLE].handle = handle; /* allocate space for watermarks table */ - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, sizeof(Watermarks_t), CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, PAGE_SIZE, @@ -451,10 +451,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(kaddr, "[vega10_smu_init] Out of memory for wmtable.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, + kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)handle); return -EINVAL); @@ -469,7 +469,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) priv->smu_tables.entry[WMTABLE].handle = handle; /* allocate space for AVFS table */ - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, sizeof(AvfsTable_t), CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, PAGE_SIZE, @@ -479,12 +479,12 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(kaddr, "[vega10_smu_init] Out of memory for avfs table.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, + kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)handle); return -EINVAL); @@ -500,7 +500,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) tools_size = 0x19000; if (tools_size) { - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, tools_size, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, PAGE_SIZE, @@ -522,7 +522,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) } /* allocate space for AVFS Fuse table */ - smu_allocate_memory(smumgr->device, + smu_allocate_memory(hwmgr->device, sizeof(AvfsFuseOverride_t), CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, PAGE_SIZE, @@ -532,16 +532,16 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(kaddr, "[vega10_smu_init] Out of memory for avfs fuse table.", - kfree(smumgr->backend); - cgs_free_gpu_mem(smumgr->device, + kfree(hwmgr->smu_backend); + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)handle); return -EINVAL); @@ -558,36 +558,36 @@ static int vega10_smu_init(struct pp_smumgr *smumgr) return 0; } -static int vega10_smu_fini(struct pp_smumgr *smumgr) +static int vega10_smu_fini(struct pp_hwmgr *hwmgr) { struct vega10_smumgr *priv = - (struct vega10_smumgr *)(smumgr->backend); + (struct vega10_smumgr *)(hwmgr->smu_backend); if (priv) { - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle); if (priv->smu_tables.entry[TOOLSTABLE].table) - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); - cgs_free_gpu_mem(smumgr->device, + cgs_free_gpu_mem(hwmgr->device, (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle); - kfree(smumgr->backend); - smumgr->backend = NULL; + kfree(hwmgr->smu_backend); + hwmgr->smu_backend = NULL; } return 0; } -static int vega10_start_smu(struct pp_smumgr *smumgr) +static int vega10_start_smu(struct pp_hwmgr *hwmgr) { - PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr), + PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr), "Failed to verify SMC interface!", return -EINVAL); - vega10_set_tools_address(smumgr); + vega10_set_tools_address(hwmgr); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h index 821425c1e4e0..0695455b21b2 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h @@ -52,19 +52,19 @@ struct vega10_smumgr { struct smu_table_array smu_tables; }; -int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg); -int vega10_copy_table_from_smc(struct pp_smumgr *smumgr, +int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg); +int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id); -int vega10_copy_table_to_smc(struct pp_smumgr *smumgr, +int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, uint8_t *table, int16_t table_id); -int vega10_enable_smc_features(struct pp_smumgr *smumgr, +int vega10_enable_smc_features(struct pp_hwmgr *hwmgr, bool enable, uint32_t feature_mask); -int vega10_get_smc_features(struct pp_smumgr *smumgr, +int vega10_get_smc_features(struct pp_hwmgr *hwmgr, uint32_t *features_enabled); -int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table); -int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table); +int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table); +int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table); -int vega10_set_tools_address(struct pp_smumgr *smumgr); +int vega10_set_tools_address(struct pp_hwmgr *hwmgr); #endif diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 38cea6fb25a8..97c94f9683fa 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -205,17 +205,32 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity) { struct amd_sched_rq *rq = entity->rq; + int r; if (!amd_sched_entity_is_initialized(sched, entity)) return; - /** * The client will not queue more IBs during this fini, consume existing - * queued IBs + * queued IBs or discard them on SIGKILL */ - wait_event(sched->job_scheduled, amd_sched_entity_is_idle(entity)); - + if ((current->flags & PF_SIGNALED) && current->exit_code == SIGKILL) + r = -ERESTARTSYS; + else + r = wait_event_killable(sched->job_scheduled, + amd_sched_entity_is_idle(entity)); amd_sched_rq_remove_entity(rq, entity); + if (r) { + struct amd_sched_job *job; + + /* Park the kernel for a moment to make sure it isn't processing + * our enity. + */ + kthread_park(sched->thread); + kthread_unpark(sched->thread); + while (kfifo_out(&entity->job_queue, &job, sizeof(job))) + sched->ops->free_job(job); + + } kfifo_free(&entity->job_queue); } diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index 2d51a2269fc6..5131bfb94f06 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -597,9 +597,9 @@ static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, struct sii8620_mt_msg *msg) { - u8 reg = msg->reg[0] & 0x7f; + u8 reg = msg->reg[1] & 0x7f; - if (msg->reg[0] & 0x80) + if (msg->reg[1] & 0x80) ctx->xdevcap[reg] = msg->ret; else ctx->devcap[reg] = msg->ret; diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 9e787621b4f5..366c56fe5f58 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -1628,6 +1628,9 @@ int drm_atomic_check_only(struct drm_atomic_state *state) if (config->funcs->atomic_check) ret = config->funcs->atomic_check(state->dev, state); + if (ret) + return ret; + if (!state->allow_modeset) { for_each_new_crtc_in_state(state, crtc, crtc_state, i) { if (drm_atomic_crtc_needs_modeset(crtc_state)) { @@ -1638,7 +1641,7 @@ int drm_atomic_check_only(struct drm_atomic_state *state) } } - return ret; + return 0; } EXPORT_SYMBOL(drm_atomic_check_only); @@ -2200,10 +2203,10 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, struct drm_atomic_state *state; struct drm_modeset_acquire_ctx ctx; struct drm_plane *plane; - struct drm_out_fence_state *fence_state = NULL; + struct drm_out_fence_state *fence_state; unsigned plane_mask; int ret = 0; - unsigned int i, j, num_fences = 0; + unsigned int i, j, num_fences; /* disallow for drivers not supporting atomic: */ if (!drm_core_check_feature(dev, DRIVER_ATOMIC)) @@ -2244,6 +2247,8 @@ retry: plane_mask = 0; copied_objs = 0; copied_props = 0; + fence_state = NULL; + num_fences = 0; for (i = 0; i < arg->count_objs; i++) { uint32_t obj_id, count_props; diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index b97c054f9786..01c34bc5b5b0 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -2808,6 +2808,7 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, struct drm_plane *plane; struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; + unsigned plane_mask = 0; int ret, i; state = drm_atomic_state_alloc(dev); @@ -2850,10 +2851,14 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, goto free; drm_atomic_set_fb_for_plane(plane_state, NULL); + plane_mask |= BIT(drm_plane_index(plane)); + plane->old_fb = plane->fb; } ret = drm_atomic_commit(state); free: + if (plane_mask) + drm_atomic_clean_old_fb(dev, plane_mask, ret); drm_atomic_state_put(state); return ret; } @@ -2984,11 +2989,16 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, struct drm_connector_state *new_conn_state; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; + unsigned plane_mask = 0; + struct drm_device *dev = state->dev; + int ret; state->acquire_ctx = ctx; - for_each_new_plane_in_state(state, plane, new_plane_state, i) + for_each_new_plane_in_state(state, plane, new_plane_state, i) { + plane_mask |= BIT(drm_plane_index(plane)); state->planes[i].old_state = plane->state; + } for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) state->crtcs[i].old_state = crtc->state; @@ -2996,7 +3006,11 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, for_each_new_connector_in_state(state, connector, new_conn_state, i) state->connectors[i].old_state = connector->state; - return drm_atomic_commit(state); + ret = drm_atomic_commit(state); + if (plane_mask) + drm_atomic_clean_old_fb(dev, plane_mask, ret); + + return ret; } EXPORT_SYMBOL(drm_atomic_helper_commit_duplicated_state); diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c index db6aeec50b82..2e5e089dd912 100644 --- a/drivers/gpu/drm/drm_blend.c +++ b/drivers/gpu/drm/drm_blend.c @@ -319,7 +319,7 @@ static int drm_atomic_helper_crtc_normalize_zpos(struct drm_crtc *crtc, DRM_DEBUG_ATOMIC("[CRTC:%d:%s] calculating normalized zpos values\n", crtc->base.id, crtc->name); - states = kmalloc_array(total_planes, sizeof(*states), GFP_TEMPORARY); + states = kmalloc_array(total_planes, sizeof(*states), GFP_KERNEL); if (!states) return -ENOMEM; diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c b/drivers/gpu/drm/drm_dp_dual_mode_helper.c index 80e62f669321..0ef9011a1856 100644 --- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c +++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c @@ -111,7 +111,7 @@ ssize_t drm_dp_dual_mode_write(struct i2c_adapter *adapter, void *data; int ret; - data = kmalloc(msg.len, GFP_TEMPORARY); + data = kmalloc(msg.len, GFP_KERNEL); if (!data) return -ENOMEM; diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index 4e710ec40599..811f6d26d108 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -36,6 +36,7 @@ #include <linux/pagemap.h> #include <linux/shmem_fs.h> #include <linux/dma-buf.h> +#include <linux/mem_encrypt.h> #include <drm/drmP.h> #include <drm/drm_vma_manager.h> #include <drm/drm_gem.h> @@ -962,6 +963,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, vma->vm_ops = dev->driver->gem_vm_ops; vma->vm_private_data = obj; vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); /* Take a ref for this mapping of the object, so that the fault * handler can dereference the mmap offset's pointer to the object. diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h index 4e906b82a170..fbc3f308fa19 100644 --- a/drivers/gpu/drm/drm_internal.h +++ b/drivers/gpu/drm/drm_internal.h @@ -167,3 +167,9 @@ int drm_syncobj_handle_to_fd_ioctl(struct drm_device *dev, void *data, struct drm_file *file_private); int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, void *data, struct drm_file *file_private); +int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_private); +int drm_syncobj_reset_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_private); +int drm_syncobj_signal_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_private); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index d920b2118a39..a9ae6dd2d593 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -657,6 +657,12 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, drm_syncobj_fd_to_handle_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl, + DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_RESET, drm_syncobj_reset_ioctl, + DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl, + DRM_UNLOCKED|DRM_RENDER_ALLOW), }; #define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls ) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index f794089d30ac..61a1c8ea74bc 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -169,7 +169,7 @@ INTERVAL_TREE_DEFINE(struct drm_mm_node, rb, struct drm_mm_node * __drm_mm_interval_first(const struct drm_mm *mm, u64 start, u64 last) { - return drm_mm_interval_tree_iter_first((struct rb_root *)&mm->interval_tree, + return drm_mm_interval_tree_iter_first((struct rb_root_cached *)&mm->interval_tree, start, last) ?: (struct drm_mm_node *)&mm->head_node; } EXPORT_SYMBOL(__drm_mm_interval_first); @@ -180,6 +180,7 @@ static void drm_mm_interval_tree_add_node(struct drm_mm_node *hole_node, struct drm_mm *mm = hole_node->mm; struct rb_node **link, *rb; struct drm_mm_node *parent; + bool leftmost = true; node->__subtree_last = LAST(node); @@ -196,9 +197,10 @@ static void drm_mm_interval_tree_add_node(struct drm_mm_node *hole_node, rb = &hole_node->rb; link = &hole_node->rb.rb_right; + leftmost = false; } else { rb = NULL; - link = &mm->interval_tree.rb_node; + link = &mm->interval_tree.rb_root.rb_node; } while (*link) { @@ -208,14 +210,15 @@ static void drm_mm_interval_tree_add_node(struct drm_mm_node *hole_node, parent->__subtree_last = node->__subtree_last; if (node->start < parent->start) link = &parent->rb.rb_left; - else + else { link = &parent->rb.rb_right; + leftmost = true; + } } rb_link_node(&node->rb, rb, link); - rb_insert_augmented(&node->rb, - &mm->interval_tree, - &drm_mm_interval_tree_augment); + rb_insert_augmented_cached(&node->rb, &mm->interval_tree, leftmost, + &drm_mm_interval_tree_augment); } #define RB_INSERT(root, member, expr) do { \ @@ -577,7 +580,7 @@ void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new) *new = *old; list_replace(&old->node_list, &new->node_list); - rb_replace_node(&old->rb, &new->rb, &old->mm->interval_tree); + rb_replace_node(&old->rb, &new->rb, &old->mm->interval_tree.rb_root); if (drm_mm_hole_follows(old)) { list_replace(&old->hole_stack, &new->hole_stack); @@ -863,7 +866,7 @@ void drm_mm_init(struct drm_mm *mm, u64 start, u64 size) mm->color_adjust = NULL; INIT_LIST_HEAD(&mm->hole_stack); - mm->interval_tree = RB_ROOT; + mm->interval_tree = RB_ROOT_CACHED; mm->holes_size = RB_ROOT; mm->holes_addr = RB_ROOT; diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 5d1c4f452ca8..72cba9805edc 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -720,6 +720,7 @@ int drm_mode_setplane(struct drm_device *dev, void *data, crtc = drm_crtc_find(dev, plane_req->crtc_id); if (!crtc) { + drm_framebuffer_put(fb); DRM_DEBUG_KMS("Unknown crtc ID %d\n", plane_req->crtc_id); return -ENOENT; diff --git a/drivers/gpu/drm/drm_scdc_helper.c b/drivers/gpu/drm/drm_scdc_helper.c index 5b89a5c6114f..657ea5ab6c3f 100644 --- a/drivers/gpu/drm/drm_scdc_helper.c +++ b/drivers/gpu/drm/drm_scdc_helper.c @@ -102,7 +102,7 @@ ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, void *data; int err; - data = kmalloc(1 + size, GFP_TEMPORARY); + data = kmalloc(1 + size, GFP_KERNEL); if (!data) return -ENOMEM; diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index 3db042501a3a..26d60615b4d4 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -1,5 +1,7 @@ /* * Copyright 2017 Red Hat + * Parts ported from amdgpu (fence wait code). + * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,6 +33,9 @@ * that contain an optional fence. The fence can be updated with a new * fence, or be NULL. * + * syncobj's can be waited upon, where it will wait for the underlying + * fence. + * * syncobj's can be export to fd's and back, these fd's are opaque and * have no other use case, except passing the syncobj between processes. * @@ -46,6 +51,7 @@ #include <linux/fs.h> #include <linux/anon_inodes.h> #include <linux/sync_file.h> +#include <linux/sched/signal.h> #include "drm_internal.h" #include <drm/drm_syncobj.h> @@ -75,6 +81,75 @@ struct drm_syncobj *drm_syncobj_find(struct drm_file *file_private, } EXPORT_SYMBOL(drm_syncobj_find); +static void drm_syncobj_add_callback_locked(struct drm_syncobj *syncobj, + struct drm_syncobj_cb *cb, + drm_syncobj_func_t func) +{ + cb->func = func; + list_add_tail(&cb->node, &syncobj->cb_list); +} + +static int drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj, + struct dma_fence **fence, + struct drm_syncobj_cb *cb, + drm_syncobj_func_t func) +{ + int ret; + + *fence = drm_syncobj_fence_get(syncobj); + if (*fence) + return 1; + + spin_lock(&syncobj->lock); + /* We've already tried once to get a fence and failed. Now that we + * have the lock, try one more time just to be sure we don't add a + * callback when a fence has already been set. + */ + if (syncobj->fence) { + *fence = dma_fence_get(syncobj->fence); + ret = 1; + } else { + *fence = NULL; + drm_syncobj_add_callback_locked(syncobj, cb, func); + ret = 0; + } + spin_unlock(&syncobj->lock); + + return ret; +} + +/** + * drm_syncobj_add_callback - adds a callback to syncobj::cb_list + * @syncobj: Sync object to which to add the callback + * @cb: Callback to add + * @func: Func to use when initializing the drm_syncobj_cb struct + * + * This adds a callback to be called next time the fence is replaced + */ +void drm_syncobj_add_callback(struct drm_syncobj *syncobj, + struct drm_syncobj_cb *cb, + drm_syncobj_func_t func) +{ + spin_lock(&syncobj->lock); + drm_syncobj_add_callback_locked(syncobj, cb, func); + spin_unlock(&syncobj->lock); +} +EXPORT_SYMBOL(drm_syncobj_add_callback); + +/** + * drm_syncobj_add_callback - removes a callback to syncobj::cb_list + * @syncobj: Sync object from which to remove the callback + * @cb: Callback to remove + */ +void drm_syncobj_remove_callback(struct drm_syncobj *syncobj, + struct drm_syncobj_cb *cb) +{ + spin_lock(&syncobj->lock); + list_del_init(&cb->node); + spin_unlock(&syncobj->lock); +} +EXPORT_SYMBOL(drm_syncobj_remove_callback); + /** * drm_syncobj_replace_fence - replace fence in a sync object. * @syncobj: Sync object to replace fence in @@ -86,18 +161,75 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj, struct dma_fence *fence) { struct dma_fence *old_fence; + struct drm_syncobj_cb *cur, *tmp; if (fence) dma_fence_get(fence); - old_fence = xchg(&syncobj->fence, fence); + + spin_lock(&syncobj->lock); + + old_fence = syncobj->fence; + syncobj->fence = fence; + + if (fence != old_fence) { + list_for_each_entry_safe(cur, tmp, &syncobj->cb_list, node) { + list_del_init(&cur->node); + cur->func(syncobj, cur); + } + } + + spin_unlock(&syncobj->lock); dma_fence_put(old_fence); } EXPORT_SYMBOL(drm_syncobj_replace_fence); -int drm_syncobj_fence_get(struct drm_file *file_private, - u32 handle, - struct dma_fence **fence) +struct drm_syncobj_null_fence { + struct dma_fence base; + spinlock_t lock; +}; + +static const char *drm_syncobj_null_fence_get_name(struct dma_fence *fence) +{ + return "syncobjnull"; +} + +static bool drm_syncobj_null_fence_enable_signaling(struct dma_fence *fence) +{ + dma_fence_enable_sw_signaling(fence); + return !dma_fence_is_signaled(fence); +} + +static const struct dma_fence_ops drm_syncobj_null_fence_ops = { + .get_driver_name = drm_syncobj_null_fence_get_name, + .get_timeline_name = drm_syncobj_null_fence_get_name, + .enable_signaling = drm_syncobj_null_fence_enable_signaling, + .wait = dma_fence_default_wait, + .release = NULL, +}; + +static int drm_syncobj_assign_null_handle(struct drm_syncobj *syncobj) +{ + struct drm_syncobj_null_fence *fence; + fence = kzalloc(sizeof(*fence), GFP_KERNEL); + if (fence == NULL) + return -ENOMEM; + + spin_lock_init(&fence->lock); + dma_fence_init(&fence->base, &drm_syncobj_null_fence_ops, + &fence->lock, 0, 0); + dma_fence_signal(&fence->base); + + drm_syncobj_replace_fence(syncobj, &fence->base); + + dma_fence_put(&fence->base); + + return 0; +} + +int drm_syncobj_find_fence(struct drm_file *file_private, + u32 handle, + struct dma_fence **fence) { struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle); int ret = 0; @@ -105,14 +237,14 @@ int drm_syncobj_fence_get(struct drm_file *file_private, if (!syncobj) return -ENOENT; - *fence = dma_fence_get(syncobj->fence); + *fence = drm_syncobj_fence_get(syncobj); if (!*fence) { ret = -EINVAL; } drm_syncobj_put(syncobj); return ret; } -EXPORT_SYMBOL(drm_syncobj_fence_get); +EXPORT_SYMBOL(drm_syncobj_find_fence); /** * drm_syncobj_free - free a sync object. @@ -125,13 +257,13 @@ void drm_syncobj_free(struct kref *kref) struct drm_syncobj *syncobj = container_of(kref, struct drm_syncobj, refcount); - dma_fence_put(syncobj->fence); + drm_syncobj_replace_fence(syncobj, NULL); kfree(syncobj); } EXPORT_SYMBOL(drm_syncobj_free); static int drm_syncobj_create(struct drm_file *file_private, - u32 *handle) + u32 *handle, uint32_t flags) { int ret; struct drm_syncobj *syncobj; @@ -141,6 +273,16 @@ static int drm_syncobj_create(struct drm_file *file_private, return -ENOMEM; kref_init(&syncobj->refcount); + INIT_LIST_HEAD(&syncobj->cb_list); + spin_lock_init(&syncobj->lock); + + if (flags & DRM_SYNCOBJ_CREATE_SIGNALED) { + ret = drm_syncobj_assign_null_handle(syncobj); + if (ret < 0) { + drm_syncobj_put(syncobj); + return ret; + } + } idr_preload(GFP_KERNEL); spin_lock(&file_private->syncobj_table_lock); @@ -307,7 +449,7 @@ static int drm_syncobj_export_sync_file(struct drm_file *file_private, if (fd < 0) return fd; - ret = drm_syncobj_fence_get(file_private, handle, &fence); + ret = drm_syncobj_find_fence(file_private, handle, &fence); if (ret) goto err_put_fd; @@ -377,11 +519,11 @@ drm_syncobj_create_ioctl(struct drm_device *dev, void *data, return -ENODEV; /* no valid flags yet */ - if (args->flags) + if (args->flags & ~DRM_SYNCOBJ_CREATE_SIGNALED) return -EINVAL; return drm_syncobj_create(file_private, - &args->handle); + &args->handle, args->flags); } int @@ -447,3 +589,368 @@ drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, void *data, return drm_syncobj_fd_to_handle(file_private, args->fd, &args->handle); } + +struct syncobj_wait_entry { + struct task_struct *task; + struct dma_fence *fence; + struct dma_fence_cb fence_cb; + struct drm_syncobj_cb syncobj_cb; +}; + +static void syncobj_wait_fence_func(struct dma_fence *fence, + struct dma_fence_cb *cb) +{ + struct syncobj_wait_entry *wait = + container_of(cb, struct syncobj_wait_entry, fence_cb); + + wake_up_process(wait->task); +} + +static void syncobj_wait_syncobj_func(struct drm_syncobj *syncobj, + struct drm_syncobj_cb *cb) +{ + struct syncobj_wait_entry *wait = + container_of(cb, struct syncobj_wait_entry, syncobj_cb); + + /* This happens inside the syncobj lock */ + wait->fence = dma_fence_get(syncobj->fence); + wake_up_process(wait->task); +} + +static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs, + uint32_t count, + uint32_t flags, + signed long timeout, + uint32_t *idx) +{ + struct syncobj_wait_entry *entries; + struct dma_fence *fence; + signed long ret; + uint32_t signaled_count, i; + + entries = kcalloc(count, sizeof(*entries), GFP_KERNEL); + if (!entries) + return -ENOMEM; + + /* Walk the list of sync objects and initialize entries. We do + * this up-front so that we can properly return -EINVAL if there is + * a syncobj with a missing fence and then never have the chance of + * returning -EINVAL again. + */ + signaled_count = 0; + for (i = 0; i < count; ++i) { + entries[i].task = current; + entries[i].fence = drm_syncobj_fence_get(syncobjs[i]); + if (!entries[i].fence) { + if (flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT) { + continue; + } else { + ret = -EINVAL; + goto cleanup_entries; + } + } + + if (dma_fence_is_signaled(entries[i].fence)) { + if (signaled_count == 0 && idx) + *idx = i; + signaled_count++; + } + } + + /* Initialize ret to the max of timeout and 1. That way, the + * default return value indicates a successful wait and not a + * timeout. + */ + ret = max_t(signed long, timeout, 1); + + if (signaled_count == count || + (signaled_count > 0 && + !(flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL))) + goto cleanup_entries; + + /* There's a very annoying laxness in the dma_fence API here, in + * that backends are not required to automatically report when a + * fence is signaled prior to fence->ops->enable_signaling() being + * called. So here if we fail to match signaled_count, we need to + * fallthough and try a 0 timeout wait! + */ + + if (flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT) { + for (i = 0; i < count; ++i) { + drm_syncobj_fence_get_or_add_callback(syncobjs[i], + &entries[i].fence, + &entries[i].syncobj_cb, + syncobj_wait_syncobj_func); + } + } + + do { + set_current_state(TASK_INTERRUPTIBLE); + + signaled_count = 0; + for (i = 0; i < count; ++i) { + fence = entries[i].fence; + if (!fence) + continue; + + if (dma_fence_is_signaled(fence) || + (!entries[i].fence_cb.func && + dma_fence_add_callback(fence, + &entries[i].fence_cb, + syncobj_wait_fence_func))) { + /* The fence has been signaled */ + if (flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL) { + signaled_count++; + } else { + if (idx) + *idx = i; + goto done_waiting; + } + } + } + + if (signaled_count == count) + goto done_waiting; + + if (timeout == 0) { + /* If we are doing a 0 timeout wait and we got + * here, then we just timed out. + */ + ret = 0; + goto done_waiting; + } + + ret = schedule_timeout(ret); + + if (ret > 0 && signal_pending(current)) + ret = -ERESTARTSYS; + } while (ret > 0); + +done_waiting: + __set_current_state(TASK_RUNNING); + +cleanup_entries: + for (i = 0; i < count; ++i) { + if (entries[i].syncobj_cb.func) + drm_syncobj_remove_callback(syncobjs[i], + &entries[i].syncobj_cb); + if (entries[i].fence_cb.func) + dma_fence_remove_callback(entries[i].fence, + &entries[i].fence_cb); + dma_fence_put(entries[i].fence); + } + kfree(entries); + + return ret; +} + +/** + * drm_timeout_abs_to_jiffies - calculate jiffies timeout from absolute value + * + * @timeout_nsec: timeout nsec component in ns, 0 for poll + * + * Calculate the timeout in jiffies from an absolute time in sec/nsec. + */ +static signed long drm_timeout_abs_to_jiffies(int64_t timeout_nsec) +{ + ktime_t abs_timeout, now; + u64 timeout_ns, timeout_jiffies64; + + /* make 0 timeout means poll - absolute 0 doesn't seem valid */ + if (timeout_nsec == 0) + return 0; + + abs_timeout = ns_to_ktime(timeout_nsec); + now = ktime_get(); + + if (!ktime_after(abs_timeout, now)) + return 0; + + timeout_ns = ktime_to_ns(ktime_sub(abs_timeout, now)); + + timeout_jiffies64 = nsecs_to_jiffies64(timeout_ns); + /* clamp timeout to avoid infinite timeout */ + if (timeout_jiffies64 >= MAX_SCHEDULE_TIMEOUT - 1) + return MAX_SCHEDULE_TIMEOUT - 1; + + return timeout_jiffies64 + 1; +} + +static int drm_syncobj_array_wait(struct drm_device *dev, + struct drm_file *file_private, + struct drm_syncobj_wait *wait, + struct drm_syncobj **syncobjs) +{ + signed long timeout = drm_timeout_abs_to_jiffies(wait->timeout_nsec); + signed long ret = 0; + uint32_t first = ~0; + + ret = drm_syncobj_array_wait_timeout(syncobjs, + wait->count_handles, + wait->flags, + timeout, &first); + if (ret < 0) + return ret; + + wait->first_signaled = first; + if (ret == 0) + return -ETIME; + return 0; +} + +static int drm_syncobj_array_find(struct drm_file *file_private, + void *user_handles, uint32_t count_handles, + struct drm_syncobj ***syncobjs_out) +{ + uint32_t i, *handles; + struct drm_syncobj **syncobjs; + int ret; + + handles = kmalloc_array(count_handles, sizeof(*handles), GFP_KERNEL); + if (handles == NULL) + return -ENOMEM; + + if (copy_from_user(handles, user_handles, + sizeof(uint32_t) * count_handles)) { + ret = -EFAULT; + goto err_free_handles; + } + + syncobjs = kmalloc_array(count_handles, sizeof(*syncobjs), GFP_KERNEL); + if (syncobjs == NULL) { + ret = -ENOMEM; + goto err_free_handles; + } + + for (i = 0; i < count_handles; i++) { + syncobjs[i] = drm_syncobj_find(file_private, handles[i]); + if (!syncobjs[i]) { + ret = -ENOENT; + goto err_put_syncobjs; + } + } + + kfree(handles); + *syncobjs_out = syncobjs; + return 0; + +err_put_syncobjs: + while (i-- > 0) + drm_syncobj_put(syncobjs[i]); + kfree(syncobjs); +err_free_handles: + kfree(handles); + + return ret; +} + +static void drm_syncobj_array_free(struct drm_syncobj **syncobjs, + uint32_t count) +{ + uint32_t i; + for (i = 0; i < count; i++) + drm_syncobj_put(syncobjs[i]); + kfree(syncobjs); +} + +int +drm_syncobj_wait_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_private) +{ + struct drm_syncobj_wait *args = data; + struct drm_syncobj **syncobjs; + int ret = 0; + + if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ)) + return -ENODEV; + + if (args->flags & ~(DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL | + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT)) + return -EINVAL; + + if (args->count_handles == 0) + return -EINVAL; + + ret = drm_syncobj_array_find(file_private, + u64_to_user_ptr(args->handles), + args->count_handles, + &syncobjs); + if (ret < 0) + return ret; + + ret = drm_syncobj_array_wait(dev, file_private, + args, syncobjs); + + drm_syncobj_array_free(syncobjs, args->count_handles); + + return ret; +} + +int +drm_syncobj_reset_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_private) +{ + struct drm_syncobj_array *args = data; + struct drm_syncobj **syncobjs; + uint32_t i; + int ret; + + if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ)) + return -ENODEV; + + if (args->pad != 0) + return -EINVAL; + + if (args->count_handles == 0) + return -EINVAL; + + ret = drm_syncobj_array_find(file_private, + u64_to_user_ptr(args->handles), + args->count_handles, + &syncobjs); + if (ret < 0) + return ret; + + for (i = 0; i < args->count_handles; i++) + drm_syncobj_replace_fence(syncobjs[i], NULL); + + drm_syncobj_array_free(syncobjs, args->count_handles); + + return 0; +} + +int +drm_syncobj_signal_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_private) +{ + struct drm_syncobj_array *args = data; + struct drm_syncobj **syncobjs; + uint32_t i; + int ret; + + if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ)) + return -ENODEV; + + if (args->pad != 0) + return -EINVAL; + + if (args->count_handles == 0) + return -EINVAL; + + ret = drm_syncobj_array_find(file_private, + u64_to_user_ptr(args->handles), + args->count_handles, + &syncobjs); + if (ret < 0) + return ret; + + for (i = 0; i < args->count_handles; i++) { + ret = drm_syncobj_assign_null_handle(syncobjs[i]); + if (ret < 0) + break; + } + + drm_syncobj_array_free(syncobjs, args->count_handles); + + return ret; +} diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index 13a59ed2afbc..2660543ad86a 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -40,6 +40,7 @@ #include <linux/efi.h> #include <linux/slab.h> #endif +#include <linux/mem_encrypt.h> #include <asm/pgtable.h> #include "drm_internal.h" #include "drm_legacy.h" @@ -58,6 +59,9 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, { pgprot_t tmp = vm_get_page_prot(vma->vm_flags); + /* We don't want graphics memory to be mapped encrypted */ + tmp = pgprot_decrypted(tmp); + #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING)) tmp = pgprot_noncached(tmp); diff --git a/drivers/gpu/drm/drm_vma_manager.c b/drivers/gpu/drm/drm_vma_manager.c index d9100b565198..28f1226576f8 100644 --- a/drivers/gpu/drm/drm_vma_manager.c +++ b/drivers/gpu/drm/drm_vma_manager.c @@ -147,7 +147,7 @@ struct drm_vma_offset_node *drm_vma_offset_lookup_locked(struct drm_vma_offset_m struct rb_node *iter; unsigned long offset; - iter = mgr->vm_addr_space_mm.interval_tree.rb_node; + iter = mgr->vm_addr_space_mm.interval_tree.rb_root.rb_node; best = NULL; while (likely(iter)) { diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig index 71cee4e9fefb..38b477b5fbf9 100644 --- a/drivers/gpu/drm/etnaviv/Kconfig +++ b/drivers/gpu/drm/etnaviv/Kconfig @@ -10,6 +10,8 @@ config DRM_ETNAVIV select IOMMU_API select IOMMU_SUPPORT select WANT_DEV_COREDUMP + select CMA if HAVE_DMA_CONTIGUOUS + select DMA_CMA if HAVE_DMA_CONTIGUOUS help DRM driver for Vivante GPUs. diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index 91e17aeee1da..2cb4773823c2 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -316,7 +316,7 @@ static int etnaviv_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, ret = etnaviv_gem_cpu_prep(obj, args->op, &TS(args->timeout)); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -337,7 +337,7 @@ static int etnaviv_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, ret = etnaviv_gem_cpu_fini(obj); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -357,7 +357,7 @@ static int etnaviv_ioctl_gem_info(struct drm_device *dev, void *data, return -ENOENT; ret = etnaviv_gem_mmap_offset(obj, &args->offset); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -446,7 +446,7 @@ static int etnaviv_ioctl_gem_wait(struct drm_device *dev, void *data, ret = etnaviv_gem_wait_bo(gpu, obj, timeout); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c index 9a3bea738330..57881167ccd2 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c @@ -68,7 +68,7 @@ static int etnaviv_gem_shmem_get_pages(struct etnaviv_gem_object *etnaviv_obj) struct page **p = drm_gem_get_pages(&etnaviv_obj->base); if (IS_ERR(p)) { - dev_err(dev->dev, "could not get pages: %ld\n", PTR_ERR(p)); + dev_dbg(dev->dev, "could not get pages: %ld\n", PTR_ERR(p)); return PTR_ERR(p); } @@ -265,7 +265,7 @@ void etnaviv_gem_mapping_reference(struct etnaviv_vram_mapping *mapping) { struct etnaviv_gem_object *etnaviv_obj = mapping->object; - drm_gem_object_reference(&etnaviv_obj->base); + drm_gem_object_get(&etnaviv_obj->base); mutex_lock(&etnaviv_obj->lock); WARN_ON(mapping->use == 0); @@ -282,7 +282,7 @@ void etnaviv_gem_mapping_unreference(struct etnaviv_vram_mapping *mapping) mapping->use -= 1; mutex_unlock(&etnaviv_obj->lock); - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); } struct etnaviv_vram_mapping *etnaviv_gem_mapping_get( @@ -358,7 +358,7 @@ out: return ERR_PTR(ret); /* Take a reference on the object */ - drm_gem_object_reference(obj); + drm_gem_object_get(obj); return mapping; } @@ -413,6 +413,16 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op, bool write = !!(op & ETNA_PREP_WRITE); int ret; + if (!etnaviv_obj->sgt) { + void *ret; + + mutex_lock(&etnaviv_obj->lock); + ret = etnaviv_gem_get_pages(etnaviv_obj); + mutex_unlock(&etnaviv_obj->lock); + if (IS_ERR(ret)) + return PTR_ERR(ret); + } + if (op & ETNA_PREP_NOSYNC) { if (!reservation_object_test_signaled_rcu(etnaviv_obj->resv, write)) @@ -427,16 +437,6 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op, } if (etnaviv_obj->flags & ETNA_BO_CACHED) { - if (!etnaviv_obj->sgt) { - void *ret; - - mutex_lock(&etnaviv_obj->lock); - ret = etnaviv_gem_get_pages(etnaviv_obj); - mutex_unlock(&etnaviv_obj->lock); - if (IS_ERR(ret)) - return PTR_ERR(ret); - } - dma_sync_sg_for_cpu(dev->dev, etnaviv_obj->sgt->sgl, etnaviv_obj->sgt->nents, etnaviv_op_to_dma_dir(op)); @@ -551,12 +551,15 @@ static const struct etnaviv_gem_ops etnaviv_gem_shmem_ops = { void etnaviv_gem_free_object(struct drm_gem_object *obj) { struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj); + struct etnaviv_drm_private *priv = obj->dev->dev_private; struct etnaviv_vram_mapping *mapping, *tmp; /* object should not be active */ WARN_ON(is_active(etnaviv_obj)); + mutex_lock(&priv->gem_lock); list_del(&etnaviv_obj->gem_node); + mutex_unlock(&priv->gem_lock); list_for_each_entry_safe(mapping, tmp, &etnaviv_obj->vram_list, obj_node) { @@ -662,7 +665,8 @@ static struct drm_gem_object *__etnaviv_gem_new(struct drm_device *dev, * going to pin these pages. */ mapping = obj->filp->f_mapping; - mapping_set_gfp_mask(mapping, GFP_HIGHUSER); + mapping_set_gfp_mask(mapping, GFP_HIGHUSER | + __GFP_RETRY_MAYFAIL | __GFP_NOWARN); } if (ret) @@ -671,7 +675,7 @@ static struct drm_gem_object *__etnaviv_gem_new(struct drm_device *dev, return obj; fail: - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(ret); } @@ -688,14 +692,14 @@ int etnaviv_gem_new_handle(struct drm_device *dev, struct drm_file *file, ret = etnaviv_gem_obj_add(dev, obj); if (ret < 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } ret = drm_gem_handle_create(file, obj, handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -712,7 +716,7 @@ struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev, ret = etnaviv_gem_obj_add(dev, obj); if (ret < 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(ret); } @@ -800,7 +804,7 @@ static void __etnaviv_gem_userptr_get_pages(struct work_struct *_work) } mutex_unlock(&etnaviv_obj->lock); - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); mmput(work->mm); put_task_struct(work->task); @@ -858,7 +862,7 @@ static int etnaviv_gem_userptr_get_pages(struct etnaviv_gem_object *etnaviv_obj) } get_task_struct(current); - drm_gem_object_reference(&etnaviv_obj->base); + drm_gem_object_get(&etnaviv_obj->base); work->mm = mm; work->task = current; @@ -924,6 +928,6 @@ int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file, ret = drm_gem_handle_create(file, &etnaviv_obj->base, handle); unreference: /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); return ret; } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index e5da4f2300ba..ae884723e9b1 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -146,7 +146,7 @@ struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev, return &etnaviv_obj->base; fail: - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c index 6463fc2c736f..46dfe0737f43 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c @@ -37,7 +37,7 @@ static struct etnaviv_gem_submit *submit_create(struct drm_device *dev, struct etnaviv_gem_submit *submit; size_t sz = size_vstruct(nr, sizeof(submit->bos[0]), sizeof(*submit)); - submit = kmalloc(sz, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); + submit = kmalloc(sz, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); if (submit) { submit->dev = dev; submit->gpu = gpu; @@ -88,7 +88,7 @@ static int submit_lookup_objects(struct etnaviv_gem_submit *submit, * Take a refcount on the object. The file table lock * prevents the object_idr's refcount on this being dropped. */ - drm_gem_object_reference(obj); + drm_gem_object_get(obj); submit->bos[i].obj = to_etnaviv_bo(obj); } @@ -291,7 +291,7 @@ static void submit_cleanup(struct etnaviv_gem_submit *submit) struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; submit_unlock_object(submit, i); - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); } ww_acquire_fini(&submit->ticket); @@ -445,8 +445,10 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data, cmdbuf->user_size = ALIGN(args->stream_size, 8); ret = etnaviv_gpu_submit(gpu, submit, cmdbuf); - if (ret == 0) - cmdbuf = NULL; + if (ret) + goto out; + + cmdbuf = NULL; if (args->flags & ETNA_SUBMIT_FENCE_FD_OUT) { /* diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index ada45fdd0eae..fc9a6a83dfc7 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1622,10 +1622,12 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master, struct etnaviv_gpu *gpu = dev_get_drvdata(dev); int ret; - gpu->cooling = thermal_of_cooling_device_register(dev->of_node, + if (IS_ENABLED(CONFIG_THERMAL)) { + gpu->cooling = thermal_of_cooling_device_register(dev->of_node, (char *)dev_name(dev), gpu, &cooling_ops); - if (IS_ERR(gpu->cooling)) - return PTR_ERR(gpu->cooling); + if (IS_ERR(gpu->cooling)) + return PTR_ERR(gpu->cooling); + } #ifdef CONFIG_PM ret = pm_runtime_get_sync(gpu->dev); diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 5792ca88ab7a..6be5b53c3b27 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -13,6 +13,8 @@ #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/component.h> +#include <linux/iopoll.h> +#include <linux/irq.h> #include <linux/mfd/syscon.h> #include <linux/of_device.h> #include <linux/of_gpio.h> @@ -33,9 +35,8 @@ #define WINDOWS_NR 3 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 -#define IFTYPE_I80 (1 << 0) -#define I80_HW_TRG (1 << 1) -#define IFTYPE_HDMI (1 << 2) +#define I80_HW_TRG (1 << 0) +#define IFTYPE_HDMI (1 << 1) static const char * const decon_clks_name[] = { "pclk", @@ -57,6 +58,8 @@ struct decon_context { struct regmap *sysreg; struct clk *clks[ARRAY_SIZE(decon_clks_name)]; unsigned int irq; + unsigned int irq_vsync; + unsigned int irq_lcd_sys; unsigned int te_irq; unsigned long out_type; int first_win; @@ -90,7 +93,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc) u32 val; val = VIDINTCON0_INTEN; - if (ctx->out_type & IFTYPE_I80) + if (crtc->i80_mode) val |= VIDINTCON0_FRAMEDONE; else val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP; @@ -139,7 +142,7 @@ static u32 decon_get_frame_count(struct decon_context *ctx, bool end) switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) { case VIDCON1_VSTATUS_VS: - if (!(ctx->out_type & IFTYPE_I80)) + if (!(ctx->crtc->i80_mode)) --frm; break; case VIDCON1_VSTATUS_BP: @@ -166,7 +169,7 @@ static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc) static void decon_setup_trigger(struct decon_context *ctx) { - if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG))) + if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) return; if (!(ctx->out_type & I80_HW_TRG)) { @@ -206,7 +209,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc) val = VIDOUT_LCD_ON; if (interlaced) val |= VIDOUT_INTERLACE_EN_F; - if (ctx->out_type & IFTYPE_I80) { + if (crtc->i80_mode) { val |= VIDOUT_COMMAND_IF; } else { val |= VIDOUT_RGB_IF; @@ -222,7 +225,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc) VIDTCON2_HOZVAL(m->hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON2); - if (!(ctx->out_type & IFTYPE_I80)) { + if (!crtc->i80_mode) { int vbp = m->crtc_vtotal - m->crtc_vsync_end; int vfp = m->crtc_vsync_start - m->crtc_vdisplay; @@ -277,16 +280,14 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val |= WINCONx_BURSTLEN_16WORD; break; case DRM_FORMAT_ARGB8888: + default: val |= WINCONx_BPPMODE_32BPP_A8888; val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; val |= WINCONx_BURSTLEN_16WORD; break; - default: - DRM_ERROR("Proper pixel format is not set\n"); - return; } - DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8); + DRM_DEBUG_KMS("cpp = %u\n", fb->format->cpp[0]); /* * In case of exynos, setting dma-burst to 16Word causes permanent @@ -329,7 +330,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, struct decon_context *ctx = crtc->ctx; struct drm_framebuffer *fb = state->base.fb; unsigned int win = plane->index; - unsigned int bpp = fb->format->cpp[0]; + unsigned int cpp = fb->format->cpp[0]; unsigned int pitch = fb->pitches[0]; dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); u32 val; @@ -365,11 +366,11 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); if (!(ctx->out_type & IFTYPE_HDMI)) - val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14) - | BIT_VAL(state->crtc.w * bpp, 13, 0); + val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14) + | BIT_VAL(state->crtc.w * cpp, 13, 0); else - val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15) - | BIT_VAL(state->crtc.w * bpp, 14, 0); + val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15) + | BIT_VAL(state->crtc.w * cpp, 14, 0); writel(val, ctx->addr + DECON_VIDW0xADD2(win)); decon_win_set_pixfmt(ctx, win, fb); @@ -407,24 +408,19 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc) static void decon_swreset(struct decon_context *ctx) { - unsigned int tries; unsigned long flags; + u32 val; + int ret; writel(0, ctx->addr + DECON_VIDCON0); - for (tries = 2000; tries; --tries) { - if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS) - break; - udelay(10); - } + readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, + ~val & VIDCON0_STOP_STATUS, 12, 20000); writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); - for (tries = 2000; tries; --tries) { - if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET) - break; - udelay(10); - } + ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, + ~val & VIDCON0_SWRESET, 12, 20000); - WARN(tries == 0, "failed to software reset DECON\n"); + WARN(ret < 0, "failed to software reset DECON\n"); spin_lock_irqsave(&ctx->vblank_lock, flags); ctx->frame_id = 0; @@ -515,6 +511,22 @@ err: clk_disable_unprepare(ctx->clks[i]); } +static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct decon_context *ctx = crtc->ctx; + + ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync; + + if (ctx->irq) + return MODE_OK; + + dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n", + crtc->i80_mode ? "command" : "video"); + + return MODE_BAD; +} + static const struct exynos_drm_crtc_ops decon_crtc_ops = { .enable = decon_enable, .disable = decon_disable, @@ -524,6 +536,7 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = { .atomic_begin = decon_atomic_begin, .update_plane = decon_update_plane, .disable_plane = decon_disable_plane, + .mode_valid = decon_mode_valid, .atomic_flush = decon_atomic_flush, }; @@ -674,19 +687,22 @@ static const struct of_device_id exynos5433_decon_driver_dt_match[] = { MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); static int decon_conf_irq(struct decon_context *ctx, const char *name, - irq_handler_t handler, unsigned long int flags, bool required) + irq_handler_t handler, unsigned long int flags) { struct platform_device *pdev = to_platform_device(ctx->dev); int ret, irq = platform_get_irq_byname(pdev, name); if (irq < 0) { - if (irq == -EPROBE_DEFER) + switch (irq) { + case -EPROBE_DEFER: return irq; - if (required) - dev_err(ctx->dev, "cannot get %s IRQ\n", name); - else - irq = 0; - return irq; + case -ENODATA: + case -ENXIO: + return 0; + default: + dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq); + return irq; + } } irq_set_status_flags(irq, IRQ_NOAUTOEN); ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx); @@ -714,11 +730,8 @@ static int exynos5433_decon_probe(struct platform_device *pdev) ctx->out_type = (unsigned long)of_device_get_match_data(dev); spin_lock_init(&ctx->vblank_lock); - if (ctx->out_type & IFTYPE_HDMI) { + if (ctx->out_type & IFTYPE_HDMI) ctx->first_win = 1; - } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) { - ctx->out_type |= IFTYPE_I80; - } for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { struct clk *clk; @@ -742,25 +755,23 @@ static int exynos5433_decon_probe(struct platform_device *pdev) return PTR_ERR(ctx->addr); } - if (ctx->out_type & IFTYPE_I80) { - ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0, true); - if (ret < 0) - return ret; - ctx->irq = ret; + ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0); + if (ret < 0) + return ret; + ctx->irq_vsync = ret; - ret = decon_conf_irq(ctx, "te", decon_te_irq_handler, - IRQF_TRIGGER_RISING, false); - if (ret < 0) - return ret; - if (ret) { - ctx->te_irq = ret; - ctx->out_type &= ~I80_HW_TRG; - } - } else { - ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0, true); - if (ret < 0) + ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0); + if (ret < 0) + return ret; + ctx->irq_lcd_sys = ret; + + ret = decon_conf_irq(ctx, "te", decon_te_irq_handler, + IRQF_TRIGGER_RISING); + if (ret < 0) return ret; - ctx->irq = ret; + if (ret) { + ctx->te_irq = ret; + ctx->out_type &= ~I80_HW_TRG; } if (ctx->out_type & I80_HW_TRG) { diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 3e88269fdc2e..615efcf7782a 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -309,19 +309,14 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val |= WINCONx_BURSTLEN_16WORD; break; case DRM_FORMAT_BGRA8888: + default: val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | WINCONx_ALPHA_SEL; val |= WINCONx_BURSTLEN_16WORD; break; - default: - DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); - - val |= WINCONx_BPPMODE_24BPP_xRGB; - val |= WINCONx_BURSTLEN_16WORD; - break; } - DRM_DEBUG_KMS("bpp = %d\n", fb->format->cpp[0] * 8); + DRM_DEBUG_KMS("cpp = %d\n", fb->format->cpp[0]); /* * In case of exynos, setting dma-burst to 16Word causes permanent @@ -398,7 +393,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, unsigned int last_x; unsigned int last_y; unsigned int win = plane->index; - unsigned int bpp = fb->format->cpp[0]; + unsigned int cpp = fb->format->cpp[0]; unsigned int pitch = fb->pitches[0]; if (ctx->suspended) @@ -418,7 +413,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); writel(val, ctx->regs + VIDW_BUF_START(win)); - padding = (pitch / bpp) - fb->width; + padding = (pitch / cpp) - fb->width; /* buffer size */ writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c index 385537b726a6..39629e7a80b9 100644 --- a/drivers/gpu/drm/exynos/exynos_dp.c +++ b/drivers/gpu/drm/exynos/exynos_dp.c @@ -155,7 +155,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data) struct exynos_dp_device *dp = dev_get_drvdata(dev); struct drm_encoder *encoder = &dp->encoder; struct drm_device *drm_dev = data; - int pipe, ret; + int ret; /* * Just like the probe function said, we don't need the @@ -179,20 +179,15 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data) return ret; } - pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev, - EXYNOS_DISPLAY_TYPE_LCD); - if (pipe < 0) - return pipe; - - encoder->possible_crtcs = 1 << pipe; - - DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); - drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs); + ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); + if (ret < 0) + return ret; + dp->plat_data.encoder = encoder; return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data); diff --git a/drivers/gpu/drm/exynos/exynos_drm_core.c b/drivers/gpu/drm/exynos/exynos_drm_core.c index edbd98ff293e..b0c0621fcdf7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_core.c +++ b/drivers/gpu/drm/exynos/exynos_drm_core.c @@ -13,6 +13,7 @@ */ #include <drm/drmP.h> + #include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index c37078fbe0ea..6ce0821590df 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -16,6 +16,7 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_encoder.h> #include "exynos_drm_crtc.h" #include "exynos_drm_drv.h" @@ -83,7 +84,19 @@ static void exynos_crtc_atomic_flush(struct drm_crtc *crtc, exynos_crtc->ops->atomic_flush(exynos_crtc); } +static enum drm_mode_status exynos_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); + + if (exynos_crtc->ops->mode_valid) + return exynos_crtc->ops->mode_valid(exynos_crtc, mode); + + return MODE_OK; +} + static const struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = { + .mode_valid = exynos_crtc_mode_valid, .atomic_check = exynos_crtc_atomic_check, .atomic_begin = exynos_crtc_atomic_begin, .atomic_flush = exynos_crtc_atomic_flush, @@ -191,16 +204,30 @@ err_crtc: return ERR_PTR(ret); } -int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev, +struct exynos_drm_crtc *exynos_drm_crtc_get_by_type(struct drm_device *drm_dev, enum exynos_drm_output_type out_type) { struct drm_crtc *crtc; drm_for_each_crtc(crtc, drm_dev) if (to_exynos_crtc(crtc)->type == out_type) - return drm_crtc_index(crtc); + return to_exynos_crtc(crtc); - return -EPERM; + return ERR_PTR(-EPERM); +} + +int exynos_drm_set_possible_crtcs(struct drm_encoder *encoder, + enum exynos_drm_output_type out_type) +{ + struct exynos_drm_crtc *crtc = exynos_drm_crtc_get_by_type(encoder->dev, + out_type); + + if (IS_ERR(crtc)) + return PTR_ERR(crtc); + + encoder->possible_crtcs = drm_crtc_mask(&crtc->base); + + return 0; } void exynos_drm_crtc_te_handler(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h b/drivers/gpu/drm/exynos/exynos_drm_crtc.h index ef58b64e3d2d..dec446109e6c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h @@ -15,21 +15,25 @@ #ifndef _EXYNOS_DRM_CRTC_H_ #define _EXYNOS_DRM_CRTC_H_ + #include "exynos_drm_drv.h" struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev, struct drm_plane *plane, - enum exynos_drm_output_type type, + enum exynos_drm_output_type out_type, const struct exynos_drm_crtc_ops *ops, void *context); void exynos_drm_crtc_wait_pending_update(struct exynos_drm_crtc *exynos_crtc); void exynos_drm_crtc_finish_update(struct exynos_drm_crtc *exynos_crtc, struct exynos_drm_plane *exynos_plane); -/* This function gets pipe value to crtc device matched with out_type. */ -int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev, +/* This function gets crtc device matched with out_type. */ +struct exynos_drm_crtc *exynos_drm_crtc_get_by_type(struct drm_device *drm_dev, enum exynos_drm_output_type out_type); +int exynos_drm_set_possible_crtcs(struct drm_encoder *encoder, + enum exynos_drm_output_type out_type); + /* * This function calls the crtc device(manager)'s te_handler() callback * to trigger to transfer video image at the tearing effect synchronization diff --git a/drivers/gpu/drm/exynos/exynos_drm_dpi.c b/drivers/gpu/drm/exynos/exynos_drm_dpi.c index 76d80e5de521..66945e0dc57f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dpi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dpi.c @@ -202,19 +202,15 @@ int exynos_dpi_bind(struct drm_device *dev, struct drm_encoder *encoder) { int ret; - ret = exynos_drm_crtc_get_pipe_from_type(dev, EXYNOS_DISPLAY_TYPE_LCD); - if (ret < 0) - return ret; - - encoder->possible_crtcs = 1 << ret; - - DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); - drm_encoder_init(dev, encoder, &exynos_dpi_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); drm_encoder_helper_add(encoder, &exynos_dpi_encoder_helper_funcs); + ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); + if (ret < 0) + return ret; + ret = exynos_dpi_create_connector(encoder); if (ret) { DRM_ERROR("failed to create connector ret = %d\n", ret); diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index b1f7299600f0..e651a58c18cf 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -168,23 +168,19 @@ static struct drm_driver exynos_drm_driver = { static int exynos_drm_suspend(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); - struct drm_connector *connector; - struct drm_connector_list_iter conn_iter; + struct exynos_drm_private *private = drm_dev->dev_private; if (pm_runtime_suspended(dev) || !drm_dev) return 0; - drm_connector_list_iter_begin(drm_dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { - int old_dpms = connector->dpms; - - if (connector->funcs->dpms) - connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF); - - /* Set the old mode back to the connector for resume */ - connector->dpms = old_dpms; + drm_kms_helper_poll_disable(drm_dev); + exynos_drm_fbdev_suspend(drm_dev); + private->suspend_state = drm_atomic_helper_suspend(drm_dev); + if (IS_ERR(private->suspend_state)) { + exynos_drm_fbdev_resume(drm_dev); + drm_kms_helper_poll_enable(drm_dev); + return PTR_ERR(private->suspend_state); } - drm_connector_list_iter_end(&conn_iter); return 0; } @@ -192,22 +188,14 @@ static int exynos_drm_suspend(struct device *dev) static int exynos_drm_resume(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); - struct drm_connector *connector; - struct drm_connector_list_iter conn_iter; + struct exynos_drm_private *private = drm_dev->dev_private; if (pm_runtime_suspended(dev) || !drm_dev) return 0; - drm_connector_list_iter_begin(drm_dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { - if (connector->funcs->dpms) { - int dpms = connector->dpms; - - connector->dpms = DRM_MODE_DPMS_OFF; - connector->funcs->dpms(connector, dpms); - } - } - drm_connector_list_iter_end(&conn_iter); + drm_atomic_helper_resume(drm_dev, private->suspend_state); + exynos_drm_fbdev_resume(drm_dev); + drm_kms_helper_poll_enable(drm_dev); return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index a93de321706b..f8bae4cb4823 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -91,6 +91,7 @@ struct exynos_drm_plane { #define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) #define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) #define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) +#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) /* * Exynos DRM plane configuration structure. @@ -117,6 +118,7 @@ struct exynos_drm_plane_config { * @disable: disable the device * @enable_vblank: specific driver callback for enabling vblank interrupt. * @disable_vblank: specific driver callback for disabling vblank interrupt. + * @mode_valid: specific driver callback for mode validation * @atomic_check: validate state * @atomic_begin: prepare device to receive an update * @atomic_flush: mark the end of device update @@ -132,6 +134,8 @@ struct exynos_drm_crtc_ops { int (*enable_vblank)(struct exynos_drm_crtc *crtc); void (*disable_vblank)(struct exynos_drm_crtc *crtc); u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc); + enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode); int (*atomic_check)(struct exynos_drm_crtc *crtc, struct drm_crtc_state *state); void (*atomic_begin)(struct exynos_drm_crtc *crtc); @@ -162,6 +166,7 @@ struct exynos_drm_crtc { const struct exynos_drm_crtc_ops *ops; void *ctx; struct exynos_drm_clk *pipe_clk; + bool i80_mode : 1; }; static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc, @@ -197,6 +202,7 @@ struct drm_exynos_file_private { */ struct exynos_drm_private { struct drm_fb_helper *fb_helper; + struct drm_atomic_state *suspend_state; struct device *dma_dev; void *mapping; diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index c399dc9b325f..7904ffa9abfb 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -254,7 +254,6 @@ struct exynos_dsi { struct drm_encoder encoder; struct mipi_dsi_host dsi_host; struct drm_connector connector; - struct device_node *panel_node; struct drm_panel *panel; struct device *dev; @@ -1329,12 +1328,13 @@ static int exynos_dsi_init(struct exynos_dsi *dsi) return 0; } -static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) +static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, + struct device *panel) { int ret; int te_gpio_irq; - dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); + dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0); if (dsi->te_gpio == -ENOENT) return 0; @@ -1374,85 +1374,6 @@ static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) } } -static int exynos_dsi_host_attach(struct mipi_dsi_host *host, - struct mipi_dsi_device *device) -{ - struct exynos_dsi *dsi = host_to_dsi(host); - - dsi->lanes = device->lanes; - dsi->format = device->format; - dsi->mode_flags = device->mode_flags; - dsi->panel_node = device->dev.of_node; - - /* - * This is a temporary solution and should be made by more generic way. - * - * If attached panel device is for command mode one, dsi should register - * TE interrupt handler. - */ - if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { - int ret = exynos_dsi_register_te_irq(dsi); - - if (ret) - return ret; - } - - if (dsi->connector.dev) - drm_helper_hpd_irq_event(dsi->connector.dev); - - return 0; -} - -static int exynos_dsi_host_detach(struct mipi_dsi_host *host, - struct mipi_dsi_device *device) -{ - struct exynos_dsi *dsi = host_to_dsi(host); - - exynos_dsi_unregister_te_irq(dsi); - - dsi->panel_node = NULL; - - if (dsi->connector.dev) - drm_helper_hpd_irq_event(dsi->connector.dev); - - return 0; -} - -static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, - const struct mipi_dsi_msg *msg) -{ - struct exynos_dsi *dsi = host_to_dsi(host); - struct exynos_dsi_transfer xfer; - int ret; - - if (!(dsi->state & DSIM_STATE_ENABLED)) - return -EINVAL; - - if (!(dsi->state & DSIM_STATE_INITIALIZED)) { - ret = exynos_dsi_init(dsi); - if (ret) - return ret; - dsi->state |= DSIM_STATE_INITIALIZED; - } - - ret = mipi_dsi_create_packet(&xfer.packet, msg); - if (ret < 0) - return ret; - - xfer.rx_len = msg->rx_len; - xfer.rx_payload = msg->rx_buf; - xfer.flags = msg->flags; - - ret = exynos_dsi_transfer(dsi, &xfer); - return (ret < 0) ? ret : xfer.rx_done; -} - -static const struct mipi_dsi_host_ops exynos_dsi_ops = { - .attach = exynos_dsi_host_attach, - .detach = exynos_dsi_host_detach, - .transfer = exynos_dsi_host_transfer, -}; - static void exynos_dsi_enable(struct drm_encoder *encoder) { struct exynos_dsi *dsi = encoder_to_dsi(encoder); @@ -1508,25 +1429,7 @@ static void exynos_dsi_disable(struct drm_encoder *encoder) static enum drm_connector_status exynos_dsi_detect(struct drm_connector *connector, bool force) { - struct exynos_dsi *dsi = connector_to_dsi(connector); - - if (!dsi->panel) { - dsi->panel = of_drm_find_panel(dsi->panel_node); - if (dsi->panel) - drm_panel_attach(dsi->panel, &dsi->connector); - } else if (!dsi->panel_node) { - struct drm_encoder *encoder; - - encoder = platform_get_drvdata(to_platform_device(dsi->dev)); - exynos_dsi_disable(encoder); - drm_panel_detach(dsi->panel); - dsi->panel = NULL; - } - - if (dsi->panel) - return connector_status_connected; - - return connector_status_disconnected; + return connector->status; } static void exynos_dsi_connector_destroy(struct drm_connector *connector) @@ -1575,6 +1478,7 @@ static int exynos_dsi_create_connector(struct drm_encoder *encoder) return ret; } + connector->status = connector_status_disconnected; drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); drm_mode_connector_attach_encoder(connector, encoder); @@ -1611,6 +1515,105 @@ static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = { MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); +static int exynos_dsi_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct exynos_dsi *dsi = host_to_dsi(host); + struct drm_device *drm = dsi->connector.dev; + + /* + * This is a temporary solution and should be made by more generic way. + * + * If attached panel device is for command mode one, dsi should register + * TE interrupt handler. + */ + if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { + int ret = exynos_dsi_register_te_irq(dsi, &device->dev); + if (ret) + return ret; + } + + mutex_lock(&drm->mode_config.mutex); + + dsi->lanes = device->lanes; + dsi->format = device->format; + dsi->mode_flags = device->mode_flags; + dsi->panel = of_drm_find_panel(device->dev.of_node); + if (dsi->panel) { + drm_panel_attach(dsi->panel, &dsi->connector); + dsi->connector.status = connector_status_connected; + } + exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = + !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); + + mutex_unlock(&drm->mode_config.mutex); + + if (drm->mode_config.poll_enabled) + drm_kms_helper_hotplug_event(drm); + + return 0; +} + +static int exynos_dsi_host_detach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct exynos_dsi *dsi = host_to_dsi(host); + struct drm_device *drm = dsi->connector.dev; + + mutex_lock(&drm->mode_config.mutex); + + if (dsi->panel) { + exynos_dsi_disable(&dsi->encoder); + drm_panel_detach(dsi->panel); + dsi->panel = NULL; + dsi->connector.status = connector_status_disconnected; + } + + mutex_unlock(&drm->mode_config.mutex); + + if (drm->mode_config.poll_enabled) + drm_kms_helper_hotplug_event(drm); + + exynos_dsi_unregister_te_irq(dsi); + + return 0; +} + +static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct exynos_dsi *dsi = host_to_dsi(host); + struct exynos_dsi_transfer xfer; + int ret; + + if (!(dsi->state & DSIM_STATE_ENABLED)) + return -EINVAL; + + if (!(dsi->state & DSIM_STATE_INITIALIZED)) { + ret = exynos_dsi_init(dsi); + if (ret) + return ret; + dsi->state |= DSIM_STATE_INITIALIZED; + } + + ret = mipi_dsi_create_packet(&xfer.packet, msg); + if (ret < 0) + return ret; + + xfer.rx_len = msg->rx_len; + xfer.rx_payload = msg->rx_buf; + xfer.flags = msg->flags; + + ret = exynos_dsi_transfer(dsi, &xfer); + return (ret < 0) ? ret : xfer.rx_done; +} + +static const struct mipi_dsi_host_ops exynos_dsi_ops = { + .attach = exynos_dsi_host_attach, + .detach = exynos_dsi_host_detach, + .transfer = exynos_dsi_host_transfer, +}; + static int exynos_dsi_of_read_u32(const struct device_node *np, const char *propname, u32 *out_value) { @@ -1662,20 +1665,15 @@ static int exynos_dsi_bind(struct device *dev, struct device *master, struct drm_bridge *bridge; int ret; - ret = exynos_drm_crtc_get_pipe_from_type(drm_dev, - EXYNOS_DISPLAY_TYPE_LCD); - if (ret < 0) - return ret; - - encoder->possible_crtcs = 1 << ret; - - DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); - drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); + ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); + if (ret < 0) + return ret; + ret = exynos_dsi_create_connector(encoder); if (ret) { DRM_ERROR("failed to create connector ret = %d\n", ret); diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index 6592f50d460a..8208df56a88f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -225,4 +225,6 @@ void exynos_drm_mode_config_init(struct drm_device *dev) dev->mode_config.funcs = &exynos_drm_mode_config_funcs; dev->mode_config.helper_private = &exynos_drm_mode_config_helpers; + + dev->mode_config.allow_fb_modifiers = true; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c index c3a068409b48..dfb66ecf417b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c @@ -18,6 +18,8 @@ #include <drm/drm_crtc_helper.h> #include <drm/exynos_drm.h> +#include <linux/console.h> + #include "exynos_drm_drv.h" #include "exynos_drm_fb.h" #include "exynos_drm_fbdev.h" @@ -285,3 +287,21 @@ void exynos_drm_output_poll_changed(struct drm_device *dev) drm_fb_helper_hotplug_event(fb_helper); } + +void exynos_drm_fbdev_suspend(struct drm_device *dev) +{ + struct exynos_drm_private *private = dev->dev_private; + + console_lock(); + drm_fb_helper_set_suspend(private->fb_helper, 1); + console_unlock(); +} + +void exynos_drm_fbdev_resume(struct drm_device *dev) +{ + struct exynos_drm_private *private = dev->dev_private; + + console_lock(); + drm_fb_helper_set_suspend(private->fb_helper, 0); + console_unlock(); +} diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h index 330eef87f718..645d1bb7f665 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h @@ -21,6 +21,8 @@ int exynos_drm_fbdev_init(struct drm_device *dev); void exynos_drm_fbdev_fini(struct drm_device *dev); void exynos_drm_fbdev_restore_mode(struct drm_device *dev); void exynos_drm_output_poll_changed(struct drm_device *dev); +void exynos_drm_fbdev_suspend(struct drm_device *drm); +void exynos_drm_fbdev_resume(struct drm_device *drm); #else @@ -39,6 +41,14 @@ static inline void exynos_drm_fbdev_restore_mode(struct drm_device *dev) #define exynos_drm_output_poll_changed (NULL) +static inline void exynos_drm_fbdev_suspend(struct drm_device *drm) +{ +} + +static inline void exynos_drm_fbdev_resume(struct drm_device *drm) +{ +} + #endif #endif diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 60f93cad6643..d42ae2bc3e56 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -583,18 +583,12 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, val |= WINCONx_BURSTLEN_16WORD; break; case DRM_FORMAT_ARGB8888: + default: val |= WINCON1_BPPMODE_25BPP_A1888 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; val |= WINCONx_WSWP; val |= WINCONx_BURSTLEN_16WORD; break; - default: - DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); - - val |= WINCON0_BPPMODE_24BPP_888; - val |= WINCONx_WSWP; - val |= WINCONx_BURSTLEN_16WORD; - break; } /* @@ -718,13 +712,13 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, unsigned long val, size, offset; unsigned int last_x, last_y, buf_offsize, line_size; unsigned int win = plane->index; - unsigned int bpp = fb->format->cpp[0]; + unsigned int cpp = fb->format->cpp[0]; unsigned int pitch = fb->pitches[0]; if (ctx->suspended) return; - offset = state->src.x * bpp; + offset = state->src.x * cpp; offset += state->src.y * pitch; /* buffer start address */ @@ -743,8 +737,8 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, state->crtc.w, state->crtc.h); /* buffer size */ - buf_offsize = pitch - (state->crtc.w * bpp); - line_size = state->crtc.w * bpp; + buf_offsize = pitch - (state->crtc.w * cpp); + line_size = state->crtc.w * cpp; val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c index ab333d5b2727..2174814273e2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_mic.c +++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c @@ -21,9 +21,12 @@ #include <linux/component.h> #include <linux/pm_runtime.h> #include <drm/drmP.h> +#include <drm/drm_encoder.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> +#include "exynos_drm_drv.h" + /* Sysreg registers for MIC */ #define DSD_CFG_MUX 0x1004 #define MIC0_RGB_MUX (1 << 0) @@ -85,12 +88,6 @@ #define MIC_BS_SIZE_2D(x) ((x) & 0x3fff) -enum { - ENDPOINT_DECON_NODE, - ENDPOINT_DSI_NODE, - NUM_ENDPOINTS -}; - static char *clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" }; #define NUM_CLKS ARRAY_SIZE(clk_names) static DEFINE_MUTEX(mic_mutex); @@ -229,36 +226,6 @@ static void mic_set_reg_on(struct exynos_mic *mic, bool enable) writel(reg, mic->reg + MIC_OP); } -static int parse_dt(struct exynos_mic *mic) -{ - int ret = 0, i, j; - struct device_node *remote_node; - struct device_node *nodes[3]; - - /* - * The order of endpoints does matter. - * The first node must be for decon and the second one must be for dsi. - */ - for (i = 0, j = 0; i < NUM_ENDPOINTS; i++) { - remote_node = of_graph_get_remote_node(mic->dev->of_node, i, 0); - if (!remote_node) { - ret = -EPIPE; - goto exit; - } - nodes[j++] = remote_node; - - if (i == ENDPOINT_DECON_NODE && - of_get_child_by_name(remote_node, "i80-if-timings")) - mic->i80_mode = 1; - } - -exit: - while (--j > -1) - of_node_put(nodes[j]); - - return ret; -} - static void mic_disable(struct drm_bridge *bridge) { } static void mic_post_disable(struct drm_bridge *bridge) @@ -286,6 +253,7 @@ static void mic_mode_set(struct drm_bridge *bridge, mutex_lock(&mic_mutex); drm_display_mode_to_videomode(mode, &mic->vm); + mic->i80_mode = to_exynos_crtc(bridge->encoder->crtc)->i80_mode; mutex_unlock(&mic_mutex); } @@ -417,10 +385,6 @@ static int exynos_mic_probe(struct platform_device *pdev) mic->dev = dev; - ret = parse_dt(mic); - if (ret) - goto err; - ret = of_address_to_resource(dev->of_node, 0, &res); if (ret) { DRM_ERROR("mic: Failed to get mem region for MIC\n"); diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 8de74009dee4..d2a90dae5c71 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -179,6 +179,29 @@ static struct drm_plane_funcs exynos_plane_funcs = { }; static int +exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config, + struct exynos_drm_plane_state *state) +{ + struct drm_framebuffer *fb = state->base.fb; + + switch (fb->modifier) { + case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: + if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE)) + return -ENOTSUPP; + break; + + case DRM_FORMAT_MOD_LINEAR: + break; + + default: + DRM_ERROR("unsupported pixel format modifier"); + return -ENOTSUPP; + } + + return 0; +} + +static int exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, struct exynos_drm_plane_state *state) { @@ -222,6 +245,10 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, /* translate state into exynos_state */ exynos_plane_mode_set(exynos_state); + ret = exynos_drm_plane_check_format(exynos_plane->config, exynos_state); + if (ret) + return ret; + ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state); return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 9186a654c3b5..53e03f8af3d5 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -381,7 +381,7 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) struct exynos_drm_plane *exynos_plane; struct exynos_drm_plane_config plane_config = { 0 }; unsigned int i; - int pipe, ret; + int ret; ctx->drm_dev = drm_dev; @@ -406,20 +406,15 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(ctx->crtc); } - pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev, - EXYNOS_DISPLAY_TYPE_VIDI); - if (pipe < 0) - return pipe; - - encoder->possible_crtcs = 1 << pipe; - - DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); - drm_encoder_init(drm_dev, encoder, &exynos_vidi_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); drm_encoder_helper_add(encoder, &exynos_vidi_encoder_helper_funcs); + ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_VIDI); + if (ret < 0) + return ret; + ret = vidi_create_connector(encoder); if (ret) { DRM_ERROR("failed to create connector ret = %d\n", ret); diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index d70eeb8c5f75..0109ff40b1db 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -944,22 +944,27 @@ static bool hdmi_mode_fixup(struct drm_encoder *encoder, struct drm_device *dev = encoder->dev; struct drm_connector *connector; struct drm_display_mode *m; + struct drm_connector_list_iter conn_iter; int mode_ok; drm_mode_set_crtcinfo(adjusted_mode, 0); - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { if (connector->encoder == encoder) break; } + if (connector) + drm_connector_get(connector); + drm_connector_list_iter_end(&conn_iter); - if (connector->encoder != encoder) + if (!connector) return true; mode_ok = hdmi_mode_valid(connector, adjusted_mode); if (mode_ok == MODE_OK) - return true; + goto cleanup; /* * Find the most suitable mode and copy it to adjusted_mode. @@ -979,6 +984,9 @@ static bool hdmi_mode_fixup(struct drm_encoder *encoder, } } +cleanup: + drm_connector_put(connector); + return true; } @@ -1697,32 +1705,25 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct hdmi_context *hdata = dev_get_drvdata(dev); struct drm_encoder *encoder = &hdata->encoder; - struct exynos_drm_crtc *exynos_crtc; - struct drm_crtc *crtc; - int ret, pipe; + struct exynos_drm_crtc *crtc; + int ret; hdata->drm_dev = drm_dev; - pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev, - EXYNOS_DISPLAY_TYPE_HDMI); - if (pipe < 0) - return pipe; - hdata->phy_clk.enable = hdmiphy_clk_enable; - crtc = drm_crtc_from_index(drm_dev, pipe); - exynos_crtc = to_exynos_crtc(crtc); - exynos_crtc->pipe_clk = &hdata->phy_clk; - - encoder->possible_crtcs = 1 << pipe; - - DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); - drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs); + ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_HDMI); + if (ret < 0) + return ret; + + crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI); + crtc->pipe_clk = &hdata->phy_clk; + ret = hdmi_create_connector(encoder); if (ret) { DRM_ERROR("failed to create connector ret = %d\n", ret); diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index a998a8dd783c..002755415e00 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -148,7 +148,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { .pixel_formats = vp_formats, .num_pixel_formats = ARRAY_SIZE(vp_formats), .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | - EXYNOS_DRM_PLANE_CAP_ZPOS, + EXYNOS_DRM_PLANE_CAP_ZPOS | + EXYNOS_DRM_PLANE_CAP_TILE, }, }; @@ -483,29 +484,18 @@ static void vp_video_buffer(struct mixer_context *ctx, unsigned int priority = state->base.normalized_zpos + 1; unsigned long flags; dma_addr_t luma_addr[2], chroma_addr[2]; - bool tiled_mode = false; - bool crcb_mode = false; + bool is_tiled, is_nv21; u32 val; - switch (fb->format->format) { - case DRM_FORMAT_NV12: - crcb_mode = false; - break; - case DRM_FORMAT_NV21: - crcb_mode = true; - break; - default: - DRM_ERROR("pixel format for vp is wrong [%d].\n", - fb->format->format); - return; - } + is_nv21 = (fb->format->format == DRM_FORMAT_NV21); + is_tiled = (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE); luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0); chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1); if (mode->flags & DRM_MODE_FLAG_INTERLACE) { __set_bit(MXR_BIT_INTERLACE, &ctx->flags); - if (tiled_mode) { + if (is_tiled) { luma_addr[1] = luma_addr[0] + 0x40; chroma_addr[1] = chroma_addr[0] + 0x40; } else { @@ -525,14 +515,14 @@ static void vp_video_buffer(struct mixer_context *ctx, vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP); /* setup format */ - val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12); - val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR); + val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12); + val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR); vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK); /* setting size of input image */ vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | VP_IMG_VSIZE(fb->height)); - /* chroma height has to reduced by 2 to avoid chroma distorions */ + /* chroma plane for NV12/NV21 is half the height of the luma plane */ vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) | VP_IMG_VSIZE(fb->height / 2)); @@ -594,7 +584,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, unsigned long flags; unsigned int win = plane->index; unsigned int x_ratio = 0, y_ratio = 0; - unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset; + unsigned int dst_x_offset, dst_y_offset; dma_addr_t dma_addr; unsigned int fmt; u32 val; @@ -616,12 +606,9 @@ static void mixer_graph_buffer(struct mixer_context *ctx, case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + default: fmt = MXR_FORMAT_ARGB8888; break; - - default: - DRM_DEBUG_KMS("pixelformat unsupported by mixer\n"); - return; } /* ratio is already checked by common plane code */ @@ -631,12 +618,10 @@ static void mixer_graph_buffer(struct mixer_context *ctx, dst_x_offset = state->crtc.x; dst_y_offset = state->crtc.y; - /* converting dma address base and source offset */ + /* translate dma address base s.t. the source image offset is zero */ dma_addr = exynos_drm_fb_dma_addr(fb, 0) + (state->src.x * fb->format->cpp[0]) + (state->src.y * fb->pitches[0]); - src_x_offset = 0; - src_y_offset = 0; if (mode->flags & DRM_MODE_FLAG_INTERLACE) __set_bit(MXR_BIT_INTERLACE, &ctx->flags); @@ -667,11 +652,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx, val |= MXR_GRP_WH_V_SCALE(y_ratio); mixer_reg_write(res, MXR_GRAPHIC_WH(win), val); - /* setup offsets in source image */ - val = MXR_GRP_SXY_SX(src_x_offset); - val |= MXR_GRP_SXY_SY(src_y_offset); - mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val); - /* setup offsets in display image */ val = MXR_GRP_DXY_DX(dst_x_offset); val |= MXR_GRP_DXY_DY(dst_y_offset); @@ -748,6 +728,10 @@ static void mixer_win_reset(struct mixer_context *ctx) if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); + /* set all source image offsets to zero */ + mixer_reg_write(res, MXR_GRAPHIC_SXY(0), 0); + mixer_reg_write(res, MXR_GRAPHIC_SXY(1), 0); + spin_unlock_irqrestore(&res->reg_slock, flags); } diff --git a/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c index 771ff66711af..37c997e24b9e 100644 --- a/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c +++ b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c @@ -26,7 +26,7 @@ #include "mdfld_output.h" #include "mdfld_dsi_pkg_sender.h" #include "tc35876x-dsi-lvds.h" -#include <linux/i2c/tc35876x.h> +#include <linux/platform_data/tc35876x.h> #include <linux/kernel.h> #include <linux/module.h> #include <asm/intel_scu_ipc.h> diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index f77dcfaade6c..b4c7af3ab6ae 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -603,6 +603,72 @@ static void dsi_encoder_enable(struct drm_encoder *encoder) dsi->enable = true; } +static enum drm_mode_status dsi_encoder_phy_mode_valid( + struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct dw_dsi *dsi = encoder_to_dsi(encoder); + struct mipi_phy_params phy; + u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + u32 req_kHz, act_kHz, lane_byte_clk_kHz; + + /* Calculate the lane byte clk using the adjusted mode clk */ + memset(&phy, 0, sizeof(phy)); + req_kHz = mode->clock * bpp / dsi->lanes; + act_kHz = dsi_calc_phy_rate(req_kHz, &phy); + lane_byte_clk_kHz = act_kHz / 8; + + DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...", + mode->hdisplay, mode->vdisplay, bpp, + drm_mode_vrefresh(mode), mode->clock); + + /* + * Make sure the adjusted mode clock and the lane byte clk + * have a common denominator base frequency + */ + if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) { + DRM_DEBUG_DRIVER("OK!\n"); + return MODE_OK; + } + + DRM_DEBUG_DRIVER("BAD!\n"); + return MODE_BAD; +} + +static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) + +{ + const struct drm_crtc_helper_funcs *crtc_funcs = NULL; + struct drm_crtc *crtc = NULL; + struct drm_display_mode adj_mode; + enum drm_mode_status ret; + + /* + * The crtc might adjust the mode, so go through the + * possible crtcs (technically just one) and call + * mode_fixup to figure out the adjusted mode before we + * validate it. + */ + drm_for_each_crtc(crtc, encoder->dev) { + /* + * reset adj_mode to the mode value each time, + * so we don't adjust the mode twice + */ + drm_mode_copy(&adj_mode, mode); + + crtc_funcs = crtc->helper_private; + if (crtc_funcs && crtc_funcs->mode_fixup) + if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode)) + return MODE_BAD; + + ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode); + if (ret != MODE_OK) + return ret; + } + return MODE_OK; +} + static void dsi_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -622,6 +688,7 @@ static int dsi_encoder_atomic_check(struct drm_encoder *encoder, static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = { .atomic_check = dsi_encoder_atomic_check, + .mode_valid = dsi_encoder_mode_valid, .mode_set = dsi_encoder_mode_set, .enable = dsi_encoder_enable, .disable = dsi_encoder_disable diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index 39f7d15673ed..9823477b1855 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -178,6 +178,19 @@ static void ade_init(struct ade_hw_ctx *ctx) FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); } +static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + + adjusted_mode->clock = + clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000; + return true; +} + + static void ade_set_pix_clk(struct ade_hw_ctx *ctx, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -555,6 +568,7 @@ static void ade_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { + .mode_fixup = ade_crtc_mode_fixup, .mode_set_nofb = ade_crtc_mode_set_nofb, .atomic_begin = ade_crtc_atomic_begin, .atomic_flush = ade_crtc_atomic_flush, diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 78c5c049a347..aed7d207ea84 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -25,6 +25,7 @@ config DRM_I915_DEBUG select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks) select DRM_DEBUG_MM if DRM=y select DRM_DEBUG_MM_SELFTEST + select SW_SYNC # signaling validation framework (igt/syncobj*) select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST default n diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f8227318dcaf..1cb8059a3a16 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -39,6 +39,7 @@ i915-y += i915_cmd_parser.o \ i915_gem_gtt.o \ i915_gem_internal.o \ i915_gem.o \ + i915_gem_object.o \ i915_gem_render_state.o \ i915_gem_request.o \ i915_gem_shrinker.o \ @@ -149,5 +150,3 @@ endif i915-y += intel_lpe_audio.o obj-$(CONFIG_DRM_I915) += i915.o - -CFLAGS_i915_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c index 325618d969fe..7c9ec4f4f36c 100644 --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c @@ -173,8 +173,8 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu) _clear_vgpu_fence(vgpu); for (i = 0; i < vgpu_fence_sz(vgpu); i++) { reg = vgpu->fence.regs[i]; - list_add_tail(®->link, - &dev_priv->mm.fence_list); + i915_unreserve_fence(reg); + vgpu->fence.regs[i] = NULL; } mutex_unlock(&dev_priv->drm.struct_mutex); @@ -187,24 +187,19 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) struct drm_i915_private *dev_priv = gvt->dev_priv; struct drm_i915_fence_reg *reg; int i; - struct list_head *pos, *q; intel_runtime_pm_get(dev_priv); /* Request fences from host */ mutex_lock(&dev_priv->drm.struct_mutex); - i = 0; - list_for_each_safe(pos, q, &dev_priv->mm.fence_list) { - reg = list_entry(pos, struct drm_i915_fence_reg, link); - if (reg->pin_count || reg->vma) - continue; - list_del(pos); + + for (i = 0; i < vgpu_fence_sz(vgpu); i++) { + reg = i915_reserve_fence(dev_priv); + if (IS_ERR(reg)) + goto out_free_fence; + vgpu->fence.regs[i] = reg; - if (++i == vgpu_fence_sz(vgpu)) - break; } - if (i != vgpu_fence_sz(vgpu)) - goto out_free_fence; _clear_vgpu_fence(vgpu); @@ -212,13 +207,14 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) intel_runtime_pm_put(dev_priv); return 0; out_free_fence: + gvt_vgpu_err("Failed to alloc fences\n"); /* Return fences to host, if fail */ for (i = 0; i < vgpu_fence_sz(vgpu); i++) { reg = vgpu->fence.regs[i]; if (!reg) continue; - list_add_tail(®->link, - &dev_priv->mm.fence_list); + i915_unreserve_fence(reg); + vgpu->fence.regs[i] = NULL; } mutex_unlock(&dev_priv->drm.struct_mutex); intel_runtime_pm_put(dev_priv); @@ -285,8 +281,8 @@ static int alloc_resource(struct intel_vgpu *vgpu, return 0; no_enough_resource: - gvt_vgpu_err("fail to allocate resource %s\n", item); - gvt_vgpu_err("request %luMB avail %luMB max %luMB taken %luMB\n", + gvt_err("fail to allocate resource %s\n", item); + gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n", BYTES_TO_MB(request), BYTES_TO_MB(avail), BYTES_TO_MB(max), BYTES_TO_MB(taken)); return -ENOSPC; diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index 40af17ec6312..ff3154fe6588 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -197,78 +197,65 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - unsigned int bar_index = - (rounddown(offset, 8) % PCI_BASE_ADDRESS_0) / 8; u32 new = *(u32 *)(p_data); bool lo = IS_ALIGNED(offset, 8); u64 size; int ret = 0; bool mmio_enabled = vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; + struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; - if (WARN_ON(bar_index >= INTEL_GVT_PCI_BAR_MAX)) - return -EINVAL; - + /* + * Power-up software can determine how much address + * space the device requires by writing a value of + * all 1's to the register and then reading the value + * back. The device will return 0's in all don't-care + * address bits. + */ if (new == 0xffffffff) { - /* - * Power-up software can determine how much address - * space the device requires by writing a value of - * all 1's to the register and then reading the value - * back. The device will return 0's in all don't-care - * address bits. - */ - size = vgpu->cfg_space.bar[bar_index].size; - if (lo) { - new = rounddown(new, size); - } else { - u32 val = vgpu_cfg_space(vgpu)[rounddown(offset, 8)]; - /* for 32bit mode bar it returns all-0 in upper 32 - * bit, for 64bit mode bar it will calculate the - * size with lower 32bit and return the corresponding - * value + switch (offset) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1); + intel_vgpu_write_pci_bar(vgpu, offset, + size >> (lo ? 0 : 32), lo); + /* + * Untrap the BAR, since guest hasn't configured a + * valid GPA */ - if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) - new &= (~(size-1)) >> 32; - else - new = 0; - } - /* - * Unmapp & untrap the BAR, since guest hasn't configured a - * valid GPA - */ - switch (bar_index) { - case INTEL_GVT_PCI_BAR_GTTMMIO: ret = trap_gttmmio(vgpu, false); break; - case INTEL_GVT_PCI_BAR_APERTURE: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); + intel_vgpu_write_pci_bar(vgpu, offset, + size >> (lo ? 0 : 32), lo); ret = map_aperture(vgpu, false); break; + default: + /* Unimplemented BARs */ + intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false); } - intel_vgpu_write_pci_bar(vgpu, offset, new, lo); } else { - /* - * Unmapp & untrap the old BAR first, since guest has - * re-configured the BAR - */ - switch (bar_index) { - case INTEL_GVT_PCI_BAR_GTTMMIO: - ret = trap_gttmmio(vgpu, false); + switch (offset) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + /* + * Untrap the old BAR first, since guest has + * re-configured the BAR + */ + trap_gttmmio(vgpu, false); + intel_vgpu_write_pci_bar(vgpu, offset, new, lo); + ret = trap_gttmmio(vgpu, mmio_enabled); break; - case INTEL_GVT_PCI_BAR_APERTURE: - ret = map_aperture(vgpu, false); + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + map_aperture(vgpu, false); + intel_vgpu_write_pci_bar(vgpu, offset, new, lo); + ret = map_aperture(vgpu, mmio_enabled); break; - } - intel_vgpu_write_pci_bar(vgpu, offset, new, lo); - /* Track the new BAR */ - if (mmio_enabled) { - switch (bar_index) { - case INTEL_GVT_PCI_BAR_GTTMMIO: - ret = trap_gttmmio(vgpu, true); - break; - case INTEL_GVT_PCI_BAR_APERTURE: - ret = map_aperture(vgpu, true); - break; - } + default: + intel_vgpu_write_pci_bar(vgpu, offset, new, lo); } } return ret; @@ -299,10 +286,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, } switch (rounddown(offset, 4)) { - case PCI_BASE_ADDRESS_0: - case PCI_BASE_ADDRESS_1: - case PCI_BASE_ADDRESS_2: - case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: if (WARN_ON(!IS_ALIGNED(offset, 4))) return -EINVAL; return emulate_pci_bar_write(vgpu, offset, p_data, bytes); @@ -344,7 +328,6 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, struct intel_gvt *gvt = vgpu->gvt; const struct intel_gvt_device_info *info = &gvt->device_info; u16 *gmch_ctl; - int i; memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, info->cfg_space_size); @@ -371,13 +354,13 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, */ memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); + memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8); memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); - for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) { - vgpu->cfg_space.bar[i].size = pci_resource_len( - gvt->dev_priv->drm.pdev, i * 2); - vgpu->cfg_space.bar[i].tracked = false; - } + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = + pci_resource_len(gvt->dev_priv->drm.pdev, 0); + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = + pci_resource_len(gvt->dev_priv->drm.pdev, 2); } /** diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 713848c36349..21c36e256884 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1382,13 +1382,13 @@ static inline int cmd_address_audit(struct parser_exec_state *s, ret = -EINVAL; goto err; } - } else if ((!vgpu_gmadr_is_valid(s->vgpu, guest_gma)) || - (!vgpu_gmadr_is_valid(s->vgpu, - guest_gma + op_size - 1))) { + } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) { ret = -EINVAL; goto err; } + return 0; + err: gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", s->info->name, guest_gma, op_size); @@ -2647,7 +2647,7 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) return 0; } -int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) +int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) { int ret; struct intel_vgpu *vgpu = workload->vgpu; @@ -2714,7 +2714,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) unmap_src: i915_gem_object_unpin_map(obj); put_obj: - i915_gem_object_put(wa_ctx->indirect_ctx.obj); + i915_gem_object_put(obj); return ret; } diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.h b/drivers/gpu/drm/i915/gvt/cmd_parser.h index bed33514103c..286703643002 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.h +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.h @@ -42,7 +42,7 @@ void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt); int intel_gvt_init_cmd_parser(struct intel_gvt *gvt); -int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); +int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload); int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx); diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 7cb0818a13de..3c318439a659 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SDE_PORTE_HOTPLUG_SPT); vgpu_vreg(vgpu, SKL_FUSE_STATUS) |= SKL_FUSE_DOWNLOAD_STATUS | - SKL_FUSE_PG0_DIST_STATUS | - SKL_FUSE_PG1_DIST_STATUS | - SKL_FUSE_PG2_DIST_STATUS; + SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG2); vgpu_vreg(vgpu, LCPLL1_CTL) |= LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index 1648887d3f55..91b4300f3b39 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -622,6 +622,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, struct list_head *q = workload_q_head(vgpu, ring_id); struct intel_vgpu_workload *last_workload = get_last_workload(q); struct intel_vgpu_workload *workload = NULL; + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; u64 ring_context_gpa; u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; int ret; @@ -685,6 +686,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, workload->complete = complete_execlist_workload; workload->status = -EINPROGRESS; workload->emulate_schedule_in = emulate_schedule_in; + workload->shadowed = false; if (ring_id == RCS) { intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + @@ -718,6 +720,17 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, return ret; } + /* Only scan and shadow the first workload in the queue + * as there is only one pre-allocated buf-obj for shadow. + */ + if (list_empty(workload_q_head(vgpu, ring_id))) { + intel_runtime_pm_get(dev_priv); + mutex_lock(&dev_priv->drm.struct_mutex); + intel_gvt_scan_and_shadow_workload(workload); + mutex_unlock(&dev_priv->drm.struct_mutex); + intel_runtime_pm_put(dev_priv); + } + queue_workload(workload); return 0; } @@ -800,6 +813,8 @@ static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask) list_del_init(&pos->list); free_workload(pos); } + + clear_bit(engine->id, vgpu->shadow_ctx_desc_updated); } } diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 6166e34d892b..e6dfc3331f4b 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -259,7 +259,7 @@ static void write_pte64(struct drm_i915_private *dev_priv, writeq(pte, addr); } -static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt, +static inline int gtt_get_entry64(void *pt, struct intel_gvt_gtt_entry *e, unsigned long index, bool hypervisor_access, unsigned long gpa, struct intel_vgpu *vgpu) @@ -268,22 +268,23 @@ static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt, int ret; if (WARN_ON(info->gtt_entry_size != 8)) - return e; + return -EINVAL; if (hypervisor_access) { ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa + (index << info->gtt_entry_size_shift), &e->val64, 8); - WARN_ON(ret); + if (WARN_ON(ret)) + return ret; } else if (!pt) { e->val64 = read_pte64(vgpu->gvt->dev_priv, index); } else { e->val64 = *((u64 *)pt + index); } - return e; + return 0; } -static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt, +static inline int gtt_set_entry64(void *pt, struct intel_gvt_gtt_entry *e, unsigned long index, bool hypervisor_access, unsigned long gpa, struct intel_vgpu *vgpu) @@ -292,19 +293,20 @@ static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt, int ret; if (WARN_ON(info->gtt_entry_size != 8)) - return e; + return -EINVAL; if (hypervisor_access) { ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa + (index << info->gtt_entry_size_shift), &e->val64, 8); - WARN_ON(ret); + if (WARN_ON(ret)) + return ret; } else if (!pt) { write_pte64(vgpu->gvt->dev_priv, index, e->val64); } else { *((u64 *)pt + index) = e->val64; } - return e; + return 0; } #define GTT_HAW 46 @@ -445,21 +447,25 @@ static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p, /* * MM helpers. */ -struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm, +int intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index) { struct intel_gvt *gvt = mm->vgpu->gvt; struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; + int ret; e->type = mm->page_table_entry_type; - ops->get_entry(page_table, e, index, false, 0, mm->vgpu); + ret = ops->get_entry(page_table, e, index, false, 0, mm->vgpu); + if (ret) + return ret; + ops->test_pse(e); - return e; + return 0; } -struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, +int intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index) { @@ -472,7 +478,7 @@ struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, /* * PPGTT shadow page table helpers. */ -static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry( +static inline int ppgtt_spt_get_entry( struct intel_vgpu_ppgtt_spt *spt, void *page_table, int type, struct intel_gvt_gtt_entry *e, unsigned long index, @@ -480,20 +486,24 @@ static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry( { struct intel_gvt *gvt = spt->vgpu->gvt; struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; + int ret; e->type = get_entry_type(type); if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) - return e; + return -EINVAL; - ops->get_entry(page_table, e, index, guest, + ret = ops->get_entry(page_table, e, index, guest, spt->guest_page.gfn << GTT_PAGE_SHIFT, spt->vgpu); + if (ret) + return ret; + ops->test_pse(e); - return e; + return 0; } -static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry( +static inline int ppgtt_spt_set_entry( struct intel_vgpu_ppgtt_spt *spt, void *page_table, int type, struct intel_gvt_gtt_entry *e, unsigned long index, @@ -503,7 +513,7 @@ static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry( struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) - return e; + return -EINVAL; return ops->set_entry(page_table, e, index, guest, spt->guest_page.gfn << GTT_PAGE_SHIFT, @@ -792,13 +802,13 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page( #define for_each_present_guest_entry(spt, e, i) \ for (i = 0; i < pt_entries(spt); i++) \ - if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ - ppgtt_get_guest_entry(spt, e, i))) + if (!ppgtt_get_guest_entry(spt, e, i) && \ + spt->vgpu->gvt->gtt.pte_ops->test_present(e)) #define for_each_present_shadow_entry(spt, e, i) \ for (i = 0; i < pt_entries(spt); i++) \ - if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ - ppgtt_get_shadow_entry(spt, e, i))) + if (!ppgtt_get_shadow_entry(spt, e, i) && \ + spt->vgpu->gvt->gtt.pte_ops->test_present(e)) static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt *spt) { @@ -979,29 +989,26 @@ fail: } static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, - unsigned long index) + struct intel_gvt_gtt_entry *se, unsigned long index) { struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu_shadow_page *sp = &spt->shadow_page; struct intel_vgpu *vgpu = spt->vgpu; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; - struct intel_gvt_gtt_entry e; int ret; - ppgtt_get_shadow_entry(spt, &e, index); - - trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, e.val64, + trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, se->val64, index); - if (!ops->test_present(&e)) + if (!ops->test_present(se)) return 0; - if (ops->get_pfn(&e) == vgpu->gtt.scratch_pt[sp->type].page_mfn) + if (ops->get_pfn(se) == vgpu->gtt.scratch_pt[sp->type].page_mfn) return 0; - if (gtt_type_is_pt(get_next_pt_type(e.type))) { + if (gtt_type_is_pt(get_next_pt_type(se->type))) { struct intel_vgpu_ppgtt_spt *s = - ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e)); + ppgtt_find_shadow_page(vgpu, ops->get_pfn(se)); if (!s) { gvt_vgpu_err("fail to find guest page\n"); ret = -ENXIO; @@ -1011,12 +1018,10 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, if (ret) goto fail; } - ops->set_pfn(&e, vgpu->gtt.scratch_pt[sp->type].page_mfn); - ppgtt_set_shadow_entry(spt, &e, index); return 0; fail: gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", - spt, e.val64, e.type); + spt, se->val64, se->type); return ret; } @@ -1236,22 +1241,37 @@ static int ppgtt_handle_guest_write_page_table( { struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu *vgpu = spt->vgpu; + int type = spt->shadow_page.type; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; + struct intel_gvt_gtt_entry se; int ret; int new_present; new_present = ops->test_present(we); - ret = ppgtt_handle_guest_entry_removal(gpt, index); - if (ret) - goto fail; + /* + * Adding the new entry first and then removing the old one, that can + * guarantee the ppgtt table is validated during the window between + * adding and removal. + */ + ppgtt_get_shadow_entry(spt, &se, index); if (new_present) { ret = ppgtt_handle_guest_entry_add(gpt, we, index); if (ret) goto fail; } + + ret = ppgtt_handle_guest_entry_removal(gpt, &se, index); + if (ret) + goto fail; + + if (!new_present) { + ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn); + ppgtt_set_shadow_entry(spt, &se, index); + } + return 0; fail: gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n", @@ -1323,7 +1343,7 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, struct intel_vgpu *vgpu = spt->vgpu; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; - struct intel_gvt_gtt_entry we; + struct intel_gvt_gtt_entry we, se; unsigned long index; int ret; @@ -1339,7 +1359,8 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, return ret; } else { if (!test_bit(index, spt->post_shadow_bitmap)) { - ret = ppgtt_handle_guest_entry_removal(gpt, index); + ppgtt_get_shadow_entry(spt, &se, index); + ret = ppgtt_handle_guest_entry_removal(gpt, &se, index); if (ret) return ret; } @@ -1713,8 +1734,10 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) if (!vgpu_gmadr_is_valid(vgpu, gma)) goto err; - ggtt_get_guest_entry(mm, &e, - gma_ops->gma_to_ggtt_pte_index(gma)); + ret = ggtt_get_guest_entry(mm, &e, + gma_ops->gma_to_ggtt_pte_index(gma)); + if (ret) + goto err; gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) + (gma & ~GTT_PAGE_MASK); @@ -1724,7 +1747,9 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) switch (mm->page_table_level) { case 4: - ppgtt_get_shadow_root_entry(mm, &e, 0); + ret = ppgtt_get_shadow_root_entry(mm, &e, 0); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pml4_index(gma); gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma); gma_index[2] = gma_ops->gma_to_pde_index(gma); @@ -1732,15 +1757,19 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) index = 4; break; case 3: - ppgtt_get_shadow_root_entry(mm, &e, + ret = ppgtt_get_shadow_root_entry(mm, &e, gma_ops->gma_to_l3_pdp_index(gma)); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pde_index(gma); gma_index[1] = gma_ops->gma_to_pte_index(gma); index = 2; break; case 2: - ppgtt_get_shadow_root_entry(mm, &e, + ret = ppgtt_get_shadow_root_entry(mm, &e, gma_ops->gma_to_pde_index(gma)); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pte_index(gma); index = 1; break; @@ -1755,6 +1784,11 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) (i == index - 1)); if (ret) goto err; + + if (!pte_ops->test_present(&e)) { + gvt_dbg_core("GMA 0x%lx is not present\n", gma); + goto err; + } } gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) @@ -2329,13 +2363,12 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) /** * intel_vgpu_reset_gtt - reset the all GTT related status * @vgpu: a vGPU - * @dmlr: true for vGPU Device Model Level Reset, false for GT Reset * * This function is called from vfio core to reset reset all * GTT related status, including GGTT, PPGTT, scratch page. * */ -void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) +void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu) { int i; @@ -2347,9 +2380,6 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) */ intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_PPGTT); - if (!dmlr) - return; - intel_vgpu_reset_ggtt(vgpu); /* clear scratch page for security */ diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index f88eb5e89bea..30a4c8d16026 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -49,14 +49,18 @@ struct intel_gvt_gtt_entry { }; struct intel_gvt_gtt_pte_ops { - struct intel_gvt_gtt_entry *(*get_entry)(void *pt, - struct intel_gvt_gtt_entry *e, - unsigned long index, bool hypervisor_access, unsigned long gpa, - struct intel_vgpu *vgpu); - struct intel_gvt_gtt_entry *(*set_entry)(void *pt, - struct intel_gvt_gtt_entry *e, - unsigned long index, bool hypervisor_access, unsigned long gpa, - struct intel_vgpu *vgpu); + int (*get_entry)(void *pt, + struct intel_gvt_gtt_entry *e, + unsigned long index, + bool hypervisor_access, + unsigned long gpa, + struct intel_vgpu *vgpu); + int (*set_entry)(void *pt, + struct intel_gvt_gtt_entry *e, + unsigned long index, + bool hypervisor_access, + unsigned long gpa, + struct intel_vgpu *vgpu); bool (*test_present)(struct intel_gvt_gtt_entry *e); void (*clear_present)(struct intel_gvt_gtt_entry *e); bool (*test_pse)(struct intel_gvt_gtt_entry *e); @@ -143,12 +147,12 @@ struct intel_vgpu_mm { struct intel_vgpu *vgpu; }; -extern struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry( +extern int intel_vgpu_mm_get_entry( struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index); -extern struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry( +extern int intel_vgpu_mm_set_entry( struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index); @@ -208,7 +212,7 @@ extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu); extern int intel_gvt_init_gtt(struct intel_gvt *gvt); -extern void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr); +void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); extern void intel_gvt_clean_gtt(struct intel_gvt *gvt); extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 2964a4d01a66..44b719eda8c4 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -167,6 +167,7 @@ struct intel_vgpu { atomic_t running_workload_num; DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); struct i915_gem_context *shadow_ctx; + DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) struct { @@ -482,6 +483,8 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); void populate_pvinfo_page(struct intel_vgpu *vgpu); +int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); + struct intel_gvt_ops { int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, unsigned int); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index feed9921b3b3..2294466dd415 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -113,9 +113,17 @@ static int new_mmio_info(struct intel_gvt *gvt, info->offset = i; p = find_mmio_info(gvt, info->offset); - if (p) - gvt_err("dup mmio definition offset %x\n", + if (p) { + WARN(1, "dup mmio definition offset %x\n", info->offset); + kfree(info); + + /* We return -EEXIST here to make GVT-g load fail. + * So duplicated MMIO can be found as soon as + * possible. + */ + return -EEXIST; + } info->ro_mask = ro_mask; info->device = device; @@ -1222,10 +1230,12 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, { write_vreg(vgpu, offset, p_data, bytes); - if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) - vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; + if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) + vgpu_vreg(vgpu, offset) |= + HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); else - vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; + vgpu_vreg(vgpu, offset) &= + ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); return 0; } @@ -2242,10 +2252,17 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); MMIO_D(GEN6_PMINTRMSK, D_ALL); - MMIO_DH(HSW_PWR_WELL_BIOS, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_DRIVER, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_DEBUG, D_BDW, NULL, power_well_ctl_mmio_write); + /* + * Use an arbitrary power well controlled by the PWR_WELL_CTL + * register. + */ + MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); @@ -2581,7 +2598,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, force_nonpriv_write); - MMIO_D(0x22040, D_BDW_PLUS); MMIO_D(0x44484, D_BDW_PLUS); MMIO_D(0x4448c, D_BDW_PLUS); @@ -2636,10 +2652,13 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, dp_aux_ch_ctl_mmio_write); - MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS); - MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL, - skl_power_well_ctl_write); - MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write); + /* + * Use an arbitrary power well controlled by the PWR_WELL_CTL + * register. + */ + MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); + MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, + skl_power_well_ctl_write); MMIO_D(0xa210, D_SKL_PLUS); MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); @@ -2831,7 +2850,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(0x320f0, D_SKL | D_KBL); MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); - MMIO_DFH(_REG_VECS_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); MMIO_D(0x70034, D_SKL_PLUS); MMIO_D(0x71034, D_SKL_PLUS); MMIO_D(0x72034, D_SKL_PLUS); @@ -2849,10 +2867,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) NULL, NULL); MMIO_D(0x4ab8, D_KBL); - MMIO_D(0x940c, D_SKL_PLUS); MMIO_D(0x2248, D_SKL_PLUS | D_KBL); - MMIO_D(0x4ab0, D_SKL | D_KBL); - MMIO_D(0x20d4, D_SKL | D_KBL); return 0; } diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index fd0c85f9ef3c..83e88c70272a 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -1170,10 +1170,27 @@ vgpu_id_show(struct device *dev, struct device_attribute *attr, return sprintf(buf, "\n"); } +static ssize_t +hw_id_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mdev_device *mdev = mdev_from_dev(dev); + + if (mdev) { + struct intel_vgpu *vgpu = (struct intel_vgpu *) + mdev_get_drvdata(mdev); + return sprintf(buf, "%u\n", + vgpu->shadow_ctx->hw_id); + } + return sprintf(buf, "\n"); +} + static DEVICE_ATTR_RO(vgpu_id); +static DEVICE_ATTR_RO(hw_id); static struct attribute *intel_vgpu_attrs[] = { &dev_attr_vgpu_id.attr, + &dev_attr_hw_id.attr, NULL }; diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 504e57c3bc23..2ea542257f03 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -207,18 +207,16 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { - gen9_render_mocs[ring_id][i] = I915_READ(offset); + gen9_render_mocs[ring_id][i] = I915_READ_FW(offset); I915_WRITE(offset, vgpu_vreg(vgpu, offset)); - POSTING_READ(offset); offset.reg += 4; } if (ring_id == RCS) { l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { - gen9_render_mocs_L3[i] = I915_READ(l3_offset); - I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset)); - POSTING_READ(l3_offset); + gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset); + I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset)); l3_offset.reg += 4; } } @@ -242,18 +240,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { - vgpu_vreg(vgpu, offset) = I915_READ(offset); - I915_WRITE(offset, gen9_render_mocs[ring_id][i]); - POSTING_READ(offset); + vgpu_vreg(vgpu, offset) = I915_READ_FW(offset); + I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]); offset.reg += 4; } if (ring_id == RCS) { l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { - vgpu_vreg(vgpu, l3_offset) = I915_READ(l3_offset); - I915_WRITE(l3_offset, gen9_render_mocs_L3[i]); - POSTING_READ(l3_offset); + vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset); + I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]); l3_offset.reg += 4; } } @@ -272,6 +268,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL]; u32 inhibit_mask = _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); + i915_reg_t last_reg = _MMIO(0); if (IS_SKYLAKE(vgpu->gvt->dev_priv) || IS_KABYLAKE(vgpu->gvt->dev_priv)) { @@ -287,7 +284,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) if (mmio->ring_id != ring_id) continue; - mmio->value = I915_READ(mmio->reg); + mmio->value = I915_READ_FW(mmio->reg); /* * if it is an inhibit context, load in_context mmio @@ -304,13 +301,18 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) else v = vgpu_vreg(vgpu, mmio->reg); - I915_WRITE(mmio->reg, v); - POSTING_READ(mmio->reg); + I915_WRITE_FW(mmio->reg, v); + last_reg = mmio->reg; trace_render_mmio(vgpu->id, "load", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } + + /* Make sure the swiched MMIOs has taken effect. */ + if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + I915_READ_FW(last_reg); + handle_tlb_pending_event(vgpu, ring_id); } @@ -319,6 +321,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; struct render_mmio *mmio; + i915_reg_t last_reg = _MMIO(0); u32 v; int i, array_size; @@ -335,7 +338,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) if (mmio->ring_id != ring_id) continue; - vgpu_vreg(vgpu, mmio->reg) = I915_READ(mmio->reg); + vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg); if (mmio->mask) { vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16); @@ -346,13 +349,17 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) if (mmio->in_context) continue; - I915_WRITE(mmio->reg, v); - POSTING_READ(mmio->reg); + I915_WRITE_FW(mmio->reg, v); + last_reg = mmio->reg; trace_render_mmio(vgpu->id, "restore", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } + + /* Make sure the swiched MMIOs has taken effect. */ + if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + I915_READ_FW(last_reg); } /** @@ -367,12 +374,23 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) void intel_gvt_switch_mmio(struct intel_vgpu *pre, struct intel_vgpu *next, int ring_id) { + struct drm_i915_private *dev_priv; + if (WARN_ON(!pre && !next)) return; gvt_dbg_render("switch ring %d from %s to %s\n", ring_id, pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); + dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; + + /** + * We are using raw mmio access wrapper to improve the + * performace for batch mmio read/write, so we need + * handle forcewake mannually. + */ + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + /** * TODO: Optimize for vGPU to vGPU switch by merging * switch_mmio_to_host() and switch_mmio_to_vgpu(). @@ -382,4 +400,6 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, if (next) switch_mmio_to_vgpu(next, ring_id); + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index c873136add97..391800d2067b 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -184,41 +184,52 @@ static int shadow_context_status_change(struct notifier_block *nb, return NOTIFY_OK; } -static int dispatch_workload(struct intel_vgpu_workload *workload) +static void shadow_context_descriptor_update(struct i915_gem_context *ctx, + struct intel_engine_cs *engine) +{ + struct intel_context *ce = &ctx->engine[engine->id]; + u64 desc = 0; + + desc = ce->lrc_desc; + + /* Update bits 0-11 of the context descriptor which includes flags + * like GEN8_CTX_* cached in desc_template + */ + desc &= U64_MAX << 12; + desc |= ctx->desc_template & ((1ULL << 12) - 1); + + ce->lrc_desc = desc; +} + +/** + * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and + * shadow it as well, include ringbuffer,wa_ctx and ctx. + * @workload: an abstract entity for each execlist submission. + * + * This function is called before the workload submitting to i915, to make + * sure the content of the workload is valid. + */ +int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) { int ring_id = workload->ring_id; struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; - struct intel_engine_cs *engine = dev_priv->engine[ring_id]; struct drm_i915_gem_request *rq; struct intel_vgpu *vgpu = workload->vgpu; - struct intel_ring *ring; int ret; - gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", - ring_id, workload); + lockdep_assert_held(&dev_priv->drm.struct_mutex); + + if (workload->shadowed) + return 0; shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; - mutex_lock(&dev_priv->drm.struct_mutex); - - /* pin shadow context by gvt even the shadow context will be pinned - * when i915 alloc request. That is because gvt will update the guest - * context from shadow context when workload is completed, and at that - * moment, i915 may already unpined the shadow context to make the - * shadow_ctx pages invalid. So gvt need to pin itself. After update - * the guest context, gvt can unpin the shadow_ctx safely. - */ - ring = engine->context_pin(engine, shadow_ctx); - if (IS_ERR(ring)) { - ret = PTR_ERR(ring); - gvt_vgpu_err("fail to pin shadow context\n"); - workload->status = ret; - mutex_unlock(&dev_priv->drm.struct_mutex); - return ret; - } + if (!test_and_set_bit(ring_id, vgpu->shadow_ctx_desc_updated)) + shadow_context_descriptor_update(shadow_ctx, + dev_priv->engine[ring_id]); rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); if (IS_ERR(rq)) { @@ -231,7 +242,7 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) workload->req = i915_gem_request_get(rq); - ret = intel_gvt_scan_and_shadow_workload(workload); + ret = intel_gvt_scan_and_shadow_ringbuffer(workload); if (ret) goto out; @@ -246,25 +257,61 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) if (ret) goto out; + workload->shadowed = true; + +out: + return ret; +} + +static int dispatch_workload(struct intel_vgpu_workload *workload) +{ + int ring_id = workload->ring_id; + struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; + struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; + struct intel_engine_cs *engine = dev_priv->engine[ring_id]; + struct intel_vgpu *vgpu = workload->vgpu; + struct intel_ring *ring; + int ret = 0; + + gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", + ring_id, workload); + + mutex_lock(&dev_priv->drm.struct_mutex); + + ret = intel_gvt_scan_and_shadow_workload(workload); + if (ret) + goto out; + if (workload->prepare) { ret = workload->prepare(workload); if (ret) goto out; } - gvt_dbg_sched("ring id %d submit workload to i915 %p\n", - ring_id, workload->req); + /* pin shadow context by gvt even the shadow context will be pinned + * when i915 alloc request. That is because gvt will update the guest + * context from shadow context when workload is completed, and at that + * moment, i915 may already unpined the shadow context to make the + * shadow_ctx pages invalid. So gvt need to pin itself. After update + * the guest context, gvt can unpin the shadow_ctx safely. + */ + ring = engine->context_pin(engine, shadow_ctx); + if (IS_ERR(ring)) { + ret = PTR_ERR(ring); + gvt_vgpu_err("fail to pin shadow context\n"); + goto out; + } - ret = 0; - workload->dispatched = true; out: if (ret) workload->status = ret; - if (!IS_ERR_OR_NULL(rq)) - i915_add_request(rq); - else - engine->context_unpin(engine, shadow_ctx); + if (!IS_ERR_OR_NULL(workload->req)) { + gvt_dbg_sched("ring id %d submit workload to i915 %p\n", + ring_id, workload->req); + i915_add_request(workload->req); + workload->dispatched = true; + } mutex_unlock(&dev_priv->drm.struct_mutex); return ret; @@ -631,5 +678,7 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu) vgpu->shadow_ctx->engine[RCS].initialised = true; + bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES); + return 0; } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h index 9b6bf51e9b9b..0d431a968a32 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.h +++ b/drivers/gpu/drm/i915/gvt/scheduler.h @@ -82,6 +82,7 @@ struct intel_vgpu_workload { struct drm_i915_gem_request *req; /* if this workload has been dispatched to i915? */ bool dispatched; + bool shadowed; int status; struct intel_vgpu_mm *shadow_mm; diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 3deadcbd5a24..02c61a1ad56a 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -43,6 +43,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0; vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0; vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id; + vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT; vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = vgpu_aperture_gmadr_base(vgpu); vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = @@ -504,11 +505,11 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, /* full GPU reset or device model level reset */ if (engine_mask == ALL_ENGINES || dmlr) { - intel_vgpu_reset_gtt(vgpu, dmlr); - /*fence will not be reset during virtual reset */ - if (dmlr) + if (dmlr) { + intel_vgpu_reset_gtt(vgpu); intel_vgpu_reset_resource(vgpu); + } intel_vgpu_reset_mmio(vgpu, dmlr); populate_pvinfo_page(vgpu); diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index f0cb22cc0dd6..8ba932b22f7c 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -1073,7 +1073,7 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, goto unpin_src; } - dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB); + dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB); if (IS_ERR(dst)) goto unpin_dst; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2ef75c1a6119..e4d4b6b41e26 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -28,6 +28,7 @@ #include <linux/debugfs.h> #include <linux/sort.h> +#include <linux/sched/mm.h> #include "intel_drv.h" static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) @@ -543,75 +544,6 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data) return 0; } -static int i915_gem_pageflip_info(struct seq_file *m, void *data) -{ - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc; - int ret; - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - for_each_intel_crtc(dev, crtc) { - const char pipe = pipe_name(crtc->pipe); - const char plane = plane_name(crtc->plane); - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = crtc->flip_work; - if (work == NULL) { - seq_printf(m, "No flip due on pipe %c (plane %c)\n", - pipe, plane); - } else { - u32 pending; - u32 addr; - - pending = atomic_read(&work->pending); - if (pending) { - seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", - pipe, plane); - } else { - seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", - pipe, plane); - } - if (work->flip_queued_req) { - struct intel_engine_cs *engine = work->flip_queued_req->engine; - - seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", - engine->name, - work->flip_queued_req->global_seqno, - intel_engine_last_submit(engine), - intel_engine_get_seqno(engine), - i915_gem_request_completed(work->flip_queued_req)); - } else - seq_printf(m, "Flip not associated with any ring\n"); - seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", - work->flip_queued_vblank, - work->flip_ready_vblank, - intel_crtc_get_vblank_counter(crtc)); - seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); - - if (INTEL_GEN(dev_priv) >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); - else - addr = I915_READ(DSPADDR(crtc->plane)); - seq_printf(m, "Current scanout address 0x%08x\n", addr); - - if (work->pending_flip_obj) { - seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); - seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); - } - } - spin_unlock_irq(&dev->event_lock); - } - - mutex_unlock(&dev->struct_mutex); - - return 0; -} - static int i915_gem_batch_pool_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -2023,12 +1955,6 @@ static int i915_context_status(struct seq_file *m, void *unused) seq_putc(m, '\n'); } - seq_printf(m, - "\tvma hashtable size=%u (actual %lu), count=%u\n", - ctx->vma_lut.ht_size, - BIT(ctx->vma_lut.ht_bits), - ctx->vma_lut.ht_count); - seq_putc(m, '\n'); } @@ -2852,7 +2778,7 @@ out: static int i915_energy_uJ(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - u64 power; + unsigned long long power; u32 units; if (INTEL_GEN(dev_priv) < 6) @@ -2860,15 +2786,18 @@ static int i915_energy_uJ(struct seq_file *m, void *data) intel_runtime_pm_get(dev_priv); - rdmsrl(MSR_RAPL_POWER_UNIT, power); - power = (power & 0x1f00) >> 8; - units = 1000000 / (1 << power); /* convert to uJ */ + if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { + intel_runtime_pm_put(dev_priv); + return -ENODEV; + } + + units = (power & 0x1f00) >> 8; power = I915_READ(MCH_SECP_NRG_STTS); - power *= units; + power = (1000000 * power) >> units; /* convert to uJ */ intel_runtime_pm_put(dev_priv); - seq_printf(m, "%llu", (long long unsigned)power); + seq_printf(m, "%llu", power); return 0; } @@ -3394,8 +3323,10 @@ static int i915_engine_info(struct seq_file *m, void *unused) ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); read = GEN8_CSB_READ_PTR(ptr); write = GEN8_CSB_WRITE_PTR(ptr); - seq_printf(m, "\tExeclist CSB read %d, write %d\n", - read, write); + seq_printf(m, "\tExeclist CSB read %d, write %d, interrupt posted? %s\n", + read, write, + yesno(test_bit(ENGINE_IRQ_EXECLIST, + &engine->irq_posted))); if (read >= GEN8_CSB_ENTRIES) read = 0; if (write >= GEN8_CSB_ENTRIES) @@ -4375,16 +4306,16 @@ i915_drop_caches_set(void *data, u64 val) mutex_unlock(&dev->struct_mutex); } - lockdep_set_current_reclaim_state(GFP_KERNEL); + fs_reclaim_acquire(GFP_KERNEL); if (val & DROP_BOUND) - i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); + i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND); if (val & DROP_UNBOUND) - i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); + i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND); if (val & DROP_SHRINK_ALL) i915_gem_shrink_all(dev_priv); - lockdep_clear_current_reclaim_state(); + fs_reclaim_release(GFP_KERNEL); if (val & DROP_FREED) { synchronize_rcu(); @@ -4624,7 +4555,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); - if (IS_GEN9_BC(dev_priv)) + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; @@ -4854,7 +4785,6 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_gem_gtt", i915_gem_gtt_info, 0}, {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, {"i915_gem_stolen", i915_gem_stolen_list_info }, - {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, {"i915_gem_request", i915_gem_request_info, 0}, {"i915_gem_seqno", i915_gem_seqno_info, 0}, {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4c96a7214482..ff70fc45ba7c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -237,17 +237,18 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv) !IS_KABYLAKE(dev_priv)); } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_KBP; - DRM_DEBUG_KMS("Found KabyPoint PCH\n"); + DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n"); WARN_ON(!IS_SKYLAKE(dev_priv) && - !IS_KABYLAKE(dev_priv)); + !IS_KABYLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv)); } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_CNP; - DRM_DEBUG_KMS("Found CannonPoint PCH\n"); + DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n"); WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_CNP; - DRM_DEBUG_KMS("Found CannonPoint LP PCH\n"); + DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n"); WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || @@ -388,6 +389,7 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_EXEC_FENCE: case I915_PARAM_HAS_EXEC_CAPTURE: case I915_PARAM_HAS_EXEC_BATCH_FIRST: + case I915_PARAM_HAS_EXEC_FENCE_ARRAY: /* For the time being all of these are always true; * if some supported hardware does not have one of these * features this value needs to be provided from @@ -596,7 +598,8 @@ static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { static void i915_gem_fini(struct drm_i915_private *dev_priv) { - flush_workqueue(dev_priv->wq); + /* Flush any outstanding unpin_work. */ + i915_gem_drain_workqueue(dev_priv); mutex_lock(&dev_priv->drm.struct_mutex); intel_uc_fini_hw(dev_priv); @@ -875,7 +878,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, spin_lock_init(&dev_priv->uncore.lock); spin_lock_init(&dev_priv->mm.object_stat_lock); - spin_lock_init(&dev_priv->mmio_flip_lock); mutex_init(&dev_priv->sb_lock); mutex_init(&dev_priv->modeset_restore_lock); mutex_init(&dev_priv->av_mutex); @@ -1240,6 +1242,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) */ static void i915_driver_unregister(struct drm_i915_private *dev_priv) { + intel_fbdev_unregister(dev_priv); intel_audio_deinit(dev_priv); intel_gpu_ips_teardown(); @@ -1371,7 +1374,7 @@ void i915_driver_unload(struct drm_device *dev) struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; - intel_fbdev_fini(dev); + i915_driver_unregister(dev_priv); if (i915_gem_suspend(dev_priv)) DRM_ERROR("failed to idle hardware; continuing to unload!\n"); @@ -1382,8 +1385,6 @@ void i915_driver_unload(struct drm_device *dev) intel_gvt_cleanup(dev_priv); - i915_driver_unregister(dev_priv); - intel_modeset_cleanup(dev); /* @@ -1409,9 +1410,6 @@ void i915_driver_unload(struct drm_device *dev) cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); i915_reset_error_state(dev_priv); - /* Flush any outstanding unpin_work. */ - drain_workqueue(dev_priv->wq); - i915_gem_fini(dev_priv); intel_uc_fini_fw(dev_priv); intel_fbc_cleanup_cfb(dev_priv); @@ -1835,7 +1833,8 @@ static int i915_resume_switcheroo(struct drm_device *dev) /** * i915_reset - reset chip after a hang - * @dev_priv: device private to reset + * @i915: #drm_i915_private to reset + * @flags: Instructions * * Reset the chip. Useful if a hang is detected. Marks the device as wedged * on failure. @@ -1850,33 +1849,34 @@ static int i915_resume_switcheroo(struct drm_device *dev) * - re-init interrupt state * - re-init display */ -void i915_reset(struct drm_i915_private *dev_priv) +void i915_reset(struct drm_i915_private *i915, unsigned int flags) { - struct i915_gpu_error *error = &dev_priv->gpu_error; + struct i915_gpu_error *error = &i915->gpu_error; int ret; - lockdep_assert_held(&dev_priv->drm.struct_mutex); + lockdep_assert_held(&i915->drm.struct_mutex); GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags)); if (!test_bit(I915_RESET_HANDOFF, &error->flags)) return; /* Clear any previous failed attempts at recovery. Time to try again. */ - if (!i915_gem_unset_wedged(dev_priv)) + if (!i915_gem_unset_wedged(i915)) goto wakeup; + if (!(flags & I915_RESET_QUIET)) + dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n"); error->reset_count++; - pr_notice("drm/i915: Resetting chip after gpu hang\n"); - disable_irq(dev_priv->drm.irq); - ret = i915_gem_reset_prepare(dev_priv); + disable_irq(i915->drm.irq); + ret = i915_gem_reset_prepare(i915); if (ret) { DRM_ERROR("GPU recovery failed\n"); - intel_gpu_reset(dev_priv, ALL_ENGINES); + intel_gpu_reset(i915, ALL_ENGINES); goto error; } - ret = intel_gpu_reset(dev_priv, ALL_ENGINES); + ret = intel_gpu_reset(i915, ALL_ENGINES); if (ret) { if (ret != -ENODEV) DRM_ERROR("Failed to reset chip: %i\n", ret); @@ -1885,16 +1885,22 @@ void i915_reset(struct drm_i915_private *dev_priv) goto error; } - i915_gem_reset(dev_priv); - intel_overlay_reset(dev_priv); + i915_gem_reset(i915); + intel_overlay_reset(i915); /* Ok, now get things going again... */ /* * Everything depends on having the GTT running, so we need to start - * there. Fortunately we don't need to do this unless we reset the - * chip at a PCI level. - * + * there. + */ + ret = i915_ggtt_enable_hw(i915); + if (ret) { + DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret); + goto error; + } + + /* * Next we need to restore the context, but we don't use those * yet either... * @@ -1902,17 +1908,17 @@ void i915_reset(struct drm_i915_private *dev_priv) * was running at the time of the reset (i.e. we weren't VT * switched away). */ - ret = i915_gem_init_hw(dev_priv); + ret = i915_gem_init_hw(i915); if (ret) { DRM_ERROR("Failed hw init on reset %d\n", ret); goto error; } - i915_queue_hangcheck(dev_priv); + i915_queue_hangcheck(i915); finish: - i915_gem_reset_finish(dev_priv); - enable_irq(dev_priv->drm.irq); + i915_gem_reset_finish(i915); + enable_irq(i915->drm.irq); wakeup: clear_bit(I915_RESET_HANDOFF, &error->flags); @@ -1920,14 +1926,15 @@ wakeup: return; error: - i915_gem_set_wedged(dev_priv); - i915_gem_retire_requests(dev_priv); + i915_gem_set_wedged(i915); + i915_gem_retire_requests(i915); goto finish; } /** * i915_reset_engine - reset GPU engine to recover from a hang * @engine: engine to reset + * @flags: options * * Reset a specific GPU engine. Useful if a hang is detected. * Returns zero on successful reset or otherwise an error code. @@ -1937,7 +1944,7 @@ error: * - reset engine (which will force the engine to idle) * - re-init/configure engine */ -int i915_reset_engine(struct intel_engine_cs *engine) +int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags) { struct i915_gpu_error *error = &engine->i915->gpu_error; struct drm_i915_gem_request *active_request; @@ -1945,7 +1952,11 @@ int i915_reset_engine(struct intel_engine_cs *engine) GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); - DRM_DEBUG_DRIVER("resetting %s\n", engine->name); + if (!(flags & I915_RESET_QUIET)) { + dev_notice(engine->i915->drm.dev, + "Resetting %s after gpu hang\n", engine->name); + } + error->reset_engine_count[engine->id]++; active_request = i915_gem_reset_prepare_engine(engine); if (IS_ERR(active_request)) { @@ -1954,18 +1965,7 @@ int i915_reset_engine(struct intel_engine_cs *engine) goto out; } - /* - * The request that caused the hang is stuck on elsp, we know the - * active request and can drop it, adjust head to skip the offending - * request to resume executing remaining requests in the queue. - */ - i915_gem_reset_engine(engine, active_request); - - /* Finally, reset just this engine. */ ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine)); - - i915_gem_reset_finish_engine(engine); - if (ret) { /* If we fail here, we expect to fallback to a global reset */ DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n", @@ -1974,6 +1974,13 @@ int i915_reset_engine(struct intel_engine_cs *engine) } /* + * The request that caused the hang is stuck on elsp, we know the + * active request and can drop it, adjust head to skip the offending + * request to resume executing remaining requests in the queue. + */ + i915_gem_reset_engine(engine, active_request); + + /* * The engine and its registers (and workarounds in case of render) * have been reset to their default values. Follow the init_ring * process to program RING_MODE, HWSP and re-enable submission. @@ -1982,8 +1989,8 @@ int i915_reset_engine(struct intel_engine_cs *engine) if (ret) goto out; - error->reset_engine_count[engine->id]++; out: + i915_gem_reset_finish_engine(engine); return ret; } @@ -2730,6 +2737,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), }; static struct drm_driver driver = { @@ -2738,7 +2747,7 @@ static struct drm_driver driver = { */ .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | - DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC, + DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ, .release = i915_driver_release, .open = i915_driver_open, .lastclose = i915_driver_lastclose, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6b4771adb8ba..b1fa81348ee9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -80,8 +80,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20170717" -#define DRIVER_TIMESTAMP 1500275179 +#define DRIVER_DATE "20170907" +#define DRIVER_TIMESTAMP 1504772900 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and * WARN_ON()) for hw state sanity checks to check for unexpected conditions @@ -569,6 +569,24 @@ struct i915_hotplug { (__i)++) \ for_each_if (plane_state) +#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->base.dev->mode_config.num_crtc && \ + ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ + (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ + (__i)++) \ + for_each_if (crtc) + + +#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->base.dev->mode_config.num_total_plane && \ + ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ + (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ + (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ + (__i)++) \ + for_each_if (plane) + struct drm_i915_private; struct i915_mm_struct; struct i915_mmu_object; @@ -602,7 +620,7 @@ struct drm_i915_file_private { * to limit the badly behaving clients access to gpu. */ #define I915_MAX_CLIENT_CONTEXT_BANS 3 - int context_bans; + atomic_t context_bans; }; /* Used by dp and fdi links */ @@ -646,6 +664,7 @@ struct intel_opregion { u32 swsci_sbcb_sub_functions; struct opregion_asle *asle; void *rvda; + void *vbt_firmware; const void *vbt; u32 vbt_size; u32 *lid_state; @@ -714,11 +733,6 @@ struct drm_i915_display_funcs { void (*fdi_link_train)(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); void (*init_clock_gating)(struct drm_i915_private *dev_priv); - int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags); void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); /* clock updates for mode set */ /* cursor updates */ @@ -845,6 +859,7 @@ struct intel_device_info { u8 gen; u16 gen_mask; enum intel_platform platform; + u8 gt; /* GT number, 0 if undefined */ u8 ring_mask; /* Rings supported by the HW */ u8 num_rings; #define DEFINE_FLAG(name) u8 name:1 @@ -1062,6 +1077,11 @@ struct intel_fbc { bool underrun_detected; struct work_struct underrun_work; + /* + * Due to the atomic rules we can't access some structures without the + * appropriate locking, so we cache information here in order to avoid + * these problems. + */ struct intel_fbc_state_cache { struct i915_vma *vma; @@ -1083,6 +1103,13 @@ struct intel_fbc { } fb; } state_cache; + /* + * This structure contains everything that's relevant to program the + * hardware registers. When we want to figure out if we need to disable + * and re-enable FBC for a new configuration we just check if there's + * something different in the struct. The genx_fbc_activate functions + * are supposed to read from it in order to program the registers. + */ struct intel_fbc_reg_params { struct i915_vma *vma; @@ -1098,6 +1125,7 @@ struct intel_fbc { } fb; int cfb_size; + unsigned int gen9_wa_cfb_stride; } params; struct intel_fbc_work { @@ -1158,8 +1186,8 @@ enum intel_pch { PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ PCH_SPT, /* Sunrisepoint PCH */ - PCH_KBP, /* Kabypoint PCH */ - PCH_CNP, /* Cannonpoint PCH */ + PCH_KBP, /* Kaby Lake PCH */ + PCH_CNP, /* Cannon Lake PCH */ PCH_NOP, }; @@ -1387,12 +1415,23 @@ struct i915_power_well { bool hw_enabled; u64 domains; /* unique identifier for this power well */ - unsigned long id; + enum i915_power_well_id id; /* * Arbitraty data associated with this power well. Platform and power * well specific. */ - unsigned long data; + union { + struct { + enum dpio_phy phy; + } bxt; + struct { + /* Mask of pipes whose IRQ logic is backed by the pw */ + u8 irq_pipe_mask; + /* The pw is backing the VGA functionality */ + bool has_vga:1; + bool has_fuses:1; + } hsw; + }; const struct i915_power_well_ops *ops; }; @@ -1445,6 +1484,11 @@ struct i915_gem_mm { struct llist_head free_list; struct work_struct free_work; + /** + * Small stash of WC pages + */ + struct pagevec wc_stash; + /** Usable portion of the GTT for GEM */ dma_addr_t stolen_base; /* limited to low memory (32-bit) */ @@ -1509,6 +1553,8 @@ struct i915_gpu_error { /* Protected by the above dev->gpu_error.lock. */ struct i915_gpu_state *first_error; + atomic_t pending_fb_pin; + unsigned long missed_irq_rings; /** @@ -1568,6 +1614,7 @@ struct i915_gpu_error { unsigned long flags; #define I915_RESET_BACKOFF 0 #define I915_RESET_HANDOFF 1 +#define I915_RESET_MODESET 2 #define I915_WEDGED (BITS_PER_LONG - 1) #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES) @@ -1695,7 +1742,7 @@ struct intel_vbt_data { int crt_ddc_pin; int child_dev_num; - union child_device_config *child_dev; + struct child_device_config *child_dev; struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; struct sdvo_device_mapping sdvo_mappings[2]; @@ -1883,6 +1930,7 @@ struct i915_workarounds { struct i915_virtual_gpu { bool active; + u32 caps; }; /* used in computing the new watermarks state */ @@ -1902,6 +1950,24 @@ struct i915_oa_reg { u32 value; }; +struct i915_oa_config { + char uuid[UUID_STRING_LEN + 1]; + int id; + + const struct i915_oa_reg *mux_regs; + u32 mux_regs_len; + const struct i915_oa_reg *b_counter_regs; + u32 b_counter_regs_len; + const struct i915_oa_reg *flex_regs; + u32 flex_regs_len; + + struct attribute_group sysfs_metric; + struct attribute *attrs[2]; + struct device_attribute sysfs_metric_id; + + atomic_t ref_count; +}; + struct i915_perf_stream; /** @@ -2014,6 +2080,11 @@ struct i915_perf_stream { * type of configured stream. */ const struct i915_perf_stream_ops *ops; + + /** + * @oa_config: The OA configuration used by the stream. + */ + struct i915_oa_config *oa_config; }; /** @@ -2021,6 +2092,25 @@ struct i915_perf_stream { */ struct i915_oa_ops { /** + * @is_valid_b_counter_reg: Validates register's address for + * programming boolean counters for a particular platform. + */ + bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, + u32 addr); + + /** + * @is_valid_mux_reg: Validates register's address for programming mux + * for a particular platform. + */ + bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); + + /** + * @is_valid_flex_reg: Validates register's address for programming + * flex EU filtering for a particular platform. + */ + bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); + + /** * @init_oa_buffer: Resets the head and tail pointers of the * circular buffer for periodic OA reports. * @@ -2038,20 +2128,13 @@ struct i915_oa_ops { void (*init_oa_buffer)(struct drm_i915_private *dev_priv); /** - * @select_metric_set: The auto generated code that checks whether a - * requested OA config is applicable to the system and if so sets up - * the mux, oa and flex eu register config pointers according to the - * current dev_priv->perf.oa.metrics_set. - */ - int (*select_metric_set)(struct drm_i915_private *dev_priv); - - /** * @enable_metric_set: Selects and applies any MUX configuration to set * up the Boolean and Custom (B/C) counters that are part of the * counter reports being sampled. May apply system constraints such as * disabling EU clock gating as required. */ - int (*enable_metric_set)(struct drm_i915_private *dev_priv); + int (*enable_metric_set)(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config); /** * @disable_metric_set: Remove system constraints associated with using @@ -2097,6 +2180,7 @@ struct drm_i915_private { struct kmem_cache *objects; struct kmem_cache *vmas; + struct kmem_cache *luts; struct kmem_cache *requests; struct kmem_cache *dependencies; struct kmem_cache *priorities; @@ -2147,9 +2231,6 @@ struct drm_i915_private { /* protects the irq masks */ spinlock_t irq_lock; - /* protects the mmio flip data */ - spinlock_t mmio_flip_lock; - bool display_irqs_enabled; /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ @@ -2254,7 +2335,6 @@ struct drm_i915_private { struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; - wait_queue_head_t pending_flip_queue; #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; @@ -2273,7 +2353,8 @@ struct drm_i915_private { struct mutex dpll_lock; unsigned int active_crtcs; - unsigned int min_pixclk[I915_MAX_PIPES]; + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; @@ -2415,10 +2496,32 @@ struct drm_i915_private { struct kobject *metrics_kobj; struct ctl_table_header *sysctl_header; + /* + * Lock associated with adding/modifying/removing OA configs + * in dev_priv->perf.metrics_idr. + */ + struct mutex metrics_lock; + + /* + * List of dynamic configurations, you need to hold + * dev_priv->perf.metrics_lock to access it. + */ + struct idr metrics_idr; + + /* + * Lock associated with anything below within this structure + * except exclusive_stream. + */ struct mutex lock; struct list_head streams; struct { + /* + * The stream currently using the OA unit. If accessed + * outside a syscall associated to its file + * descriptor, you need to hold + * dev_priv->drm.struct_mutex. + */ struct i915_perf_stream *exclusive_stream; u32 specific_ctx_id; @@ -2437,16 +2540,7 @@ struct drm_i915_private { int period_exponent; int timestamp_frequency; - int metrics_set; - - const struct i915_oa_reg *mux_regs[6]; - int mux_regs_lens[6]; - int n_mux_configs; - - const struct i915_oa_reg *b_counter_regs; - int b_counter_regs_len; - const struct i915_oa_reg *flex_regs; - int flex_regs_len; + struct i915_oa_config test_config; struct { struct i915_vma *vma; @@ -2533,7 +2627,6 @@ struct drm_i915_private { struct i915_oa_ops ops; const struct i915_oa_format *oa_formats; - int n_builtin_sets; } oa; } perf; @@ -2794,9 +2887,8 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33) #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE) -#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \ - INTEL_DEVID(dev_priv) == 0x0152 || \ - INTEL_DEVID(dev_priv) == 0x015a) +#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ + (dev_priv)->info.gt == 1) #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW) #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW) #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL) @@ -2818,11 +2910,11 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xf) == 0xe) #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) + (dev_priv)->info.gt == 3) #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) + (dev_priv)->info.gt == 3) /* ULX machines are also considered ULT. */ #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ INTEL_DEVID(dev_priv) == 0x0A1E) @@ -2843,15 +2935,15 @@ intel_info(const struct drm_i915_private *dev_priv) INTEL_DEVID(dev_priv) == 0x5915 || \ INTEL_DEVID(dev_priv) == 0x591E) #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010) + (dev_priv)->info.gt == 2) #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) + (dev_priv)->info.gt == 3) #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) + (dev_priv)->info.gt == 4) #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010) + (dev_priv)->info.gt == 2) #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) + (dev_priv)->info.gt == 3) #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) @@ -3107,8 +3199,12 @@ extern int i915_driver_load(struct pci_dev *pdev, extern void i915_driver_unload(struct drm_device *dev); extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); -extern void i915_reset(struct drm_i915_private *dev_priv); -extern int i915_reset_engine(struct intel_engine_cs *engine); + +#define I915_RESET_QUIET BIT(0) +extern void i915_reset(struct drm_i915_private *i915, unsigned int flags); +extern int i915_reset_engine(struct intel_engine_cs *engine, + unsigned int flags); + extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); extern int intel_guc_reset(struct drm_i915_private *dev_priv); extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); @@ -3128,7 +3224,8 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, void intel_hpd_init(struct drm_i915_private *dev_priv); void intel_hpd_init_work(struct drm_i915_private *dev_priv); void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); -bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); +enum port intel_hpd_pin_to_port(enum hpd_pin pin); +enum hpd_pin intel_hpd_pin(enum port port); bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); @@ -3297,6 +3394,26 @@ static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) } while (flush_work(&i915->mm.free_work)); } +static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) +{ + /* + * Similar to objects above (see i915_gem_drain_freed-objects), in + * general we have workers that are armed by RCU and then rearm + * themselves in their callbacks. To be paranoid, we need to + * drain the workqueue a second time after waiting for the RCU + * grace period so that we catch work queued via RCU from the first + * pass. As neither drain_workqueue() nor flush_workqueue() report + * a result, we make an assumption that we only don't require more + * than 2 passes to catch all recursive RCU delayed work. + * + */ + int pass = 2; + do { + rcu_barrier(); + drain_workqueue(i915->wq); + } while (--pass); +} + struct i915_vma * __must_check i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, @@ -3386,6 +3503,9 @@ void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); enum i915_map_type { I915_MAP_WB = 0, I915_MAP_WC, +#define I915_MAP_OVERRIDE BIT(31) + I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE, + I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE, }; /** @@ -3552,6 +3672,9 @@ i915_vm_to_ppgtt(struct i915_address_space *vm) /* i915_gem_fence_reg.c */ int __must_check i915_vma_get_fence(struct i915_vma *vma); int __must_check i915_vma_put_fence(struct i915_vma *vma); +struct drm_i915_fence_reg * +i915_reserve_fence(struct drm_i915_private *dev_priv); +void i915_unreserve_fence(struct drm_i915_fence_reg *fence); void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); void i915_gem_restore_fences(struct drm_i915_private *dev_priv); @@ -3594,6 +3717,10 @@ i915_gem_context_lookup_timeline(struct i915_gem_context *ctx, int i915_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct i915_gem_context *ctx, uint32_t *reg_state); @@ -3645,6 +3772,7 @@ i915_gem_object_create_internal(struct drm_i915_private *dev_priv, /* i915_gem_shrinker.c */ unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, unsigned long target, + unsigned long *nr_scanned, unsigned flags); #define I915_SHRINK_PURGEABLE 0x1 #define I915_SHRINK_UNBOUND 0x2 @@ -4081,6 +4209,11 @@ static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) { + /* nsecs_to_jiffies64() does not guard against overflow */ + if (NSEC_PER_SEC % HZ && + div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) + return MAX_JIFFY_OFFSET; + return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); } @@ -4227,10 +4360,4 @@ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, struct io_mapping *iomap); -static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj) -{ - return (obj->cache_level != I915_CACHE_NONE || - HAS_LLC(to_i915(obj->base.dev))); -} - #endif diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d6f9b4cb6e9b..8f074c7f6253 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -52,7 +52,7 @@ static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) if (obj->cache_dirty) return false; - if (!obj->cache_coherent) + if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) return true; return obj->pin_display; @@ -253,7 +253,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, if (needs_clflush && (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && - !obj->cache_coherent) + !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) drm_clflush_sg(pages); __start_cpu_write(obj); @@ -561,46 +561,6 @@ static struct intel_rps_client *to_rps_client(struct drm_file *file) return &fpriv->rps; } -int -i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, - int align) -{ - int ret; - - if (align > obj->base.size) - return -EINVAL; - - if (obj->ops == &i915_gem_phys_ops) - return 0; - - if (obj->mm.madv != I915_MADV_WILLNEED) - return -EFAULT; - - if (obj->base.filp == NULL) - return -EINVAL; - - ret = i915_gem_object_unbind(obj); - if (ret) - return ret; - - __i915_gem_object_put_pages(obj, I915_MM_NORMAL); - if (obj->mm.pages) - return -EBUSY; - - GEM_BUG_ON(obj->ops != &i915_gem_object_ops); - obj->ops = &i915_gem_phys_ops; - - ret = i915_gem_object_pin_pages(obj); - if (ret) - goto err_xfer; - - return 0; - -err_xfer: - obj->ops = &i915_gem_object_ops; - return ret; -} - static int i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, struct drm_i915_gem_pwrite *args, @@ -735,12 +695,11 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) switch (obj->base.write_domain) { case I915_GEM_DOMAIN_GTT: if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) { - if (intel_runtime_pm_get_if_in_use(dev_priv)) { - spin_lock_irq(&dev_priv->uncore.lock); - POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); - spin_unlock_irq(&dev_priv->uncore.lock); - intel_runtime_pm_put(dev_priv); - } + intel_runtime_pm_get(dev_priv); + spin_lock_irq(&dev_priv->uncore.lock); + POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); + spin_unlock_irq(&dev_priv->uncore.lock); + intel_runtime_pm_put(dev_priv); } intel_fb_obj_flush(obj, @@ -840,7 +799,8 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, if (ret) return ret; - if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { + if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || + !static_cpu_has(X86_FEATURE_CLFLUSH)) { ret = i915_gem_object_set_to_cpu_domain(obj, false); if (ret) goto err_unpin; @@ -892,7 +852,8 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, if (ret) return ret; - if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { + if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || + !static_cpu_has(X86_FEATURE_CLFLUSH)) { ret = i915_gem_object_set_to_cpu_domain(obj, true); if (ret) goto err_unpin; @@ -1052,17 +1013,20 @@ gtt_user_read(struct io_mapping *mapping, loff_t base, int offset, char __user *user_data, int length) { - void *vaddr; + void __iomem *vaddr; unsigned long unwritten; /* We can use the cpu mem copy function because this is X86. */ - vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); - unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); + vaddr = io_mapping_map_atomic_wc(mapping, base); + unwritten = __copy_to_user_inatomic(user_data, + (void __force *)vaddr + offset, + length); io_mapping_unmap_atomic(vaddr); if (unwritten) { - vaddr = (void __force *) - io_mapping_map_wc(mapping, base, PAGE_SIZE); - unwritten = copy_to_user(user_data, vaddr + offset, length); + vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); + unwritten = copy_to_user(user_data, + (void __force *)vaddr + offset, + length); io_mapping_unmap(vaddr); } return unwritten; @@ -1228,18 +1192,18 @@ ggtt_write(struct io_mapping *mapping, loff_t base, int offset, char __user *user_data, int length) { - void *vaddr; + void __iomem *vaddr; unsigned long unwritten; /* We can use the cpu mem copy function because this is X86. */ - vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); - unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, + vaddr = io_mapping_map_atomic_wc(mapping, base); + unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset, user_data, length); io_mapping_unmap_atomic(vaddr); if (unwritten) { - vaddr = (void __force *) - io_mapping_map_wc(mapping, base, PAGE_SIZE); - unwritten = copy_from_user(vaddr + offset, user_data, length); + vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); + unwritten = copy_from_user((void __force *)vaddr + offset, + user_data, length); io_mapping_unmap(vaddr); } @@ -2251,7 +2215,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) { struct radix_tree_iter iter; - void **slot; + void __rcu **slot; radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) radix_tree_delete(&obj->mm.get_page.radix, iter.index); @@ -2392,7 +2356,7 @@ rebuild_st: goto err_sg; } - i915_gem_shrink(dev_priv, 2 * page_count, *s++); + i915_gem_shrink(dev_priv, 2 * page_count, NULL, *s++); cond_resched(); /* We've tried hard to allocate the memory by reaping @@ -2515,8 +2479,6 @@ static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) { struct sg_table *pages; - GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); - if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { DRM_DEBUG("Attempting to obtain a purgeable object\n"); return -EFAULT; @@ -2546,6 +2508,8 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) return err; if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { + GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); + err = ____i915_gem_object_get_pages(obj); if (err) goto unlock; @@ -2579,7 +2543,7 @@ static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, if (n_pages > ARRAY_SIZE(stack_pages)) { /* Too big for stack -- allocate temporary array instead */ - pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY); + pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_KERNEL); if (!pages) return NULL; } @@ -2591,6 +2555,9 @@ static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, GEM_BUG_ON(i != n_pages); switch (type) { + default: + MISSING_CASE(type); + /* fallthrough to use PAGE_KERNEL anyway */ case I915_MAP_WB: pgprot = PAGE_KERNEL; break; @@ -2621,9 +2588,13 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, if (ret) return ERR_PTR(ret); - pinned = true; + pinned = !(type & I915_MAP_OVERRIDE); + type &= ~I915_MAP_OVERRIDE; + if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { + GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); + ret = ____i915_gem_object_get_pages(obj); if (ret) goto err_unlock; @@ -2740,34 +2711,38 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, return 0; } -static bool ban_context(const struct i915_gem_context *ctx) +static bool ban_context(const struct i915_gem_context *ctx, + unsigned int score) { return (i915_gem_context_is_bannable(ctx) && - ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD); + score >= CONTEXT_SCORE_BAN_THRESHOLD); } static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) { - ctx->guilty_count++; - ctx->ban_score += CONTEXT_SCORE_GUILTY; - if (ban_context(ctx)) - i915_gem_context_set_banned(ctx); + unsigned int score; + bool banned; - DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", - ctx->name, ctx->ban_score, - yesno(i915_gem_context_is_banned(ctx))); + atomic_inc(&ctx->guilty_count); - if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv)) + score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score); + banned = ban_context(ctx, score); + DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", + ctx->name, score, yesno(banned)); + if (!banned) return; - ctx->file_priv->context_bans++; - DRM_DEBUG_DRIVER("client %s has had %d context banned\n", - ctx->name, ctx->file_priv->context_bans); + i915_gem_context_set_banned(ctx); + if (!IS_ERR_OR_NULL(ctx->file_priv)) { + atomic_inc(&ctx->file_priv->context_bans); + DRM_DEBUG_DRIVER("client %s has had %d context banned\n", + ctx->name, atomic_read(&ctx->file_priv->context_bans)); + } } static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) { - ctx->active_count++; + atomic_inc(&ctx->active_count); } struct drm_i915_gem_request * @@ -2850,11 +2825,9 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine) if (engine->irq_seqno_barrier) engine->irq_seqno_barrier(engine); - if (engine_stalled(engine)) { - request = i915_gem_find_active_request(engine); - if (request && request->fence.error == -EIO) - request = ERR_PTR(-EIO); /* Previous reset failed! */ - } + request = i915_gem_find_active_request(engine); + if (request && request->fence.error == -EIO) + request = ERR_PTR(-EIO); /* Previous reset failed! */ return request; } @@ -2923,12 +2896,11 @@ static void engine_skip_context(struct drm_i915_gem_request *request) spin_unlock_irqrestore(&engine->timeline->lock, flags); } -/* Returns true if the request was guilty of hang */ -static bool i915_gem_reset_request(struct drm_i915_gem_request *request) +/* Returns the request if it was guilty of the hang */ +static struct drm_i915_gem_request * +i915_gem_reset_request(struct intel_engine_cs *engine, + struct drm_i915_gem_request *request) { - /* Read once and return the resolution */ - const bool guilty = !i915_gem_request_completed(request); - /* The guilty request will get skipped on a hung engine. * * Users of client default contexts do not rely on logical @@ -2950,27 +2922,47 @@ static bool i915_gem_reset_request(struct drm_i915_gem_request *request) * subsequent hangs. */ - if (guilty) { + if (engine_stalled(engine)) { i915_gem_context_mark_guilty(request->ctx); skip_request(request); + + /* If this context is now banned, skip all pending requests. */ + if (i915_gem_context_is_banned(request->ctx)) + engine_skip_context(request); } else { - i915_gem_context_mark_innocent(request->ctx); - dma_fence_set_error(&request->fence, -EAGAIN); + /* + * Since this is not the hung engine, it may have advanced + * since the hang declaration. Double check by refinding + * the active request at the time of the reset. + */ + request = i915_gem_find_active_request(engine); + if (request) { + i915_gem_context_mark_innocent(request->ctx); + dma_fence_set_error(&request->fence, -EAGAIN); + + /* Rewind the engine to replay the incomplete rq */ + spin_lock_irq(&engine->timeline->lock); + request = list_prev_entry(request, link); + if (&request->link == &engine->timeline->requests) + request = NULL; + spin_unlock_irq(&engine->timeline->lock); + } } - return guilty; + return request; } void i915_gem_reset_engine(struct intel_engine_cs *engine, struct drm_i915_gem_request *request) { - if (request && i915_gem_reset_request(request)) { + engine->irq_posted = 0; + + if (request) + request = i915_gem_reset_request(engine, request); + + if (request) { DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", engine->name, request->global_seqno); - - /* If this context is now banned, skip all pending requests. */ - if (i915_gem_context_is_banned(request->ctx)) - engine_skip_context(request); } /* Setup the CS to resume from the breadcrumb of the hung request */ @@ -3026,6 +3018,7 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) static void nop_submit_request(struct drm_i915_gem_request *request) { + GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error)); dma_fence_set_error(&request->fence, -EIO); i915_gem_request_submit(request); intel_engine_init_global_seqno(request->engine, request->global_seqno); @@ -3051,13 +3044,6 @@ static void engine_set_wedged(struct intel_engine_cs *engine) dma_fence_set_error(&request->fence, -EIO); spin_unlock_irqrestore(&engine->timeline->lock, flags); - /* Mark all pending requests as complete so that any concurrent - * (lockless) lookup doesn't try and wait upon the request as we - * reset it. - */ - intel_engine_init_global_seqno(engine, - intel_engine_last_submit(engine)); - /* * Clear the execlists queue up before freeing the requests, as those * are the ones that keep the context and ringbuffer backing objects @@ -3086,6 +3072,13 @@ static void engine_set_wedged(struct intel_engine_cs *engine) */ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); } + + /* Mark all pending requests as complete so that any concurrent + * (lockless) lookup doesn't try and wait upon the request as we + * reset it. + */ + intel_engine_init_global_seqno(engine, + intel_engine_last_submit(engine)); } static int __i915_gem_set_wedged_BKL(void *data) @@ -3094,10 +3087,12 @@ static int __i915_gem_set_wedged_BKL(void *data) struct intel_engine_cs *engine; enum intel_engine_id id; - set_bit(I915_WEDGED, &i915->gpu_error.flags); for_each_engine(engine, i915, id) engine_set_wedged(engine); + set_bit(I915_WEDGED, &i915->gpu_error.flags); + wake_up_all(&i915->gpu_error.reset_queue); + return 0; } @@ -3256,25 +3251,39 @@ out_rearm: void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) { + struct drm_i915_private *i915 = to_i915(gem->dev); struct drm_i915_gem_object *obj = to_intel_bo(gem); struct drm_i915_file_private *fpriv = file->driver_priv; - struct i915_vma *vma, *vn; + struct i915_lut_handle *lut, *ln; - mutex_lock(&obj->base.dev->struct_mutex); - list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) - if (vma->vm->file == fpriv) + mutex_lock(&i915->drm.struct_mutex); + + list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { + struct i915_gem_context *ctx = lut->ctx; + struct i915_vma *vma; + + GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF)); + if (ctx->file_priv != fpriv) + continue; + + vma = radix_tree_delete(&ctx->handles_vma, lut->handle); + GEM_BUG_ON(vma->obj != obj); + + /* We allow the process to have multiple handles to the same + * vma, in the same fd namespace, by virtue of flink/open. + */ + GEM_BUG_ON(!vma->open_count); + if (!--vma->open_count && !i915_vma_is_ggtt(vma)) i915_vma_close(vma); - vma = obj->vma_hashed; - if (vma && vma->ctx->file_priv == fpriv) - i915_vma_unlink_ctx(vma); + list_del(&lut->obj_link); + list_del(&lut->ctx_link); - if (i915_gem_object_is_active(obj) && - !i915_gem_object_has_active_reference(obj)) { - i915_gem_object_set_active_reference(obj); - i915_gem_object_get(obj); + kmem_cache_free(i915->luts, lut); + __i915_gem_object_release_unless_active(obj); } - mutex_unlock(&obj->base.dev->struct_mutex); + + mutex_unlock(&i915->drm.struct_mutex); } static unsigned long to_wait_timeout(s64 timeout_ns) @@ -3300,7 +3309,7 @@ static unsigned long to_wait_timeout(s64 timeout_ns) * -ERESTARTSYS: signal interrupted the wait * -ENONENT: object doesn't exist * Also possible, but rare: - * -EAGAIN: GPU wedged + * -EAGAIN: incomplete, restart syscall * -ENOMEM: damn * -ENODEV: Internal IRQ fail * -E?: The add request failed @@ -3348,6 +3357,10 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) */ if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) args->timeout_ns = 0; + + /* Asked to wait beyond the jiffie/scheduler precision? */ + if (ret == -ETIME && args->timeout_ns) + ret = -EAGAIN; } i915_gem_object_put(obj); @@ -3367,24 +3380,12 @@ static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) return 0; } -static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms) -{ - return wait_for(intel_engine_is_idle(engine), timeout_ms); -} - static int wait_for_engines(struct drm_i915_private *i915) { - struct intel_engine_cs *engine; - enum intel_engine_id id; - - for_each_engine(engine, i915, id) { - if (GEM_WARN_ON(wait_for_engine(engine, 50))) { - i915_gem_set_wedged(i915); - return -EIO; - } - - GEM_BUG_ON(intel_engine_get_seqno(engine) != - intel_engine_last_submit(engine)); + if (wait_for(intel_engines_are_idle(i915), 50)) { + DRM_ERROR("Failed to idle engines, declaring wedged!\n"); + i915_gem_set_wedged(i915); + return -EIO; } return 0; @@ -3689,8 +3690,7 @@ restart: list_for_each_entry(vma, &obj->vma_list, obj_link) vma->node.color = cache_level; - obj->cache_level = cache_level; - obj->cache_coherent = i915_gem_object_is_coherent(obj); + i915_gem_object_set_cache_coherency(obj, cache_level); obj->cache_dirty = true; /* Always invalidate stale cachelines */ return 0; @@ -4263,6 +4263,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, INIT_LIST_HEAD(&obj->global_link); INIT_LIST_HEAD(&obj->userfault_link); INIT_LIST_HEAD(&obj->vma_list); + INIT_LIST_HEAD(&obj->lut_list); INIT_LIST_HEAD(&obj->batch_pool_link); obj->ops = ops; @@ -4295,6 +4296,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) { struct drm_i915_gem_object *obj; struct address_space *mapping; + unsigned int cache_level; gfp_t mask; int ret; @@ -4333,7 +4335,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(dev_priv)) { + if (HAS_LLC(dev_priv)) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than @@ -4346,12 +4348,11 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) * However, we maintain the display planes as UC, and so * need to rebind when first used as such. */ - obj->cache_level = I915_CACHE_LLC; - } else - obj->cache_level = I915_CACHE_NONE; + cache_level = I915_CACHE_LLC; + else + cache_level = I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + i915_gem_object_set_cache_coherency(obj, cache_level); trace_i915_gem_object_create(obj); @@ -4418,6 +4419,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, llist_for_each_entry_safe(obj, on, freed, freed) { GEM_BUG_ON(obj->bind_count); GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); + GEM_BUG_ON(!list_empty(&obj->lut_list)); if (obj->ops->release) obj->ops->release(obj); @@ -4506,8 +4508,8 @@ void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) { lockdep_assert_held(&obj->base.dev->struct_mutex); - GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); - if (i915_gem_object_is_active(obj)) + if (!i915_gem_object_has_active_reference(obj) && + i915_gem_object_is_active(obj)) i915_gem_object_set_active_reference(obj); else i915_gem_object_put(obj); @@ -4525,6 +4527,12 @@ static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) void i915_gem_sanitize(struct drm_i915_private *i915) { + if (i915_terminally_wedged(&i915->gpu_error)) { + mutex_lock(&i915->drm.struct_mutex); + i915_gem_unset_wedged(i915); + mutex_unlock(&i915->drm.struct_mutex); + } + /* * If we inherit context state from the BIOS or earlier occupants * of the GPU, the GPU may be in an inconsistent state when we @@ -4564,7 +4572,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) ret = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED); - if (ret) + if (ret && ret != -EIO) goto err_unlock; assert_kernel_context_is_current(dev_priv); @@ -4586,7 +4594,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) * reset the GPU back to its idle, low power state. */ WARN_ON(dev_priv->gt.awake); - WARN_ON(!intel_engines_are_idle(dev_priv)); + if (WARN_ON(!intel_engines_are_idle(dev_priv))) + i915_gem_set_wedged(dev_priv); /* no hope, discard everything */ /* * Neither the BIOS, ourselves or any other kernel @@ -4608,11 +4617,12 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv) * machine in an unusable condition. */ i915_gem_sanitize(dev_priv); - goto out_rpm_put; + + intel_runtime_pm_put(dev_priv); + return 0; err_unlock: mutex_unlock(&dev->struct_mutex); -out_rpm_put: intel_runtime_pm_put(dev_priv); return ret; } @@ -4899,12 +4909,16 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) if (!dev_priv->vmas) goto err_objects; + dev_priv->luts = KMEM_CACHE(i915_lut_handle, 0); + if (!dev_priv->luts) + goto err_vmas; + dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, SLAB_HWCACHE_ALIGN | SLAB_RECLAIM_ACCOUNT | SLAB_TYPESAFE_BY_RCU); if (!dev_priv->requests) - goto err_vmas; + goto err_luts; dev_priv->dependencies = KMEM_CACHE(i915_dependency, SLAB_HWCACHE_ALIGN | @@ -4936,8 +4950,6 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) init_waitqueue_head(&dev_priv->gpu_error.wait_queue); init_waitqueue_head(&dev_priv->gpu_error.reset_queue); - init_waitqueue_head(&dev_priv->pending_flip_queue); - atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); spin_lock_init(&dev_priv->fb_tracking.lock); @@ -4950,6 +4962,8 @@ err_dependencies: kmem_cache_destroy(dev_priv->dependencies); err_requests: kmem_cache_destroy(dev_priv->requests); +err_luts: + kmem_cache_destroy(dev_priv->luts); err_vmas: kmem_cache_destroy(dev_priv->vmas); err_objects: @@ -4972,6 +4986,7 @@ void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) kmem_cache_destroy(dev_priv->priorities); kmem_cache_destroy(dev_priv->dependencies); kmem_cache_destroy(dev_priv->requests); + kmem_cache_destroy(dev_priv->luts); kmem_cache_destroy(dev_priv->vmas); kmem_cache_destroy(dev_priv->objects); @@ -5012,7 +5027,7 @@ int i915_gem_freeze_late(struct drm_i915_private *dev_priv) * the objects as well, see i915_gem_freeze() */ - i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); + i915_gem_shrink(dev_priv, -1UL, NULL, I915_SHRINK_UNBOUND); i915_gem_drain_freed_objects(dev_priv); mutex_lock(&dev_priv->drm.struct_mutex); @@ -5304,6 +5319,64 @@ i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, return sg_dma_address(sg) + (offset << PAGE_SHIFT); } +int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) +{ + struct sg_table *pages; + int err; + + if (align > obj->base.size) + return -EINVAL; + + if (obj->ops == &i915_gem_phys_ops) + return 0; + + if (obj->ops != &i915_gem_object_ops) + return -EINVAL; + + err = i915_gem_object_unbind(obj); + if (err) + return err; + + mutex_lock(&obj->mm.lock); + + if (obj->mm.madv != I915_MADV_WILLNEED) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.quirked) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.mapping) { + err = -EBUSY; + goto err_unlock; + } + + pages = obj->mm.pages; + obj->ops = &i915_gem_phys_ops; + + err = ____i915_gem_object_get_pages(obj); + if (err) + goto err_xfer; + + /* Perma-pin (until release) the physical set of pages */ + __i915_gem_object_pin_pages(obj); + + if (!IS_ERR_OR_NULL(pages)) + i915_gem_object_ops.put_pages(obj, pages); + mutex_unlock(&obj->mm.lock); + return 0; + +err_xfer: + obj->ops = &i915_gem_object_ops; + obj->mm.pages = pages; +err_unlock: + mutex_unlock(&obj->mm.lock); + return err; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/scatterlist.c" #include "selftests/mock_gem_device.c" diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c index 348b29a845c9..8a04d33055be 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c @@ -139,7 +139,8 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, * snooping behaviour occurs naturally as the result of our domain * tracking. */ - if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent) + if (!(flags & I915_CLFLUSH_FORCE) && + obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) return false; trace_i915_gem_object_clflush(obj); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 1a87d04e7937..58a2a44f88bd 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -93,69 +93,28 @@ #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 -/* Initial size (as log2) to preallocate the handle->object hashtable */ -#define VMA_HT_BITS 2u /* 4 x 2 pointers, 64 bytes minimum */ - -static void resize_vma_ht(struct work_struct *work) +static void lut_close(struct i915_gem_context *ctx) { - struct i915_gem_context_vma_lut *lut = - container_of(work, typeof(*lut), resize); - unsigned int bits, new_bits, size, i; - struct hlist_head *new_ht; - - GEM_BUG_ON(!(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)); - - bits = 1 + ilog2(4*lut->ht_count/3 + 1); - new_bits = min_t(unsigned int, - max(bits, VMA_HT_BITS), - sizeof(unsigned int) * BITS_PER_BYTE - 1); - if (new_bits == lut->ht_bits) - goto out; - - new_ht = kzalloc(sizeof(*new_ht)<<new_bits, GFP_KERNEL | __GFP_NOWARN); - if (!new_ht) - new_ht = vzalloc(sizeof(*new_ht)<<new_bits); - if (!new_ht) - /* Pretend resize succeeded and stop calling us for a bit! */ - goto out; + struct i915_lut_handle *lut, *ln; + struct radix_tree_iter iter; + void __rcu **slot; - size = BIT(lut->ht_bits); - for (i = 0; i < size; i++) { - struct i915_vma *vma; - struct hlist_node *tmp; - - hlist_for_each_entry_safe(vma, tmp, &lut->ht[i], ctx_node) - hlist_add_head(&vma->ctx_node, - &new_ht[hash_32(vma->ctx_handle, - new_bits)]); + list_for_each_entry_safe(lut, ln, &ctx->handles_list, ctx_link) { + list_del(&lut->obj_link); + kmem_cache_free(ctx->i915->luts, lut); } - kvfree(lut->ht); - lut->ht = new_ht; - lut->ht_bits = new_bits; -out: - smp_store_release(&lut->ht_size, BIT(bits)); - GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); -} -static void vma_lut_free(struct i915_gem_context *ctx) -{ - struct i915_gem_context_vma_lut *lut = &ctx->vma_lut; - unsigned int i, size; + radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) { + struct i915_vma *vma = rcu_dereference_raw(*slot); + struct drm_i915_gem_object *obj = vma->obj; - if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) - cancel_work_sync(&lut->resize); + radix_tree_iter_delete(&ctx->handles_vma, &iter, slot); - size = BIT(lut->ht_bits); - for (i = 0; i < size; i++) { - struct i915_vma *vma; + if (!i915_vma_is_ggtt(vma)) + i915_vma_close(vma); - hlist_for_each_entry(vma, &lut->ht[i], ctx_node) { - vma->obj->vma_hashed = NULL; - vma->ctx = NULL; - i915_vma_put(vma); - } + __i915_gem_object_release_unless_active(obj); } - kvfree(lut->ht); } static void i915_gem_context_free(struct i915_gem_context *ctx) @@ -165,7 +124,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx) lockdep_assert_held(&ctx->i915->drm.struct_mutex); GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); - vma_lut_free(ctx); i915_ppgtt_put(ctx->ppgtt); for (i = 0; i < I915_NUM_ENGINES; i++) { @@ -239,8 +197,11 @@ void i915_gem_context_release(struct kref *ref) static void context_close(struct i915_gem_context *ctx) { i915_gem_context_set_closed(ctx); + + lut_close(ctx); if (ctx->ppgtt) i915_ppgtt_close(&ctx->ppgtt->base); + ctx->file_priv = ERR_PTR(-EBADF); i915_gem_context_put(ctx); } @@ -313,16 +274,8 @@ __create_hw_context(struct drm_i915_private *dev_priv, ctx->i915 = dev_priv; ctx->priority = I915_PRIORITY_NORMAL; - ctx->vma_lut.ht_bits = VMA_HT_BITS; - ctx->vma_lut.ht_size = BIT(VMA_HT_BITS); - BUILD_BUG_ON(BIT(VMA_HT_BITS) == I915_CTX_RESIZE_IN_PROGRESS); - ctx->vma_lut.ht = kcalloc(ctx->vma_lut.ht_size, - sizeof(*ctx->vma_lut.ht), - GFP_KERNEL); - if (!ctx->vma_lut.ht) - goto err_out; - - INIT_WORK(&ctx->vma_lut.resize, resize_vma_ht); + INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); + INIT_LIST_HEAD(&ctx->handles_list); /* Default context will never have a file_priv */ ret = DEFAULT_CONTEXT_HANDLE; @@ -372,8 +325,6 @@ err_pid: put_pid(ctx->pid); idr_remove(&file_priv->context_idr, ctx->user_handle); err_lut: - kvfree(ctx->vma_lut.ht); -err_out: context_close(ctx); return ERR_PTR(ret); } @@ -741,19 +692,19 @@ static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, } static bool -needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, - struct intel_engine_cs *engine, - struct i915_gem_context *to) +needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine) { + struct i915_gem_context *from = engine->legacy_active_context; + if (!ppgtt) return false; /* Always load the ppgtt on first use */ - if (!engine->legacy_active_context) + if (!from) return true; /* Same context without new entries, skip */ - if (engine->legacy_active_context == to && + if ((!from->ppgtt || from->ppgtt == ppgtt) && !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) return false; @@ -797,7 +748,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) if (skip_rcs_switch(ppgtt, engine, to)) return 0; - if (needs_pd_load_pre(ppgtt, engine, to)) { + if (needs_pd_load_pre(ppgtt, engine)) { /* Older GENs and non render rings still want the load first, * "PP_DCLV followed by PP_DIR_BASE register through Load * Register Immediate commands in Ring Buffer before submitting @@ -894,7 +845,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; - if (needs_pd_load_pre(ppgtt, engine, to)) { + if (needs_pd_load_pre(ppgtt, engine)) { int ret; trace_switch_mm(engine, to); @@ -905,6 +856,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); } + engine->legacy_active_context = to; return 0; } @@ -977,7 +929,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) static bool client_is_banned(struct drm_i915_file_private *file_priv) { - return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS; + return atomic_read(&file_priv->context_bans) > I915_MAX_CLIENT_CONTEXT_BANS; } int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, @@ -1179,8 +1131,8 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, else args->reset_count = 0; - args->batch_active = READ_ONCE(ctx->guilty_count); - args->batch_pending = READ_ONCE(ctx->active_count); + args->batch_active = atomic_read(&ctx->guilty_count); + args->batch_pending = atomic_read(&ctx->active_count); ret = 0; out: diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 04320f80f9f4..44688e22a5c2 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -27,6 +27,7 @@ #include <linux/bitops.h> #include <linux/list.h> +#include <linux/radix-tree.h> struct pid; @@ -149,32 +150,6 @@ struct i915_gem_context { /** ggtt_offset_bias: placement restriction for context objects */ u32 ggtt_offset_bias; - struct i915_gem_context_vma_lut { - /** ht_size: last request size to allocate the hashtable for. */ - unsigned int ht_size; -#define I915_CTX_RESIZE_IN_PROGRESS BIT(0) - /** ht_bits: real log2(size) of hashtable. */ - unsigned int ht_bits; - /** ht_count: current number of entries inside the hashtable */ - unsigned int ht_count; - - /** ht: the array of buckets comprising the simple hashtable */ - struct hlist_head *ht; - - /** - * resize: After an execbuf completes, we check the load factor - * of the hashtable. If the hashtable is too full, or too empty, - * we schedule a task to resize the hashtable. During the - * resize, the entries are moved between different buckets and - * so we cannot simultaneously read the hashtable as it is - * being resized (unlike rhashtable). Therefore we treat the - * active work as a strong barrier, pausing a subsequent - * execbuf to wait for the resize worker to complete, if - * required. - */ - struct work_struct resize; - } vma_lut; - /** engine: per-engine logical HW state */ struct intel_context { struct i915_vma *state; @@ -191,20 +166,32 @@ struct i915_gem_context { u32 desc_template; /** guilty_count: How many times this context has caused a GPU hang. */ - unsigned int guilty_count; + atomic_t guilty_count; /** * @active_count: How many times this context was active during a GPU * hang, but did not cause it. */ - unsigned int active_count; + atomic_t active_count; #define CONTEXT_SCORE_GUILTY 10 #define CONTEXT_SCORE_BAN_THRESHOLD 40 /** ban_score: Accumulated score of all hangs caused by this context. */ - int ban_score; + atomic_t ban_score; /** remap_slice: Bitmask of cache lines that need remapping */ u8 remap_slice; + + /** handles_vma: rbtree to look up our context specific obj/vma for + * the user handle. (user handles are per fd, but the binding is + * per vm, which may be one per context or shared with the global GTT) + */ + struct radix_tree_root handles_vma; + + /** handles_list: reverse list of all the rbtree entries in use for + * this context, which allows us to free all the allocations on + * context close. + */ + struct list_head handles_list; }; static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c index a193f1b36c67..4df039ef2ce3 100644 --- a/drivers/gpu/drm/i915/i915_gem_evict.c +++ b/drivers/gpu/drm/i915/i915_gem_evict.c @@ -318,8 +318,8 @@ int i915_gem_evict_for_node(struct i915_address_space *vm, /* Overlap of objects in the same batch? */ if (i915_vma_is_pinned(vma)) { ret = -ENOSPC; - if (vma->exec_entry && - vma->exec_entry->flags & EXEC_OBJECT_PINNED) + if (vma->exec_flags && + *vma->exec_flags & EXEC_OBJECT_PINNED) ret = -EINVAL; break; } diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 5fa44767c29e..ca0eab343644 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -32,6 +32,7 @@ #include <linux/uaccess.h> #include <drm/drmP.h> +#include <drm/drm_syncobj.h> #include <drm/i915_drm.h> #include "i915_drv.h" @@ -191,6 +192,8 @@ struct i915_execbuffer { struct drm_file *file; /** per-file lookup tables and limits */ struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */ struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */ + struct i915_vma **vma; + unsigned int *flags; struct intel_engine_cs *engine; /** engine to queue the request to */ struct i915_gem_context *ctx; /** context for building the request */ @@ -244,13 +247,7 @@ struct i915_execbuffer { struct hlist_head *buckets; /** ht for relocation handles */ }; -/* - * As an alternative to creating a hashtable of handle-to-vma for a batch, - * we used the last available reserved field in the execobject[] and stash - * a link from the execobj to its vma. - */ -#define __exec_to_vma(ee) (ee)->rsvd2 -#define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee)) +#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags]) /* * Used to convert any address to canonical form. @@ -271,6 +268,11 @@ static inline u64 gen8_noncanonical_addr(u64 address) return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0); } +static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) +{ + return eb->engine->needs_cmd_parser && eb->batch_len; +} + static int eb_create(struct i915_execbuffer *eb) { if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { @@ -288,7 +290,7 @@ static int eb_create(struct i915_execbuffer *eb) * direct lookup. */ do { - unsigned int flags; + gfp_t flags; /* While we can still reduce the allocation size, don't * raise a warning and allow the allocation to fail. @@ -296,7 +298,7 @@ static int eb_create(struct i915_execbuffer *eb) * as possible to perform the allocation and warn * if it fails. */ - flags = GFP_TEMPORARY; + flags = GFP_KERNEL; if (size > 1) flags |= __GFP_NORETRY | __GFP_NOWARN; @@ -319,85 +321,82 @@ static int eb_create(struct i915_execbuffer *eb) static bool eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, - const struct i915_vma *vma) + const struct i915_vma *vma, + unsigned int flags) { - if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) - return true; - if (vma->node.size < entry->pad_to_size) return true; if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) return true; - if (entry->flags & EXEC_OBJECT_PINNED && + if (flags & EXEC_OBJECT_PINNED && vma->node.start != entry->offset) return true; - if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && + if (flags & __EXEC_OBJECT_NEEDS_BIAS && vma->node.start < BATCH_OFFSET_BIAS) return true; - if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && + if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && (vma->node.start + vma->node.size - 1) >> 32) return true; return false; } -static inline void +static inline bool eb_pin_vma(struct i915_execbuffer *eb, - struct drm_i915_gem_exec_object2 *entry, + const struct drm_i915_gem_exec_object2 *entry, struct i915_vma *vma) { - u64 flags; + unsigned int exec_flags = *vma->exec_flags; + u64 pin_flags; if (vma->node.size) - flags = vma->node.start; + pin_flags = vma->node.start; else - flags = entry->offset & PIN_OFFSET_MASK; + pin_flags = entry->offset & PIN_OFFSET_MASK; - flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_GTT)) - flags |= PIN_GLOBAL; + pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT)) + pin_flags |= PIN_GLOBAL; - if (unlikely(i915_vma_pin(vma, 0, 0, flags))) - return; + if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) + return false; - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { if (unlikely(i915_vma_get_fence(vma))) { i915_vma_unpin(vma); - return; + return false; } if (i915_vma_pin_fence(vma)) - entry->flags |= __EXEC_OBJECT_HAS_FENCE; + exec_flags |= __EXEC_OBJECT_HAS_FENCE; } - entry->flags |= __EXEC_OBJECT_HAS_PIN; + *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN; + return !eb_vma_misplaced(entry, vma, exec_flags); } -static inline void -__eb_unreserve_vma(struct i915_vma *vma, - const struct drm_i915_gem_exec_object2 *entry) +static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) { - GEM_BUG_ON(!(entry->flags & __EXEC_OBJECT_HAS_PIN)); + GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); - if (unlikely(entry->flags & __EXEC_OBJECT_HAS_FENCE)) + if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) i915_vma_unpin_fence(vma); __i915_vma_unpin(vma); } static inline void -eb_unreserve_vma(struct i915_vma *vma, - struct drm_i915_gem_exec_object2 *entry) +eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags) { - if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) + if (!(*flags & __EXEC_OBJECT_HAS_PIN)) return; - __eb_unreserve_vma(vma, entry); - entry->flags &= ~__EXEC_OBJECT_RESERVED; + __eb_unreserve_vma(vma, *flags); + *flags &= ~__EXEC_OBJECT_RESERVED; } static int @@ -427,7 +426,7 @@ eb_validate_vma(struct i915_execbuffer *eb, entry->pad_to_size = 0; } - if (unlikely(vma->exec_entry)) { + if (unlikely(vma->exec_flags)) { DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n", entry->handle, (int)(entry - eb->exec)); return -EINVAL; @@ -440,14 +439,25 @@ eb_validate_vma(struct i915_execbuffer *eb, */ entry->offset = gen8_noncanonical_addr(entry->offset); + if (!eb->reloc_cache.has_fence) { + entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; + } else { + if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || + eb->reloc_cache.needs_unfenced) && + i915_gem_object_is_tiled(vma->obj)) + entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; + } + + if (!(entry->flags & EXEC_OBJECT_PINNED)) + entry->flags |= eb->context_flags; + return 0; } static int -eb_add_vma(struct i915_execbuffer *eb, - struct drm_i915_gem_exec_object2 *entry, - struct i915_vma *vma) +eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma) { + struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; int err; GEM_BUG_ON(i915_vma_is_closed(vma)); @@ -468,40 +478,28 @@ eb_add_vma(struct i915_execbuffer *eb, if (entry->relocation_count) list_add_tail(&vma->reloc_link, &eb->relocs); - if (!eb->reloc_cache.has_fence) { - entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; - } else { - if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || - eb->reloc_cache.needs_unfenced) && - i915_gem_object_is_tiled(vma->obj)) - entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; - } - - if (!(entry->flags & EXEC_OBJECT_PINNED)) - entry->flags |= eb->context_flags; - /* * Stash a pointer from the vma to execobj, so we can query its flags, * size, alignment etc as provided by the user. Also we stash a pointer * to the vma inside the execobj so that we can use a direct lookup * to find the right target VMA when doing relocations. */ - vma->exec_entry = entry; - __exec_to_vma(entry) = (uintptr_t)vma; + eb->vma[i] = vma; + eb->flags[i] = entry->flags; + vma->exec_flags = &eb->flags[i]; err = 0; - eb_pin_vma(eb, entry, vma); - if (eb_vma_misplaced(entry, vma)) { - eb_unreserve_vma(vma, entry); - - list_add_tail(&vma->exec_link, &eb->unbound); - if (drm_mm_node_allocated(&vma->node)) - err = i915_vma_unbind(vma); - } else { + if (eb_pin_vma(eb, entry, vma)) { if (entry->offset != vma->node.start) { entry->offset = vma->node.start | UPDATE; eb->args->flags |= __EXEC_HAS_RELOC; } + } else { + eb_unreserve_vma(vma, vma->exec_flags); + + list_add_tail(&vma->exec_link, &eb->unbound); + if (drm_mm_node_allocated(&vma->node)) + err = i915_vma_unbind(vma); } return err; } @@ -526,32 +524,35 @@ static inline int use_cpu_reloc(const struct reloc_cache *cache, static int eb_reserve_vma(const struct i915_execbuffer *eb, struct i915_vma *vma) { - struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; - u64 flags; + struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); + unsigned int exec_flags = *vma->exec_flags; + u64 pin_flags; int err; - flags = PIN_USER | PIN_NONBLOCK; - if (entry->flags & EXEC_OBJECT_NEEDS_GTT) - flags |= PIN_GLOBAL; + pin_flags = PIN_USER | PIN_NONBLOCK; + if (exec_flags & EXEC_OBJECT_NEEDS_GTT) + pin_flags |= PIN_GLOBAL; /* * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, * limit address to the first 4GBs for unflagged objects. */ - if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) - flags |= PIN_ZONE_4G; + if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) + pin_flags |= PIN_ZONE_4G; - if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) - flags |= PIN_MAPPABLE; + if (exec_flags & __EXEC_OBJECT_NEEDS_MAP) + pin_flags |= PIN_MAPPABLE; - if (entry->flags & EXEC_OBJECT_PINNED) { - flags |= entry->offset | PIN_OFFSET_FIXED; - flags &= ~PIN_NONBLOCK; /* force overlapping PINNED checks */ - } else if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) { - flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; + if (exec_flags & EXEC_OBJECT_PINNED) { + pin_flags |= entry->offset | PIN_OFFSET_FIXED; + pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */ + } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) { + pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; } - err = i915_vma_pin(vma, entry->pad_to_size, entry->alignment, flags); + err = i915_vma_pin(vma, + entry->pad_to_size, entry->alignment, + pin_flags); if (err) return err; @@ -560,7 +561,7 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, eb->args->flags |= __EXEC_HAS_RELOC; } - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { err = i915_vma_get_fence(vma); if (unlikely(err)) { i915_vma_unpin(vma); @@ -568,11 +569,11 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, } if (i915_vma_pin_fence(vma)) - entry->flags |= __EXEC_OBJECT_HAS_FENCE; + exec_flags |= __EXEC_OBJECT_HAS_FENCE; } - entry->flags |= __EXEC_OBJECT_HAS_PIN; - GEM_BUG_ON(eb_vma_misplaced(entry, vma)); + *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN; + GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags)); return 0; } @@ -614,18 +615,18 @@ static int eb_reserve(struct i915_execbuffer *eb) INIT_LIST_HEAD(&eb->unbound); INIT_LIST_HEAD(&last); for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; - if (entry->flags & EXEC_OBJECT_PINNED && - entry->flags & __EXEC_OBJECT_HAS_PIN) + if (flags & EXEC_OBJECT_PINNED && + flags & __EXEC_OBJECT_HAS_PIN) continue; - vma = exec_to_vma(entry); - eb_unreserve_vma(vma, entry); + eb_unreserve_vma(vma, &eb->flags[i]); - if (entry->flags & EXEC_OBJECT_PINNED) + if (flags & EXEC_OBJECT_PINNED) list_add(&vma->exec_link, &eb->unbound); - else if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) + else if (flags & __EXEC_OBJECT_NEEDS_MAP) list_add_tail(&vma->exec_link, &eb->unbound); else list_add_tail(&vma->exec_link, &last); @@ -649,19 +650,6 @@ static int eb_reserve(struct i915_execbuffer *eb) } while (1); } -static inline struct hlist_head * -ht_head(const struct i915_gem_context_vma_lut *lut, u32 handle) -{ - return &lut->ht[hash_32(handle, lut->ht_bits)]; -} - -static inline bool -ht_needs_resize(const struct i915_gem_context_vma_lut *lut) -{ - return (4*lut->ht_count > 3*lut->ht_size || - 4*lut->ht_count + 1 < lut->ht_size); -} - static unsigned int eb_batch_index(const struct i915_execbuffer *eb) { if (eb->args->flags & I915_EXEC_BATCH_FIRST) @@ -678,13 +666,6 @@ static int eb_select_context(struct i915_execbuffer *eb) if (unlikely(!ctx)) return -ENOENT; - if (unlikely(i915_gem_context_is_banned(ctx))) { - DRM_DEBUG("Context %u tried to submit while banned\n", - ctx->user_handle); - i915_gem_context_put(ctx); - return -EIO; - } - eb->ctx = ctx; eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base; @@ -697,132 +678,75 @@ static int eb_select_context(struct i915_execbuffer *eb) static int eb_lookup_vmas(struct i915_execbuffer *eb) { -#define INTERMEDIATE BIT(0) - const unsigned int count = eb->buffer_count; - struct i915_gem_context_vma_lut *lut = &eb->ctx->vma_lut; - struct i915_vma *vma; - struct idr *idr; + struct radix_tree_root *handles_vma = &eb->ctx->handles_vma; + struct drm_i915_gem_object *uninitialized_var(obj); unsigned int i; - int slow_pass = -1; int err; - INIT_LIST_HEAD(&eb->relocs); - INIT_LIST_HEAD(&eb->unbound); - - if (unlikely(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)) - flush_work(&lut->resize); - GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); - - for (i = 0; i < count; i++) { - __exec_to_vma(&eb->exec[i]) = 0; - - hlist_for_each_entry(vma, - ht_head(lut, eb->exec[i].handle), - ctx_node) { - if (vma->ctx_handle != eb->exec[i].handle) - continue; - - err = eb_add_vma(eb, &eb->exec[i], vma); - if (unlikely(err)) - return err; - - goto next_vma; - } + if (unlikely(i915_gem_context_is_closed(eb->ctx))) + return -ENOENT; - if (slow_pass < 0) - slow_pass = i; -next_vma: ; - } + if (unlikely(i915_gem_context_is_banned(eb->ctx))) + return -EIO; - if (slow_pass < 0) - goto out; + INIT_LIST_HEAD(&eb->relocs); + INIT_LIST_HEAD(&eb->unbound); - spin_lock(&eb->file->table_lock); - /* - * Grab a reference to the object and release the lock so we can lookup - * or create the VMA without using GFP_ATOMIC - */ - idr = &eb->file->object_idr; - for (i = slow_pass; i < count; i++) { - struct drm_i915_gem_object *obj; + for (i = 0; i < eb->buffer_count; i++) { + u32 handle = eb->exec[i].handle; + struct i915_lut_handle *lut; + struct i915_vma *vma; - if (__exec_to_vma(&eb->exec[i])) - continue; + vma = radix_tree_lookup(handles_vma, handle); + if (likely(vma)) + goto add_vma; - obj = to_intel_bo(idr_find(idr, eb->exec[i].handle)); + obj = i915_gem_object_lookup(eb->file, handle); if (unlikely(!obj)) { - spin_unlock(&eb->file->table_lock); - DRM_DEBUG("Invalid object handle %d at index %d\n", - eb->exec[i].handle, i); err = -ENOENT; - goto err; + goto err_vma; } - __exec_to_vma(&eb->exec[i]) = INTERMEDIATE | (uintptr_t)obj; - } - spin_unlock(&eb->file->table_lock); - - for (i = slow_pass; i < count; i++) { - struct drm_i915_gem_object *obj; - - if (!(__exec_to_vma(&eb->exec[i]) & INTERMEDIATE)) - continue; - - /* - * NOTE: We can leak any vmas created here when something fails - * later on. But that's no issue since vma_unbind can deal with - * vmas which are not actually bound. And since only - * lookup_or_create exists as an interface to get at the vma - * from the (obj, vm) we don't run the risk of creating - * duplicated vmas for the same vm. - */ - obj = u64_to_ptr(typeof(*obj), - __exec_to_vma(&eb->exec[i]) & ~INTERMEDIATE); vma = i915_vma_instance(obj, eb->vm, NULL); if (unlikely(IS_ERR(vma))) { - DRM_DEBUG("Failed to lookup VMA\n"); err = PTR_ERR(vma); - goto err; + goto err_obj; } - /* First come, first served */ - if (!vma->ctx) { - vma->ctx = eb->ctx; - vma->ctx_handle = eb->exec[i].handle; - hlist_add_head(&vma->ctx_node, - ht_head(lut, eb->exec[i].handle)); - lut->ht_count++; - lut->ht_size |= I915_CTX_RESIZE_IN_PROGRESS; - if (i915_vma_is_ggtt(vma)) { - GEM_BUG_ON(obj->vma_hashed); - obj->vma_hashed = vma; - } + lut = kmem_cache_alloc(eb->i915->luts, GFP_KERNEL); + if (unlikely(!lut)) { + err = -ENOMEM; + goto err_obj; + } - i915_vma_get(vma); + err = radix_tree_insert(handles_vma, handle, vma); + if (unlikely(err)) { + kfree(lut); + goto err_obj; } - err = eb_add_vma(eb, &eb->exec[i], vma); - if (unlikely(err)) - goto err; + vma->open_count++; + list_add(&lut->obj_link, &obj->lut_list); + list_add(&lut->ctx_link, &eb->ctx->handles_list); + lut->ctx = eb->ctx; + lut->handle = handle; - /* Only after we validated the user didn't use our bits */ - if (vma->ctx != eb->ctx) { - i915_vma_get(vma); - eb->exec[i].flags |= __EXEC_OBJECT_HAS_REF; - } - } + /* transfer ref to ctx */ + obj = NULL; - if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) { - if (ht_needs_resize(lut)) - queue_work(system_highpri_wq, &lut->resize); - else - lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; +add_vma: + err = eb_add_vma(eb, i, vma); + if (unlikely(err)) + goto err_obj; + + GEM_BUG_ON(vma != eb->vma[i]); + GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); } -out: /* take note of the batch buffer before we might reorder the lists */ i = eb_batch_index(eb); - eb->batch = exec_to_vma(&eb->exec[i]); + eb->batch = eb->vma[i]; + GEM_BUG_ON(eb->batch->exec_flags != &eb->flags[i]); /* * SNA is doing fancy tricks with compressing batch buffers, which leads @@ -833,22 +757,20 @@ out: * Note that actual hangs have only been observed on gen7, but for * paranoia do it everywhere. */ - if (!(eb->exec[i].flags & EXEC_OBJECT_PINNED)) - eb->exec[i].flags |= __EXEC_OBJECT_NEEDS_BIAS; + if (!(eb->flags[i] & EXEC_OBJECT_PINNED)) + eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS; if (eb->reloc_cache.has_fence) - eb->exec[i].flags |= EXEC_OBJECT_NEEDS_FENCE; + eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE; eb->args->flags |= __EXEC_VALIDATED; return eb_reserve(eb); -err: - for (i = slow_pass; i < count; i++) { - if (__exec_to_vma(&eb->exec[i]) & INTERMEDIATE) - __exec_to_vma(&eb->exec[i]) = 0; - } - lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; +err_obj: + if (obj) + i915_gem_object_put(obj); +err_vma: + eb->vma[i] = NULL; return err; -#undef INTERMEDIATE } static struct i915_vma * @@ -857,7 +779,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) if (eb->lut_size < 0) { if (handle >= -eb->lut_size) return NULL; - return exec_to_vma(&eb->exec[handle]); + return eb->vma[handle]; } else { struct hlist_head *head; struct i915_vma *vma; @@ -877,24 +799,21 @@ static void eb_release_vmas(const struct i915_execbuffer *eb) unsigned int i; for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + struct i915_vma *vma = eb->vma[i]; + unsigned int flags = eb->flags[i]; if (!vma) - continue; + break; - GEM_BUG_ON(vma->exec_entry != entry); - vma->exec_entry = NULL; - __exec_to_vma(entry) = 0; + GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); + vma->exec_flags = NULL; + eb->vma[i] = NULL; - if (entry->flags & __EXEC_OBJECT_HAS_PIN) - __eb_unreserve_vma(vma, entry); + if (flags & __EXEC_OBJECT_HAS_PIN) + __eb_unreserve_vma(vma, flags); - if (entry->flags & __EXEC_OBJECT_HAS_REF) + if (flags & __EXEC_OBJECT_HAS_REF) i915_vma_put(vma); - - entry->flags &= - ~(__EXEC_OBJECT_RESERVED | __EXEC_OBJECT_HAS_REF); } } @@ -1157,7 +1076,9 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, return PTR_ERR(obj); cmd = i915_gem_object_pin_map(obj, - cache->has_llc ? I915_MAP_WB : I915_MAP_WC); + cache->has_llc ? + I915_MAP_FORCE_WB : + I915_MAP_FORCE_WC); i915_gem_object_unpin_pages(obj); if (IS_ERR(cmd)) return PTR_ERR(cmd); @@ -1243,6 +1164,13 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, if (unlikely(!cache->rq)) { int err; + /* If we need to copy for the cmdparser, we will stall anyway */ + if (eb_use_cmdparser(eb)) + return ERR_PTR(-EWOULDBLOCK); + + if (!intel_engine_can_store_dword(eb->engine)) + return ERR_PTR(-ENODEV); + err = __reloc_gpu_alloc(eb, vma, len); if (unlikely(err)) return ERR_PTR(err); @@ -1277,10 +1205,8 @@ relocate_entry(struct i915_vma *vma, len = offset & 7 ? 8 : 5; else if (gen >= 4) len = 4; - else if (gen >= 3) + else len = 3; - else /* On gen2 MI_STORE_DWORD_IMM uses a physical address */ - goto repeat; batch = reloc_gpu(eb, vma, len); if (IS_ERR(batch)) @@ -1383,7 +1309,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, } if (reloc->write_domain) { - target->exec_entry->flags |= EXEC_OBJECT_WRITE; + *target->exec_flags |= EXEC_OBJECT_WRITE; /* * Sandybridge PPGTT errata: We need a global gtt mapping @@ -1433,9 +1359,9 @@ eb_relocate_entry(struct i915_execbuffer *eb, * patching using the GPU (though that should be serialised by the * timeline). To be completely sure, and since we are required to * do relocations we are already stalling, disable the user's opt - * of our synchronisation. + * out of our synchronisation. */ - vma->exec_entry->flags &= ~EXEC_OBJECT_ASYNC; + *vma->exec_flags &= ~EXEC_OBJECT_ASYNC; /* and update the user's relocation entry */ return relocate_entry(vma, reloc, eb, target); @@ -1446,7 +1372,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma) #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; struct drm_i915_gem_relocation_entry __user *urelocs; - const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; + const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); unsigned int remain; urelocs = u64_to_user_ptr(entry->relocs_ptr); @@ -1529,7 +1455,7 @@ out: static int eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma) { - const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; + const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); struct drm_i915_gem_relocation_entry *relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); unsigned int i; @@ -1599,7 +1525,7 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb) urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr); size = nreloc * sizeof(*relocs); - relocs = kvmalloc_array(size, 1, GFP_TEMPORARY); + relocs = kvmalloc_array(size, 1, GFP_KERNEL); if (!relocs) { kvfree(relocs); err = -ENOMEM; @@ -1613,7 +1539,7 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb) min_t(u64, BIT_ULL(31), size - copied); if (__copy_from_user((char *)relocs + copied, - (char *)urelocs + copied, + (char __user *)urelocs + copied, len)) { kvfree(relocs); err = -EFAULT; @@ -1733,6 +1659,8 @@ repeat: if (err) goto err; + GEM_BUG_ON(!eb->batch); + list_for_each_entry(vma, &eb->relocs, reloc_link) { if (!have_copy) { pagefault_disable(); @@ -1826,11 +1754,11 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) int err; for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; struct drm_i915_gem_object *obj = vma->obj; - if (entry->flags & EXEC_OBJECT_CAPTURE) { + if (flags & EXEC_OBJECT_CAPTURE) { struct i915_gem_capture_list *capture; capture = kmalloc(sizeof(*capture), GFP_KERNEL); @@ -1838,35 +1766,47 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) return -ENOMEM; capture->next = eb->request->capture_list; - capture->vma = vma; + capture->vma = eb->vma[i]; eb->request->capture_list = capture; } - if (unlikely(obj->cache_dirty && !obj->cache_coherent)) { + /* + * If the GPU is not _reading_ through the CPU cache, we need + * to make sure that any writes (both previous GPU writes from + * before a change in snooping levels and normal CPU writes) + * caught in that cache are flushed to main memory. + * + * We want to say + * obj->cache_dirty && + * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) + * but gcc's optimiser doesn't handle that as well and emits + * two jumps instead of one. Maybe one day... + */ + if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) { if (i915_gem_clflush_object(obj, 0)) - entry->flags &= ~EXEC_OBJECT_ASYNC; + flags &= ~EXEC_OBJECT_ASYNC; } - if (entry->flags & EXEC_OBJECT_ASYNC) - goto skip_flushes; + if (flags & EXEC_OBJECT_ASYNC) + continue; err = i915_gem_request_await_object - (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE); + (eb->request, obj, flags & EXEC_OBJECT_WRITE); if (err) return err; - -skip_flushes: - i915_vma_move_to_active(vma, eb->request, entry->flags); - __eb_unreserve_vma(vma, entry); - vma->exec_entry = NULL; } for (i = 0; i < count; i++) { - const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; - eb_export_fence(vma, eb->request, entry->flags); - if (unlikely(entry->flags & __EXEC_OBJECT_HAS_REF)) + i915_vma_move_to_active(vma, eb->request, flags); + eb_export_fence(vma, eb->request, flags); + + __eb_unreserve_vma(vma, flags); + vma->exec_flags = NULL; + + if (unlikely(flags & __EXEC_OBJECT_HAS_REF)) i915_vma_put(vma); } eb->exec = NULL; @@ -1884,8 +1824,10 @@ static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) return false; /* Kernel clipping was a DRI1 misfeature */ - if (exec->num_cliprects || exec->cliprects_ptr) - return false; + if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) { + if (exec->num_cliprects || exec->cliprects_ptr) + return false; + } if (exec->DR4 == 0xffffffff) { DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); @@ -1993,11 +1935,11 @@ static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master) if (IS_ERR(vma)) goto out; - vma->exec_entry = - memset(&eb->exec[eb->buffer_count++], - 0, sizeof(*vma->exec_entry)); - vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF; - __exec_to_vma(vma->exec_entry) = (uintptr_t)i915_vma_get(vma); + eb->vma[eb->buffer_count] = i915_vma_get(vma); + eb->flags[eb->buffer_count] = + __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF; + vma->exec_flags = &eb->flags[eb->buffer_count]; + eb->buffer_count++; out: i915_gem_object_unpin_pages(shadow_batch_obj); @@ -2116,11 +2058,129 @@ eb_select_engine(struct drm_i915_private *dev_priv, return engine; } +static void +__free_fence_array(struct drm_syncobj **fences, unsigned int n) +{ + while (n--) + drm_syncobj_put(ptr_mask_bits(fences[n], 2)); + kvfree(fences); +} + +static struct drm_syncobj ** +get_fence_array(struct drm_i915_gem_execbuffer2 *args, + struct drm_file *file) +{ + const unsigned int nfences = args->num_cliprects; + struct drm_i915_gem_exec_fence __user *user; + struct drm_syncobj **fences; + unsigned int n; + int err; + + if (!(args->flags & I915_EXEC_FENCE_ARRAY)) + return NULL; + + if (nfences > SIZE_MAX / sizeof(*fences)) + return ERR_PTR(-EINVAL); + + user = u64_to_user_ptr(args->cliprects_ptr); + if (!access_ok(VERIFY_READ, user, nfences * 2 * sizeof(u32))) + return ERR_PTR(-EFAULT); + + fences = kvmalloc_array(args->num_cliprects, sizeof(*fences), + __GFP_NOWARN | GFP_KERNEL); + if (!fences) + return ERR_PTR(-ENOMEM); + + for (n = 0; n < nfences; n++) { + struct drm_i915_gem_exec_fence fence; + struct drm_syncobj *syncobj; + + if (__copy_from_user(&fence, user++, sizeof(fence))) { + err = -EFAULT; + goto err; + } + + syncobj = drm_syncobj_find(file, fence.handle); + if (!syncobj) { + DRM_DEBUG("Invalid syncobj handle provided\n"); + err = -ENOENT; + goto err; + } + + fences[n] = ptr_pack_bits(syncobj, fence.flags, 2); + } + + return fences; + +err: + __free_fence_array(fences, n); + return ERR_PTR(err); +} + +static void +put_fence_array(struct drm_i915_gem_execbuffer2 *args, + struct drm_syncobj **fences) +{ + if (fences) + __free_fence_array(fences, args->num_cliprects); +} + +static int +await_fence_array(struct i915_execbuffer *eb, + struct drm_syncobj **fences) +{ + const unsigned int nfences = eb->args->num_cliprects; + unsigned int n; + int err; + + for (n = 0; n < nfences; n++) { + struct drm_syncobj *syncobj; + struct dma_fence *fence; + unsigned int flags; + + syncobj = ptr_unpack_bits(fences[n], &flags, 2); + if (!(flags & I915_EXEC_FENCE_WAIT)) + continue; + + fence = drm_syncobj_fence_get(syncobj); + if (!fence) + return -EINVAL; + + err = i915_gem_request_await_dma_fence(eb->request, fence); + dma_fence_put(fence); + if (err < 0) + return err; + } + + return 0; +} + +static void +signal_fence_array(struct i915_execbuffer *eb, + struct drm_syncobj **fences) +{ + const unsigned int nfences = eb->args->num_cliprects; + struct dma_fence * const fence = &eb->request->fence; + unsigned int n; + + for (n = 0; n < nfences; n++) { + struct drm_syncobj *syncobj; + unsigned int flags; + + syncobj = ptr_unpack_bits(fences[n], &flags, 2); + if (!(flags & I915_EXEC_FENCE_SIGNAL)) + continue; + + drm_syncobj_replace_fence(syncobj, fence); + } +} + static int i915_gem_do_execbuffer(struct drm_device *dev, struct drm_file *file, struct drm_i915_gem_execbuffer2 *args, - struct drm_i915_gem_exec_object2 *exec) + struct drm_i915_gem_exec_object2 *exec, + struct drm_syncobj **fences) { struct i915_execbuffer eb; struct dma_fence *in_fence = NULL; @@ -2136,7 +2196,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.args = args; if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) args->flags |= __EXEC_HAS_RELOC; + eb.exec = exec; + eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1); + eb.vma[0] = NULL; + eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1); + eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; if (USES_FULL_PPGTT(eb.i915)) eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT; @@ -2224,7 +2289,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } - if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) { + if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) { DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); err = -EINVAL; goto err_vma; @@ -2236,7 +2301,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } - if (eb.engine->needs_cmd_parser && eb.batch_len) { + if (eb_use_cmdparser(&eb)) { struct i915_vma *vma; vma = eb_parse(&eb, drm_is_current_master(file)); @@ -2306,6 +2371,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_request; } + if (fences) { + err = await_fence_array(&eb, fences); + if (err) + goto err_request; + } + if (out_fence_fd != -1) { out_fence = sync_file_create(&eb.request->fence); if (!out_fence) { @@ -2329,6 +2400,9 @@ err_request: __i915_add_request(eb.request, err == 0); add_to_client(eb.request, file); + if (fences) + signal_fence_array(&eb, fences); + if (out_fence) { if (err == 0) { fd_install(out_fence_fd, out_fence->file); @@ -2368,7 +2442,9 @@ int i915_gem_execbuffer(struct drm_device *dev, void *data, struct drm_file *file) { - const size_t sz = sizeof(struct drm_i915_gem_exec_object2); + const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) + + sizeof(struct i915_vma *) + + sizeof(unsigned int)); struct drm_i915_gem_execbuffer *args = data; struct drm_i915_gem_execbuffer2 exec2; struct drm_i915_gem_exec_object *exec_list = NULL; @@ -2397,9 +2473,9 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, /* Copy in the exec list from userland */ exec_list = kvmalloc_array(args->buffer_count, sizeof(*exec_list), - __GFP_NOWARN | GFP_TEMPORARY); + __GFP_NOWARN | GFP_KERNEL); exec2_list = kvmalloc_array(args->buffer_count + 1, sz, - __GFP_NOWARN | GFP_TEMPORARY); + __GFP_NOWARN | GFP_KERNEL); if (exec_list == NULL || exec2_list == NULL) { DRM_DEBUG("Failed to allocate exec list for %d buffers\n", args->buffer_count); @@ -2430,7 +2506,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, exec2_list[i].flags = 0; } - err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list); + err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL); if (exec2.flags & __EXEC_HAS_RELOC) { struct drm_i915_gem_exec_object __user *user_exec_list = u64_to_user_ptr(args->buffers_ptr); @@ -2459,9 +2535,12 @@ int i915_gem_execbuffer2(struct drm_device *dev, void *data, struct drm_file *file) { - const size_t sz = sizeof(struct drm_i915_gem_exec_object2); + const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) + + sizeof(struct i915_vma *) + + sizeof(unsigned int)); struct drm_i915_gem_execbuffer2 *args = data; struct drm_i915_gem_exec_object2 *exec2_list; + struct drm_syncobj **fences = NULL; int err; if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) { @@ -2474,7 +2553,7 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, /* Allocate an extra slot for use by the command parser */ exec2_list = kvmalloc_array(args->buffer_count + 1, sz, - __GFP_NOWARN | GFP_TEMPORARY); + __GFP_NOWARN | GFP_KERNEL); if (exec2_list == NULL) { DRM_DEBUG("Failed to allocate exec list for %d buffers\n", args->buffer_count); @@ -2488,7 +2567,15 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, return -EFAULT; } - err = i915_gem_do_execbuffer(dev, file, args, exec2_list); + if (args->flags & I915_EXEC_FENCE_ARRAY) { + fences = get_fence_array(args, file); + if (IS_ERR(fences)) { + kvfree(exec2_list); + return PTR_ERR(fences); + } + } + + err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences); /* * Now that we have begun execution of the batchbuffer, we ignore @@ -2518,6 +2605,7 @@ end_user: } args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS; + put_fence_array(args, fences); kvfree(exec2_list); return err; } diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 5fe2cd8c8f28..2783d63bd1ad 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -360,6 +360,57 @@ i915_vma_get_fence(struct i915_vma *vma) } /** + * i915_reserve_fence - Reserve a fence for vGPU + * @dev_priv: i915 device private + * + * This function walks the fence regs looking for a free one and remove + * it from the fence_list. It is used to reserve fence for vGPU to use. + */ +struct drm_i915_fence_reg * +i915_reserve_fence(struct drm_i915_private *dev_priv) +{ + struct drm_i915_fence_reg *fence; + int count; + int ret; + + lockdep_assert_held(&dev_priv->drm.struct_mutex); + + /* Keep at least one fence available for the display engine. */ + count = 0; + list_for_each_entry(fence, &dev_priv->mm.fence_list, link) + count += !fence->pin_count; + if (count <= 1) + return ERR_PTR(-ENOSPC); + + fence = fence_find(dev_priv); + if (IS_ERR(fence)) + return fence; + + if (fence->vma) { + /* Force-remove fence from VMA */ + ret = fence_update(fence, NULL); + if (ret) + return ERR_PTR(ret); + } + + list_del(&fence->link); + return fence; +} + +/** + * i915_unreserve_fence - Reclaim a reserved fence + * @fence: the fence reg + * + * This function add a reserved fence register from vGPU to the fence_list. + */ +void i915_unreserve_fence(struct drm_i915_fence_reg *fence) +{ + lockdep_assert_held(&fence->i915->drm.struct_mutex); + + list_add(&fence->link, &fence->i915->mm.fence_list); +} + +/** * i915_gem_revoke_fences - revoke fence state * @dev_priv: i915 device private * diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 10aa7762d9a6..40d446ba0b85 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -144,9 +144,9 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; if (intel_vgpu_active(dev_priv)) { - /* emulation is too hard */ + /* GVT-g has no support for 32bit ppgtt */ has_full_ppgtt = false; - has_full_48bit_ppgtt = false; + has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv); } if (!has_aliasing_ppgtt) @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, return 0; } - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) - return has_full_48bit_ppgtt ? 3 : 2; - else - return has_aliasing_ppgtt ? 1 : 0; + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { + if (has_full_48bit_ppgtt) + return 3; + + if (has_full_ppgtt) + return 2; + } + + return has_aliasing_ppgtt ? 1 : 0; } static int ppgtt_bind_vma(struct i915_vma *vma, @@ -351,39 +356,86 @@ static gen6_pte_t iris_pte_encode(dma_addr_t addr, static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp) { - struct page *page; + struct pagevec *pvec = &vm->free_pages; if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) i915_gem_shrink_all(vm->i915); - if (vm->free_pages.nr) - return vm->free_pages.pages[--vm->free_pages.nr]; + if (likely(pvec->nr)) + return pvec->pages[--pvec->nr]; + + if (!vm->pt_kmap_wc) + return alloc_page(gfp); + + /* A placeholder for a specific mutex to guard the WC stash */ + lockdep_assert_held(&vm->i915->drm.struct_mutex); + + /* Look in our global stash of WC pages... */ + pvec = &vm->i915->mm.wc_stash; + if (likely(pvec->nr)) + return pvec->pages[--pvec->nr]; + + /* Otherwise batch allocate pages to amoritize cost of set_pages_wc. */ + do { + struct page *page; - page = alloc_page(gfp); - if (!page) + page = alloc_page(gfp); + if (unlikely(!page)) + break; + + pvec->pages[pvec->nr++] = page; + } while (pagevec_space(pvec)); + + if (unlikely(!pvec->nr)) return NULL; - if (vm->pt_kmap_wc) - set_pages_array_wc(&page, 1); + set_pages_array_wc(pvec->pages, pvec->nr); - return page; + return pvec->pages[--pvec->nr]; } -static void vm_free_pages_release(struct i915_address_space *vm) +static void vm_free_pages_release(struct i915_address_space *vm, + bool immediate) { - GEM_BUG_ON(!pagevec_count(&vm->free_pages)); + struct pagevec *pvec = &vm->free_pages; + + GEM_BUG_ON(!pagevec_count(pvec)); - if (vm->pt_kmap_wc) - set_pages_array_wb(vm->free_pages.pages, - pagevec_count(&vm->free_pages)); + if (vm->pt_kmap_wc) { + struct pagevec *stash = &vm->i915->mm.wc_stash; - __pagevec_release(&vm->free_pages); + /* When we use WC, first fill up the global stash and then + * only if full immediately free the overflow. + */ + + lockdep_assert_held(&vm->i915->drm.struct_mutex); + if (pagevec_space(stash)) { + do { + stash->pages[stash->nr++] = + pvec->pages[--pvec->nr]; + if (!pvec->nr) + return; + } while (pagevec_space(stash)); + + /* As we have made some room in the VM's free_pages, + * we can wait for it to fill again. Unless we are + * inside i915_address_space_fini() and must + * immediately release the pages! + */ + if (!immediate) + return; + } + + set_pages_array_wb(pvec->pages, pvec->nr); + } + + __pagevec_release(pvec); } static void vm_free_page(struct i915_address_space *vm, struct page *page) { if (!pagevec_add(&vm->free_pages, page)) - vm_free_pages_release(vm); + vm_free_pages_release(vm, false); } static int __setup_page_dma(struct i915_address_space *vm, @@ -447,12 +499,31 @@ static void fill_page_dma_32(struct i915_address_space *vm, static int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) { - return __setup_page_dma(vm, &vm->scratch_page, gfp | __GFP_ZERO); + struct page *page; + dma_addr_t addr; + + page = alloc_page(gfp | __GFP_ZERO); + if (unlikely(!page)) + return -ENOMEM; + + addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE, + PCI_DMA_BIDIRECTIONAL); + if (unlikely(dma_mapping_error(vm->dma, addr))) { + __free_page(page); + return -ENOMEM; + } + + vm->scratch_page.page = page; + vm->scratch_page.daddr = addr; + return 0; } static void cleanup_scratch_page(struct i915_address_space *vm) { - cleanup_page_dma(vm, &vm->scratch_page); + struct i915_page_dma *p = &vm->scratch_page; + + dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + __free_page(p->page); } static struct i915_page_table *alloc_pt(struct i915_address_space *vm) @@ -1332,18 +1403,18 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 1ULL << 48 : 1ULL << 32; - ret = gen8_init_scratch(&ppgtt->base); - if (ret) { - ppgtt->base.total = 0; - return ret; - } - /* There are only few exceptions for gen >=6. chv and bxt. * And we are not sure about the latter so play safe for now. */ if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) ppgtt->base.pt_kmap_wc = true; + ret = gen8_init_scratch(&ppgtt->base); + if (ret) { + ppgtt->base.total = 0; + return ret; + } + if (use_4lvl(vm)) { ret = setup_px(&ppgtt->base, &ppgtt->pml4); if (ret) @@ -1867,7 +1938,7 @@ static void i915_address_space_init(struct i915_address_space *vm, static void i915_address_space_fini(struct i915_address_space *vm) { if (pagevec_count(&vm->free_pages)) - vm_free_pages_release(vm); + vm_free_pages_release(vm, true); i915_gem_timeline_fini(&vm->timeline); drm_mm_takedown(&vm->mm); @@ -1880,12 +1951,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) * called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. */ - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */ + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */ if (IS_BROADWELL(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); else if (IS_CHERRYVIEW(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); - else if (IS_GEN9_BC(dev_priv)) + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); else if (IS_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); @@ -2057,7 +2128,7 @@ int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, */ GEM_BUG_ON(obj->mm.pages == pages); } while (i915_gem_shrink(to_i915(obj->base.dev), - obj->base.size >> PAGE_SHIFT, + obj->base.size >> PAGE_SHIFT, NULL, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_ACTIVE)); @@ -2593,6 +2664,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) { struct i915_ggtt *ggtt = &dev_priv->ggtt; struct i915_vma *vma, *vn; + struct pagevec *pvec; ggtt->base.closed = true; @@ -2616,6 +2688,13 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) } ggtt->base.cleanup(&ggtt->base); + + pvec = &dev_priv->mm.wc_stash; + if (pvec->nr) { + set_pages_array_wb(pvec->pages, pvec->nr); + __pagevec_release(pvec); + } + mutex_unlock(&dev_priv->drm.struct_mutex); arch_phys_wc_del(ggtt->mtrr); @@ -2711,13 +2790,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; /* - * On BXT writes larger than 64 bit to the GTT pagetable range will be - * dropped. For WC mappings in general we have 64 byte burst writes - * when the WC buffer is flushed, so we can't use it, but have to + * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range + * will be dropped. For WC mappings in general we have 64 byte burst + * writes when the WC buffer is flushed, so we can't use it, but have to * resort to an uncached mapping. The WC issue is easily caught by the * readback check when writing GTT PTE entries. */ - if (IS_GEN9_LP(dev_priv)) + if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) ggtt->gsm = ioremap_nocache(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size); @@ -2737,6 +2816,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return 0; } +static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv) +{ + /* XXX: spec is unclear if this is still needed for CNL+ */ + if (!USES_PPGTT(dev_priv)) { + I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC); + return; + } + + I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC); + I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); + I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); + I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC); + I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); + I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); + I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); + I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); +} + /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability * bits. When using advanced contexts each context stores its own PAT, but * writing this data shouldn't be harmful even in those cases. */ @@ -2851,7 +2948,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; - if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + cnl_setup_private_ppat(dev_priv); + else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); @@ -3133,7 +3232,9 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) ggtt->base.closed = false; if (INTEL_GEN(dev_priv) >= 8) { - if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + cnl_setup_private_ppat(dev_priv); + else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); @@ -3204,7 +3305,7 @@ intel_rotate_pages(struct intel_rotation_info *rot_info, /* Allocate a temporary list of source pages for random access. */ page_addr_list = kvmalloc_array(n_pages, sizeof(dma_addr_t), - GFP_TEMPORARY); + GFP_KERNEL); if (!page_addr_list) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c b/drivers/gpu/drm/i915/i915_gem_internal.c index 568bf83af1f5..c1f64ddaf8aa 100644 --- a/drivers/gpu/drm/i915/i915_gem_internal.c +++ b/drivers/gpu/drm/i915/i915_gem_internal.c @@ -174,6 +174,7 @@ i915_gem_object_create_internal(struct drm_i915_private *i915, phys_addr_t size) { struct drm_i915_gem_object *obj; + unsigned int cache_level; GEM_BUG_ON(!size); GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE)); @@ -190,9 +191,9 @@ i915_gem_object_create_internal(struct drm_i915_private *i915, obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); return obj; } diff --git a/drivers/gpu/drm/i915/i915_gem_object.c b/drivers/gpu/drm/i915/i915_gem_object.c new file mode 100644 index 000000000000..aab8cdd80e6d --- /dev/null +++ b/drivers/gpu/drm/i915/i915_gem_object.c @@ -0,0 +1,48 @@ +/* + * Copyright © 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include "i915_drv.h" +#include "i915_gem_object.h" + +/** + * Mark up the object's coherency levels for a given cache_level + * @obj: #drm_i915_gem_object + * @cache_level: cache level + */ +void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, + unsigned int cache_level) +{ + obj->cache_level = cache_level; + + if (cache_level != I915_CACHE_NONE) + obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ | + I915_BO_CACHE_COHERENT_FOR_WRITE); + else if (HAS_LLC(to_i915(obj->base.dev))) + obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ; + else + obj->cache_coherent = 0; + + obj->cache_dirty = + !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE); +} diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h index 5b19a4916a4d..c30d8f808185 100644 --- a/drivers/gpu/drm/i915/i915_gem_object.h +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -33,8 +33,24 @@ #include <drm/i915_drm.h> +#include "i915_gem_request.h" #include "i915_selftest.h" +struct drm_i915_gem_object; + +/* + * struct i915_lut_handle tracks the fast lookups from handle to vma used + * for execbuf. Although we use a radixtree for that mapping, in order to + * remove them as the object or context is closed, we need a secondary list + * and a translation entry (i915_lut_handle). + */ +struct i915_lut_handle { + struct list_head obj_link; + struct list_head ctx_link; + struct i915_gem_context *ctx; + u32 handle; +}; + struct drm_i915_gem_object_ops { unsigned int flags; #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0) @@ -86,7 +102,15 @@ struct drm_i915_gem_object { * They are also added to @vma_list for easy iteration. */ struct rb_root vma_tree; - struct i915_vma *vma_hashed; + + /** + * @lut_list: List of vma lookup entries in use for this object. + * + * If this object is closed, we need to remove all of its VMA from + * the fast lookup index in associated contexts; @lut_list provides + * this translation from object to context->handles_vma. + */ + struct list_head lut_list; /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; @@ -118,8 +142,10 @@ struct drm_i915_gem_object { */ unsigned long gt_ro:1; unsigned int cache_level:3; + unsigned int cache_coherent:2; +#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) +#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) unsigned int cache_dirty:1; - unsigned int cache_coherent:1; atomic_t frontbuffer_bits; unsigned int frontbuffer_ggtt_origin; /* write once */ @@ -391,6 +417,8 @@ i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) return engine; } +void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, + unsigned int cache_level); void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj); #endif diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 7032c542a9b1..4dd4c2159a92 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *req) goto err_unpin; } + ret = req->engine->emit_flush(req, EMIT_INVALIDATE); + if (ret) + goto err_unpin; + ret = req->engine->emit_bb_start(req, so->batch_offset, so->batch_size, I915_DISPATCH_SECURE); diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 483af8921060..813a3b546d6e 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -213,6 +213,10 @@ static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) cond_resched(); } + /* Check we are idle before we fiddle with hw state! */ + GEM_BUG_ON(!intel_engine_is_idle(engine)); + GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request)); + /* Finally reset hw state */ intel_engine_init_global_seqno(engine, seqno); tl->seqno = seqno; @@ -240,27 +244,60 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) return reset_all_global_seqno(dev_priv, seqno - 1); } -static int reserve_seqno(struct intel_engine_cs *engine) +static void mark_busy(struct drm_i915_private *i915) { + if (i915->gt.awake) + return; + + GEM_BUG_ON(!i915->gt.active_requests); + + intel_runtime_pm_get_noresume(i915); + i915->gt.awake = true; + + intel_enable_gt_powersave(i915); + i915_update_gfx_val(i915); + if (INTEL_GEN(i915) >= 6) + gen6_rps_busy(i915); + + queue_delayed_work(i915->wq, + &i915->gt.retire_work, + round_jiffies_up_relative(HZ)); +} + +static int reserve_engine(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; u32 active = ++engine->timeline->inflight_seqnos; u32 seqno = engine->timeline->seqno; int ret; /* Reservation is fine until we need to wrap around */ - if (likely(!add_overflows(seqno, active))) - return 0; - - ret = reset_all_global_seqno(engine->i915, 0); - if (ret) { - engine->timeline->inflight_seqnos--; - return ret; + if (unlikely(add_overflows(seqno, active))) { + ret = reset_all_global_seqno(i915, 0); + if (ret) { + engine->timeline->inflight_seqnos--; + return ret; + } } + if (!i915->gt.active_requests++) + mark_busy(i915); + return 0; } -static void unreserve_seqno(struct intel_engine_cs *engine) +static void unreserve_engine(struct intel_engine_cs *engine) { + struct drm_i915_private *i915 = engine->i915; + + if (!--i915->gt.active_requests) { + /* Cancel the mark_busy() from our reserve_engine() */ + GEM_BUG_ON(!i915->gt.awake); + mod_delayed_work(i915->wq, + &i915->gt.idle_work, + msecs_to_jiffies(100)); + } + GEM_BUG_ON(!engine->timeline->inflight_seqnos); engine->timeline->inflight_seqnos--; } @@ -329,13 +366,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) list_del_init(&request->link); spin_unlock_irq(&engine->timeline->lock); - if (!--request->i915->gt.active_requests) { - GEM_BUG_ON(!request->i915->gt.awake); - mod_delayed_work(request->i915->wq, - &request->i915->gt.idle_work, - msecs_to_jiffies(100)); - } - unreserve_seqno(request->engine); + unreserve_engine(request->engine); advance_ring(request); free_capture_list(request); @@ -370,8 +401,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) i915_gem_request_remove_from_client(request); /* Retirement decays the ban score as it is a sign of ctx progress */ - if (request->ctx->ban_score > 0) - request->ctx->ban_score--; + atomic_dec_if_positive(&request->ctx->ban_score); /* The backing object for the context is done after switching to the * *next* context. Therefore we cannot retire the previous context until @@ -572,7 +602,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, return ERR_CAST(ring); GEM_BUG_ON(!ring); - ret = reserve_seqno(engine); + ret = reserve_engine(engine); if (ret) goto err_unpin; @@ -678,7 +708,7 @@ err_ctx: kmem_cache_free(dev_priv->requests, req); err_unreserve: - unreserve_seqno(engine); + unreserve_engine(engine); err_unpin: engine->context_unpin(engine, ctx); return ERR_PTR(ret); @@ -860,28 +890,6 @@ i915_gem_request_await_object(struct drm_i915_gem_request *to, return ret; } -static void i915_gem_mark_busy(const struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; - - if (dev_priv->gt.awake) - return; - - GEM_BUG_ON(!dev_priv->gt.active_requests); - - intel_runtime_pm_get_noresume(dev_priv); - dev_priv->gt.awake = true; - - intel_enable_gt_powersave(dev_priv); - i915_update_gfx_val(dev_priv); - if (INTEL_GEN(dev_priv) >= 6) - gen6_rps_busy(dev_priv); - - queue_delayed_work(dev_priv->wq, - &dev_priv->gt.retire_work, - round_jiffies_up_relative(HZ)); -} - /* * NB: This function is not allowed to fail. Doing so would mean the the * request is not being tracked for completion but the work itself is @@ -963,9 +971,6 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) list_add_tail(&request->ring_link, &ring->request_list); request->emitted_jiffies = jiffies; - if (!request->i915->gt.active_requests++) - i915_gem_mark_busy(engine); - /* Let the backend know a new request has arrived that may need * to adjust the existing execution schedule due to a high priority * request - i.e. we may want to preempt the current request in order @@ -1068,7 +1073,7 @@ static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *req return false; __set_current_state(TASK_RUNNING); - i915_reset(request->i915); + i915_reset(request->i915, 0); return true; } diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index 77fb39808131..74002b2d1b6f 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -136,6 +136,7 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object *obj) * i915_gem_shrink - Shrink buffer object caches * @dev_priv: i915 device * @target: amount of memory to make available, in pages + * @nr_scanned: optional output for number of pages scanned (incremental) * @flags: control flags for selecting cache types * * This function is the main interface to the shrinker. It will try to release @@ -158,7 +159,9 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object *obj) */ unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, - unsigned long target, unsigned flags) + unsigned long target, + unsigned long *nr_scanned, + unsigned flags) { const struct { struct list_head *list; @@ -169,6 +172,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, { NULL, 0 }, }, *phase; unsigned long count = 0; + unsigned long scanned = 0; bool unlock; if (!shrinker_lock(dev_priv, &unlock)) @@ -249,6 +253,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, count += obj->base.size >> PAGE_SHIFT; } mutex_unlock(&obj->mm.lock); + scanned += obj->base.size >> PAGE_SHIFT; } } list_splice_tail(&still_in_list, phase->list); @@ -261,6 +266,8 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, shrinker_unlock(dev_priv, unlock); + if (nr_scanned) + *nr_scanned += scanned; return count; } @@ -283,7 +290,7 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv) unsigned long freed; intel_runtime_pm_get(dev_priv); - freed = i915_gem_shrink(dev_priv, -1UL, + freed = i915_gem_shrink(dev_priv, -1UL, NULL, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_ACTIVE); @@ -329,23 +336,28 @@ i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) unsigned long freed; bool unlock; + sc->nr_scanned = 0; + if (!shrinker_lock(dev_priv, &unlock)) return SHRINK_STOP; freed = i915_gem_shrink(dev_priv, sc->nr_to_scan, + &sc->nr_scanned, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE); if (freed < sc->nr_to_scan) freed += i915_gem_shrink(dev_priv, - sc->nr_to_scan - freed, + sc->nr_to_scan - sc->nr_scanned, + &sc->nr_scanned, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); if (freed < sc->nr_to_scan && current_is_kswapd()) { intel_runtime_pm_get(dev_priv); freed += i915_gem_shrink(dev_priv, - sc->nr_to_scan - freed, + sc->nr_to_scan - sc->nr_scanned, + &sc->nr_scanned, I915_SHRINK_ACTIVE | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); @@ -354,7 +366,7 @@ i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) shrinker_unlock(dev_priv, unlock); - return freed; + return sc->nr_scanned ? freed : SHRINK_STOP; } static bool @@ -453,7 +465,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr goto out; intel_runtime_pm_get(dev_priv); - freed_pages += i915_gem_shrink(dev_priv, -1UL, + freed_pages += i915_gem_shrink(dev_priv, -1UL, NULL, I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_ACTIVE | diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index a817b3e0b17e..507c9f0d8df1 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -254,9 +254,10 @@ static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv) * This is a BIOS w/a: Some BIOS wrap stolen in the root * PCI bus, but have an off-by-one error. Hence retry the * reservation starting from 1 instead of 0. + * There's also BIOS with off-by-one on the other end. */ r = devm_request_mem_region(dev_priv->drm.dev, base + 1, - ggtt->stolen_size - 1, + ggtt->stolen_size - 2, "Graphics Stolen Memory"); /* * GEN3 firmware likes to smash pci bridges into the stolen @@ -579,6 +580,7 @@ _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, struct drm_mm_node *stolen) { struct drm_i915_gem_object *obj; + unsigned int cache_level; obj = i915_gem_object_alloc(dev_priv); if (obj == NULL) @@ -589,8 +591,8 @@ _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, obj->stolen = stolen; obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT; - obj->cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = true; /* assumptions! more like cache_oblivious */ + cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); if (i915_gem_object_pin_pages(obj)) goto cleanup; diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c index ccd09e8419f5..709efe2357ea 100644 --- a/drivers/gpu/drm/i915/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c @@ -49,7 +49,7 @@ struct i915_mmu_notifier { spinlock_t lock; struct hlist_node node; struct mmu_notifier mn; - struct rb_root objects; + struct rb_root_cached objects; struct workqueue_struct *wq; }; @@ -123,7 +123,7 @@ static void i915_gem_userptr_mn_invalidate_range_start(struct mmu_notifier *_mn, struct interval_tree_node *it; LIST_HEAD(cancelled); - if (RB_EMPTY_ROOT(&mn->objects)) + if (RB_EMPTY_ROOT(&mn->objects.rb_root)) return; /* interval ranges are inclusive, but invalidate range is exclusive */ @@ -172,7 +172,7 @@ i915_mmu_notifier_create(struct mm_struct *mm) spin_lock_init(&mn->lock); mn->mn.ops = &i915_gem_userptr_notifier; - mn->objects = RB_ROOT; + mn->objects = RB_ROOT_CACHED; mn->wq = alloc_workqueue("i915-userptr-release", WQ_UNBOUND, 0); if (mn->wq == NULL) { kfree(mn); @@ -507,7 +507,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) ret = -ENOMEM; pinned = 0; - pvec = kvmalloc_array(npages, sizeof(struct page *), GFP_TEMPORARY); + pvec = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL); if (pvec != NULL) { struct mm_struct *mm = obj->userptr.mm->mm; unsigned int flags = 0; @@ -643,7 +643,7 @@ i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) if (mm == current->mm) { pvec = kvmalloc_array(num_pages, sizeof(struct page *), - GFP_TEMPORARY | + GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN); if (pvec) /* defer to worker if malloc fails */ @@ -804,9 +804,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file i915_gem_object_init(obj, &i915_gem_userptr_ops); obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = I915_CACHE_LLC; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); obj->userptr.ptr = args->user_ptr; obj->userptr.read_only = !!(args->flags & I915_USERPTR_READ_ONLY); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index ae70283470a6..0c779671fe2d 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -787,16 +787,16 @@ int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, */ ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; ebuf->buf = kmalloc(ebuf->size, - GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); + GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN); if (ebuf->buf == NULL) { ebuf->size = PAGE_SIZE; - ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); + ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL); } if (ebuf->buf == NULL) { ebuf->size = 128; - ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); + ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL); } if (ebuf->buf == NULL) @@ -1266,7 +1266,7 @@ static void record_request(struct drm_i915_gem_request *request, struct drm_i915_error_request *erq) { erq->context = request->ctx->hw_id; - erq->ban_score = request->ctx->ban_score; + erq->ban_score = atomic_read(&request->ctx->ban_score); erq->seqno = request->global_seqno; erq->jiffies = request->emitted_jiffies; erq->head = request->head; @@ -1357,9 +1357,9 @@ static void record_context(struct drm_i915_error_context *e, e->handle = ctx->user_handle; e->hw_id = ctx->hw_id; - e->ban_score = ctx->ban_score; - e->guilty = ctx->guilty_count; - e->active = ctx->active_count; + e->ban_score = atomic_read(&ctx->ban_score); + e->guilty = atomic_read(&ctx->guilty_count); + e->active = atomic_read(&ctx->active_count); } static void request_record_user_bo(struct drm_i915_gem_request *request, diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index eb4f1dca2077..2fe92d2e0f62 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -275,17 +275,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; } static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; } static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; } /** @@ -336,7 +336,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) __gen6_mask_pm_irq(dev_priv, mask); } -void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) +static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) { i915_reg_t reg = gen6_pm_iir(dev_priv); @@ -347,7 +347,7 @@ void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) POSTING_READ(reg); } -void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) +static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) { lockdep_assert_held(&dev_priv->irq_lock); @@ -357,7 +357,7 @@ void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */ } -void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) +static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) { lockdep_assert_held(&dev_priv->irq_lock); @@ -405,7 +405,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) synchronize_irq(dev_priv->drm.irq); /* Now that we will not be generating any more work, flush any - * outsanding tasks. As we are called on the RPS idle path, + * outstanding tasks. As we are called on the RPS idle path, * we will reset the GPU to minimum frequencies, so the current * state of the worker can be discarded. */ @@ -839,7 +839,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, pipe); int position; int vbl_start, vbl_end, hsync_start, htotal, vtotal; - bool in_vbl = true; unsigned long irqflags; if (WARN_ON(!mode->crtc_clock)) { @@ -922,8 +921,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); - in_vbl = position >= vbl_start && position < vbl_end; - /* * While in vblank, position will be negative * counting up towards 0 at vbl_end. And outside @@ -1501,7 +1498,8 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, *pin_mask |= BIT(i); - if (!intel_hpd_pin_to_port(i, &port)) + port = intel_hpd_pin_to_port(i); + if (port == PORT_NONE) continue; if (long_pulse_detect(port, dig_hotplug_reg)) @@ -1661,7 +1659,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) spin_unlock(&dev_priv->irq_lock); } - if (INTEL_INFO(dev_priv)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) return; if (HAS_VEBOX(dev_priv)) { @@ -1708,18 +1706,6 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) } } -static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, - enum pipe pipe) -{ - bool ret; - - ret = drm_handle_vblank(&dev_priv->drm, pipe); - if (ret) - intel_finish_page_flip_mmio(dev_priv, pipe); - - return ret; -} - static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, u32 iir, u32 pipe_stats[I915_MAX_PIPES]) { @@ -1784,12 +1770,8 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe; for_each_pipe(dev_priv, pipe) { - if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) - intel_finish_page_flip_cs(dev_priv, pipe); + if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -2086,10 +2068,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); if (pch_iir & SDE_TRANSA_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); if (pch_iir & SDE_TRANSB_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); } static void ivb_err_int_handler(struct drm_i915_private *dev_priv) @@ -2123,13 +2105,13 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) DRM_ERROR("PCH poison interrupt\n"); if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C); I915_WRITE(SERR_INT, serr_int); } @@ -2241,19 +2223,14 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, DRM_ERROR("Poison interrupt\n"); for_each_pipe(dev_priv, pipe) { - if (de_iir & DE_PIPE_VBLANK(pipe) && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); + if (de_iir & DE_PIPE_VBLANK(pipe)) + drm_handle_vblank(&dev_priv->drm, pipe); if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); if (de_iir & DE_PIPE_CRC_DONE(pipe)) i9xx_pipe_crc_irq_handler(dev_priv, pipe); - - /* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE(pipe)) - intel_finish_page_flip_cs(dev_priv, pipe); } /* check event from PCH */ @@ -2292,13 +2269,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, intel_opregion_asle_intr(dev_priv); for_each_pipe(dev_priv, pipe) { - if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - /* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) - intel_finish_page_flip_cs(dev_priv, pipe); + if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) + drm_handle_vblank(&dev_priv->drm, pipe); } /* check event from PCH */ @@ -2440,7 +2412,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; tmp_mask = GEN8_AUX_CHANNEL_A; - if (INTEL_INFO(dev_priv)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) tmp_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; @@ -2479,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } for_each_pipe(dev_priv, pipe) { - u32 flip_done, fault_errors; + u32 fault_errors; if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) continue; @@ -2493,18 +2465,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); - if (iir & GEN8_PIPE_VBLANK && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - flip_done = iir; - if (INTEL_INFO(dev_priv)->gen >= 9) - flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; - else - flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; - - if (flip_done) - intel_finish_page_flip_cs(dev_priv, pipe); + if (iir & GEN8_PIPE_VBLANK) + drm_handle_vblank(&dev_priv->drm, pipe); if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); @@ -2513,7 +2475,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); fault_errors = iir; - if (INTEL_INFO(dev_priv)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; else fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; @@ -2660,7 +2622,7 @@ static void i915_reset_device(struct drm_i915_private *dev_priv) */ do { if (mutex_trylock(&dev_priv->drm.struct_mutex)) { - i915_reset(dev_priv); + i915_reset(dev_priv, 0); mutex_unlock(&dev_priv->drm.struct_mutex); } } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags, @@ -2676,32 +2638,6 @@ static void i915_reset_device(struct drm_i915_private *dev_priv) KOBJ_CHANGE, reset_done_event); } -static inline void -i915_err_print_instdone(struct drm_i915_private *dev_priv, - struct intel_instdone *instdone) -{ - int slice; - int subslice; - - pr_err(" INSTDONE: 0x%08x\n", instdone->instdone); - - if (INTEL_GEN(dev_priv) <= 3) - return; - - pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common); - - if (INTEL_GEN(dev_priv) <= 6) - return; - - for_each_instdone_slice_subslice(dev_priv, slice, subslice) - pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", - slice, subslice, instdone->sampler[slice][subslice]); - - for_each_instdone_slice_subslice(dev_priv, slice, subslice) - pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n", - slice, subslice, instdone->row[slice][subslice]); -} - static void i915_clear_error_registers(struct drm_i915_private *dev_priv) { u32 eir; @@ -2770,12 +2706,12 @@ void i915_handle_error(struct drm_i915_private *dev_priv, */ if (intel_has_reset_engine(dev_priv)) { for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { - BUILD_BUG_ON(I915_RESET_HANDOFF >= I915_RESET_ENGINE); + BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE); if (test_and_set_bit(I915_RESET_ENGINE + engine->id, &dev_priv->gpu_error.flags)) continue; - if (i915_reset_engine(engine) == 0) + if (i915_reset_engine(engine, 0) == 0) engine_mask &= ~intel_engine_flag(engine); clear_bit(I915_RESET_ENGINE + engine->id, @@ -3074,7 +3010,7 @@ static void gen8_irq_reset(struct drm_device *dev) } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask) + u8 pipe_mask) { uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; @@ -3088,7 +3024,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, } void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask) + u8 pipe_mask) { enum pipe pipe; @@ -3492,7 +3428,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_misc_masked = GEN8_DE_MISC_GSE; enum pipe pipe; - if (INTEL_INFO(dev_priv)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | @@ -3675,34 +3611,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev) /* * Returns true when a page flip has completed. */ -static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, - int plane, int pipe, u32 iir) -{ - u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); - - if (!intel_pipe_handle_vblank(dev_priv, pipe)) - return false; - - if ((iir & flip_pending) == 0) - goto check_page_flip; - - /* We detect FlipDone by looking for the change in PendingFlip from '1' - * to '0' on the following vblank, i.e. IIR has the Pendingflip - * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence - * the flip is completed (no longer pending). Since this doesn't raise - * an interrupt per se, we watch for the change at vblank. - */ - if (I915_READ16(ISR) & flip_pending) - goto check_page_flip; - - intel_finish_page_flip_cs(dev_priv, pipe); - return true; - -check_page_flip: - intel_check_page_flip(dev_priv, pipe); - return false; -} - static irqreturn_t i8xx_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; @@ -3710,9 +3618,6 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) u16 iir, new_iir; u32 pipe_stats[2]; int pipe; - u16 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; irqreturn_t ret; if (!intel_irqs_enabled(dev_priv)) @@ -3726,7 +3631,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) if (iir == 0) goto out; - while (iir & ~flip_mask) { + while (iir) { /* Can't rely on pipestat interrupt bit in iir as it might * have been cleared after the pipestat interrupt was received. * It doesn't set the bit in iir again, but it still produces @@ -3748,7 +3653,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) } spin_unlock(&dev_priv->irq_lock); - I915_WRITE16(IIR, iir & ~flip_mask); + I915_WRITE16(IIR, iir); new_iir = I915_READ16(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -3759,9 +3664,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) if (HAS_FBC(dev_priv)) plane = !plane; - if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && - i8xx_handle_vblank(dev_priv, plane, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); + if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -3861,45 +3765,11 @@ static int i915_irq_postinstall(struct drm_device *dev) return 0; } -/* - * Returns true when a page flip has completed. - */ -static bool i915_handle_vblank(struct drm_i915_private *dev_priv, - int plane, int pipe, u32 iir) -{ - u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); - - if (!intel_pipe_handle_vblank(dev_priv, pipe)) - return false; - - if ((iir & flip_pending) == 0) - goto check_page_flip; - - /* We detect FlipDone by looking for the change in PendingFlip from '1' - * to '0' on the following vblank, i.e. IIR has the Pendingflip - * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence - * the flip is completed (no longer pending). Since this doesn't raise - * an interrupt per se, we watch for the change at vblank. - */ - if (I915_READ(ISR) & flip_pending) - goto check_page_flip; - - intel_finish_page_flip_cs(dev_priv, pipe); - return true; - -check_page_flip: - intel_check_page_flip(dev_priv, pipe); - return false; -} - static irqreturn_t i915_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; struct drm_i915_private *dev_priv = to_i915(dev); u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; - u32 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; int pipe, ret = IRQ_NONE; if (!intel_irqs_enabled(dev_priv)) @@ -3910,7 +3780,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) iir = I915_READ(IIR); do { - bool irq_received = (iir & ~flip_mask) != 0; + bool irq_received = (iir) != 0; bool blc_event = false; /* Can't rely on pipestat interrupt bit in iir as it might @@ -3945,7 +3815,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) i9xx_hpd_irq_handler(dev_priv, hotplug_status); } - I915_WRITE(IIR, iir & ~flip_mask); + I915_WRITE(IIR, iir); new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -3956,9 +3826,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) if (HAS_FBC(dev_priv)) plane = !plane; - if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && - i915_handle_vblank(dev_priv, plane, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); + if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; @@ -3991,7 +3860,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) */ ret = IRQ_HANDLED; iir = new_iir; - } while (iir & ~flip_mask); + } while (iir); enable_rpm_wakeref_asserts(dev_priv); @@ -4126,9 +3995,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) u32 iir, new_iir; u32 pipe_stats[I915_MAX_PIPES]; int ret = IRQ_NONE, pipe; - u32 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; if (!intel_irqs_enabled(dev_priv)) return IRQ_NONE; @@ -4139,7 +4005,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) iir = I915_READ(IIR); for (;;) { - bool irq_received = (iir & ~flip_mask) != 0; + bool irq_received = (iir) != 0; bool blc_event = false; /* Can't rely on pipestat interrupt bit in iir as it might @@ -4177,7 +4043,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) i9xx_hpd_irq_handler(dev_priv, hotplug_status); } - I915_WRITE(IIR, iir & ~flip_mask); + I915_WRITE(IIR, iir); new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -4186,9 +4052,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) notify_ring(dev_priv->engine[VCS]); for_each_pipe(dev_priv, pipe) { - if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && - i915_handle_vblank(dev_priv, pipe, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); + if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; @@ -4290,16 +4155,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv) * * TODO: verify if this can be reproduced on VLV,CHV. */ - if (INTEL_INFO(dev_priv)->gen <= 7) + if (INTEL_GEN(dev_priv) <= 7) dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; - if (INTEL_INFO(dev_priv)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; if (IS_GEN2(dev_priv)) { /* Gen2 doesn't have a hardware frame counter */ dev->max_vblank_count = 0; - } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { + } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ dev->driver->get_vblank_counter = g4x_get_vblank_counter; } else { @@ -4346,7 +4211,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->enable_vblank = i965_enable_vblank; dev->driver->disable_vblank = i965_disable_vblank; dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; - } else if (INTEL_INFO(dev_priv)->gen >= 8) { + } else if (INTEL_GEN(dev_priv) >= 8) { dev->driver->irq_handler = gen8_irq_handler; dev->driver->irq_preinstall = gen8_irq_reset; dev->driver->irq_postinstall = gen8_irq_postinstall; diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c index d4462c2aaaee..abdf4d0abcce 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.c +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c @@ -31,3981 +31,6 @@ #include "i915_drv.h" #include "i915_oa_bdw.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_DATA_PORT_READS_COALESCING, - METRIC_SET_ID_DATA_PORT_WRITES_COALESCING, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_L3_4, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER_1, - METRIC_SET_ID_SAMPLER_2, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_bdw = 22; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_0_slices_0x01[] = { - { _MMIO(0x9888), 0x143f000f }, - { _MMIO(0x9888), 0x14110014 }, - { _MMIO(0x9888), 0x14310014 }, - { _MMIO(0x9888), 0x14bf000f }, - { _MMIO(0x9888), 0x118a0317 }, - { _MMIO(0x9888), 0x13837be0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x005c4000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x003d8000 }, - { _MMIO(0x9888), 0x183d0800 }, - { _MMIO(0x9888), 0x0a3f0023 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x00584000 }, - { _MMIO(0x9888), 0x08584000 }, - { _MMIO(0x9888), 0x0a5a4000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b8000 }, - { _MMIO(0x9888), 0x185b2400 }, - { _MMIO(0x9888), 0x0a1d4000 }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18380001 }, - { _MMIO(0x9888), 0x00392000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a391000 }, - { _MMIO(0x9888), 0x00104000 }, - { _MMIO(0x9888), 0x08104000 }, - { _MMIO(0x9888), 0x00110030 }, - { _MMIO(0x9888), 0x08110031 }, - { _MMIO(0x9888), 0x10110000 }, - { _MMIO(0x9888), 0x00134000 }, - { _MMIO(0x9888), 0x16130020 }, - { _MMIO(0x9888), 0x06308000 }, - { _MMIO(0x9888), 0x08308000 }, - { _MMIO(0x9888), 0x06311800 }, - { _MMIO(0x9888), 0x08311880 }, - { _MMIO(0x9888), 0x10310000 }, - { _MMIO(0x9888), 0x0e334000 }, - { _MMIO(0x9888), 0x16330080 }, - { _MMIO(0x9888), 0x0abf1180 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x0ada8000 }, - { _MMIO(0x9888), 0x0a9d8000 }, - { _MMIO(0x9888), 0x109f0002 }, - { _MMIO(0x9888), 0x0ab94000 }, - { _MMIO(0x9888), 0x0d888000 }, - { _MMIO(0x9888), 0x038a0380 }, - { _MMIO(0x9888), 0x058a000e }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a00a0 }, - { _MMIO(0x9888), 0x078a0000 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x238b2820 }, - { _MMIO(0x9888), 0x258b2550 }, - { _MMIO(0x9888), 0x198c1000 }, - { _MMIO(0x9888), 0x0b8d8000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x0d831021 }, - { _MMIO(0x9888), 0x0f83572f }, - { _MMIO(0x9888), 0x01835680 }, - { _MMIO(0x9888), 0x0383002c }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830001 }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0x9888), 0x4d801110 }, - { _MMIO(0x9888), 0x4f800331 }, - { _MMIO(0x9888), 0x43800802 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801465 }, - { _MMIO(0x9888), 0x53801111 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800ca5 }, - { _MMIO(0x9888), 0x41800003 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_1_slices_0x02[] = { - { _MMIO(0x9888), 0x143f000f }, - { _MMIO(0x9888), 0x14bf000f }, - { _MMIO(0x9888), 0x14910014 }, - { _MMIO(0x9888), 0x14b10014 }, - { _MMIO(0x9888), 0x118a0317 }, - { _MMIO(0x9888), 0x13837be0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x0a3f0023 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x0a5a4000 }, - { _MMIO(0x9888), 0x0a1d4000 }, - { _MMIO(0x9888), 0x0e1f8000 }, - { _MMIO(0x9888), 0x0a391000 }, - { _MMIO(0x9888), 0x00dc4000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x00bd8000 }, - { _MMIO(0x9888), 0x18bd0800 }, - { _MMIO(0x9888), 0x0abf1180 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x00d84000 }, - { _MMIO(0x9888), 0x08d84000 }, - { _MMIO(0x9888), 0x0ada8000 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db2400 }, - { _MMIO(0x9888), 0x0a9d8000 }, - { _MMIO(0x9888), 0x0c9f0800 }, - { _MMIO(0x9888), 0x0e9f2a00 }, - { _MMIO(0x9888), 0x109f0002 }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b80001 }, - { _MMIO(0x9888), 0x00b92000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab94000 }, - { _MMIO(0x9888), 0x00904000 }, - { _MMIO(0x9888), 0x08904000 }, - { _MMIO(0x9888), 0x00910030 }, - { _MMIO(0x9888), 0x08910031 }, - { _MMIO(0x9888), 0x10910000 }, - { _MMIO(0x9888), 0x00934000 }, - { _MMIO(0x9888), 0x16930020 }, - { _MMIO(0x9888), 0x06b08000 }, - { _MMIO(0x9888), 0x08b08000 }, - { _MMIO(0x9888), 0x06b11800 }, - { _MMIO(0x9888), 0x08b11880 }, - { _MMIO(0x9888), 0x10b10000 }, - { _MMIO(0x9888), 0x0eb34000 }, - { _MMIO(0x9888), 0x16b30080 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88b800 }, - { _MMIO(0x9888), 0x038a0380 }, - { _MMIO(0x9888), 0x058a000e }, - { _MMIO(0x9888), 0x1b8a0080 }, - { _MMIO(0x9888), 0x078a0000 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x238b2840 }, - { _MMIO(0x9888), 0x258b26a0 }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1100 }, - { _MMIO(0x9888), 0x018d2000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8d8000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x0d831021 }, - { _MMIO(0x9888), 0x0f83572f }, - { _MMIO(0x9888), 0x01835680 }, - { _MMIO(0x9888), 0x0383002c }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830001 }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0x9888), 0x4d801550 }, - { _MMIO(0x9888), 0x4f800331 }, - { _MMIO(0x9888), 0x43800802 }, - { _MMIO(0x9888), 0x51800400 }, - { _MMIO(0x9888), 0x458004a1 }, - { _MMIO(0x9888), 0x53805555 }, - { _MMIO(0x9888), 0x47800421 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f801421 }, - { _MMIO(0x9888), 0x41800845 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) { - regs[n] = mux_config_render_basic_0_slices_0x01; - lens[n] = ARRAY_SIZE(mux_config_render_basic_0_slices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) { - regs[n] = mux_config_render_basic_1_slices_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_basic_1_slices_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01[] = { - { _MMIO(0x9888), 0x105c00e0 }, - { _MMIO(0x9888), 0x105800e0 }, - { _MMIO(0x9888), 0x103800e0 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x065c2100 }, - { _MMIO(0x9888), 0x0a5c0041 }, - { _MMIO(0x9888), 0x0c5c6600 }, - { _MMIO(0x9888), 0x005c6580 }, - { _MMIO(0x9888), 0x085c8000 }, - { _MMIO(0x9888), 0x0e5c8000 }, - { _MMIO(0x9888), 0x00580042 }, - { _MMIO(0x9888), 0x08582080 }, - { _MMIO(0x9888), 0x0c58004c }, - { _MMIO(0x9888), 0x0e582580 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x185b1000 }, - { _MMIO(0x9888), 0x1a5b0104 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x08380042 }, - { _MMIO(0x9888), 0x0a382080 }, - { _MMIO(0x9888), 0x0e38404c }, - { _MMIO(0x9888), 0x0238404b }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x16380000 }, - { _MMIO(0x9888), 0x18381145 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b5550 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f850a80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x03844000 }, - { _MMIO(0x9888), 0x17808137 }, - { _MMIO(0x9888), 0x1980c147 }, - { _MMIO(0x9888), 0x1b80c0e5 }, - { _MMIO(0x9888), 0x1d80c0e3 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x13804000 }, - { _MMIO(0x9888), 0x15800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x4f800111 }, - { _MMIO(0x9888), 0x43800062 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800062 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800062 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f801062 }, - { _MMIO(0x9888), 0x41801084 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_2_slices_0x02[] = { - { _MMIO(0x9888), 0x10dc00e0 }, - { _MMIO(0x9888), 0x10d800e0 }, - { _MMIO(0x9888), 0x10b800e0 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x06dc2100 }, - { _MMIO(0x9888), 0x0adc0041 }, - { _MMIO(0x9888), 0x0cdc6600 }, - { _MMIO(0x9888), 0x00dc6580 }, - { _MMIO(0x9888), 0x08dc8000 }, - { _MMIO(0x9888), 0x0edc8000 }, - { _MMIO(0x9888), 0x00d80042 }, - { _MMIO(0x9888), 0x08d82080 }, - { _MMIO(0x9888), 0x0cd8004c }, - { _MMIO(0x9888), 0x0ed82580 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x18db1000 }, - { _MMIO(0x9888), 0x1adb0104 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x08b80042 }, - { _MMIO(0x9888), 0x0ab82080 }, - { _MMIO(0x9888), 0x0eb8404c }, - { _MMIO(0x9888), 0x02b8404b }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x16b80000 }, - { _MMIO(0x9888), 0x18b81145 }, - { _MMIO(0x9888), 0x04b80000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b92000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x238b0540 }, - { _MMIO(0x9888), 0x258baaa0 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d2000 }, - { _MMIO(0x9888), 0x1f850a80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x03844000 }, - { _MMIO(0x9888), 0x17808137 }, - { _MMIO(0x9888), 0x1980c147 }, - { _MMIO(0x9888), 0x1b80c0e5 }, - { _MMIO(0x9888), 0x1d80c0e3 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x13804000 }, - { _MMIO(0x9888), 0x15800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d805000 }, - { _MMIO(0x9888), 0x4f800555 }, - { _MMIO(0x9888), 0x43800062 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800062 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800062 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800062 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) { - regs[n] = mux_config_compute_basic_0_slices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) { - regs[n] = mux_config_compute_basic_2_slices_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_2_slices_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0a1e0000 }, - { _MMIO(0x9888), 0x0c1f000f }, - { _MMIO(0x9888), 0x10176800 }, - { _MMIO(0x9888), 0x1191001f }, - { _MMIO(0x9888), 0x0b880320 }, - { _MMIO(0x9888), 0x01890c40 }, - { _MMIO(0x9888), 0x118a1c00 }, - { _MMIO(0x9888), 0x118d7c00 }, - { _MMIO(0x9888), 0x118e0020 }, - { _MMIO(0x9888), 0x118f4c00 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x13900001 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x0c3d8000 }, - { _MMIO(0x9888), 0x06584000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x081e0040 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x021f5400 }, - { _MMIO(0x9888), 0x001f0000 }, - { _MMIO(0x9888), 0x101f0010 }, - { _MMIO(0x9888), 0x0e1f0080 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c13c000 }, - { _MMIO(0x9888), 0x06164000 }, - { _MMIO(0x9888), 0x06170012 }, - { _MMIO(0x9888), 0x00170000 }, - { _MMIO(0x9888), 0x01910005 }, - { _MMIO(0x9888), 0x07880002 }, - { _MMIO(0x9888), 0x01880c00 }, - { _MMIO(0x9888), 0x0f880000 }, - { _MMIO(0x9888), 0x0d880000 }, - { _MMIO(0x9888), 0x05880000 }, - { _MMIO(0x9888), 0x09890032 }, - { _MMIO(0x9888), 0x078a0800 }, - { _MMIO(0x9888), 0x0f8a0a00 }, - { _MMIO(0x9888), 0x198a4000 }, - { _MMIO(0x9888), 0x1b8a2000 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x038a4000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b54c0 }, - { _MMIO(0x9888), 0x258baa55 }, - { _MMIO(0x9888), 0x278b0019 }, - { _MMIO(0x9888), 0x198c0100 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x0f8d0015 }, - { _MMIO(0x9888), 0x018d1000 }, - { _MMIO(0x9888), 0x098d8000 }, - { _MMIO(0x9888), 0x0b8df000 }, - { _MMIO(0x9888), 0x0d8d3000 }, - { _MMIO(0x9888), 0x038de000 }, - { _MMIO(0x9888), 0x058d3000 }, - { _MMIO(0x9888), 0x0d8e0004 }, - { _MMIO(0x9888), 0x058e000c }, - { _MMIO(0x9888), 0x098e0000 }, - { _MMIO(0x9888), 0x078e0000 }, - { _MMIO(0x9888), 0x038e0000 }, - { _MMIO(0x9888), 0x0b8f0020 }, - { _MMIO(0x9888), 0x198f0c00 }, - { _MMIO(0x9888), 0x078f8000 }, - { _MMIO(0x9888), 0x098f4000 }, - { _MMIO(0x9888), 0x0b900980 }, - { _MMIO(0x9888), 0x03900d80 }, - { _MMIO(0x9888), 0x01900000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801111 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f801011 }, - { _MMIO(0x9888), 0x43800443 }, - { _MMIO(0x9888), 0x51801111 }, - { _MMIO(0x9888), 0x45800422 }, - { _MMIO(0x9888), 0x53801111 }, - { _MMIO(0x9888), 0x47800c60 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800422 }, - { _MMIO(0x9888), 0x41800021 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x198b0343 }, - { _MMIO(0x9888), 0x13845800 }, - { _MMIO(0x9888), 0x15840018 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b6b62 }, - { _MMIO(0x9888), 0x078b006a }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b0000 }, - { _MMIO(0x9888), 0x258b0000 }, - { _MMIO(0x9888), 0x1f85a080 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385000a }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01840018 }, - { _MMIO(0x9888), 0x07844c80 }, - { _MMIO(0x9888), 0x09840d9a }, - { _MMIO(0x9888), 0x0b840e9c }, - { _MMIO(0x9888), 0x0d840f9e }, - { _MMIO(0x9888), 0x0f840010 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x03848000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x2f8000e5 }, - { _MMIO(0x9888), 0x138080e3 }, - { _MMIO(0x9888), 0x1580c0e1 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f804000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800842 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801042 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800084 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x198b0343 }, - { _MMIO(0x9888), 0x13845400 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3d800805 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b6b62 }, - { _MMIO(0x9888), 0x078b006a }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b0000 }, - { _MMIO(0x9888), 0x258b0000 }, - { _MMIO(0x9888), 0x1f85a080 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x23850002 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01840010 }, - { _MMIO(0x9888), 0x07844880 }, - { _MMIO(0x9888), 0x09840992 }, - { _MMIO(0x9888), 0x0b840a94 }, - { _MMIO(0x9888), 0x0d840b96 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x03848000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x2d800147 }, - { _MMIO(0x9888), 0x2f8000e5 }, - { _MMIO(0x9888), 0x138080e3 }, - { _MMIO(0x9888), 0x1580c0e1 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800842 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801082 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800084 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x143d0160 }, - { _MMIO(0x9888), 0x163d2800 }, - { _MMIO(0x9888), 0x183d0120 }, - { _MMIO(0x9888), 0x105800e0 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x003d0011 }, - { _MMIO(0x9888), 0x063d0900 }, - { _MMIO(0x9888), 0x083d0a13 }, - { _MMIO(0x9888), 0x0a3d0b15 }, - { _MMIO(0x9888), 0x0c3d2317 }, - { _MMIO(0x9888), 0x043d21b7 }, - { _MMIO(0x9888), 0x103d0000 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0e5825c1 }, - { _MMIO(0x9888), 0x00586100 }, - { _MMIO(0x9888), 0x0258204c }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x0c58c000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5400 }, - { _MMIO(0x9888), 0x1a5b0155 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_2_subslices_0x02[] = { - { _MMIO(0x9888), 0x105c00e0 }, - { _MMIO(0x9888), 0x145b0160 }, - { _MMIO(0x9888), 0x165b2800 }, - { _MMIO(0x9888), 0x185b0120 }, - { _MMIO(0x9888), 0x0e5c25c1 }, - { _MMIO(0x9888), 0x005c6100 }, - { _MMIO(0x9888), 0x025c204c }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x005b0011 }, - { _MMIO(0x9888), 0x065b0900 }, - { _MMIO(0x9888), 0x085b0a13 }, - { _MMIO(0x9888), 0x0a5b0b15 }, - { _MMIO(0x9888), 0x0c5b2317 }, - { _MMIO(0x9888), 0x045b21b7 }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x0e5b0000 }, - { _MMIO(0x9888), 0x1a5b0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_4_subslices_0x04[] = { - { _MMIO(0x9888), 0x103800e0 }, - { _MMIO(0x9888), 0x143a0160 }, - { _MMIO(0x9888), 0x163a2800 }, - { _MMIO(0x9888), 0x183a0120 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e38a5c1 }, - { _MMIO(0x9888), 0x0038a100 }, - { _MMIO(0x9888), 0x0238204c }, - { _MMIO(0x9888), 0x16388000 }, - { _MMIO(0x9888), 0x183802aa }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06380000 }, - { _MMIO(0x9888), 0x08388000 }, - { _MMIO(0x9888), 0x0a388000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x003a0011 }, - { _MMIO(0x9888), 0x063a0900 }, - { _MMIO(0x9888), 0x083a0a13 }, - { _MMIO(0x9888), 0x0a3a0b15 }, - { _MMIO(0x9888), 0x0c3a2317 }, - { _MMIO(0x9888), 0x043a21b7 }, - { _MMIO(0x9888), 0x103a0000 }, - { _MMIO(0x9888), 0x0e3a0000 }, - { _MMIO(0x9888), 0x1a3a0000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_1_subslices_0x08[] = { - { _MMIO(0x9888), 0x14bd0160 }, - { _MMIO(0x9888), 0x16bd2800 }, - { _MMIO(0x9888), 0x18bd0120 }, - { _MMIO(0x9888), 0x10d800e0 }, - { _MMIO(0x9888), 0x00dcc000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x00bd0011 }, - { _MMIO(0x9888), 0x06bd0900 }, - { _MMIO(0x9888), 0x08bd0a13 }, - { _MMIO(0x9888), 0x0abd0b15 }, - { _MMIO(0x9888), 0x0cbd2317 }, - { _MMIO(0x9888), 0x04bd21b7 }, - { _MMIO(0x9888), 0x10bd0000 }, - { _MMIO(0x9888), 0x0ebd0000 }, - { _MMIO(0x9888), 0x1abd0000 }, - { _MMIO(0x9888), 0x0ed825c1 }, - { _MMIO(0x9888), 0x00d86100 }, - { _MMIO(0x9888), 0x02d8204c }, - { _MMIO(0x9888), 0x06d88000 }, - { _MMIO(0x9888), 0x08d8c000 }, - { _MMIO(0x9888), 0x0ad8c000 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x04d8c000 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x0edb4000 }, - { _MMIO(0x9888), 0x18db5400 }, - { _MMIO(0x9888), 0x1adb0155 }, - { _MMIO(0x9888), 0x02db4000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db4000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b81555 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_3_subslices_0x10[] = { - { _MMIO(0x9888), 0x10dc00e0 }, - { _MMIO(0x9888), 0x14db0160 }, - { _MMIO(0x9888), 0x16db2800 }, - { _MMIO(0x9888), 0x18db0120 }, - { _MMIO(0x9888), 0x0edc25c1 }, - { _MMIO(0x9888), 0x00dc6100 }, - { _MMIO(0x9888), 0x02dc204c }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x00db0011 }, - { _MMIO(0x9888), 0x06db0900 }, - { _MMIO(0x9888), 0x08db0a13 }, - { _MMIO(0x9888), 0x0adb0b15 }, - { _MMIO(0x9888), 0x0cdb2317 }, - { _MMIO(0x9888), 0x04db21b7 }, - { _MMIO(0x9888), 0x10db0000 }, - { _MMIO(0x9888), 0x0edb0000 }, - { _MMIO(0x9888), 0x1adb0000 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b81555 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_5_subslices_0x20[] = { - { _MMIO(0x9888), 0x10b800e0 }, - { _MMIO(0x9888), 0x14ba0160 }, - { _MMIO(0x9888), 0x16ba2800 }, - { _MMIO(0x9888), 0x18ba0120 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb8a5c1 }, - { _MMIO(0x9888), 0x00b8a100 }, - { _MMIO(0x9888), 0x02b8204c }, - { _MMIO(0x9888), 0x16b88000 }, - { _MMIO(0x9888), 0x18b802aa }, - { _MMIO(0x9888), 0x04b80000 }, - { _MMIO(0x9888), 0x06b80000 }, - { _MMIO(0x9888), 0x08b88000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x00ba0011 }, - { _MMIO(0x9888), 0x06ba0900 }, - { _MMIO(0x9888), 0x08ba0a13 }, - { _MMIO(0x9888), 0x0aba0b15 }, - { _MMIO(0x9888), 0x0cba2317 }, - { _MMIO(0x9888), 0x04ba21b7 }, - { _MMIO(0x9888), 0x10ba0000 }, - { _MMIO(0x9888), 0x0eba0000 }, - { _MMIO(0x9888), 0x1aba0000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 6); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 6); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_compute_extended_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) { - regs[n] = mux_config_compute_extended_1_subslices_0x08; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_1_subslices_0x08); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) { - regs[n] = mux_config_compute_extended_2_subslices_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_2_subslices_0x02); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) { - regs[n] = mux_config_compute_extended_3_subslices_0x10; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_3_subslices_0x10); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) { - regs[n] = mux_config_compute_extended_4_subslices_0x04; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_4_subslices_0x04); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) { - regs[n] = mux_config_compute_extended_5_subslices_0x20; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_5_subslices_0x20); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x143f00b3 }, - { _MMIO(0x9888), 0x14bf00b3 }, - { _MMIO(0x9888), 0x138303c0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800805 }, - { _MMIO(0x9888), 0x003f0029 }, - { _MMIO(0x9888), 0x063f1400 }, - { _MMIO(0x9888), 0x083f1225 }, - { _MMIO(0x9888), 0x0e3f1327 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x005a4000 }, - { _MMIO(0x9888), 0x065a8000 }, - { _MMIO(0x9888), 0x085ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x001d4000 }, - { _MMIO(0x9888), 0x061d8000 }, - { _MMIO(0x9888), 0x081dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1f2a00 }, - { _MMIO(0x9888), 0x101f0280 }, - { _MMIO(0x9888), 0x00391000 }, - { _MMIO(0x9888), 0x06394000 }, - { _MMIO(0x9888), 0x08395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x0abf1429 }, - { _MMIO(0x9888), 0x0cbf1225 }, - { _MMIO(0x9888), 0x00bf1380 }, - { _MMIO(0x9888), 0x02bf0026 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x0adac000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02da4000 }, - { _MMIO(0x9888), 0x0a9dc000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029d4000 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f002a }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0ab95000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b91000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f880003 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a8020 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x238b0520 }, - { _MMIO(0x9888), 0x258ba950 }, - { _MMIO(0x9888), 0x278b0016 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0001 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x03835180 }, - { _MMIO(0x9888), 0x05834022 }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x4f800111 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800840 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800800 }, - { _MMIO(0x9888), 0x418014a2 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_data_port_reads_coalescing[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0xba98ba98 }, - { _MMIO(0x2748), 0xba98ba98 }, - { _MMIO(0x2744), 0x00003377 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fff2 }, - { _MMIO(0x2774), 0x00007ff0 }, - { _MMIO(0x2778), 0x0007ffe2 }, - { _MMIO(0x277c), 0x00007ff0 }, - { _MMIO(0x2780), 0x0007ffc2 }, - { _MMIO(0x2784), 0x00007ff0 }, - { _MMIO(0x2788), 0x0007ff82 }, - { _MMIO(0x278c), 0x00007ff0 }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000bfef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000bfdf }, - { _MMIO(0x27a0), 0x0007fffa }, - { _MMIO(0x27a4), 0x0000bfbf }, - { _MMIO(0x27a8), 0x0007fffa }, - { _MMIO(0x27ac), 0x0000bf7f }, -}; - -static const struct i915_oa_reg flex_eu_config_data_port_reads_coalescing[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_data_port_reads_coalescing_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x103d0005 }, - { _MMIO(0x9888), 0x163d240b }, - { _MMIO(0x9888), 0x1058022f }, - { _MMIO(0x9888), 0x185b5520 }, - { _MMIO(0x9888), 0x198b0003 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065cc000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025c4000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x003d0000 }, - { _MMIO(0x9888), 0x063d00b0 }, - { _MMIO(0x9888), 0x083d0182 }, - { _MMIO(0x9888), 0x0a3d10a0 }, - { _MMIO(0x9888), 0x0c3d11a2 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x183d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0e582242 }, - { _MMIO(0x9888), 0x00586700 }, - { _MMIO(0x9888), 0x0258004f }, - { _MMIO(0x9888), 0x0658c000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x0c58c000 }, - { _MMIO(0x9888), 0x045b6300 }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x1a5b0155 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x0a5b0000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faaa0 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x0639a000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x04398000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b0062 }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b5555 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800001 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800041 }, -}; - -static int -get_data_port_reads_coalescing_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_data_port_reads_coalescing_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_data_port_reads_coalescing_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_data_port_writes_coalescing[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0xba98ba98 }, - { _MMIO(0x2748), 0xba98ba98 }, - { _MMIO(0x2744), 0x00003377 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ff72 }, - { _MMIO(0x2774), 0x0000bfd0 }, - { _MMIO(0x2778), 0x0007ff62 }, - { _MMIO(0x277c), 0x0000bfd0 }, - { _MMIO(0x2780), 0x0007ff42 }, - { _MMIO(0x2784), 0x0000bfd0 }, - { _MMIO(0x2788), 0x0007ff02 }, - { _MMIO(0x278c), 0x0000bfd0 }, - { _MMIO(0x2790), 0x0005fff2 }, - { _MMIO(0x2794), 0x0000bfd0 }, - { _MMIO(0x2798), 0x0005ffe2 }, - { _MMIO(0x279c), 0x0000bfd0 }, - { _MMIO(0x27a0), 0x0005ffc2 }, - { _MMIO(0x27a4), 0x0000bfd0 }, - { _MMIO(0x27a8), 0x0005ff82 }, - { _MMIO(0x27ac), 0x0000bfd0 }, -}; - -static const struct i915_oa_reg flex_eu_config_data_port_writes_coalescing[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_data_port_writes_coalescing_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x103d0005 }, - { _MMIO(0x9888), 0x143d0120 }, - { _MMIO(0x9888), 0x163d2400 }, - { _MMIO(0x9888), 0x1058022f }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x198b0003 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065cc000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025c4000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x003d0000 }, - { _MMIO(0x9888), 0x063d0094 }, - { _MMIO(0x9888), 0x083d0182 }, - { _MMIO(0x9888), 0x0a3d1814 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x183d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0c3d0000 }, - { _MMIO(0x9888), 0x0e582242 }, - { _MMIO(0x9888), 0x00586700 }, - { _MMIO(0x9888), 0x0258004f }, - { _MMIO(0x9888), 0x0658c000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x045b6a80 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5400 }, - { _MMIO(0x9888), 0x1a5b0141 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x0a5b0000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faaa0 }, - { _MMIO(0x9888), 0x101f0282 }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381415 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x0639a000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x04398000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a82a0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b0062 }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b1555 }, - { _MMIO(0x9888), 0x278b0014 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x21852aaa }, - { _MMIO(0x9888), 0x23850028 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830141 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800001 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800041 }, -}; - -static int -get_data_port_writes_coalescing_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_data_port_writes_coalescing_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_data_port_writes_coalescing_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fff7 }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x105c0232 }, - { _MMIO(0x9888), 0x10580232 }, - { _MMIO(0x9888), 0x10380232 }, - { _MMIO(0x9888), 0x10dc0232 }, - { _MMIO(0x9888), 0x10d80232 }, - { _MMIO(0x9888), 0x10b80232 }, - { _MMIO(0x9888), 0x118e4400 }, - { _MMIO(0x9888), 0x025c6080 }, - { _MMIO(0x9888), 0x045c004b }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x00582080 }, - { _MMIO(0x9888), 0x0258004b }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x04386080 }, - { _MMIO(0x9888), 0x0638404b }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a380000 }, - { _MMIO(0x9888), 0x0c380000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0cdc25c1 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0ad825c1 }, - { _MMIO(0x9888), 0x18db4000 }, - { _MMIO(0x9888), 0x1adb0001 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb825c1 }, - { _MMIO(0x9888), 0x18b80154 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baa05 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x098dc000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x098e05c0 }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x198f0020 }, - { _MMIO(0x9888), 0x2185aa0a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x19835000 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x19808000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x51800040 }, - { _MMIO(0x9888), 0x43800400 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800c62 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801042 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x418014a4 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x10bf03da }, - { _MMIO(0x9888), 0x14bf0001 }, - { _MMIO(0x9888), 0x12980340 }, - { _MMIO(0x9888), 0x12990340 }, - { _MMIO(0x9888), 0x0cbf1187 }, - { _MMIO(0x9888), 0x0ebf1205 }, - { _MMIO(0x9888), 0x00bf0500 }, - { _MMIO(0x9888), 0x02bf042b }, - { _MMIO(0x9888), 0x04bf002c }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02dac000 }, - { _MMIO(0x9888), 0x04da4000 }, - { _MMIO(0x9888), 0x04983400 }, - { _MMIO(0x9888), 0x10980000 }, - { _MMIO(0x9888), 0x06990034 }, - { _MMIO(0x9888), 0x10990000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029dc000 }, - { _MMIO(0x9888), 0x049d4000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00ba }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b95000 }, - { _MMIO(0x9888), 0x04b91000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0cba4000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x258b800a }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x103f03da }, - { _MMIO(0x9888), 0x143f0001 }, - { _MMIO(0x9888), 0x12180340 }, - { _MMIO(0x9888), 0x12190340 }, - { _MMIO(0x9888), 0x0c3f1187 }, - { _MMIO(0x9888), 0x0e3f1205 }, - { _MMIO(0x9888), 0x003f0500 }, - { _MMIO(0x9888), 0x023f042b }, - { _MMIO(0x9888), 0x043f002c }, - { _MMIO(0x9888), 0x0c5ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x04183400 }, - { _MMIO(0x9888), 0x10180000 }, - { _MMIO(0x9888), 0x06190034 }, - { _MMIO(0x9888), 0x10190000 }, - { _MMIO(0x9888), 0x0c1dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x101f02a8 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00ba }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a4000 }, - { _MMIO(0x9888), 0x1b8aa800 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258b4005 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x121b0340 }, - { _MMIO(0x9888), 0x103f0274 }, - { _MMIO(0x9888), 0x123f0000 }, - { _MMIO(0x9888), 0x129b0340 }, - { _MMIO(0x9888), 0x10bf0274 }, - { _MMIO(0x9888), 0x12bf0000 }, - { _MMIO(0x9888), 0x041b3400 }, - { _MMIO(0x9888), 0x101b0000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x0a3d4000 }, - { _MMIO(0x9888), 0x003f0080 }, - { _MMIO(0x9888), 0x023f0793 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f002a }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04399000 }, - { _MMIO(0x9888), 0x069b0034 }, - { _MMIO(0x9888), 0x109b0000 }, - { _MMIO(0x9888), 0x06dc4000 }, - { _MMIO(0x9888), 0x0cbd4000 }, - { _MMIO(0x9888), 0x0cbf0981 }, - { _MMIO(0x9888), 0x0ebf0a0f }, - { _MMIO(0x9888), 0x06d84000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0cdb4000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0080 }, - { _MMIO(0x9888), 0x0cb84000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800c00 }, - { _MMIO(0x9888), 0x47800c63 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a5 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800045 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_4[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_4[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_4[] = { - { _MMIO(0x9888), 0x121a0340 }, - { _MMIO(0x9888), 0x103f0017 }, - { _MMIO(0x9888), 0x123f0020 }, - { _MMIO(0x9888), 0x129a0340 }, - { _MMIO(0x9888), 0x10bf0017 }, - { _MMIO(0x9888), 0x12bf0020 }, - { _MMIO(0x9888), 0x041a3400 }, - { _MMIO(0x9888), 0x101a0000 }, - { _MMIO(0x9888), 0x043b8000 }, - { _MMIO(0x9888), 0x0a3e0010 }, - { _MMIO(0x9888), 0x003f0200 }, - { _MMIO(0x9888), 0x023f0113 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x02592000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a1c8000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0a1e8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f001a }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x069a0034 }, - { _MMIO(0x9888), 0x109a0000 }, - { _MMIO(0x9888), 0x06bb4000 }, - { _MMIO(0x9888), 0x0abe0040 }, - { _MMIO(0x9888), 0x0cbf0984 }, - { _MMIO(0x9888), 0x0ebf0a02 }, - { _MMIO(0x9888), 0x02d94000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0c9c0400 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x0c9e0400 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0040 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x47800842 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801084 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800044 }, -}; - -static int -get_l3_4_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_4; - lens[n] = ARRAY_SIZE(mux_config_l3_4); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00006000 }, - { _MMIO(0x2774), 0x0000f3ff }, - { _MMIO(0x2778), 0x00001800 }, - { _MMIO(0x277c), 0x0000fcff }, - { _MMIO(0x2780), 0x00000600 }, - { _MMIO(0x2784), 0x0000ff3f }, - { _MMIO(0x2788), 0x00000180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000060 }, - { _MMIO(0x2794), 0x0000fff3 }, - { _MMIO(0x2798), 0x00000018 }, - { _MMIO(0x279c), 0x0000fffc }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x143b000e }, - { _MMIO(0x9888), 0x043c55c0 }, - { _MMIO(0x9888), 0x0a1e0280 }, - { _MMIO(0x9888), 0x0c1e0408 }, - { _MMIO(0x9888), 0x10390000 }, - { _MMIO(0x9888), 0x12397a1f }, - { _MMIO(0x9888), 0x14bb000e }, - { _MMIO(0x9888), 0x04bc5000 }, - { _MMIO(0x9888), 0x0a9e0296 }, - { _MMIO(0x9888), 0x0c9e0008 }, - { _MMIO(0x9888), 0x10b90000 }, - { _MMIO(0x9888), 0x12b97a1f }, - { _MMIO(0x9888), 0x063b0042 }, - { _MMIO(0x9888), 0x103b0000 }, - { _MMIO(0x9888), 0x083c0000 }, - { _MMIO(0x9888), 0x0a3e0040 }, - { _MMIO(0x9888), 0x043f8000 }, - { _MMIO(0x9888), 0x02594000 }, - { _MMIO(0x9888), 0x045a8000 }, - { _MMIO(0x9888), 0x0c1c0400 }, - { _MMIO(0x9888), 0x041d8000 }, - { _MMIO(0x9888), 0x081e02c0 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1f0260 }, - { _MMIO(0x9888), 0x101f0014 }, - { _MMIO(0x9888), 0x003905e0 }, - { _MMIO(0x9888), 0x06390bc0 }, - { _MMIO(0x9888), 0x02390018 }, - { _MMIO(0x9888), 0x04394000 }, - { _MMIO(0x9888), 0x04bb0042 }, - { _MMIO(0x9888), 0x10bb0000 }, - { _MMIO(0x9888), 0x02bc05c0 }, - { _MMIO(0x9888), 0x08bc0000 }, - { _MMIO(0x9888), 0x0abe0004 }, - { _MMIO(0x9888), 0x02bf8000 }, - { _MMIO(0x9888), 0x02d91000 }, - { _MMIO(0x9888), 0x02da8000 }, - { _MMIO(0x9888), 0x089c8000 }, - { _MMIO(0x9888), 0x029d8000 }, - { _MMIO(0x9888), 0x089e8000 }, - { _MMIO(0x9888), 0x0e9e0000 }, - { _MMIO(0x9888), 0x0e9fa806 }, - { _MMIO(0x9888), 0x109f0142 }, - { _MMIO(0x9888), 0x08b90617 }, - { _MMIO(0x9888), 0x0ab90be0 }, - { _MMIO(0x9888), 0x02b94000 }, - { _MMIO(0x9888), 0x0d88f000 }, - { _MMIO(0x9888), 0x0f88000c }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x1b8a2800 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b52a0 }, - { _MMIO(0x9888), 0x258b6a95 }, - { _MMIO(0x9888), 0x278b0029 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1500 }, - { _MMIO(0x9888), 0x1b8c0014 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d8000 }, - { _MMIO(0x9888), 0x058d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4d800444 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f804000 }, - { _MMIO(0x9888), 0x43801080 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800084 }, - { _MMIO(0x9888), 0x53800044 }, - { _MMIO(0x9888), 0x47801080 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x41800840 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_1[] = { - { _MMIO(0x9888), 0x18921400 }, - { _MMIO(0x9888), 0x149500ab }, - { _MMIO(0x9888), 0x18b21400 }, - { _MMIO(0x9888), 0x14b500ab }, - { _MMIO(0x9888), 0x18d21400 }, - { _MMIO(0x9888), 0x14d500ab }, - { _MMIO(0x9888), 0x0cdc8000 }, - { _MMIO(0x9888), 0x0edc4000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x1abd00a0 }, - { _MMIO(0x9888), 0x0abd8000 }, - { _MMIO(0x9888), 0x0cd88000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x04d88000 }, - { _MMIO(0x9888), 0x1adb0050 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x06db8000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x109f02a0 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x18b82500 }, - { _MMIO(0x9888), 0x02b88000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb98000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x1aba0200 }, - { _MMIO(0x9888), 0x02ba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04908000 }, - { _MMIO(0x9888), 0x04918000 }, - { _MMIO(0x9888), 0x04927300 }, - { _MMIO(0x9888), 0x10920000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a934000 }, - { _MMIO(0x9888), 0x0a946000 }, - { _MMIO(0x9888), 0x0c959000 }, - { _MMIO(0x9888), 0x0e950098 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b04000 }, - { _MMIO(0x9888), 0x04b14000 }, - { _MMIO(0x9888), 0x04b20073 }, - { _MMIO(0x9888), 0x10b20000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x06b38000 }, - { _MMIO(0x9888), 0x08b34000 }, - { _MMIO(0x9888), 0x04b4c000 }, - { _MMIO(0x9888), 0x02b59890 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d04000 }, - { _MMIO(0x9888), 0x06d14000 }, - { _MMIO(0x9888), 0x06d20073 }, - { _MMIO(0x9888), 0x10d20000 }, - { _MMIO(0x9888), 0x18d30020 }, - { _MMIO(0x9888), 0x02d38000 }, - { _MMIO(0x9888), 0x0cd34000 }, - { _MMIO(0x9888), 0x0ad48000 }, - { _MMIO(0x9888), 0x04d42000 }, - { _MMIO(0x9888), 0x0ed59000 }, - { _MMIO(0x9888), 0x00d59800 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0f88000e }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x258b000a }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8d8000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_1; - lens[n] = ARRAY_SIZE(mux_config_sampler_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_2[] = { - { _MMIO(0x9888), 0x18121400 }, - { _MMIO(0x9888), 0x141500ab }, - { _MMIO(0x9888), 0x18321400 }, - { _MMIO(0x9888), 0x143500ab }, - { _MMIO(0x9888), 0x18521400 }, - { _MMIO(0x9888), 0x145500ab }, - { _MMIO(0x9888), 0x0c5c8000 }, - { _MMIO(0x9888), 0x0e5c4000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x1a3d00a0 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0c588000 }, - { _MMIO(0x9888), 0x0e584000 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x1a5b0050 }, - { _MMIO(0x9888), 0x045b8000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x101f02a0 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x18382500 }, - { _MMIO(0x9888), 0x02388000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c398000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x1a3a0200 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x04108000 }, - { _MMIO(0x9888), 0x04118000 }, - { _MMIO(0x9888), 0x04127300 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x1813000a }, - { _MMIO(0x9888), 0x0a134000 }, - { _MMIO(0x9888), 0x0a146000 }, - { _MMIO(0x9888), 0x0c159000 }, - { _MMIO(0x9888), 0x0e150098 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04304000 }, - { _MMIO(0x9888), 0x04314000 }, - { _MMIO(0x9888), 0x04320073 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x04338000 }, - { _MMIO(0x9888), 0x06338000 }, - { _MMIO(0x9888), 0x08334000 }, - { _MMIO(0x9888), 0x0434c000 }, - { _MMIO(0x9888), 0x02359890 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x06504000 }, - { _MMIO(0x9888), 0x06514000 }, - { _MMIO(0x9888), 0x06520073 }, - { _MMIO(0x9888), 0x10520000 }, - { _MMIO(0x9888), 0x18530020 }, - { _MMIO(0x9888), 0x02538000 }, - { _MMIO(0x9888), 0x0c534000 }, - { _MMIO(0x9888), 0x0a548000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x0e559000 }, - { _MMIO(0x9888), 0x00559800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x1b8aa000 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_2; - lens[n] = ARRAY_SIZE(mux_config_sampler_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000ffbf }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fff7 }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fff9 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x16154d60 }, - { _MMIO(0x9888), 0x16352e60 }, - { _MMIO(0x9888), 0x16554d60 }, - { _MMIO(0x9888), 0x16950000 }, - { _MMIO(0x9888), 0x16b50000 }, - { _MMIO(0x9888), 0x16d50000 }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x025b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04388000 }, - { _MMIO(0x9888), 0x06388000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x043a8000 }, - { _MMIO(0x9888), 0x063a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x0a138000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x0415cfc7 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x02338000 }, - { _MMIO(0x9888), 0x0c338000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x0035c700 }, - { _MMIO(0x9888), 0x063500cf }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04538000 }, - { _MMIO(0x9888), 0x06538000 }, - { _MMIO(0x9888), 0x0454c000 }, - { _MMIO(0x9888), 0x0255cfc7 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dc4000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x1abd00a8 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db0800 }, - { _MMIO(0x9888), 0x1adb0254 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b8156a }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x18baa000 }, - { _MMIO(0x9888), 0x1aba0002 }, - { _MMIO(0x9888), 0x16934000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a947000 }, - { _MMIO(0x9888), 0x0c95c5c1 }, - { _MMIO(0x9888), 0x0e9500c3 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x0eb38000 }, - { _MMIO(0x9888), 0x16b30040 }, - { _MMIO(0x9888), 0x18b30020 }, - { _MMIO(0x9888), 0x06b48000 }, - { _MMIO(0x9888), 0x08b41000 }, - { _MMIO(0x9888), 0x0ab48000 }, - { _MMIO(0x9888), 0x06b5c500 }, - { _MMIO(0x9888), 0x08b500c3 }, - { _MMIO(0x9888), 0x0eb5c100 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x16d31500 }, - { _MMIO(0x9888), 0x08d4e000 }, - { _MMIO(0x9888), 0x08d5c100 }, - { _MMIO(0x9888), 0x0ad5c3c5 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baaa5 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800c42 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800063 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800800 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a4 }, - { _MMIO(0x9888), 0x41801042 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000000 }, - { _MMIO(0x2784), 0x0000ff9f }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffe7 }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fffb }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000fffd }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x16150000 }, - { _MMIO(0x9888), 0x16350000 }, - { _MMIO(0x9888), 0x16550000 }, - { _MMIO(0x9888), 0x16952e60 }, - { _MMIO(0x9888), 0x16b54d60 }, - { _MMIO(0x9888), 0x16d52e60 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5c4000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183da000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x08588000 }, - { _MMIO(0x9888), 0x0a584000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5800 }, - { _MMIO(0x9888), 0x1a5b000a }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18382a55 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x1a3a02a0 }, - { _MMIO(0x9888), 0x0e138000 }, - { _MMIO(0x9888), 0x16130500 }, - { _MMIO(0x9888), 0x06148000 }, - { _MMIO(0x9888), 0x08146000 }, - { _MMIO(0x9888), 0x0615c100 }, - { _MMIO(0x9888), 0x0815c500 }, - { _MMIO(0x9888), 0x0a1500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x16335040 }, - { _MMIO(0x9888), 0x08349000 }, - { _MMIO(0x9888), 0x0a341000 }, - { _MMIO(0x9888), 0x083500c1 }, - { _MMIO(0x9888), 0x0a35c500 }, - { _MMIO(0x9888), 0x0c3500c3 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x1853002a }, - { _MMIO(0x9888), 0x0a54e000 }, - { _MMIO(0x9888), 0x0c55c500 }, - { _MMIO(0x9888), 0x0e55c1c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dc4000 }, - { _MMIO(0x9888), 0x04bd8000 }, - { _MMIO(0x9888), 0x06bd8000 }, - { _MMIO(0x9888), 0x02d8c000 }, - { _MMIO(0x9888), 0x02db8000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0aba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04938000 }, - { _MMIO(0x9888), 0x06938000 }, - { _MMIO(0x9888), 0x0494c000 }, - { _MMIO(0x9888), 0x0295cfc7 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x02b38000 }, - { _MMIO(0x9888), 0x08b38000 }, - { _MMIO(0x9888), 0x04b42000 }, - { _MMIO(0x9888), 0x06b41000 }, - { _MMIO(0x9888), 0x00b5c700 }, - { _MMIO(0x9888), 0x04b500cf }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x0ad38000 }, - { _MMIO(0x9888), 0x0cd38000 }, - { _MMIO(0x9888), 0x06d46000 }, - { _MMIO(0x9888), 0x04d5c700 }, - { _MMIO(0x9888), 0x06d500cf }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x258b555a }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800882 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801082 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800002 }, - { _MMIO(0x9888), 0x41800c62 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x161503e0 }, - { _MMIO(0x9888), 0x163503e0 }, - { _MMIO(0x9888), 0x165503e0 }, - { _MMIO(0x9888), 0x169503e0 }, - { _MMIO(0x9888), 0x16b503e0 }, - { _MMIO(0x9888), 0x16d503e0 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x04584000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b8000 }, - { _MMIO(0x9888), 0x0e1f00a8 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x06141000 }, - { _MMIO(0x9888), 0x041500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x0a338000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x0435c300 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x0c538000 }, - { _MMIO(0x9888), 0x06544000 }, - { _MMIO(0x9888), 0x065500c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dc4000 }, - { _MMIO(0x9888), 0x02bd8000 }, - { _MMIO(0x9888), 0x00d88000 }, - { _MMIO(0x9888), 0x02db4000 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f0002 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x06ba8000 }, - { _MMIO(0x9888), 0x02938000 }, - { _MMIO(0x9888), 0x04942000 }, - { _MMIO(0x9888), 0x0095c300 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x04b44000 }, - { _MMIO(0x9888), 0x02b500c3 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d38000 }, - { _MMIO(0x9888), 0x04d48000 }, - { _MMIO(0x9888), 0x02d5c300 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b3500 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c40 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41801482 }, - { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x14100812 }, - { _MMIO(0x9888), 0x14125800 }, - { _MMIO(0x9888), 0x161200c0 }, - { _MMIO(0x9888), 0x14300812 }, - { _MMIO(0x9888), 0x14325800 }, - { _MMIO(0x9888), 0x163200c0 }, - { _MMIO(0x9888), 0x005c4000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x003d8000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183d2800 }, - { _MMIO(0x9888), 0x00584000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b9400 }, - { _MMIO(0x9888), 0x1a5b002a }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f002a }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18380155 }, - { _MMIO(0x9888), 0x00392000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x00100047 }, - { _MMIO(0x9888), 0x06101a80 }, - { _MMIO(0x9888), 0x10100000 }, - { _MMIO(0x9888), 0x0810c000 }, - { _MMIO(0x9888), 0x0811c000 }, - { _MMIO(0x9888), 0x08126151 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x00134000 }, - { _MMIO(0x9888), 0x0e134000 }, - { _MMIO(0x9888), 0x161300a0 }, - { _MMIO(0x9888), 0x0a301ac7 }, - { _MMIO(0x9888), 0x10300000 }, - { _MMIO(0x9888), 0x0c30c000 }, - { _MMIO(0x9888), 0x0c31c000 }, - { _MMIO(0x9888), 0x0c326151 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x16332a00 }, - { _MMIO(0x9888), 0x18330001 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a2aa0 }, - { _MMIO(0x9888), 0x238b0020 }, - { _MMIO(0x9888), 0x258b5550 }, - { _MMIO(0x9888), 0x278b0001 }, - { _MMIO(0x9888), 0x1f850080 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x23850002 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830015 }, - { _MMIO(0x9888), 0x01844000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800002 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800884 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800002 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -4035,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x000000a0 }, { _MMIO(0x9888), 0x198b0000 }, { _MMIO(0x9888), 0x078b0066 }, { _MMIO(0x9888), 0x118b0000 }, @@ -4047,1330 +73,38 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x4f800000 }, { _MMIO(0x9888), 0x41800000 }, { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_DATA_PORT_READS_COALESCING: - dev_priv->perf.oa.n_mux_configs = - get_data_port_reads_coalescing_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_READS_COALESCING\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_data_port_reads_coalescing; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_data_port_reads_coalescing); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_data_port_reads_coalescing; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_data_port_reads_coalescing); - - return 0; - case METRIC_SET_ID_DATA_PORT_WRITES_COALESCING: - dev_priv->perf.oa.n_mux_configs = - get_data_port_writes_coalescing_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_WRITES_COALESCING\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_data_port_writes_coalescing; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_data_port_writes_coalescing); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_data_port_writes_coalescing; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_data_port_writes_coalescing); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_L3_4: - dev_priv->perf.oa.n_mux_configs = - get_l3_4_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_4; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_4); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_4; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_4); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER_1: - dev_priv->perf.oa.n_mux_configs = - get_sampler_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_1); - - return 0; - case METRIC_SET_ID_SAMPLER_2: - dev_priv->perf.oa.n_mux_configs = - get_sampler_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_2); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "35fbc9b2-a891-40a6-a38d-022bb7057552", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "233d0544-fff7-4281-8291-e02f222aff72", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "e99ccaca-821c-4df9-97a7-96bdb7204e43", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "27a364dc-8225-4ecb-b607-d6f1925598d9", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_data_port_reads_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_READS_COALESCING); -} - -static struct device_attribute dev_attr_data_port_reads_coalescing_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_data_port_reads_coalescing_id, - .store = NULL, -}; - -static struct attribute *attrs_data_port_reads_coalescing[] = { - &dev_attr_data_port_reads_coalescing_id.attr, - NULL, -}; - -static struct attribute_group group_data_port_reads_coalescing = { - .name = "857fc630-2f09-4804-85f1-084adfadd5ab", - .attrs = attrs_data_port_reads_coalescing, -}; - -static ssize_t -show_data_port_writes_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_WRITES_COALESCING); -} - -static struct device_attribute dev_attr_data_port_writes_coalescing_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_data_port_writes_coalescing_id, - .store = NULL, -}; - -static struct attribute *attrs_data_port_writes_coalescing[] = { - &dev_attr_data_port_writes_coalescing_id.attr, - NULL, -}; - -static struct attribute_group group_data_port_writes_coalescing = { - .name = "343ebc99-4a55-414c-8c17-d8e259cf5e20", - .attrs = attrs_data_port_writes_coalescing, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "446ae59b-ff2e-41c9-b49e-0184a54bf00a", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "84a7956f-1ea4-4d0d-837f-e39a0376e38c", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); -} - -static struct device_attribute dev_attr_l3_4_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_4_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_4[] = { - &dev_attr_l3_4_id.attr, - NULL, -}; - -static struct attribute_group group_l3_4 = { - .name = "92b493d9-df18-4bed-be06-5cac6f2a6f5f", - .attrs = attrs_l3_4, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "14345c35-cc46-40d0-bb04-6ed1fbb43679", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); -} - -static struct device_attribute dev_attr_sampler_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_1_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_1[] = { - &dev_attr_sampler_1_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_1 = { - .name = "f0c6ba37-d3d3-4211-91b5-226730312a54", - .attrs = attrs_sampler_1, -}; - -static ssize_t -show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); -} - -static struct device_attribute dev_attr_sampler_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_2_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_2[] = { - &dev_attr_sampler_2_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_2 = { - .name = "30bf3702-48cf-4bca-b412-7cf50bb2f564", - .attrs = attrs_sampler_2, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "238bec85-df05-44f3-b905-d166712f2451", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "24bf02cd-8693-4583-981c-c4165b33da01", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "e1743ca0-7fc8-410b-a066-de7bbb9280b7", - .attrs = attrs_vme_pipe, + { _MMIO(0x9840), 0x00000080 }, }; static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "d6de6f55-e526-4f79-a6a6-d7315c09044e", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "d6de6f55-e526-4f79-a6a6-d7315c09044e", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); - if (ret) - goto error_data_port_reads_coalescing; - } - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); - if (ret) - goto error_data_port_writes_coalescing; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (ret) - goto error_l3_4; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (ret) - goto error_sampler_1; - } - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (ret) - goto error_sampler_2; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); -error_sampler_2: - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); -error_sampler_1: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); -error_l3_4: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); -error_data_port_writes_coalescing: - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); -error_data_port_reads_coalescing: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.h b/drivers/gpu/drm/i915/i915_oa_bdw.h index 6363ff9f64c0..b812d16162ac 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.h +++ b/drivers/gpu/drm/i915/i915_oa_bdw.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_BDW_H__ #define __I915_OA_BDW_H__ -extern int i915_oa_n_builtin_metric_sets_bdw; - -extern int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c b/drivers/gpu/drm/i915/i915_oa_bxt.c index 93864d8f32dd..b69b900de0fe 100644 --- a/drivers/gpu/drm/i915/i915_oa_bxt.c +++ b/drivers/gpu/drm/i915/i915_oa_bxt.c @@ -31,1702 +31,6 @@ #include "i915_drv.h" #include "i915_oa_bxt.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_bxt = 15; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_0_sku_gte_0x03[] = { - { _MMIO(0x9888), 0x166c00f0 }, - { _MMIO(0x9888), 0x12120280 }, - { _MMIO(0x9888), 0x12320280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x419000a0 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2e0800 }, - { _MMIO(0x9888), 0x0e2e5900 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x1c4f0010 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a0fcc00 }, - { _MMIO(0x9888), 0x1c0f0002 }, - { _MMIO(0x9888), 0x1c2c0040 }, - { _MMIO(0x9888), 0x00101000 }, - { _MMIO(0x9888), 0x04101000 }, - { _MMIO(0x9888), 0x00114000 }, - { _MMIO(0x9888), 0x08114000 }, - { _MMIO(0x9888), 0x00120020 }, - { _MMIO(0x9888), 0x08120021 }, - { _MMIO(0x9888), 0x00141000 }, - { _MMIO(0x9888), 0x08141000 }, - { _MMIO(0x9888), 0x02308000 }, - { _MMIO(0x9888), 0x04302000 }, - { _MMIO(0x9888), 0x06318000 }, - { _MMIO(0x9888), 0x08318000 }, - { _MMIO(0x9888), 0x06320800 }, - { _MMIO(0x9888), 0x08320840 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x08344000 }, - { _MMIO(0x9888), 0x0d931831 }, - { _MMIO(0x9888), 0x0f939f3f }, - { _MMIO(0x9888), 0x01939e80 }, - { _MMIO(0x9888), 0x039303bc }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1993002a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900187 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901110 }, - { _MMIO(0x9888), 0x43900423 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900c02 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900020 }, - { _MMIO(0x9888), 0x59901111 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900821 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (dev_priv->drm.pdev->revision >= 0x03) { - regs[n] = mux_config_render_basic_0_sku_gte_0x03; - lens[n] = ARRAY_SIZE(mux_config_render_basic_0_sku_gte_0x03); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d4000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x0c2e1400 }, - { _MMIO(0x9888), 0x0e2e5100 }, - { _MMIO(0x9888), 0x102e0114 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004f6b42 }, - { _MMIO(0x9888), 0x064f6200 }, - { _MMIO(0x9888), 0x084f4100 }, - { _MMIO(0x9888), 0x0a4f0061 }, - { _MMIO(0x9888), 0x0c4f6c4c }, - { _MMIO(0x9888), 0x0e4f4b00 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0f8800 }, - { _MMIO(0x9888), 0x1c0f08a2 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c1451 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c0010 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x19938a28 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x19900177 }, - { _MMIO(0x9888), 0x1b900178 }, - { _MMIO(0x9888), 0x1d900125 }, - { _MMIO(0x9888), 0x1f900123 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c2e001f }, - { _MMIO(0x9888), 0x0a2f0000 }, - { _MMIO(0x9888), 0x10186800 }, - { _MMIO(0x9888), 0x11810019 }, - { _MMIO(0x9888), 0x15810013 }, - { _MMIO(0x9888), 0x13820020 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x17840000 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x21860000 }, - { _MMIO(0x9888), 0x178703e0 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x022e5400 }, - { _MMIO(0x9888), 0x002e0000 }, - { _MMIO(0x9888), 0x0e2e0080 }, - { _MMIO(0x9888), 0x082f0040 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x06174000 }, - { _MMIO(0x9888), 0x06180012 }, - { _MMIO(0x9888), 0x00180000 }, - { _MMIO(0x9888), 0x0d804000 }, - { _MMIO(0x9888), 0x0f804000 }, - { _MMIO(0x9888), 0x05804000 }, - { _MMIO(0x9888), 0x09810200 }, - { _MMIO(0x9888), 0x0b810030 }, - { _MMIO(0x9888), 0x03810003 }, - { _MMIO(0x9888), 0x21819140 }, - { _MMIO(0x9888), 0x23819050 }, - { _MMIO(0x9888), 0x25810018 }, - { _MMIO(0x9888), 0x0b820980 }, - { _MMIO(0x9888), 0x03820d80 }, - { _MMIO(0x9888), 0x11820000 }, - { _MMIO(0x9888), 0x0182c000 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x09824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0d830004 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x0f831000 }, - { _MMIO(0x9888), 0x01848072 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x09844000 }, - { _MMIO(0x9888), 0x0f848000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x09860092 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x01869100 }, - { _MMIO(0x9888), 0x0f870065 }, - { _MMIO(0x9888), 0x01870000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b952000 }, - { _MMIO(0x9888), 0x1d955055 }, - { _MMIO(0x9888), 0x1f951455 }, - { _MMIO(0x9888), 0x0992a000 }, - { _MMIO(0x9888), 0x0f928000 }, - { _MMIO(0x9888), 0x1192a800 }, - { _MMIO(0x9888), 0x1392028a }, - { _MMIO(0x9888), 0x0b92a000 }, - { _MMIO(0x9888), 0x0d922000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c01 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900863 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900c22 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x41900003 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900170 }, - { _MMIO(0x9888), 0x21900171 }, - { _MMIO(0x9888), 0x23900172 }, - { _MMIO(0x9888), 0x25900173 }, - { _MMIO(0x9888), 0x27900174 }, - { _MMIO(0x9888), 0x29900175 }, - { _MMIO(0x9888), 0x2b900176 }, - { _MMIO(0x9888), 0x2d900177 }, - { _MMIO(0x9888), 0x2f90017f }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900000 }, - { _MMIO(0x9888), 0x41900080 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900180 }, - { _MMIO(0x9888), 0x21900181 }, - { _MMIO(0x9888), 0x23900182 }, - { _MMIO(0x9888), 0x25900183 }, - { _MMIO(0x9888), 0x27900184 }, - { _MMIO(0x9888), 0x29900185 }, - { _MMIO(0x9888), 0x2b900186 }, - { _MMIO(0x9888), 0x2d900187 }, - { _MMIO(0x9888), 0x2f900170 }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x141c0160 }, - { _MMIO(0x9888), 0x161c0015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d5000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x0c2e5400 }, - { _MMIO(0x9888), 0x0e2e5515 }, - { _MMIO(0x9888), 0x102e0155 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x0e4cc000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0a4ea000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x0e4f4b41 }, - { _MMIO(0x9888), 0x004f4200 }, - { _MMIO(0x9888), 0x024f404c }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0a1bc000 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x001c0031 }, - { _MMIO(0x9888), 0x061c1900 }, - { _MMIO(0x9888), 0x081c1a33 }, - { _MMIO(0x9888), 0x0a1c1b35 }, - { _MMIO(0x9888), 0x0c1c3337 }, - { _MMIO(0x9888), 0x041c31c7 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0fa8aa }, - { _MMIO(0x9888), 0x1c0f0aaa }, - { _MMIO(0x9888), 0x182c8000 }, - { _MMIO(0x9888), 0x1c2c6aaa }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c2950 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993aaaa }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900400 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900001 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c03b0 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x0c2e0400 }, - { _MMIO(0x9888), 0x0e2e1500 }, - { _MMIO(0x9888), 0x102e0140 }, - { _MMIO(0x9888), 0x044c4000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004e2000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x1a4f4001 }, - { _MMIO(0x9888), 0x1c4f5005 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x180f1000 }, - { _MMIO(0x9888), 0x1a0fa800 }, - { _MMIO(0x9888), 0x1c0f0a00 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c4015 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x03931980 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993a00a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900178 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900400 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x022d4000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x064c8000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x024f6100 }, - { _MMIO(0x9888), 0x044f416b }, - { _MMIO(0x9888), 0x064f004b }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1a0f02a8 }, - { _MMIO(0x9888), 0x1a2c5500 }, - { _MMIO(0x9888), 0x0f808000 }, - { _MMIO(0x9888), 0x25810020 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1f951000 }, - { _MMIO(0x9888), 0x13920200 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4d900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1_0_sku_gte_0x03[] = { - { _MMIO(0x9888), 0x12643400 }, - { _MMIO(0x9888), 0x12653400 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x0a640024 }, - { _MMIO(0x9888), 0x10640000 }, - { _MMIO(0x9888), 0x04640000 }, - { _MMIO(0x9888), 0x0c650024 }, - { _MMIO(0x9888), 0x10650000 }, - { _MMIO(0x9888), 0x06650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static const struct i915_oa_reg mux_config_l3_1_0_sku_lt_0x03[] = { - { _MMIO(0x9888), 0x14640340 }, - { _MMIO(0x9888), 0x14650340 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x04642400 }, - { _MMIO(0x9888), 0x22640000 }, - { _MMIO(0x9888), 0x1a640000 }, - { _MMIO(0x9888), 0x06650024 }, - { _MMIO(0x9888), 0x22650000 }, - { _MMIO(0x9888), 0x1c650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (dev_priv->drm.pdev->revision >= 0x03) { - regs[n] = mux_config_l3_1_0_sku_gte_0x03; - lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_gte_0x03); - n++; - } - if (dev_priv->drm.pdev->revision < 0x03) { - regs[n] = mux_config_l3_1_0_sku_lt_0x03; - lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_lt_0x03); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102d7800 }, - { _MMIO(0x9888), 0x122d79e0 }, - { _MMIO(0x9888), 0x0c2f0004 }, - { _MMIO(0x9888), 0x100e3800 }, - { _MMIO(0x9888), 0x180f0005 }, - { _MMIO(0x9888), 0x002d0940 }, - { _MMIO(0x9888), 0x022d802f }, - { _MMIO(0x9888), 0x042d4013 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0050 }, - { _MMIO(0x9888), 0x022f0010 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x040e0480 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x060f0027 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x1a0f0040 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x439014a0 }, - { _MMIO(0x9888), 0x459000a4 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x121300a0 }, - { _MMIO(0x9888), 0x141600ab }, - { _MMIO(0x9888), 0x123300a0 }, - { _MMIO(0x9888), 0x143600ab }, - { _MMIO(0x9888), 0x125300a0 }, - { _MMIO(0x9888), 0x145600ab }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e01a0 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0065 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0800 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f023f }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2cc030 }, - { _MMIO(0x9888), 0x04132180 }, - { _MMIO(0x9888), 0x02130000 }, - { _MMIO(0x9888), 0x0c148000 }, - { _MMIO(0x9888), 0x0e142000 }, - { _MMIO(0x9888), 0x04148000 }, - { _MMIO(0x9888), 0x1e150140 }, - { _MMIO(0x9888), 0x1c150040 }, - { _MMIO(0x9888), 0x0c163000 }, - { _MMIO(0x9888), 0x0e160068 }, - { _MMIO(0x9888), 0x10160000 }, - { _MMIO(0x9888), 0x18160000 }, - { _MMIO(0x9888), 0x0a164000 }, - { _MMIO(0x9888), 0x04330043 }, - { _MMIO(0x9888), 0x02330000 }, - { _MMIO(0x9888), 0x0234a000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x1c350015 }, - { _MMIO(0x9888), 0x02363460 }, - { _MMIO(0x9888), 0x10360000 }, - { _MMIO(0x9888), 0x04360000 }, - { _MMIO(0x9888), 0x06360000 }, - { _MMIO(0x9888), 0x08364000 }, - { _MMIO(0x9888), 0x06530043 }, - { _MMIO(0x9888), 0x02530000 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x06542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550100 }, - { _MMIO(0x9888), 0x0e563000 }, - { _MMIO(0x9888), 0x00563400 }, - { _MMIO(0x9888), 0x10560000 }, - { _MMIO(0x9888), 0x18560000 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x0c564000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9014a0 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900820 }, - { _MMIO(0x9888), 0x45901022 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x141a0000 }, - { _MMIO(0x9888), 0x143a0000 }, - { _MMIO(0x9888), 0x145a0000 }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0150 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e006a }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0bc0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f0302 }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2c00f0 }, - { _MMIO(0x9888), 0x021a3080 }, - { _MMIO(0x9888), 0x041a31e5 }, - { _MMIO(0x9888), 0x02148000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150054 }, - { _MMIO(0x9888), 0x06168000 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x0c3a3280 }, - { _MMIO(0x9888), 0x0e3a0063 }, - { _MMIO(0x9888), 0x063a0061 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x0c348000 }, - { _MMIO(0x9888), 0x0e342000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1e350140 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x18360028 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x0e5a3080 }, - { _MMIO(0x9888), 0x005a3280 }, - { _MMIO(0x9888), 0x025a0063 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x02542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550001 }, - { _MMIO(0x9888), 0x18560080 }, - { _MMIO(0x9888), 0x02568000 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x45901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x141a026b }, - { _MMIO(0x9888), 0x143a0173 }, - { _MMIO(0x9888), 0x145a026b }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0069 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x180f6000 }, - { _MMIO(0x9888), 0x1a0f030a }, - { _MMIO(0x9888), 0x1a2c03c0 }, - { _MMIO(0x9888), 0x041a37e7 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150050 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x003a3380 }, - { _MMIO(0x9888), 0x063a006f }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x00348000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1a352000 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x02368000 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x025a37e7 }, - { _MMIO(0x9888), 0x0254a000 }, - { _MMIO(0x9888), 0x1c550005 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x06568000 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900020 }, - { _MMIO(0x9888), 0x45901080 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x141a001f }, - { _MMIO(0x9888), 0x143a001f }, - { _MMIO(0x9888), 0x145a001f }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0094 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x1a0f00e0 }, - { _MMIO(0x9888), 0x1a2c0c00 }, - { _MMIO(0x9888), 0x061a0063 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x06142000 }, - { _MMIO(0x9888), 0x1c150100 }, - { _MMIO(0x9888), 0x0c168000 }, - { _MMIO(0x9888), 0x043a3180 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x04348000 }, - { _MMIO(0x9888), 0x1c350040 }, - { _MMIO(0x9888), 0x0a368000 }, - { _MMIO(0x9888), 0x045a0063 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x1c550010 }, - { _MMIO(0x9888), 0x08568000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900004 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1756,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x19800000 }, { _MMIO(0x9888), 0x07800063 }, { _MMIO(0x9888), 0x11800000 }, @@ -1769,922 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "012d72cf-82a9-4d25-8ddf-74076fd30797", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "ce416533-e49e-4211-80af-ec513590a914", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "398e2452-18d7-42d0-b241-e4d0a9148ada", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "00ad5a41-7eab-4f7a-9103-49d411c67219", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "8364e2a8-af63-40af-b0d5-42969a255654", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "d260f03f-b34d-4b49-a44e-436819117332", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a", - .attrs = attrs_compute_extra, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "5ee72f5c-092f-421e-8b70-225f7c3e9612", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "5ee72f5c-092f-421e-8b70-225f7c3e9612", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.h b/drivers/gpu/drm/i915/i915_oa_bxt.h index 6cf7ba746e7e..690b963a2383 100644 --- a/drivers/gpu/drm/i915/i915_oa_bxt.h +++ b/drivers/gpu/drm/i915/i915_oa_bxt.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_BXT_H__ #define __I915_OA_BXT_H__ -extern int i915_oa_n_builtin_metric_sets_bxt; - -extern int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c index aa6bece7e75f..322a3f94cd16 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.c +++ b/drivers/gpu/drm/i915/i915_oa_chv.c @@ -31,1943 +31,6 @@ #include "i915_drv.h" #include "i915_oa_chv.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_L3_4, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER_1, - METRIC_SET_ID_SAMPLER_2, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_chv = 14; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x285a0006 }, - { _MMIO(0x9888), 0x2c110014 }, - { _MMIO(0x9888), 0x2e110000 }, - { _MMIO(0x9888), 0x2c310014 }, - { _MMIO(0x9888), 0x2e310000 }, - { _MMIO(0x9888), 0x2b8303df }, - { _MMIO(0x9888), 0x3580024f }, - { _MMIO(0x9888), 0x00580888 }, - { _MMIO(0x9888), 0x1e5a0015 }, - { _MMIO(0x9888), 0x205a0014 }, - { _MMIO(0x9888), 0x045a0000 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x02180500 }, - { _MMIO(0x9888), 0x00190555 }, - { _MMIO(0x9888), 0x021d0500 }, - { _MMIO(0x9888), 0x021f0a00 }, - { _MMIO(0x9888), 0x00380444 }, - { _MMIO(0x9888), 0x02390500 }, - { _MMIO(0x9888), 0x003a0666 }, - { _MMIO(0x9888), 0x00100111 }, - { _MMIO(0x9888), 0x06110030 }, - { _MMIO(0x9888), 0x0a110031 }, - { _MMIO(0x9888), 0x0e110046 }, - { _MMIO(0x9888), 0x04110000 }, - { _MMIO(0x9888), 0x00110000 }, - { _MMIO(0x9888), 0x00130111 }, - { _MMIO(0x9888), 0x00300444 }, - { _MMIO(0x9888), 0x08310030 }, - { _MMIO(0x9888), 0x0c310031 }, - { _MMIO(0x9888), 0x10310046 }, - { _MMIO(0x9888), 0x04310000 }, - { _MMIO(0x9888), 0x00310000 }, - { _MMIO(0x9888), 0x00330444 }, - { _MMIO(0x9888), 0x038a0a00 }, - { _MMIO(0x9888), 0x018b0fff }, - { _MMIO(0x9888), 0x038b0a00 }, - { _MMIO(0x9888), 0x01855000 }, - { _MMIO(0x9888), 0x03850055 }, - { _MMIO(0x9888), 0x13830021 }, - { _MMIO(0x9888), 0x15830020 }, - { _MMIO(0x9888), 0x1783002f }, - { _MMIO(0x9888), 0x1983002e }, - { _MMIO(0x9888), 0x1b83002d }, - { _MMIO(0x9888), 0x1d83002c }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x01840555 }, - { _MMIO(0x9888), 0x03840500 }, - { _MMIO(0x9888), 0x23800074 }, - { _MMIO(0x9888), 0x2580007d }, - { _MMIO(0x9888), 0x05800000 }, - { _MMIO(0x9888), 0x01805000 }, - { _MMIO(0x9888), 0x03800055 }, - { _MMIO(0x9888), 0x01865000 }, - { _MMIO(0x9888), 0x03860055 }, - { _MMIO(0x9888), 0x01875000 }, - { _MMIO(0x9888), 0x03870055 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x4380000a }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x4780000a }, - { _MMIO(0x9888), 0x49800000 }, - { _MMIO(0x9888), 0x4b800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x55800000 }, - { _MMIO(0x9888), 0x57800000 }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x2e5800e0 }, - { _MMIO(0x9888), 0x2e3800e0 }, - { _MMIO(0x9888), 0x3580024f }, - { _MMIO(0x9888), 0x3d800140 }, - { _MMIO(0x9888), 0x08580042 }, - { _MMIO(0x9888), 0x0c580040 }, - { _MMIO(0x9888), 0x1058004c }, - { _MMIO(0x9888), 0x1458004b }, - { _MMIO(0x9888), 0x04580000 }, - { _MMIO(0x9888), 0x00580000 }, - { _MMIO(0x9888), 0x00195555 }, - { _MMIO(0x9888), 0x06380042 }, - { _MMIO(0x9888), 0x0a380040 }, - { _MMIO(0x9888), 0x0e38004c }, - { _MMIO(0x9888), 0x1238004b }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x00384444 }, - { _MMIO(0x9888), 0x003a5555 }, - { _MMIO(0x9888), 0x018bffff }, - { _MMIO(0x9888), 0x01845555 }, - { _MMIO(0x9888), 0x17800074 }, - { _MMIO(0x9888), 0x1980007d }, - { _MMIO(0x9888), 0x1b80007c }, - { _MMIO(0x9888), 0x1d8000b6 }, - { _MMIO(0x9888), 0x1f8000b7 }, - { _MMIO(0x9888), 0x05800000 }, - { _MMIO(0x9888), 0x03800000 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x438000aa }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x4980012a }, - { _MMIO(0x9888), 0x4b80012a }, - { _MMIO(0x9888), 0x4d80012a }, - { _MMIO(0x9888), 0x4f80012a }, - { _MMIO(0x9888), 0x518001ce }, - { _MMIO(0x9888), 0x538001ce }, - { _MMIO(0x9888), 0x5580000e }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x261e0000 }, - { _MMIO(0x9888), 0x281f000f }, - { _MMIO(0x9888), 0x2817001a }, - { _MMIO(0x9888), 0x2791001f }, - { _MMIO(0x9888), 0x27880019 }, - { _MMIO(0x9888), 0x2d890000 }, - { _MMIO(0x9888), 0x278a0007 }, - { _MMIO(0x9888), 0x298d001f }, - { _MMIO(0x9888), 0x278e0020 }, - { _MMIO(0x9888), 0x2b8f0012 }, - { _MMIO(0x9888), 0x29900000 }, - { _MMIO(0x9888), 0x00184000 }, - { _MMIO(0x9888), 0x02181000 }, - { _MMIO(0x9888), 0x02194000 }, - { _MMIO(0x9888), 0x141e0002 }, - { _MMIO(0x9888), 0x041e0000 }, - { _MMIO(0x9888), 0x001e0000 }, - { _MMIO(0x9888), 0x221f0015 }, - { _MMIO(0x9888), 0x041f0000 }, - { _MMIO(0x9888), 0x001f4000 }, - { _MMIO(0x9888), 0x021f0000 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0213c000 }, - { _MMIO(0x9888), 0x02164000 }, - { _MMIO(0x9888), 0x24170012 }, - { _MMIO(0x9888), 0x04170000 }, - { _MMIO(0x9888), 0x07910005 }, - { _MMIO(0x9888), 0x05910000 }, - { _MMIO(0x9888), 0x01911500 }, - { _MMIO(0x9888), 0x03910501 }, - { _MMIO(0x9888), 0x0d880002 }, - { _MMIO(0x9888), 0x1d880003 }, - { _MMIO(0x9888), 0x05880000 }, - { _MMIO(0x9888), 0x0b890032 }, - { _MMIO(0x9888), 0x1b890031 }, - { _MMIO(0x9888), 0x05890000 }, - { _MMIO(0x9888), 0x01890040 }, - { _MMIO(0x9888), 0x03890040 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x198a0004 }, - { _MMIO(0x9888), 0x058a0000 }, - { _MMIO(0x9888), 0x018a8050 }, - { _MMIO(0x9888), 0x038a2050 }, - { _MMIO(0x9888), 0x018b95a9 }, - { _MMIO(0x9888), 0x038be5a9 }, - { _MMIO(0x9888), 0x018c1500 }, - { _MMIO(0x9888), 0x038c0501 }, - { _MMIO(0x9888), 0x178d0015 }, - { _MMIO(0x9888), 0x058d0000 }, - { _MMIO(0x9888), 0x138e0004 }, - { _MMIO(0x9888), 0x218e000c }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x018e0500 }, - { _MMIO(0x9888), 0x038e0101 }, - { _MMIO(0x9888), 0x0f8f0027 }, - { _MMIO(0x9888), 0x058f0000 }, - { _MMIO(0x9888), 0x018f0000 }, - { _MMIO(0x9888), 0x038f0001 }, - { _MMIO(0x9888), 0x11900013 }, - { _MMIO(0x9888), 0x1f900017 }, - { _MMIO(0x9888), 0x05900000 }, - { _MMIO(0x9888), 0x01900100 }, - { _MMIO(0x9888), 0x03900001 }, - { _MMIO(0x9888), 0x01845555 }, - { _MMIO(0x9888), 0x03845555 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x438000aa }, - { _MMIO(0x9888), 0x458000aa }, - { _MMIO(0x9888), 0x478000aa }, - { _MMIO(0x9888), 0x4980018c }, - { _MMIO(0x9888), 0x4b80014b }, - { _MMIO(0x9888), 0x4d800128 }, - { _MMIO(0x9888), 0x4f80012a }, - { _MMIO(0x9888), 0x51800187 }, - { _MMIO(0x9888), 0x5380014b }, - { _MMIO(0x9888), 0x55800149 }, - { _MMIO(0x9888), 0x5780010a }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fff7 }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x105c0232 }, - { _MMIO(0x9888), 0x10580232 }, - { _MMIO(0x9888), 0x10380232 }, - { _MMIO(0x9888), 0x10dc0232 }, - { _MMIO(0x9888), 0x10d80232 }, - { _MMIO(0x9888), 0x10b80232 }, - { _MMIO(0x9888), 0x118e4400 }, - { _MMIO(0x9888), 0x025c6080 }, - { _MMIO(0x9888), 0x045c004b }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x00582080 }, - { _MMIO(0x9888), 0x0258004b }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x04386080 }, - { _MMIO(0x9888), 0x0638404b }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a380000 }, - { _MMIO(0x9888), 0x0c380000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0cdc25c1 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0ad825c1 }, - { _MMIO(0x9888), 0x18db4000 }, - { _MMIO(0x9888), 0x1adb0001 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb825c1 }, - { _MMIO(0x9888), 0x18b80154 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baa05 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x098dc000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x098e05c0 }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x198f0020 }, - { _MMIO(0x9888), 0x2185aa0a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x19835000 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x19808000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x51800040 }, - { _MMIO(0x9888), 0x43800400 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800c62 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801042 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x418014a4 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x10bf03da }, - { _MMIO(0x9888), 0x14bf0001 }, - { _MMIO(0x9888), 0x12980340 }, - { _MMIO(0x9888), 0x12990340 }, - { _MMIO(0x9888), 0x0cbf1187 }, - { _MMIO(0x9888), 0x0ebf1205 }, - { _MMIO(0x9888), 0x00bf0500 }, - { _MMIO(0x9888), 0x02bf042b }, - { _MMIO(0x9888), 0x04bf002c }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02dac000 }, - { _MMIO(0x9888), 0x04da4000 }, - { _MMIO(0x9888), 0x04983400 }, - { _MMIO(0x9888), 0x10980000 }, - { _MMIO(0x9888), 0x06990034 }, - { _MMIO(0x9888), 0x10990000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029dc000 }, - { _MMIO(0x9888), 0x049d4000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00ba }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b95000 }, - { _MMIO(0x9888), 0x04b91000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0cba4000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x258b800a }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x103f03da }, - { _MMIO(0x9888), 0x143f0001 }, - { _MMIO(0x9888), 0x12180340 }, - { _MMIO(0x9888), 0x12190340 }, - { _MMIO(0x9888), 0x0c3f1187 }, - { _MMIO(0x9888), 0x0e3f1205 }, - { _MMIO(0x9888), 0x003f0500 }, - { _MMIO(0x9888), 0x023f042b }, - { _MMIO(0x9888), 0x043f002c }, - { _MMIO(0x9888), 0x0c5ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x04183400 }, - { _MMIO(0x9888), 0x10180000 }, - { _MMIO(0x9888), 0x06190034 }, - { _MMIO(0x9888), 0x10190000 }, - { _MMIO(0x9888), 0x0c1dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x101f02a8 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00ba }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a4000 }, - { _MMIO(0x9888), 0x1b8aa800 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258b4005 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x121b0340 }, - { _MMIO(0x9888), 0x103f0274 }, - { _MMIO(0x9888), 0x123f0000 }, - { _MMIO(0x9888), 0x129b0340 }, - { _MMIO(0x9888), 0x10bf0274 }, - { _MMIO(0x9888), 0x12bf0000 }, - { _MMIO(0x9888), 0x041b3400 }, - { _MMIO(0x9888), 0x101b0000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x0a3d4000 }, - { _MMIO(0x9888), 0x003f0080 }, - { _MMIO(0x9888), 0x023f0793 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f002a }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04399000 }, - { _MMIO(0x9888), 0x069b0034 }, - { _MMIO(0x9888), 0x109b0000 }, - { _MMIO(0x9888), 0x06dc4000 }, - { _MMIO(0x9888), 0x0cbd4000 }, - { _MMIO(0x9888), 0x0cbf0981 }, - { _MMIO(0x9888), 0x0ebf0a0f }, - { _MMIO(0x9888), 0x06d84000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0cdb4000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0080 }, - { _MMIO(0x9888), 0x0cb84000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800c00 }, - { _MMIO(0x9888), 0x47800c63 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a5 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800045 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_4[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_4[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_4[] = { - { _MMIO(0x9888), 0x121a0340 }, - { _MMIO(0x9888), 0x103f0017 }, - { _MMIO(0x9888), 0x123f0020 }, - { _MMIO(0x9888), 0x129a0340 }, - { _MMIO(0x9888), 0x10bf0017 }, - { _MMIO(0x9888), 0x12bf0020 }, - { _MMIO(0x9888), 0x041a3400 }, - { _MMIO(0x9888), 0x101a0000 }, - { _MMIO(0x9888), 0x043b8000 }, - { _MMIO(0x9888), 0x0a3e0010 }, - { _MMIO(0x9888), 0x003f0200 }, - { _MMIO(0x9888), 0x023f0113 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x02592000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a1c8000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0a1e8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f001a }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x069a0034 }, - { _MMIO(0x9888), 0x109a0000 }, - { _MMIO(0x9888), 0x06bb4000 }, - { _MMIO(0x9888), 0x0abe0040 }, - { _MMIO(0x9888), 0x0cbf0984 }, - { _MMIO(0x9888), 0x0ebf0a02 }, - { _MMIO(0x9888), 0x02d94000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0c9c0400 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x0c9e0400 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0040 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x47800842 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801084 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800044 }, -}; - -static int -get_l3_4_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_4; - lens[n] = ARRAY_SIZE(mux_config_l3_4); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00006000 }, - { _MMIO(0x2774), 0x0000f3ff }, - { _MMIO(0x2778), 0x00001800 }, - { _MMIO(0x277c), 0x0000fcff }, - { _MMIO(0x2780), 0x00000600 }, - { _MMIO(0x2784), 0x0000ff3f }, - { _MMIO(0x2788), 0x00000180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000060 }, - { _MMIO(0x2794), 0x0000fff3 }, - { _MMIO(0x2798), 0x00000018 }, - { _MMIO(0x279c), 0x0000fffc }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x143b000e }, - { _MMIO(0x9888), 0x043c55c0 }, - { _MMIO(0x9888), 0x0a1e0280 }, - { _MMIO(0x9888), 0x0c1e0408 }, - { _MMIO(0x9888), 0x10390000 }, - { _MMIO(0x9888), 0x12397a1f }, - { _MMIO(0x9888), 0x14bb000e }, - { _MMIO(0x9888), 0x04bc5000 }, - { _MMIO(0x9888), 0x0a9e0296 }, - { _MMIO(0x9888), 0x0c9e0008 }, - { _MMIO(0x9888), 0x10b90000 }, - { _MMIO(0x9888), 0x12b97a1f }, - { _MMIO(0x9888), 0x063b0042 }, - { _MMIO(0x9888), 0x103b0000 }, - { _MMIO(0x9888), 0x083c0000 }, - { _MMIO(0x9888), 0x0a3e0040 }, - { _MMIO(0x9888), 0x043f8000 }, - { _MMIO(0x9888), 0x02594000 }, - { _MMIO(0x9888), 0x045a8000 }, - { _MMIO(0x9888), 0x0c1c0400 }, - { _MMIO(0x9888), 0x041d8000 }, - { _MMIO(0x9888), 0x081e02c0 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1f0260 }, - { _MMIO(0x9888), 0x101f0014 }, - { _MMIO(0x9888), 0x003905e0 }, - { _MMIO(0x9888), 0x06390bc0 }, - { _MMIO(0x9888), 0x02390018 }, - { _MMIO(0x9888), 0x04394000 }, - { _MMIO(0x9888), 0x04bb0042 }, - { _MMIO(0x9888), 0x10bb0000 }, - { _MMIO(0x9888), 0x02bc05c0 }, - { _MMIO(0x9888), 0x08bc0000 }, - { _MMIO(0x9888), 0x0abe0004 }, - { _MMIO(0x9888), 0x02bf8000 }, - { _MMIO(0x9888), 0x02d91000 }, - { _MMIO(0x9888), 0x02da8000 }, - { _MMIO(0x9888), 0x089c8000 }, - { _MMIO(0x9888), 0x029d8000 }, - { _MMIO(0x9888), 0x089e8000 }, - { _MMIO(0x9888), 0x0e9e0000 }, - { _MMIO(0x9888), 0x0e9fa806 }, - { _MMIO(0x9888), 0x109f0142 }, - { _MMIO(0x9888), 0x08b90617 }, - { _MMIO(0x9888), 0x0ab90be0 }, - { _MMIO(0x9888), 0x02b94000 }, - { _MMIO(0x9888), 0x0d88f000 }, - { _MMIO(0x9888), 0x0f88000c }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x1b8a2800 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b52a0 }, - { _MMIO(0x9888), 0x258b6a95 }, - { _MMIO(0x9888), 0x278b0029 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1500 }, - { _MMIO(0x9888), 0x1b8c0014 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d8000 }, - { _MMIO(0x9888), 0x058d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4d800444 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f804000 }, - { _MMIO(0x9888), 0x43801080 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800084 }, - { _MMIO(0x9888), 0x53800044 }, - { _MMIO(0x9888), 0x47801080 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x41800840 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_1[] = { - { _MMIO(0x9888), 0x18921400 }, - { _MMIO(0x9888), 0x149500ab }, - { _MMIO(0x9888), 0x18b21400 }, - { _MMIO(0x9888), 0x14b500ab }, - { _MMIO(0x9888), 0x18d21400 }, - { _MMIO(0x9888), 0x14d500ab }, - { _MMIO(0x9888), 0x0cdc8000 }, - { _MMIO(0x9888), 0x0edc4000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x1abd00a0 }, - { _MMIO(0x9888), 0x0abd8000 }, - { _MMIO(0x9888), 0x0cd88000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x04d88000 }, - { _MMIO(0x9888), 0x1adb0050 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x06db8000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x109f02a0 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x18b82500 }, - { _MMIO(0x9888), 0x02b88000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb98000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x1aba0200 }, - { _MMIO(0x9888), 0x02ba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04908000 }, - { _MMIO(0x9888), 0x04918000 }, - { _MMIO(0x9888), 0x04927300 }, - { _MMIO(0x9888), 0x10920000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a934000 }, - { _MMIO(0x9888), 0x0a946000 }, - { _MMIO(0x9888), 0x0c959000 }, - { _MMIO(0x9888), 0x0e950098 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b04000 }, - { _MMIO(0x9888), 0x04b14000 }, - { _MMIO(0x9888), 0x04b20073 }, - { _MMIO(0x9888), 0x10b20000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x06b38000 }, - { _MMIO(0x9888), 0x08b34000 }, - { _MMIO(0x9888), 0x04b4c000 }, - { _MMIO(0x9888), 0x02b59890 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d04000 }, - { _MMIO(0x9888), 0x06d14000 }, - { _MMIO(0x9888), 0x06d20073 }, - { _MMIO(0x9888), 0x10d20000 }, - { _MMIO(0x9888), 0x18d30020 }, - { _MMIO(0x9888), 0x02d38000 }, - { _MMIO(0x9888), 0x0cd34000 }, - { _MMIO(0x9888), 0x0ad48000 }, - { _MMIO(0x9888), 0x04d42000 }, - { _MMIO(0x9888), 0x0ed59000 }, - { _MMIO(0x9888), 0x00d59800 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0f88000e }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x258b000a }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8d8000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_1; - lens[n] = ARRAY_SIZE(mux_config_sampler_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_2[] = { - { _MMIO(0x9888), 0x18121400 }, - { _MMIO(0x9888), 0x141500ab }, - { _MMIO(0x9888), 0x18321400 }, - { _MMIO(0x9888), 0x143500ab }, - { _MMIO(0x9888), 0x18521400 }, - { _MMIO(0x9888), 0x145500ab }, - { _MMIO(0x9888), 0x0c5c8000 }, - { _MMIO(0x9888), 0x0e5c4000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x1a3d00a0 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0c588000 }, - { _MMIO(0x9888), 0x0e584000 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x1a5b0050 }, - { _MMIO(0x9888), 0x045b8000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x101f02a0 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x18382500 }, - { _MMIO(0x9888), 0x02388000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c398000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x1a3a0200 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x04108000 }, - { _MMIO(0x9888), 0x04118000 }, - { _MMIO(0x9888), 0x04127300 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x1813000a }, - { _MMIO(0x9888), 0x0a134000 }, - { _MMIO(0x9888), 0x0a146000 }, - { _MMIO(0x9888), 0x0c159000 }, - { _MMIO(0x9888), 0x0e150098 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04304000 }, - { _MMIO(0x9888), 0x04314000 }, - { _MMIO(0x9888), 0x04320073 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x04338000 }, - { _MMIO(0x9888), 0x06338000 }, - { _MMIO(0x9888), 0x08334000 }, - { _MMIO(0x9888), 0x0434c000 }, - { _MMIO(0x9888), 0x02359890 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x06504000 }, - { _MMIO(0x9888), 0x06514000 }, - { _MMIO(0x9888), 0x06520073 }, - { _MMIO(0x9888), 0x10520000 }, - { _MMIO(0x9888), 0x18530020 }, - { _MMIO(0x9888), 0x02538000 }, - { _MMIO(0x9888), 0x0c534000 }, - { _MMIO(0x9888), 0x0a548000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x0e559000 }, - { _MMIO(0x9888), 0x00559800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x1b8aa000 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_2; - lens[n] = ARRAY_SIZE(mux_config_sampler_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000ffbf }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fff7 }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fff9 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x16154d60 }, - { _MMIO(0x9888), 0x16352e60 }, - { _MMIO(0x9888), 0x16554d60 }, - { _MMIO(0x9888), 0x16950000 }, - { _MMIO(0x9888), 0x16b50000 }, - { _MMIO(0x9888), 0x16d50000 }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x025b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04388000 }, - { _MMIO(0x9888), 0x06388000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x043a8000 }, - { _MMIO(0x9888), 0x063a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x0a138000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x0415cfc7 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x02338000 }, - { _MMIO(0x9888), 0x0c338000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x0035c700 }, - { _MMIO(0x9888), 0x063500cf }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04538000 }, - { _MMIO(0x9888), 0x06538000 }, - { _MMIO(0x9888), 0x0454c000 }, - { _MMIO(0x9888), 0x0255cfc7 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dc4000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x1abd00a8 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db0800 }, - { _MMIO(0x9888), 0x1adb0254 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b8156a }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x18baa000 }, - { _MMIO(0x9888), 0x1aba0002 }, - { _MMIO(0x9888), 0x16934000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a947000 }, - { _MMIO(0x9888), 0x0c95c5c1 }, - { _MMIO(0x9888), 0x0e9500c3 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x0eb38000 }, - { _MMIO(0x9888), 0x16b30040 }, - { _MMIO(0x9888), 0x18b30020 }, - { _MMIO(0x9888), 0x06b48000 }, - { _MMIO(0x9888), 0x08b41000 }, - { _MMIO(0x9888), 0x0ab48000 }, - { _MMIO(0x9888), 0x06b5c500 }, - { _MMIO(0x9888), 0x08b500c3 }, - { _MMIO(0x9888), 0x0eb5c100 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x16d31500 }, - { _MMIO(0x9888), 0x08d4e000 }, - { _MMIO(0x9888), 0x08d5c100 }, - { _MMIO(0x9888), 0x0ad5c3c5 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baaa5 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800c42 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800063 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800800 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a4 }, - { _MMIO(0x9888), 0x41801042 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000000 }, - { _MMIO(0x2784), 0x0000ff9f }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffe7 }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fffb }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000fffd }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x16150000 }, - { _MMIO(0x9888), 0x16350000 }, - { _MMIO(0x9888), 0x16550000 }, - { _MMIO(0x9888), 0x16952e60 }, - { _MMIO(0x9888), 0x16b54d60 }, - { _MMIO(0x9888), 0x16d52e60 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5c4000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183da000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x08588000 }, - { _MMIO(0x9888), 0x0a584000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5800 }, - { _MMIO(0x9888), 0x1a5b000a }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18382a55 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x1a3a02a0 }, - { _MMIO(0x9888), 0x0e138000 }, - { _MMIO(0x9888), 0x16130500 }, - { _MMIO(0x9888), 0x06148000 }, - { _MMIO(0x9888), 0x08146000 }, - { _MMIO(0x9888), 0x0615c100 }, - { _MMIO(0x9888), 0x0815c500 }, - { _MMIO(0x9888), 0x0a1500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x16335040 }, - { _MMIO(0x9888), 0x08349000 }, - { _MMIO(0x9888), 0x0a341000 }, - { _MMIO(0x9888), 0x083500c1 }, - { _MMIO(0x9888), 0x0a35c500 }, - { _MMIO(0x9888), 0x0c3500c3 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x1853002a }, - { _MMIO(0x9888), 0x0a54e000 }, - { _MMIO(0x9888), 0x0c55c500 }, - { _MMIO(0x9888), 0x0e55c1c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dc4000 }, - { _MMIO(0x9888), 0x04bd8000 }, - { _MMIO(0x9888), 0x06bd8000 }, - { _MMIO(0x9888), 0x02d8c000 }, - { _MMIO(0x9888), 0x02db8000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0aba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04938000 }, - { _MMIO(0x9888), 0x06938000 }, - { _MMIO(0x9888), 0x0494c000 }, - { _MMIO(0x9888), 0x0295cfc7 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x02b38000 }, - { _MMIO(0x9888), 0x08b38000 }, - { _MMIO(0x9888), 0x04b42000 }, - { _MMIO(0x9888), 0x06b41000 }, - { _MMIO(0x9888), 0x00b5c700 }, - { _MMIO(0x9888), 0x04b500cf }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x0ad38000 }, - { _MMIO(0x9888), 0x0cd38000 }, - { _MMIO(0x9888), 0x06d46000 }, - { _MMIO(0x9888), 0x04d5c700 }, - { _MMIO(0x9888), 0x06d500cf }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x258b555a }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800882 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801082 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800002 }, - { _MMIO(0x9888), 0x41800c62 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1997,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x000000a0 }, { _MMIO(0x9888), 0x59800000 }, { _MMIO(0x9888), 0x59800001 }, { _MMIO(0x9888), 0x338b0000 }, @@ -2008,866 +72,38 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x57800000 }, { _MMIO(0x1823a4), 0x00000000 }, { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_L3_4: - dev_priv->perf.oa.n_mux_configs = - get_l3_4_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_4; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_4); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_4; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_4); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER_1: - dev_priv->perf.oa.n_mux_configs = - get_sampler_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_1); - - return 0; - case METRIC_SET_ID_SAMPLER_2: - dev_priv->perf.oa.n_mux_configs = - get_sampler_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_2); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "f522a89c-ecd1-4522-8331-3383c54af5f5", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "a9ccc03d-a943-4e6b-9cd6-13e063075927", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "78a87ff9-543a-49ce-95ea-26d86071ea93", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); -} - -static struct device_attribute dev_attr_l3_4_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_4_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_4[] = { - &dev_attr_l3_4_id.attr, - NULL, -}; - -static struct attribute_group group_l3_4 = { - .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4", - .attrs = attrs_l3_4, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); -} - -static struct device_attribute dev_attr_sampler_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_1_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_1[] = { - &dev_attr_sampler_1_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_1 = { - .name = "71148d78-baf5-474f-878a-e23158d0265d", - .attrs = attrs_sampler_1, -}; - -static ssize_t -show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); -} - -static struct device_attribute dev_attr_sampler_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_2_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_2[] = { - &dev_attr_sampler_2_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_2 = { - .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84", - .attrs = attrs_sampler_2, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d", - .attrs = attrs_tdl_2, + { _MMIO(0x9840), 0x00000080 }, }; static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "4a534b07-cba3-414d-8d60-874830e883aa", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "4a534b07-cba3-414d-8d60-874830e883aa", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (ret) - goto error_l3_4; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (ret) - goto error_sampler_1; - } - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (ret) - goto error_sampler_2; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); -error_sampler_2: - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); -error_sampler_1: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); -error_l3_4: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "4a534b07-cba3-414d-8d60-874830e883aa"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_chv.h b/drivers/gpu/drm/i915/i915_oa_chv.h index 8b8bdc26d726..b9622496979e 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.h +++ b/drivers/gpu/drm/i915/i915_oa_chv.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_CHV_H__ #define __I915_OA_CHV_H__ -extern int i915_oa_n_builtin_metric_sets_chv; - -extern int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_glk.c b/drivers/gpu/drm/i915/i915_oa_glk.c index 2f356d51bff8..4ee527e4c926 100644 --- a/drivers/gpu/drm/i915/i915_oa_glk.c +++ b/drivers/gpu/drm/i915/i915_oa_glk.c @@ -31,1614 +31,6 @@ #include "i915_drv.h" #include "i915_oa_glk.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_glk = 15; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c00f0 }, - { _MMIO(0x9888), 0x12120280 }, - { _MMIO(0x9888), 0x12320280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x419000a0 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2e0800 }, - { _MMIO(0x9888), 0x0e2e5900 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x1c4f0010 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a0fcc00 }, - { _MMIO(0x9888), 0x1c0f0002 }, - { _MMIO(0x9888), 0x1c2c0040 }, - { _MMIO(0x9888), 0x00101000 }, - { _MMIO(0x9888), 0x04101000 }, - { _MMIO(0x9888), 0x00114000 }, - { _MMIO(0x9888), 0x08114000 }, - { _MMIO(0x9888), 0x00120020 }, - { _MMIO(0x9888), 0x08120021 }, - { _MMIO(0x9888), 0x00141000 }, - { _MMIO(0x9888), 0x08141000 }, - { _MMIO(0x9888), 0x02308000 }, - { _MMIO(0x9888), 0x04302000 }, - { _MMIO(0x9888), 0x06318000 }, - { _MMIO(0x9888), 0x08318000 }, - { _MMIO(0x9888), 0x06320800 }, - { _MMIO(0x9888), 0x08320840 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x08344000 }, - { _MMIO(0x9888), 0x0d931831 }, - { _MMIO(0x9888), 0x0f939f3f }, - { _MMIO(0x9888), 0x01939e80 }, - { _MMIO(0x9888), 0x039303bc }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1993002a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900187 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901110 }, - { _MMIO(0x9888), 0x43900423 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900c02 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900020 }, - { _MMIO(0x9888), 0x59901111 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900821 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d4000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x0c2e1400 }, - { _MMIO(0x9888), 0x0e2e5100 }, - { _MMIO(0x9888), 0x102e0114 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004f6b42 }, - { _MMIO(0x9888), 0x064f6200 }, - { _MMIO(0x9888), 0x084f4100 }, - { _MMIO(0x9888), 0x0a4f0061 }, - { _MMIO(0x9888), 0x0c4f6c4c }, - { _MMIO(0x9888), 0x0e4f4b00 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0f8800 }, - { _MMIO(0x9888), 0x1c0f08a2 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c1451 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c0010 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x19938a28 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x19900177 }, - { _MMIO(0x9888), 0x1b900178 }, - { _MMIO(0x9888), 0x1d900125 }, - { _MMIO(0x9888), 0x1f900123 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c2e001f }, - { _MMIO(0x9888), 0x0a2f0000 }, - { _MMIO(0x9888), 0x10186800 }, - { _MMIO(0x9888), 0x11810019 }, - { _MMIO(0x9888), 0x15810013 }, - { _MMIO(0x9888), 0x13820020 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x17840000 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x21860000 }, - { _MMIO(0x9888), 0x178703e0 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x022e5400 }, - { _MMIO(0x9888), 0x002e0000 }, - { _MMIO(0x9888), 0x0e2e0080 }, - { _MMIO(0x9888), 0x082f0040 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x06174000 }, - { _MMIO(0x9888), 0x06180012 }, - { _MMIO(0x9888), 0x00180000 }, - { _MMIO(0x9888), 0x0d804000 }, - { _MMIO(0x9888), 0x0f804000 }, - { _MMIO(0x9888), 0x05804000 }, - { _MMIO(0x9888), 0x09810200 }, - { _MMIO(0x9888), 0x0b810030 }, - { _MMIO(0x9888), 0x03810003 }, - { _MMIO(0x9888), 0x21819140 }, - { _MMIO(0x9888), 0x23819050 }, - { _MMIO(0x9888), 0x25810018 }, - { _MMIO(0x9888), 0x0b820980 }, - { _MMIO(0x9888), 0x03820d80 }, - { _MMIO(0x9888), 0x11820000 }, - { _MMIO(0x9888), 0x0182c000 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x09824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0d830004 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x0f831000 }, - { _MMIO(0x9888), 0x01848072 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x09844000 }, - { _MMIO(0x9888), 0x0f848000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x09860092 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x01869100 }, - { _MMIO(0x9888), 0x0f870065 }, - { _MMIO(0x9888), 0x01870000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b952000 }, - { _MMIO(0x9888), 0x1d955055 }, - { _MMIO(0x9888), 0x1f951455 }, - { _MMIO(0x9888), 0x0992a000 }, - { _MMIO(0x9888), 0x0f928000 }, - { _MMIO(0x9888), 0x1192a800 }, - { _MMIO(0x9888), 0x1392028a }, - { _MMIO(0x9888), 0x0b92a000 }, - { _MMIO(0x9888), 0x0d922000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c01 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900863 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900c22 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x41900003 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900170 }, - { _MMIO(0x9888), 0x21900171 }, - { _MMIO(0x9888), 0x23900172 }, - { _MMIO(0x9888), 0x25900173 }, - { _MMIO(0x9888), 0x27900174 }, - { _MMIO(0x9888), 0x29900175 }, - { _MMIO(0x9888), 0x2b900176 }, - { _MMIO(0x9888), 0x2d900177 }, - { _MMIO(0x9888), 0x2f90017f }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900000 }, - { _MMIO(0x9888), 0x41900080 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900180 }, - { _MMIO(0x9888), 0x21900181 }, - { _MMIO(0x9888), 0x23900182 }, - { _MMIO(0x9888), 0x25900183 }, - { _MMIO(0x9888), 0x27900184 }, - { _MMIO(0x9888), 0x29900185 }, - { _MMIO(0x9888), 0x2b900186 }, - { _MMIO(0x9888), 0x2d900187 }, - { _MMIO(0x9888), 0x2f900170 }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x141c0160 }, - { _MMIO(0x9888), 0x161c0015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d5000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x0c2e5400 }, - { _MMIO(0x9888), 0x0e2e5515 }, - { _MMIO(0x9888), 0x102e0155 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x0e4cc000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0a4ea000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x0e4f4b41 }, - { _MMIO(0x9888), 0x004f4200 }, - { _MMIO(0x9888), 0x024f404c }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0a1bc000 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x001c0031 }, - { _MMIO(0x9888), 0x061c1900 }, - { _MMIO(0x9888), 0x081c1a33 }, - { _MMIO(0x9888), 0x0a1c1b35 }, - { _MMIO(0x9888), 0x0c1c3337 }, - { _MMIO(0x9888), 0x041c31c7 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0fa8aa }, - { _MMIO(0x9888), 0x1c0f0aaa }, - { _MMIO(0x9888), 0x182c8000 }, - { _MMIO(0x9888), 0x1c2c6aaa }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c2950 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993aaaa }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900400 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900001 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c03b0 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x0c2e0400 }, - { _MMIO(0x9888), 0x0e2e1500 }, - { _MMIO(0x9888), 0x102e0140 }, - { _MMIO(0x9888), 0x044c4000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004e2000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x1a4f4001 }, - { _MMIO(0x9888), 0x1c4f5005 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x180f1000 }, - { _MMIO(0x9888), 0x1a0fa800 }, - { _MMIO(0x9888), 0x1c0f0a00 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c4015 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x03931980 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993a00a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900178 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900400 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x022d4000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x064c8000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x024f6100 }, - { _MMIO(0x9888), 0x044f416b }, - { _MMIO(0x9888), 0x064f004b }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1a0f02a8 }, - { _MMIO(0x9888), 0x1a2c5500 }, - { _MMIO(0x9888), 0x0f808000 }, - { _MMIO(0x9888), 0x25810020 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1f951000 }, - { _MMIO(0x9888), 0x13920200 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4d900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x12643400 }, - { _MMIO(0x9888), 0x12653400 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x0a640024 }, - { _MMIO(0x9888), 0x10640000 }, - { _MMIO(0x9888), 0x04640000 }, - { _MMIO(0x9888), 0x0c650024 }, - { _MMIO(0x9888), 0x10650000 }, - { _MMIO(0x9888), 0x06650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102d7800 }, - { _MMIO(0x9888), 0x122d79e0 }, - { _MMIO(0x9888), 0x0c2f0004 }, - { _MMIO(0x9888), 0x100e3800 }, - { _MMIO(0x9888), 0x180f0005 }, - { _MMIO(0x9888), 0x002d0940 }, - { _MMIO(0x9888), 0x022d802f }, - { _MMIO(0x9888), 0x042d4013 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0050 }, - { _MMIO(0x9888), 0x022f0010 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x040e0480 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x060f0027 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x1a0f0040 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x439014a0 }, - { _MMIO(0x9888), 0x459000a4 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x121300a0 }, - { _MMIO(0x9888), 0x141600ab }, - { _MMIO(0x9888), 0x123300a0 }, - { _MMIO(0x9888), 0x143600ab }, - { _MMIO(0x9888), 0x125300a0 }, - { _MMIO(0x9888), 0x145600ab }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e01a0 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0065 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0800 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f023f }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2cc030 }, - { _MMIO(0x9888), 0x04132180 }, - { _MMIO(0x9888), 0x02130000 }, - { _MMIO(0x9888), 0x0c148000 }, - { _MMIO(0x9888), 0x0e142000 }, - { _MMIO(0x9888), 0x04148000 }, - { _MMIO(0x9888), 0x1e150140 }, - { _MMIO(0x9888), 0x1c150040 }, - { _MMIO(0x9888), 0x0c163000 }, - { _MMIO(0x9888), 0x0e160068 }, - { _MMIO(0x9888), 0x10160000 }, - { _MMIO(0x9888), 0x18160000 }, - { _MMIO(0x9888), 0x0a164000 }, - { _MMIO(0x9888), 0x04330043 }, - { _MMIO(0x9888), 0x02330000 }, - { _MMIO(0x9888), 0x0234a000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x1c350015 }, - { _MMIO(0x9888), 0x02363460 }, - { _MMIO(0x9888), 0x10360000 }, - { _MMIO(0x9888), 0x04360000 }, - { _MMIO(0x9888), 0x06360000 }, - { _MMIO(0x9888), 0x08364000 }, - { _MMIO(0x9888), 0x06530043 }, - { _MMIO(0x9888), 0x02530000 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x06542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550100 }, - { _MMIO(0x9888), 0x0e563000 }, - { _MMIO(0x9888), 0x00563400 }, - { _MMIO(0x9888), 0x10560000 }, - { _MMIO(0x9888), 0x18560000 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x0c564000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9014a0 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900820 }, - { _MMIO(0x9888), 0x45901022 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x141a0000 }, - { _MMIO(0x9888), 0x143a0000 }, - { _MMIO(0x9888), 0x145a0000 }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0150 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e006a }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0bc0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f0302 }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2c00f0 }, - { _MMIO(0x9888), 0x021a3080 }, - { _MMIO(0x9888), 0x041a31e5 }, - { _MMIO(0x9888), 0x02148000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150054 }, - { _MMIO(0x9888), 0x06168000 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x0c3a3280 }, - { _MMIO(0x9888), 0x0e3a0063 }, - { _MMIO(0x9888), 0x063a0061 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x0c348000 }, - { _MMIO(0x9888), 0x0e342000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1e350140 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x18360028 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x0e5a3080 }, - { _MMIO(0x9888), 0x005a3280 }, - { _MMIO(0x9888), 0x025a0063 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x02542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550001 }, - { _MMIO(0x9888), 0x18560080 }, - { _MMIO(0x9888), 0x02568000 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x45901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x141a026b }, - { _MMIO(0x9888), 0x143a0173 }, - { _MMIO(0x9888), 0x145a026b }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0069 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x180f6000 }, - { _MMIO(0x9888), 0x1a0f030a }, - { _MMIO(0x9888), 0x1a2c03c0 }, - { _MMIO(0x9888), 0x041a37e7 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150050 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x003a3380 }, - { _MMIO(0x9888), 0x063a006f }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x00348000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1a352000 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x02368000 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x025a37e7 }, - { _MMIO(0x9888), 0x0254a000 }, - { _MMIO(0x9888), 0x1c550005 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x06568000 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900020 }, - { _MMIO(0x9888), 0x45901080 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x141a001f }, - { _MMIO(0x9888), 0x143a001f }, - { _MMIO(0x9888), 0x145a001f }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0094 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x1a0f00e0 }, - { _MMIO(0x9888), 0x1a2c0c00 }, - { _MMIO(0x9888), 0x061a0063 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x06142000 }, - { _MMIO(0x9888), 0x1c150100 }, - { _MMIO(0x9888), 0x0c168000 }, - { _MMIO(0x9888), 0x043a3180 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x04348000 }, - { _MMIO(0x9888), 0x1c350040 }, - { _MMIO(0x9888), 0x0a368000 }, - { _MMIO(0x9888), 0x045a0063 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x1c550010 }, - { _MMIO(0x9888), 0x08568000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900004 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1668,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x19800000 }, { _MMIO(0x9888), 0x07800063 }, { _MMIO(0x9888), 0x11800000 }, @@ -1681,922 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "814285f6-354d-41d2-ba49-e24e622714a0", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "07d397a6-b3e6-49f6-9433-a4f293d55978", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "1a356946-5428-450b-a2f0-89f8783a302d", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "bc9bcff2-459a-4cbc-986d-a84b077153f3", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "88ec931f-5b4a-453a-9db6-a61232b6143d", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "530d176d-2a18-4014-adf8-1500c6c60835", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "fdee5a5a-f23c-43d1-aa73-f6257c71671d", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "6617623e-ca73-4791-b2b7-ddedd0846a0c", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "f3b2ea63-e82e-4234-b418-44dd20dd34d0", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "14411d35-cbf6-4f5e-b68b-190faf9a1a83", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "15274c82-27d2-4819-876a-7cb1a2c59ba4", - .attrs = attrs_compute_extra, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "dd3fd789-e783-4204-8cd0-b671bbccb0cf", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_glk.h b/drivers/gpu/drm/i915/i915_oa_glk.h index 5511bb1cecf7..63bd113f4bc9 100644 --- a/drivers/gpu/drm/i915/i915_oa_glk.h +++ b/drivers/gpu/drm/i915/i915_oa_glk.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_GLK_H__ #define __I915_OA_GLK_H__ -extern int i915_oa_n_builtin_metric_sets_glk; - -extern int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c index 10f169f683b7..56b03773bb9d 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.c +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c @@ -31,17 +31,6 @@ #include "i915_drv.h" #include "i915_oa_hsw.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_SAMPLER_BALANCE, -}; - -int i915_oa_n_builtin_metric_sets_hsw = 6; - static const struct i915_oa_reg b_counter_config_render_basic[] = { { _MMIO(0x2724), 0x00800000 }, { _MMIO(0x2720), 0x00000000 }, @@ -53,6 +42,7 @@ static const struct i915_oa_reg flex_eu_config_render_basic[] = { }; static const struct i915_oa_reg mux_config_render_basic[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x253a4), 0x01600000 }, { _MMIO(0x25440), 0x00100000 }, { _MMIO(0x25128), 0x00000000 }, @@ -114,750 +104,35 @@ static const struct i915_oa_reg mux_config_render_basic[] = { { _MMIO(0x25428), 0x00042049 }, }; -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2718), 0xaaaaaaaa }, - { _MMIO(0x271c), 0xaaaaaaaa }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2728), 0xaaaaaaaa }, - { _MMIO(0x272c), 0xaaaaaaaa }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00000000 }, - { _MMIO(0x2748), 0x00000000 }, - { _MMIO(0x274c), 0x00000000 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2754), 0x00000000 }, - { _MMIO(0x2758), 0x00000000 }, - { _MMIO(0x275c), 0x00000000 }, - { _MMIO(0x236c), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x253a4), 0x00000000 }, - { _MMIO(0x2681c), 0x01f00800 }, - { _MMIO(0x26820), 0x00001000 }, - { _MMIO(0x2781c), 0x01f00800 }, - { _MMIO(0x26520), 0x00000007 }, - { _MMIO(0x265a0), 0x00000007 }, - { _MMIO(0x25380), 0x00000010 }, - { _MMIO(0x2538c), 0x00300000 }, - { _MMIO(0x25384), 0xaa8aaaaa }, - { _MMIO(0x25404), 0xffffffff }, - { _MMIO(0x26800), 0x00004202 }, - { _MMIO(0x26808), 0x00605817 }, - { _MMIO(0x2680c), 0x10001005 }, - { _MMIO(0x26804), 0x00000000 }, - { _MMIO(0x27800), 0x00000102 }, - { _MMIO(0x27808), 0x0c0701e0 }, - { _MMIO(0x2780c), 0x000200a0 }, - { _MMIO(0x27804), 0x00000000 }, - { _MMIO(0x26484), 0x44000000 }, - { _MMIO(0x26704), 0x44000000 }, - { _MMIO(0x26500), 0x00000006 }, - { _MMIO(0x26510), 0x00000001 }, - { _MMIO(0x26504), 0x88000000 }, - { _MMIO(0x26580), 0x00000006 }, - { _MMIO(0x26590), 0x00000020 }, - { _MMIO(0x26584), 0x00000000 }, - { _MMIO(0x26104), 0x55822222 }, - { _MMIO(0x26184), 0xaa866666 }, - { _MMIO(0x25420), 0x08320c83 }, - { _MMIO(0x25424), 0x06820c83 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000c03 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2770), 0x0007fe2a }, - { _MMIO(0x2774), 0x0000ff00 }, - { _MMIO(0x2778), 0x0007fe6a }, - { _MMIO(0x277c), 0x0000ff00 }, - { _MMIO(0x2780), 0x0007fe92 }, - { _MMIO(0x2784), 0x0000ff00 }, - { _MMIO(0x2788), 0x0007fea2 }, - { _MMIO(0x278c), 0x0000ff00 }, - { _MMIO(0x2790), 0x0007fe32 }, - { _MMIO(0x2794), 0x0000ff00 }, - { _MMIO(0x2798), 0x0007fe9a }, - { _MMIO(0x279c), 0x0000ff00 }, - { _MMIO(0x27a0), 0x0007ff23 }, - { _MMIO(0x27a4), 0x0000ff00 }, - { _MMIO(0x27a8), 0x0007fff3 }, - { _MMIO(0x27ac), 0x0000fffe }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x2681c), 0x3eb00800 }, - { _MMIO(0x26820), 0x00900000 }, - { _MMIO(0x25384), 0x02aaaaaa }, - { _MMIO(0x25404), 0x03ffffff }, - { _MMIO(0x26800), 0x00142284 }, - { _MMIO(0x26808), 0x0e629062 }, - { _MMIO(0x2680c), 0x3f6f55cb }, - { _MMIO(0x26810), 0x00000014 }, - { _MMIO(0x26804), 0x00000000 }, - { _MMIO(0x26104), 0x02aaaaaa }, - { _MMIO(0x26184), 0x02aaaaaa }, - { _MMIO(0x25420), 0x00000000 }, - { _MMIO(0x25424), 0x00000000 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x76543298 }, - { _MMIO(0x2748), 0x98989898 }, - { _MMIO(0x2744), 0x000000e4 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x98a98a98 }, - { _MMIO(0x2758), 0x88888888 }, - { _MMIO(0x2754), 0x000c5500 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fc00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fc00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fc00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fc00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fc00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fc00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fc00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fc00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x253a4), 0x34300000 }, - { _MMIO(0x25440), 0x2d800000 }, - { _MMIO(0x25444), 0x00000008 }, - { _MMIO(0x25128), 0x0e600000 }, - { _MMIO(0x25380), 0x00000450 }, - { _MMIO(0x25390), 0x00052c43 }, - { _MMIO(0x25384), 0x00000000 }, - { _MMIO(0x25400), 0x00006144 }, - { _MMIO(0x25408), 0x0a418820 }, - { _MMIO(0x2540c), 0x000820e6 }, - { _MMIO(0x25404), 0xff500000 }, - { _MMIO(0x25100), 0x000005d6 }, - { _MMIO(0x2510c), 0x0ef00000 }, - { _MMIO(0x25104), 0x00000000 }, - { _MMIO(0x25420), 0x02108421 }, - { _MMIO(0x25424), 0x00008421 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x76543298 }, - { _MMIO(0x2748), 0x98989898 }, - { _MMIO(0x2744), 0x000000e4 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0xbabababa }, - { _MMIO(0x2758), 0x88888888 }, - { _MMIO(0x2754), 0x000c5500 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fc00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fc00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fc00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fc00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fc00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fc00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fc00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fc00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x253a4), 0x34300000 }, - { _MMIO(0x25440), 0x01500000 }, - { _MMIO(0x25444), 0x00000120 }, - { _MMIO(0x25128), 0x0c200000 }, - { _MMIO(0x25380), 0x00000450 }, - { _MMIO(0x25390), 0x00052c43 }, - { _MMIO(0x25384), 0x00000000 }, - { _MMIO(0x25400), 0x00007184 }, - { _MMIO(0x25408), 0x0a418820 }, - { _MMIO(0x2540c), 0x000820e6 }, - { _MMIO(0x25404), 0xff500000 }, - { _MMIO(0x25100), 0x000005d6 }, - { _MMIO(0x2510c), 0x1e700000 }, - { _MMIO(0x25104), 0x00000000 }, - { _MMIO(0x25420), 0x02108421 }, - { _MMIO(0x25424), 0x00008421 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_balance[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_balance[] = { -}; - -static const struct i915_oa_reg mux_config_sampler_balance[] = { - { _MMIO(0x2eb9c), 0x01906400 }, - { _MMIO(0x2fb9c), 0x01906400 }, - { _MMIO(0x253a4), 0x00000000 }, - { _MMIO(0x26b9c), 0x01906400 }, - { _MMIO(0x27b9c), 0x01906400 }, - { _MMIO(0x27104), 0x00a00000 }, - { _MMIO(0x27184), 0x00a50000 }, - { _MMIO(0x2e804), 0x00500000 }, - { _MMIO(0x2e984), 0x00500000 }, - { _MMIO(0x2eb04), 0x00500000 }, - { _MMIO(0x2eb80), 0x00000084 }, - { _MMIO(0x2eb8c), 0x14200000 }, - { _MMIO(0x2eb84), 0x00000000 }, - { _MMIO(0x2f804), 0x00050000 }, - { _MMIO(0x2f984), 0x00050000 }, - { _MMIO(0x2fb04), 0x00050000 }, - { _MMIO(0x2fb80), 0x00000084 }, - { _MMIO(0x2fb8c), 0x00050800 }, - { _MMIO(0x2fb84), 0x00000000 }, - { _MMIO(0x25380), 0x00000010 }, - { _MMIO(0x2538c), 0x000000c0 }, - { _MMIO(0x25384), 0xaa550000 }, - { _MMIO(0x25404), 0xffffc000 }, - { _MMIO(0x26804), 0x50000000 }, - { _MMIO(0x26984), 0x50000000 }, - { _MMIO(0x26b04), 0x50000000 }, - { _MMIO(0x26b80), 0x00000084 }, - { _MMIO(0x26b90), 0x00050800 }, - { _MMIO(0x26b84), 0x00000000 }, - { _MMIO(0x27804), 0x05000000 }, - { _MMIO(0x27984), 0x05000000 }, - { _MMIO(0x27b04), 0x05000000 }, - { _MMIO(0x27b80), 0x00000084 }, - { _MMIO(0x27b90), 0x00000142 }, - { _MMIO(0x27b84), 0x00000000 }, - { _MMIO(0x26104), 0xa0000000 }, - { _MMIO(0x26184), 0xa5000000 }, - { _MMIO(0x25424), 0x00008620 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x0004a54a }, -}; - -static int -get_sampler_balance_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_balance; - lens[n] = ARRAY_SIZE(mux_config_sampler_balance); - n++; - - return n; -} - -int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_SAMPLER_BALANCE: - dev_priv->perf.oa.n_mux_configs = - get_sampler_balance_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_BALANCE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_balance; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_balance); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_balance; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_balance); - - return 0; - default: - return -ENODEV; - } -} - static ssize_t show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "403d8832-1a27-4aa6-a64e-f5389ce7b212", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "3865be28-6982-49fe-9494-e4d1b4795413", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "bb5ed49b-2497-4095-94f6-26ba294db88a", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "3358d639-9b5f-45ab-976d-9b08cbfc6240", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_sampler_balance_id(struct device *kdev, struct device_attribute *attr, char *buf) +void +i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv) { - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_BALANCE); -} - -static struct device_attribute dev_attr_sampler_balance_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_balance_id, - .store = NULL, -}; + strncpy(dev_priv->perf.oa.test_config.uuid, + "403d8832-1a27-4aa6-a64e-f5389ce7b212", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; -static struct attribute *attrs_sampler_balance[] = { - &dev_attr_sampler_balance_id.attr, - NULL, -}; + dev_priv->perf.oa.test_config.mux_regs = mux_config_render_basic; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic); -static struct attribute_group group_sampler_balance = { - .name = "bc274488-b4b6-40c7-90da-b77d7ad16189", - .attrs = attrs_sampler_balance, -}; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_render_basic; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic); -int -i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_render_basic; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic); - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); - if (ret) - goto error_sampler_balance; - } + dev_priv->perf.oa.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; - return 0; - -error_sampler_balance: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} - -void -i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_render_basic_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.h b/drivers/gpu/drm/i915/i915_oa_hsw.h index 6fe7e0690ef3..74d03439c157 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.h +++ b/drivers/gpu/drm/i915/i915_oa_hsw.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_HSW_H__ #define __I915_OA_HSW_H__ -extern int i915_oa_n_builtin_metric_sets_hsw; - -extern int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.c b/drivers/gpu/drm/i915/i915_oa_kblgt2.c index 87dbd0a0b076..b6e7cc774136 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.c @@ -31,1828 +31,6 @@ #include "i915_drv.h" #include "i915_oa_kblgt2.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_kblgt2 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0080 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0d2000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162c2200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190001f }, - { _MMIO(0x9888), 0x51904400 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c21 }, - { _MMIO(0x9888), 0x47900061 }, - { _MMIO(0x9888), 0x57904440 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900004 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57900400 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53904444 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0e0f006c }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1190e000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c00 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x143a5800 }, - { _MMIO(0x9888), 0x163a00c0 }, - { _MMIO(0x9888), 0x12380240 }, - { _MMIO(0x9888), 0x14380002 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c1500 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f9500 }, - { _MMIO(0x9888), 0x100f002a }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x0a2dc000 }, - { _MMIO(0x9888), 0x0c2dc000 }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x06393000 }, - { _MMIO(0x9888), 0x0c3a28c1 }, - { _MMIO(0x9888), 0x003a0000 }, - { _MMIO(0x9888), 0x0a33f000 }, - { _MMIO(0x9888), 0x0c33f000 }, - { _MMIO(0x9888), 0x0a37a000 }, - { _MMIO(0x9888), 0x0c37a000 }, - { _MMIO(0x9888), 0x0a380977 }, - { _MMIO(0x9888), 0x08380000 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06383000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900800 }, - { _MMIO(0x9888), 0x47901000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900844 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1882,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1896,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "f8d677e9-ff6f-4df1-9310-0334c6efacce", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "e17fc42a-e614-41b6-90c4-1074841a6c77", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "d7a17a3a-ca71-40d2-a919-ace80d50633f", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "57b59202-172b-477a-87de-33f85572c589", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "4af0400a-81c3-47db-a6b6-deddbd75680e", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "0e22f995-79ca-4f67-83ab-e9d9772488d8", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "d2bbe790-f058-42d9-81c6-cdedcf655bc2", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "2f8e32e4-5956-46e2-af31-c8ea95887332", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "ca046aad-b5fb-4101-adce-6473ee6e5b14", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "605f388f-24bb-455c-88e3-8d57ae0d7e9f", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "105db928-5542-466b-9128-e1f3c91426cb", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "03db94d2-b37f-4c58-a791-0d2067b013bb", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "baa3c7e4-52b6-4b85-801e-465a94b746dd", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "baa3c7e4-52b6-4b85-801e-465a94b746dd", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "baa3c7e4-52b6-4b85-801e-465a94b746dd"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.h b/drivers/gpu/drm/i915/i915_oa_kblgt2.h index 7e61bfc4f9f5..25b803546dc1 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt2.h +++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_KBLGT2_H__ #define __I915_OA_KBLGT2_H__ -extern int i915_oa_n_builtin_metric_sets_kblgt2; - -extern int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.c b/drivers/gpu/drm/i915/i915_oa_kblgt3.c index 6ed092566a32..5576afdd9a7e 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.c @@ -31,1877 +31,6 @@ #include "i915_drv.h" #include "i915_oa_kblgt3.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_kblgt3 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0380 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162ca200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0200 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x51902240 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900242 }, - { _MMIO(0x9888), 0x45900084 }, - { _MMIO(0x9888), 0x47901400 }, - { _MMIO(0x9888), 0x57902220 }, - { _MMIO(0x9888), 0x49900c60 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900002 }, - { _MMIO(0x9888), 0x43900c63 }, - { _MMIO(0x9888), 0x53902222 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57900400 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53904444 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900002 }, - { _MMIO(0x9888), 0x53900420 }, - { _MMIO(0x9888), 0x459000a1 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900040 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900004 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x479008a5 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1931,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1945,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "0286c920-2f6d-493b-b22d-7a5280df43de", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "9823aaa1-b06f-40ce-884b-cd798c79f0c2", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "c7c735f3-ce58-45cf-aa04-30b183f1faff", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "96ec2219-040b-428a-856a-6bc03363a057", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "03372b64-4996-4d3b-aa18-790e75eeb9c2", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "2ce0911a-27fc-4887-96f0-11084fa807c3", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "546c4c1d-99b8-42fb-a107-5aaabb5314a8", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "4e93d156-9b39-4268-8544-a8e0480806d7", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "de1bec86-ca92-4b43-89fa-147653221cc0", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "469a05e5-e299-46f7-9598-7b05f3c34991", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "52f925c6-786a-4ec6-86ce-cba85c83453a", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "efc497ac-884e-4ee4-a4a8-15fba22aaf21", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "bfd9764d-2c5b-4c16-bfc1-89de3ca10917", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "f1792f32-6db2-4b50-b4b2-557128f1688d", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "f1792f32-6db2-4b50-b4b2-557128f1688d", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "f1792f32-6db2-4b50-b4b2-557128f1688d"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.h b/drivers/gpu/drm/i915/i915_oa_kblgt3.h index b0ca7f3114d3..d5b5b5c1923e 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt3.h +++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_KBLGT3_H__ #define __I915_OA_KBLGT3_H__ -extern int i915_oa_n_builtin_metric_sets_kblgt3; - -extern int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c b/drivers/gpu/drm/i915/i915_oa_sklgt2.c index 1268beda212c..890d55879946 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c @@ -31,2317 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt2.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt2 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_1_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0080 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0d2000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162c2200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190001f }, - { _MMIO(0x9888), 0x51904400 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c21 }, - { _MMIO(0x9888), 0x47900061 }, - { _MMIO(0x9888), 0x57904440 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900004 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (dev_priv->drm.pdev->revision >= 0x02) { - regs[n] = mux_config_render_basic_1_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_basic_1_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8200 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x004f0db2 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f1880 }, - { _MMIO(0x9888), 0x0a4f0011 }, - { _MMIO(0x9888), 0x0c4f0e3c }, - { _MMIO(0x9888), 0x0e4f1d80 }, - { _MMIO(0x9888), 0x086c0002 }, - { _MMIO(0x9888), 0x0a6c0100 }, - { _MMIO(0x9888), 0x0e6c000c }, - { _MMIO(0x9888), 0x026c000b }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x081b4000 }, - { _MMIO(0x9888), 0x0a1b8000 }, - { _MMIO(0x9888), 0x0e1b4000 }, - { _MMIO(0x9888), 0x021b4000 }, - { _MMIO(0x9888), 0x1a1c4000 }, - { _MMIO(0x9888), 0x1c1c0012 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x005bc000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5bc000 }, - { _MMIO(0x9888), 0x0e5b8000 }, - { _MMIO(0x9888), 0x105c8000 }, - { _MMIO(0x9888), 0x1a5ca000 }, - { _MMIO(0x9888), 0x1c5c002d }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x0a4c0800 }, - { _MMIO(0x9888), 0x0c4c0082 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002cc000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cbe00 }, - { _MMIO(0x9888), 0x182c00ef }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900167 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900840 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900842 }, - { _MMIO(0x9888), 0x47900840 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900840 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900840 }, - { _MMIO(0x9888), 0x53901111 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1810 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0000 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900167 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900842 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53901111 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x15968000 }, - { _MMIO(0x9888), 0x17968000 }, - { _MMIO(0x9888), 0x0f96c000 }, - { _MMIO(0x9888), 0x1f950011 }, - { _MMIO(0x9888), 0x1d950014 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x0b978000 }, - { _MMIO(0x9888), 0x0f974000 }, - { _MMIO(0x9888), 0x11974000 }, - { _MMIO(0x9888), 0x13978000 }, - { _MMIO(0x9888), 0x09974000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x419010a0 }, - { _MMIO(0x9888), 0x55904000 }, - { _MMIO(0x9888), 0x45901000 }, - { _MMIO(0x9888), 0x47900084 }, - { _MMIO(0x9888), 0x57904400 }, - { _MMIO(0x9888), 0x499000a5 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900081 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x439014a4 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x05e5a000 }, - { _MMIO(0x9888), 0x01e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x419010a0 }, - { _MMIO(0x9888), 0x55904000 }, - { _MMIO(0x9888), 0x45901000 }, - { _MMIO(0x9888), 0x47900084 }, - { _MMIO(0x9888), 0x57904400 }, - { _MMIO(0x9888), 0x499000a5 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900081 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x439014a4 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (dev_priv->drm.pdev->revision < 0x02) { - regs[n] = mux_config_render_pipe_profile_0_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_lt_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x02) { - regs[n] = mux_config_render_pipe_profile_0_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13946000 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x0f968000 }, - { _MMIO(0x9888), 0x1196c000 }, - { _MMIO(0x9888), 0x13964000 }, - { _MMIO(0x9888), 0x11938000 }, - { _MMIO(0x9888), 0x1b93fe00 }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x19940000 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x1d940000 }, - { _MMIO(0x9888), 0x1b954000 }, - { _MMIO(0x9888), 0x1d95a550 }, - { _MMIO(0x9888), 0x1f9502aa }, - { _MMIO(0x9888), 0x2f900157 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13946000 }, - { _MMIO(0x9888), 0x15940016 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x1b93aa55 }, - { _MMIO(0x9888), 0x1d9300aa }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x0f940018 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x01e58000 }, - { _MMIO(0x9888), 0x03e57000 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c20 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900421 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900421 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_sku_gte_0x05[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((dev_priv->drm.pdev->revision < 0x05) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x05) { - regs[n] = mux_config_memory_reads_0_sku_gte_0x05; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_gte_0x05); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13945400 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901400 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x0f968000 }, - { _MMIO(0x9888), 0x1196c000 }, - { _MMIO(0x9888), 0x13964000 }, - { _MMIO(0x9888), 0x11938000 }, - { _MMIO(0x9888), 0x1b93fe00 }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x19940000 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x1d940000 }, - { _MMIO(0x9888), 0x1b954000 }, - { _MMIO(0x9888), 0x1d95a550 }, - { _MMIO(0x9888), 0x1f9502aa }, - { _MMIO(0x9888), 0x2f900167 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13945400 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901400 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x1b93aa55 }, - { _MMIO(0x9888), 0x1d93002a }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x01e58000 }, - { _MMIO(0x9888), 0x03e57000 }, - { _MMIO(0x9888), 0x2f900167 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c20 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900421 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900421 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_sku_gte_0x05[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((dev_priv->drm.pdev->revision < 0x05) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x05) { - regs[n] = mux_config_memory_writes_0_sku_gte_0x05; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_gte_0x05); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_compute_extended_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900167 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900042 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53901111 }, - { _MMIO(0x9888), 0x43900420 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9000a0 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0e0f006c }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1190e000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c00 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x143a5800 }, - { _MMIO(0x9888), 0x163a00c0 }, - { _MMIO(0x9888), 0x12380240 }, - { _MMIO(0x9888), 0x14380002 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c1500 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f9500 }, - { _MMIO(0x9888), 0x100f002a }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x0a2dc000 }, - { _MMIO(0x9888), 0x0c2dc000 }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x06393000 }, - { _MMIO(0x9888), 0x0c3a28c1 }, - { _MMIO(0x9888), 0x003a0000 }, - { _MMIO(0x9888), 0x0a33f000 }, - { _MMIO(0x9888), 0x0c33f000 }, - { _MMIO(0x9888), 0x0a37a000 }, - { _MMIO(0x9888), 0x0c37a000 }, - { _MMIO(0x9888), 0x0a380977 }, - { _MMIO(0x9888), 0x08380000 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06383000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900800 }, - { _MMIO(0x9888), 0x47901000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900844 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2714), 0xf0800000 }, @@ -2370,6 +59,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810016 }, { _MMIO(0x9888), 0x1f810000 }, @@ -2384,1096 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "f519e481-24d2-4d42-87c9-3fdd12c00202", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "fe47b29d-ae51-423e-bff4-27d965a95b60", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "e0ad5ae0-84ba-4f29-a723-1906c12cb774", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "9bc436dd-6130-4add-affc-283eb6eaa864", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "2ea0da8f-3527-4669-9d9d-13099a7435bf", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "d97d16af-028b-4cd1-a672-6210cb5513dd", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "9fb22842-e708-43f7-9752-e0e41670c39e", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "5378e2a1-4248-4188-a4ae-da25a794c603", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "f42cdd6a-b000-42cb-870f-5eb423a7f514", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "b9bf2423-d88c-4a7b-a051-627611d00dcc", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "2414a93d-d84f-406e-99c0-472161194b40", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "b4cff514-a91e-4798-a0b3-426ca13fc9c1", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "7821d13b-9b8b-4405-9618-78cd56b62cce", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "893f1a4d-919d-4388-8cb7-746d73ea7259", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "41a24047-7484-4ead-ae37-de907e5ff2b2", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "95910492-943f-44bd-9461-390240f243fd", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "1651949f-0ac0-4cb1-a06f-dafd74a407d1", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.h b/drivers/gpu/drm/i915/i915_oa_sklgt2.h index f4397baf3328..fe1aa2c03958 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt2.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT2_H__ #define __I915_OA_SKLGT2_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt2; - -extern int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c b/drivers/gpu/drm/i915/i915_oa_sklgt3.c index 7765e22dfa17..85e51addf86a 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c @@ -31,1876 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt3.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt3 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0380 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162ca200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0200 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x51907710 }, - { _MMIO(0x9888), 0x419020a0 }, - { _MMIO(0x9888), 0x55901515 }, - { _MMIO(0x9888), 0x45900529 }, - { _MMIO(0x9888), 0x47901025 }, - { _MMIO(0x9888), 0x57907770 }, - { _MMIO(0x9888), 0x49902100 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900108 }, - { _MMIO(0x9888), 0x59900007 }, - { _MMIO(0x9888), 0x43902108 }, - { _MMIO(0x9888), 0x53907777 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900863 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900c62 }, - { _MMIO(0x9888), 0x53903333 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51901150 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x55905111 }, - { _MMIO(0x9888), 0x45901400 }, - { _MMIO(0x9888), 0x479004a5 }, - { _MMIO(0x9888), 0x57903455 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b9000a0 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x43900005 }, - { _MMIO(0x9888), 0x53900455 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900063 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53903333 }, - { _MMIO(0x9888), 0x43900840 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900005 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900402 }, - { _MMIO(0x9888), 0x53901550 }, - { _MMIO(0x9888), 0x45900080 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900050 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900115 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900884 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1930,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1944,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "4616d450-2393-4836-8146-53c5ed84d359", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "4ca0f3fe-7fd3-4924-98cb-1807d9879767", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "a0c0172c-ee13-403d-99ff-2bdf6936cf14", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "52435e0b-f188-42ea-8680-21a56ee20dee", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "27076eeb-49f3-4fed-8423-c66506005c63", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "8071b409-c39a-4674-94d7-32962ecfb512", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "25dc828e-1d2d-426e-9546-a1d4233cdf16", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "3dba9405-2d7e-4d70-8199-e734e82fd6bf", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "b375c985-9953-455b-bda2-b03f7594e9db", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "3e2be2bb-884a-49bb-82c5-2358e6bd5f2d", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "cfae9232-6ffc-42cc-a703-9790016925f0", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "2b985803-d3c9-4629-8a4f-634bfecba0e8", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "2b985803-d3c9-4629-8a4f-634bfecba0e8", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.h b/drivers/gpu/drm/i915/i915_oa_sklgt3.h index c0accb1f9b74..06746b2616c8 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt3.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT3_H__ #define __I915_OA_SKLGT3_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt3; - -extern int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c b/drivers/gpu/drm/i915/i915_oa_sklgt4.c index 9ddab43a2176..bce031ee4445 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt4.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c @@ -31,1930 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt4.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt4 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x176c01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e03b0 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4ca400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0230 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0acc2000 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x088d8000 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x0e8f1000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8800 }, - { _MMIO(0x9888), 0x1b4e0020 }, - { _MMIO(0x9888), 0x096c5300 }, - { _MMIO(0x9888), 0x116c0000 }, - { _MMIO(0x9888), 0x1d6c0000 }, - { _MMIO(0x9888), 0x091b8000 }, - { _MMIO(0x9888), 0x1b1c8000 }, - { _MMIO(0x9888), 0x0b4c2000 }, - { _MMIO(0x9888), 0x090d8000 }, - { _MMIO(0x9888), 0x0f0f1000 }, - { _MMIO(0x9888), 0x172c0800 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x5190ff30 }, - { _MMIO(0x9888), 0x41900060 }, - { _MMIO(0x9888), 0x55903033 }, - { _MMIO(0x9888), 0x45901421 }, - { _MMIO(0x9888), 0x47900803 }, - { _MMIO(0x9888), 0x5790fff1 }, - { _MMIO(0x9888), 0x49900001 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x5990000f }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x5390ffff }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53905555 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51901110 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55901111 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57901411 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900411 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53905555 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x131203e0 }, - { _MMIO(0x9888), 0x133203e0 }, - { _MMIO(0x9888), 0x135203e0 }, - { _MMIO(0x9888), 0x1a4ef000 }, - { _MMIO(0x9888), 0x1c4e0003 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0c4c02a0 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0150 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x182c00a8 }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1acef000 }, - { _MMIO(0x9888), 0x1cce0003 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0ccc02a0 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x0c8d8000 }, - { _MMIO(0x9888), 0x0e8da000 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x108f0150 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x18ac00a8 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x072f8000 }, - { _MMIO(0x9888), 0x0d4c0100 }, - { _MMIO(0x9888), 0x0d0d8000 }, - { _MMIO(0x9888), 0x0f0da000 }, - { _MMIO(0x9888), 0x110f01b0 }, - { _MMIO(0x9888), 0x192c0080 }, - { _MMIO(0x9888), 0x0f2d4000 }, - { _MMIO(0x9888), 0x0f108000 }, - { _MMIO(0x9888), 0x0f118000 }, - { _MMIO(0x9888), 0x0f121980 }, - { _MMIO(0x9888), 0x01120000 }, - { _MMIO(0x9888), 0x0f134000 }, - { _MMIO(0x9888), 0x0f304000 }, - { _MMIO(0x9888), 0x0f314000 }, - { _MMIO(0x9888), 0x0f320033 }, - { _MMIO(0x9888), 0x01320000 }, - { _MMIO(0x9888), 0x0f331000 }, - { _MMIO(0x9888), 0x0d508000 }, - { _MMIO(0x9888), 0x0d518000 }, - { _MMIO(0x9888), 0x0d521980 }, - { _MMIO(0x9888), 0x01520000 }, - { _MMIO(0x9888), 0x0d534000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51901100 }, - { _MMIO(0x9888), 0x41901000 }, - { _MMIO(0x9888), 0x43901423 }, - { _MMIO(0x9888), 0x53903331 }, - { _MMIO(0x9888), 0x45900044 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900010 }, - { _MMIO(0x9888), 0x41900060 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900821 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1984,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1998,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "bad77c24-cc64-480d-99bf-e7b740713800", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "7277228f-e7f3-4743-945a-6a2049d11377", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "463c668c-3f60-49b6-8f85-d995b635b3b2", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "055f256d-4052-467c-8dec-6064a4806433", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "753972d4-87cd-4460-824d-754463ac5054", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "d9e86d70-462b-462a-851e-fd63e8c13d63", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "1988315f-0a26-44df-acb0-df7ec86b1456", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "97875e21-6624-4aee-9191-682feb3eae21", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "882fa433-1f4a-4a67-a962-c741888fe5f5", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "882fa433-1f4a-4a67-a962-c741888fe5f5", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "882fa433-1f4a-4a67-a962-c741888fe5f5"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.h b/drivers/gpu/drm/i915/i915_oa_sklgt4.h index 1b718f15f62e..944fd525c8b1 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt4.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT4_H__ #define __I915_OA_SKLGT4_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt4; - -extern int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 88b9d3e6713a..8ab003dca113 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -63,9 +63,8 @@ struct i915_params i915 __read_mostly = { .huc_firmware_path = NULL, .enable_dp_mst = true, .inject_load_failure = 0, - .enable_dpcd_backlight = -1, + .enable_dpcd_backlight = false, .enable_gvt = false, - .enable_dbc = true, }; module_param_named(modeset, i915.modeset, int, 0400); @@ -119,6 +118,10 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type, module_param_named_unsafe(reset, i915.reset, int, 0600); MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); +module_param_named_unsafe(vbt_firmware, i915.vbt_firmware, charp, 0400); +MODULE_PARM_DESC(vbt_firmware, + "Load VBT from specified file under /lib/firmware"); + #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) module_param_named(error_capture, i915.error_capture, bool, 0600); MODULE_PARM_DESC(error_capture, @@ -247,15 +250,10 @@ MODULE_PARM_DESC(enable_dp_mst, module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400); MODULE_PARM_DESC(inject_load_failure, "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); -module_param_named_unsafe(enable_dpcd_backlight, i915.enable_dpcd_backlight, int, 0600); +module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600); MODULE_PARM_DESC(enable_dpcd_backlight, - "Enable support for DPCD backlight control " - "(-1:auto (default), 0:force disable, 1:force enabled if supported"); + "Enable support for DPCD backlight control (default:false)"); module_param_named(enable_gvt, i915.enable_gvt, bool, 0400); MODULE_PARM_DESC(enable_gvt, "Enable support for Intel GVT-g graphics virtualization host support(default:false)"); - -module_param_named_unsafe(enable_dbc, i915.enable_dbc, bool, 0600); -MODULE_PARM_DESC(enable_dbc, - "Enable support for dynamic backlight control (default:true)"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 057e203e6bda..ac844709c97e 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -28,6 +28,7 @@ #include <linux/cache.h> /* for __read_mostly */ #define I915_PARAMS_FOR_EACH(func) \ + func(char *, vbt_firmware); \ func(int, modeset); \ func(int, panel_ignore_lid); \ func(int, semaphores); \ @@ -53,7 +54,6 @@ func(int, edp_vswing); \ func(int, reset); \ func(unsigned int, inject_load_failure); \ - func(int, enable_dpcd_backlight); \ /* leave bools at the end to not create holes */ \ func(bool, alpha_support); \ func(bool, enable_cmd_parser); \ @@ -67,8 +67,8 @@ func(bool, verbose_state_checks); \ func(bool, nuclear_pageflip); \ func(bool, enable_dp_mst); \ - func(bool, enable_gvt); \ - func(bool, enable_dbc) + func(bool, enable_dpcd_backlight); \ + func(bool, enable_gvt) #define MEMBER(T, member) T member struct i915_params { diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a1e6b696bcfa..881b5d6708aa 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -63,22 +63,23 @@ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ .ring_mask = RENDER_RING, \ + .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS -static const struct intel_device_info intel_i830_info = { +static const struct intel_device_info intel_i830_info __initconst = { GEN2_FEATURES, .platform = INTEL_I830, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, /* legal, last one wins */ }; -static const struct intel_device_info intel_i845g_info = { +static const struct intel_device_info intel_i845g_info __initconst = { GEN2_FEATURES, .platform = INTEL_I845G, }; -static const struct intel_device_info intel_i85x_info = { +static const struct intel_device_info intel_i85x_info __initconst = { GEN2_FEATURES, .platform = INTEL_I85X, .is_mobile = 1, .num_pipes = 2, /* legal, last one wins */ @@ -86,7 +87,7 @@ static const struct intel_device_info intel_i85x_info = { .has_fbc = 1, }; -static const struct intel_device_info intel_i865g_info = { +static const struct intel_device_info intel_i865g_info __initconst = { GEN2_FEATURES, .platform = INTEL_I865G, }; @@ -95,10 +96,11 @@ static const struct intel_device_info intel_i865g_info = { .gen = 3, .num_pipes = 2, \ .has_gmch_display = 1, \ .ring_mask = RENDER_RING, \ + .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS -static const struct intel_device_info intel_i915g_info = { +static const struct intel_device_info intel_i915g_info __initconst = { GEN3_FEATURES, .platform = INTEL_I915G, .cursor_needs_physical = 1, .has_overlay = 1, .overlay_needs_physical = 1, @@ -106,7 +108,7 @@ static const struct intel_device_info intel_i915g_info = { .unfenced_needs_alignment = 1, }; -static const struct intel_device_info intel_i915gm_info = { +static const struct intel_device_info intel_i915gm_info __initconst = { GEN3_FEATURES, .platform = INTEL_I915GM, .is_mobile = 1, @@ -118,7 +120,7 @@ static const struct intel_device_info intel_i915gm_info = { .unfenced_needs_alignment = 1, }; -static const struct intel_device_info intel_i945g_info = { +static const struct intel_device_info intel_i945g_info __initconst = { GEN3_FEATURES, .platform = INTEL_I945G, .has_hotplug = 1, .cursor_needs_physical = 1, @@ -127,7 +129,7 @@ static const struct intel_device_info intel_i945g_info = { .unfenced_needs_alignment = 1, }; -static const struct intel_device_info intel_i945gm_info = { +static const struct intel_device_info intel_i945gm_info __initconst = { GEN3_FEATURES, .platform = INTEL_I945GM, .is_mobile = 1, .has_hotplug = 1, .cursor_needs_physical = 1, @@ -138,14 +140,14 @@ static const struct intel_device_info intel_i945gm_info = { .unfenced_needs_alignment = 1, }; -static const struct intel_device_info intel_g33_info = { +static const struct intel_device_info intel_g33_info __initconst = { GEN3_FEATURES, .platform = INTEL_G33, .has_hotplug = 1, .has_overlay = 1, }; -static const struct intel_device_info intel_pineview_info = { +static const struct intel_device_info intel_pineview_info __initconst = { GEN3_FEATURES, .platform = INTEL_PINEVIEW, .is_mobile = 1, .has_hotplug = 1, @@ -157,17 +159,18 @@ static const struct intel_device_info intel_pineview_info = { .has_hotplug = 1, \ .has_gmch_display = 1, \ .ring_mask = RENDER_RING, \ + .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS -static const struct intel_device_info intel_i965g_info = { +static const struct intel_device_info intel_i965g_info __initconst = { GEN4_FEATURES, .platform = INTEL_I965G, .has_overlay = 1, .hws_needs_physical = 1, }; -static const struct intel_device_info intel_i965gm_info = { +static const struct intel_device_info intel_i965gm_info __initconst = { GEN4_FEATURES, .platform = INTEL_I965GM, .is_mobile = 1, .has_fbc = 1, @@ -176,14 +179,14 @@ static const struct intel_device_info intel_i965gm_info = { .hws_needs_physical = 1, }; -static const struct intel_device_info intel_g45_info = { +static const struct intel_device_info intel_g45_info __initconst = { GEN4_FEATURES, .platform = INTEL_G45, .has_pipe_cxsr = 1, .ring_mask = RENDER_RING | BSD_RING, }; -static const struct intel_device_info intel_gm45_info = { +static const struct intel_device_info intel_gm45_info __initconst = { GEN4_FEATURES, .platform = INTEL_GM45, .is_mobile = 1, .has_fbc = 1, @@ -197,15 +200,16 @@ static const struct intel_device_info intel_gm45_info = { .has_hotplug = 1, \ .has_gmbus_irq = 1, \ .ring_mask = RENDER_RING | BSD_RING, \ + .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS -static const struct intel_device_info intel_ironlake_d_info = { +static const struct intel_device_info intel_ironlake_d_info __initconst = { GEN5_FEATURES, .platform = INTEL_IRONLAKE, }; -static const struct intel_device_info intel_ironlake_m_info = { +static const struct intel_device_info intel_ironlake_m_info __initconst = { GEN5_FEATURES, .platform = INTEL_IRONLAKE, .is_mobile = 1, .has_fbc = 1, @@ -224,15 +228,34 @@ static const struct intel_device_info intel_ironlake_m_info = { GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS -static const struct intel_device_info intel_sandybridge_d_info = { - GEN6_FEATURES, - .platform = INTEL_SANDYBRIDGE, +#define SNB_D_PLATFORM \ + GEN6_FEATURES, \ + .platform = INTEL_SANDYBRIDGE + +static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = { + SNB_D_PLATFORM, + .gt = 1, }; -static const struct intel_device_info intel_sandybridge_m_info = { - GEN6_FEATURES, - .platform = INTEL_SANDYBRIDGE, - .is_mobile = 1, +static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = { + SNB_D_PLATFORM, + .gt = 2, +}; + +#define SNB_M_PLATFORM \ + GEN6_FEATURES, \ + .platform = INTEL_SANDYBRIDGE, \ + .is_mobile = 1 + + +static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = { + SNB_M_PLATFORM, + .gt = 1, +}; + +static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = { + SNB_M_PLATFORM, + .gt = 2, }; #define GEN7_FEATURES \ @@ -249,27 +272,46 @@ static const struct intel_device_info intel_sandybridge_m_info = { GEN_DEFAULT_PIPEOFFSETS, \ IVB_CURSOR_OFFSETS -static const struct intel_device_info intel_ivybridge_d_info = { - GEN7_FEATURES, - .platform = INTEL_IVYBRIDGE, - .has_l3_dpf = 1, +#define IVB_D_PLATFORM \ + GEN7_FEATURES, \ + .platform = INTEL_IVYBRIDGE, \ + .has_l3_dpf = 1 + +static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = { + IVB_D_PLATFORM, + .gt = 1, }; -static const struct intel_device_info intel_ivybridge_m_info = { - GEN7_FEATURES, - .platform = INTEL_IVYBRIDGE, - .is_mobile = 1, - .has_l3_dpf = 1, +static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = { + IVB_D_PLATFORM, + .gt = 2, +}; + +#define IVB_M_PLATFORM \ + GEN7_FEATURES, \ + .platform = INTEL_IVYBRIDGE, \ + .is_mobile = 1, \ + .has_l3_dpf = 1 + +static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = { + IVB_M_PLATFORM, + .gt = 1, +}; + +static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = { + IVB_M_PLATFORM, + .gt = 2, }; -static const struct intel_device_info intel_ivybridge_q_info = { +static const struct intel_device_info intel_ivybridge_q_info __initconst = { GEN7_FEATURES, .platform = INTEL_IVYBRIDGE, + .gt = 2, .num_pipes = 0, /* legal, last one wins */ .has_l3_dpf = 1, }; -static const struct intel_device_info intel_valleyview_info = { +static const struct intel_device_info intel_valleyview_info __initconst = { .platform = INTEL_VALLEYVIEW, .gen = 7, .is_lp = 1, @@ -282,6 +324,7 @@ static const struct intel_device_info intel_valleyview_info = { .has_hotplug = 1, .has_aliasing_ppgtt = 1, .has_full_ppgtt = 1, + .has_snoop = true, .ring_mask = RENDER_RING | BSD_RING | BLT_RING, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_DEFAULT_PIPEOFFSETS, @@ -299,10 +342,24 @@ static const struct intel_device_info intel_valleyview_info = { .has_rc6p = 0 /* RC6p removed-by HSW */, \ .has_runtime_pm = 1 -static const struct intel_device_info intel_haswell_info = { - HSW_FEATURES, - .platform = INTEL_HASWELL, - .has_l3_dpf = 1, +#define HSW_PLATFORM \ + HSW_FEATURES, \ + .platform = INTEL_HASWELL, \ + .has_l3_dpf = 1 + +static const struct intel_device_info intel_haswell_gt1_info __initconst = { + HSW_PLATFORM, + .gt = 1, +}; + +static const struct intel_device_info intel_haswell_gt2_info __initconst = { + HSW_PLATFORM, + .gt = 2, +}; + +static const struct intel_device_info intel_haswell_gt3_info __initconst = { + HSW_PLATFORM, + .gt = 3, }; #define BDW_FEATURES \ @@ -318,16 +375,31 @@ static const struct intel_device_info intel_haswell_info = { .gen = 8, \ .platform = INTEL_BROADWELL -static const struct intel_device_info intel_broadwell_info = { +static const struct intel_device_info intel_broadwell_gt1_info __initconst = { BDW_PLATFORM, + .gt = 1, }; -static const struct intel_device_info intel_broadwell_gt3_info = { +static const struct intel_device_info intel_broadwell_gt2_info __initconst = { BDW_PLATFORM, + .gt = 2, +}; + +static const struct intel_device_info intel_broadwell_rsvd_info __initconst = { + BDW_PLATFORM, + .gt = 3, + /* According to the device ID those devices are GT3, they were + * previously treated as not GT3, keep it like that. + */ +}; + +static const struct intel_device_info intel_broadwell_gt3_info __initconst = { + BDW_PLATFORM, + .gt = 3, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; -static const struct intel_device_info intel_cherryview_info = { +static const struct intel_device_info intel_cherryview_info __initconst = { .gen = 8, .num_pipes = 3, .has_hotplug = 1, .is_lp = 1, @@ -344,6 +416,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_aliasing_ppgtt = 1, .has_full_ppgtt = 1, .has_reset_engine = 1, + .has_snoop = true, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_CHV_PIPEOFFSETS, CURSOR_OFFSETS, @@ -358,13 +431,29 @@ static const struct intel_device_info intel_cherryview_info = { .has_guc = 1, \ .ddb_size = 896 -static const struct intel_device_info intel_skylake_info = { +static const struct intel_device_info intel_skylake_gt1_info __initconst = { SKL_PLATFORM, + .gt = 1, }; -static const struct intel_device_info intel_skylake_gt3_info = { +static const struct intel_device_info intel_skylake_gt2_info __initconst = { SKL_PLATFORM, - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .gt = 2, +}; + +#define SKL_GT3_PLUS_PLATFORM \ + SKL_PLATFORM, \ + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING + + +static const struct intel_device_info intel_skylake_gt3_info __initconst = { + SKL_GT3_PLUS_PLATFORM, + .gt = 3, +}; + +static const struct intel_device_info intel_skylake_gt4_info __initconst = { + SKL_GT3_PLUS_PLATFORM, + .gt = 4, }; #define GEN9_LP_FEATURES \ @@ -390,17 +479,18 @@ static const struct intel_device_info intel_skylake_gt3_info = { .has_full_ppgtt = 1, \ .has_full_48bit_ppgtt = 1, \ .has_reset_engine = 1, \ + .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ IVB_CURSOR_OFFSETS, \ BDW_COLORS -static const struct intel_device_info intel_broxton_info = { +static const struct intel_device_info intel_broxton_info __initconst = { GEN9_LP_FEATURES, .platform = INTEL_BROXTON, .ddb_size = 512, }; -static const struct intel_device_info intel_geminilake_info = { +static const struct intel_device_info intel_geminilake_info __initconst = { GEN9_LP_FEATURES, .platform = INTEL_GEMINILAKE, .ddb_size = 1024, @@ -415,12 +505,19 @@ static const struct intel_device_info intel_geminilake_info = { .has_guc = 1, \ .ddb_size = 896 -static const struct intel_device_info intel_kabylake_info = { +static const struct intel_device_info intel_kabylake_gt1_info __initconst = { KBL_PLATFORM, + .gt = 1, }; -static const struct intel_device_info intel_kabylake_gt3_info = { +static const struct intel_device_info intel_kabylake_gt2_info __initconst = { KBL_PLATFORM, + .gt = 2, +}; + +static const struct intel_device_info intel_kabylake_gt3_info __initconst = { + KBL_PLATFORM, + .gt = 3, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; @@ -433,20 +530,28 @@ static const struct intel_device_info intel_kabylake_gt3_info = { .has_guc = 1, \ .ddb_size = 896 -static const struct intel_device_info intel_coffeelake_info = { +static const struct intel_device_info intel_coffeelake_gt1_info __initconst = { + CFL_PLATFORM, + .gt = 1, +}; + +static const struct intel_device_info intel_coffeelake_gt2_info __initconst = { CFL_PLATFORM, + .gt = 2, }; -static const struct intel_device_info intel_coffeelake_gt3_info = { +static const struct intel_device_info intel_coffeelake_gt3_info __initconst = { CFL_PLATFORM, + .gt = 3, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; -static const struct intel_device_info intel_cannonlake_info = { +static const struct intel_device_info intel_cannonlake_gt2_info __initconst = { BDW_FEATURES, .is_alpha_support = 1, .platform = INTEL_CANNONLAKE, .gen = 10, + .gt = 2, .ddb_size = 1024, .has_csr = 1, .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } @@ -475,31 +580,40 @@ static const struct pci_device_id pciidlist[] = { INTEL_PINEVIEW_IDS(&intel_pineview_info), INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), - INTEL_SNB_D_IDS(&intel_sandybridge_d_info), - INTEL_SNB_M_IDS(&intel_sandybridge_m_info), + INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), + INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), + INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), + INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ - INTEL_IVB_M_IDS(&intel_ivybridge_m_info), - INTEL_IVB_D_IDS(&intel_ivybridge_d_info), - INTEL_HSW_IDS(&intel_haswell_info), + INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), + INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), + INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), + INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), + INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), + INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), + INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), INTEL_VLV_IDS(&intel_valleyview_info), - INTEL_BDW_GT12_IDS(&intel_broadwell_info), + INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), + INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), - INTEL_BDW_RSVD_IDS(&intel_broadwell_info), + INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), INTEL_CHV_IDS(&intel_cherryview_info), - INTEL_SKL_GT1_IDS(&intel_skylake_info), - INTEL_SKL_GT2_IDS(&intel_skylake_info), + INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), + INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), - INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), + INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), INTEL_BXT_IDS(&intel_broxton_info), INTEL_GLK_IDS(&intel_geminilake_info), - INTEL_KBL_GT1_IDS(&intel_kabylake_info), - INTEL_KBL_GT2_IDS(&intel_kabylake_info), + INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), + INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), - INTEL_CFL_S_IDS(&intel_coffeelake_info), - INTEL_CFL_H_IDS(&intel_coffeelake_info), - INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info), - INTEL_CNL_IDS(&intel_cannonlake_info), + INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), + INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), + INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), + INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), + INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info), + INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info), {0, 0, 0} }; MODULE_DEVICE_TABLE(pci, pciidlist); diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index ed396f7b7dca..94185d610673 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -193,6 +193,7 @@ #include <linux/anon_inodes.h> #include <linux/sizes.h> +#include <linux/uuid.h> #include "i915_drv.h" #include "i915_oa_hsw.h" @@ -357,6 +358,54 @@ struct perf_open_properties { int oa_period_exponent; }; +static void free_oa_config(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + if (!PTR_ERR(oa_config->flex_regs)) + kfree(oa_config->flex_regs); + if (!PTR_ERR(oa_config->b_counter_regs)) + kfree(oa_config->b_counter_regs); + if (!PTR_ERR(oa_config->mux_regs)) + kfree(oa_config->mux_regs); + kfree(oa_config); +} + +static void put_oa_config(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + if (!atomic_dec_and_test(&oa_config->ref_count)) + return; + + free_oa_config(dev_priv, oa_config); +} + +static int get_oa_config(struct drm_i915_private *dev_priv, + int metrics_set, + struct i915_oa_config **out_config) +{ + int ret; + + if (metrics_set == 1) { + *out_config = &dev_priv->perf.oa.test_config; + atomic_inc(&dev_priv->perf.oa.test_config.ref_count); + return 0; + } + + ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (ret) + return ret; + + *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set); + if (!*out_config) + ret = -EINVAL; + else + atomic_inc(&(*out_config)->ref_count); + + mutex_unlock(&dev_priv->perf.metrics_lock); + + return ret; +} + static u32 gen8_oa_hw_tail_read(struct drm_i915_private *dev_priv) { return I915_READ(GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK; @@ -1246,10 +1295,12 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) BUG_ON(stream != dev_priv->perf.oa.exclusive_stream); /* - * Unset exclusive_stream first, it might be checked while - * disabling the metric set on gen8+. + * Unset exclusive_stream first, it will be checked while disabling + * the metric set on gen8+. */ + mutex_lock(&dev_priv->drm.struct_mutex); dev_priv->perf.oa.exclusive_stream = NULL; + mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv->perf.oa.ops.disable_metric_set(dev_priv); @@ -1261,6 +1312,8 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) if (stream->ctx) oa_put_render_ctx_id(stream); + put_oa_config(dev_priv, stream->oa_config); + if (dev_priv->perf.oa.spurious_report_rs.missed) { DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n", dev_priv->perf.oa.spurious_report_rs.missed); @@ -1440,9 +1493,9 @@ unlock: static void config_oa_regs(struct drm_i915_private *dev_priv, const struct i915_oa_reg *regs, - int n_regs) + u32 n_regs) { - int i; + u32 i; for (i = 0; i < n_regs; i++) { const struct i915_oa_reg *reg = regs + i; @@ -1451,17 +1504,9 @@ static void config_oa_regs(struct drm_i915_private *dev_priv, } } -static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) +static int hsw_enable_metric_set(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { - int ret = i915_oa_select_metric_set_hsw(dev_priv); - int i; - - if (ret) - return ret; - - I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) | - GT_NOA_ENABLE)); - /* PRM: * * OA unit is using “crclk” for its functionality. When trunk @@ -1476,10 +1521,7 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | GEN6_CSUNIT_CLOCK_GATE_DISABLE)); - for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) { - config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i], - dev_priv->perf.oa.mux_regs_lens[i]); - } + config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); /* It apparently takes a fairly long time for a new MUX * configuration to be be applied after these register writes. @@ -1504,8 +1546,8 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) */ usleep_range(15000, 20000); - config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, - dev_priv->perf.oa.b_counter_regs_len); + config_oa_regs(dev_priv, oa_config->b_counter_regs, + oa_config->b_counter_regs_len); return 0; } @@ -1529,11 +1571,10 @@ static void hsw_disable_metric_set(struct drm_i915_private *dev_priv) * in the case that the OA unit has been disabled. */ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, - u32 *reg_state) + u32 *reg_state, + const struct i915_oa_config *oa_config) { struct drm_i915_private *dev_priv = ctx->i915; - const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; - int n_flex_regs = dev_priv->perf.oa.flex_regs_len; u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset; u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset; /* The MMIO offsets for Flex EU registers aren't contiguous */ @@ -1565,12 +1606,15 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, * will be an explicit 'No Event' we can select, but not yet... */ u32 value = 0; - int j; - for (j = 0; j < n_flex_regs; j++) { - if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) { - value = flex_regs[j].value; - break; + if (oa_config) { + u32 j; + + for (j = 0; j < oa_config->flex_regs_len; j++) { + if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) { + value = oa_config->flex_regs[j].value; + break; + } } } @@ -1583,11 +1627,10 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, * Same as gen8_update_reg_state_unlocked only through the batchbuffer. This * is only used by the kernel context. */ -static int gen8_emit_oa_config(struct drm_i915_gem_request *req) +static int gen8_emit_oa_config(struct drm_i915_gem_request *req, + const struct i915_oa_config *oa_config) { struct drm_i915_private *dev_priv = req->i915; - const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; - int n_flex_regs = dev_priv->perf.oa.flex_regs_len; /* The MMIO offsets for Flex EU registers aren't contiguous */ u32 flex_mmio[] = { i915_mmio_reg_offset(EU_PERF_CNTL0), @@ -1622,12 +1665,15 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) * yet... */ u32 value = 0; - int j; - for (j = 0; j < n_flex_regs; j++) { - if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) { - value = flex_regs[j].value; - break; + if (oa_config) { + u32 j; + + for (j = 0; j < oa_config->flex_regs_len; j++) { + if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) { + value = oa_config->flex_regs[j].value; + break; + } } } @@ -1641,7 +1687,8 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) return 0; } -static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv) +static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { struct intel_engine_cs *engine = dev_priv->engine[RCS]; struct i915_gem_timeline *timeline; @@ -1656,7 +1703,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr if (IS_ERR(req)) return PTR_ERR(req); - ret = gen8_emit_oa_config(req); + ret = gen8_emit_oa_config(req, oa_config); if (ret) { i915_add_request(req); return ret; @@ -1707,6 +1754,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr * Note: it's only the RCS/Render context that has any OA state. */ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config, bool interruptible) { struct i915_gem_context *ctx; @@ -1724,7 +1772,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, } /* Switch away from any user context. */ - ret = gen8_switch_to_updated_kernel_context(dev_priv); + ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config); if (ret) goto out; @@ -1763,7 +1811,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, ce->state->obj->mm.dirty = true; regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs); - gen8_update_reg_state_unlocked(ctx, regs); + gen8_update_reg_state_unlocked(ctx, regs, oa_config); i915_gem_object_unpin_map(ce->state->obj); } @@ -1774,13 +1822,10 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, return ret; } -static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) +static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { - int ret = dev_priv->perf.oa.ops.select_metric_set(dev_priv); - int i; - - if (ret) - return ret; + int ret; /* * We disable slice/unslice clock ratio change reports on SKL since @@ -1817,19 +1862,14 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) * to make sure all slices/subslices are ON before writing to NOA * registers. */ - ret = gen8_configure_all_contexts(dev_priv, true); + ret = gen8_configure_all_contexts(dev_priv, oa_config, true); if (ret) return ret; - I915_WRITE(GDT_CHICKEN_BITS, 0xA0); - for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) { - config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i], - dev_priv->perf.oa.mux_regs_lens[i]); - } - I915_WRITE(GDT_CHICKEN_BITS, 0x80); + config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); - config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, - dev_priv->perf.oa.b_counter_regs_len); + config_oa_regs(dev_priv, oa_config->b_counter_regs, + oa_config->b_counter_regs_len); return 0; } @@ -1837,7 +1877,11 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) static void gen8_disable_metric_set(struct drm_i915_private *dev_priv) { /* Reset all contexts' slices/subslices configurations. */ - gen8_configure_all_contexts(dev_priv, false); + gen8_configure_all_contexts(dev_priv, NULL, false); + + I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) & + ~GT_NOA_ENABLE)); + } static void gen7_oa_enable(struct drm_i915_private *dev_priv) @@ -2011,11 +2055,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, return -EBUSY; } - if (!props->metrics_set) { - DRM_DEBUG("OA metric set not specified\n"); - return -EINVAL; - } - if (!props->oa_format) { DRM_DEBUG("OA report format not specified\n"); return -EINVAL; @@ -2055,8 +2094,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, dev_priv->perf.oa.oa_buffer.format = dev_priv->perf.oa.oa_formats[props->oa_format].format; - dev_priv->perf.oa.metrics_set = props->metrics_set; - dev_priv->perf.oa.periodic = props->oa_periodic; if (dev_priv->perf.oa.periodic) dev_priv->perf.oa.period_exponent = props->oa_period_exponent; @@ -2067,6 +2104,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, return ret; } + ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config); + if (ret) + goto err_config; + /* PRM - observability performance counters: * * OACONTROL, performance counter enable, note: @@ -2086,22 +2127,39 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, if (ret) goto err_oa_buf_alloc; - ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv); + ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv, + stream->oa_config); if (ret) goto err_enable; stream->ops = &i915_oa_stream_ops; + /* Lock device for exclusive_stream access late because + * enable_metric_set() might lock as well on gen8+. + */ + ret = i915_mutex_lock_interruptible(&dev_priv->drm); + if (ret) + goto err_lock; + dev_priv->perf.oa.exclusive_stream = stream; + mutex_unlock(&dev_priv->drm.struct_mutex); + return 0; +err_lock: + dev_priv->perf.oa.ops.disable_metric_set(dev_priv); + err_enable: free_oa_buffer(dev_priv); err_oa_buf_alloc: + put_oa_config(dev_priv, stream->oa_config); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); intel_runtime_pm_put(dev_priv); + +err_config: if (stream->ctx) oa_put_render_ctx_id(stream); @@ -2112,15 +2170,14 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct i915_gem_context *ctx, u32 *reg_state) { - struct drm_i915_private *dev_priv = engine->i915; + struct i915_perf_stream *stream; if (engine->id != RCS) return; - if (!dev_priv->perf.initialized) - return; - - gen8_update_reg_state_unlocked(ctx, reg_state); + stream = engine->i915->perf.oa.exclusive_stream; + if (stream) + gen8_update_reg_state_unlocked(ctx, reg_state, stream->oa_config); } /** @@ -2483,27 +2540,6 @@ static const struct file_operations fops = { }; -static struct i915_gem_context * -lookup_context(struct drm_i915_private *dev_priv, - struct drm_i915_file_private *file_priv, - u32 ctx_user_handle) -{ - struct i915_gem_context *ctx; - int ret; - - ret = i915_mutex_lock_interruptible(&dev_priv->drm); - if (ret) - return ERR_PTR(ret); - - ctx = i915_gem_context_lookup(file_priv, ctx_user_handle); - if (!IS_ERR(ctx)) - i915_gem_context_get(ctx); - - mutex_unlock(&dev_priv->drm.struct_mutex); - - return ctx; -} - /** * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD * @dev_priv: i915 device instance @@ -2545,12 +2581,11 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, u32 ctx_handle = props->ctx_handle; struct drm_i915_file_private *file_priv = file->driver_priv; - specific_ctx = lookup_context(dev_priv, file_priv, ctx_handle); - if (IS_ERR(specific_ctx)) { - ret = PTR_ERR(specific_ctx); - if (ret != -EINTR) - DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n", - ctx_handle); + specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle); + if (!specific_ctx) { + DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n", + ctx_handle); + ret = -ENOENT; goto err; } } @@ -2665,7 +2700,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, struct perf_open_properties *props) { u64 __user *uprop = uprops; - int i; + u32 i; memset(props, 0, sizeof(struct perf_open_properties)); @@ -2712,8 +2747,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, props->sample_flags |= SAMPLE_OA_REPORT; break; case DRM_I915_PERF_PROP_OA_METRICS_SET: - if (value == 0 || - value > dev_priv->perf.oa.n_builtin_sets) { + if (value == 0) { DRM_DEBUG("Unknown OA metric set ID\n"); return -EINVAL; } @@ -2852,6 +2886,8 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data, */ void i915_perf_register(struct drm_i915_private *dev_priv) { + int ret; + if (!dev_priv->perf.initialized) return; @@ -2867,44 +2903,42 @@ void i915_perf_register(struct drm_i915_private *dev_priv) if (!dev_priv->perf.metrics_kobj) goto exit; + sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr); + if (IS_HASWELL(dev_priv)) { - if (i915_perf_register_sysfs_hsw(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_hsw(dev_priv); } else if (IS_BROADWELL(dev_priv)) { - if (i915_perf_register_sysfs_bdw(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_bdw(dev_priv); } else if (IS_CHERRYVIEW(dev_priv)) { - if (i915_perf_register_sysfs_chv(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_chv(dev_priv); } else if (IS_SKYLAKE(dev_priv)) { - if (IS_SKL_GT2(dev_priv)) { - if (i915_perf_register_sysfs_sklgt2(dev_priv)) - goto sysfs_error; - } else if (IS_SKL_GT3(dev_priv)) { - if (i915_perf_register_sysfs_sklgt3(dev_priv)) - goto sysfs_error; - } else if (IS_SKL_GT4(dev_priv)) { - if (i915_perf_register_sysfs_sklgt4(dev_priv)) - goto sysfs_error; - } else - goto sysfs_error; + if (IS_SKL_GT2(dev_priv)) + i915_perf_load_test_config_sklgt2(dev_priv); + else if (IS_SKL_GT3(dev_priv)) + i915_perf_load_test_config_sklgt3(dev_priv); + else if (IS_SKL_GT4(dev_priv)) + i915_perf_load_test_config_sklgt4(dev_priv); } else if (IS_BROXTON(dev_priv)) { - if (i915_perf_register_sysfs_bxt(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_bxt(dev_priv); } else if (IS_KABYLAKE(dev_priv)) { - if (IS_KBL_GT2(dev_priv)) { - if (i915_perf_register_sysfs_kblgt2(dev_priv)) - goto sysfs_error; - } else if (IS_KBL_GT3(dev_priv)) { - if (i915_perf_register_sysfs_kblgt3(dev_priv)) - goto sysfs_error; - } else - goto sysfs_error; + if (IS_KBL_GT2(dev_priv)) + i915_perf_load_test_config_kblgt2(dev_priv); + else if (IS_KBL_GT3(dev_priv)) + i915_perf_load_test_config_kblgt3(dev_priv); } else if (IS_GEMINILAKE(dev_priv)) { - if (i915_perf_register_sysfs_glk(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_glk(dev_priv); } + if (dev_priv->perf.oa.test_config.id == 0) + goto sysfs_error; + + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, + &dev_priv->perf.oa.test_config.sysfs_metric); + if (ret) + goto sysfs_error; + + atomic_set(&dev_priv->perf.oa.test_config.ref_count, 1); + goto exit; sysfs_error: @@ -2929,34 +2963,375 @@ void i915_perf_unregister(struct drm_i915_private *dev_priv) if (!dev_priv->perf.metrics_kobj) return; - if (IS_HASWELL(dev_priv)) - i915_perf_unregister_sysfs_hsw(dev_priv); - else if (IS_BROADWELL(dev_priv)) - i915_perf_unregister_sysfs_bdw(dev_priv); - else if (IS_CHERRYVIEW(dev_priv)) - i915_perf_unregister_sysfs_chv(dev_priv); - else if (IS_SKYLAKE(dev_priv)) { - if (IS_SKL_GT2(dev_priv)) - i915_perf_unregister_sysfs_sklgt2(dev_priv); - else if (IS_SKL_GT3(dev_priv)) - i915_perf_unregister_sysfs_sklgt3(dev_priv); - else if (IS_SKL_GT4(dev_priv)) - i915_perf_unregister_sysfs_sklgt4(dev_priv); - } else if (IS_BROXTON(dev_priv)) - i915_perf_unregister_sysfs_bxt(dev_priv); - else if (IS_KABYLAKE(dev_priv)) { - if (IS_KBL_GT2(dev_priv)) - i915_perf_unregister_sysfs_kblgt2(dev_priv); - else if (IS_KBL_GT3(dev_priv)) - i915_perf_unregister_sysfs_kblgt3(dev_priv); - } else if (IS_GEMINILAKE(dev_priv)) - i915_perf_unregister_sysfs_glk(dev_priv); - + sysfs_remove_group(dev_priv->perf.metrics_kobj, + &dev_priv->perf.oa.test_config.sysfs_metric); kobject_put(dev_priv->perf.metrics_kobj); dev_priv->perf.metrics_kobj = NULL; } +static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + static const i915_reg_t flex_eu_regs[] = { + EU_PERF_CNTL0, + EU_PERF_CNTL1, + EU_PERF_CNTL2, + EU_PERF_CNTL3, + EU_PERF_CNTL4, + EU_PERF_CNTL5, + EU_PERF_CNTL6, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) { + if (flex_eu_regs[i].reg == addr) + return true; + } + return false; +} + +static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return (addr >= OASTARTTRIG1.reg && addr <= OASTARTTRIG8.reg) || + (addr >= OAREPORTTRIG1.reg && addr <= OAREPORTTRIG8.reg) || + (addr >= OACEC0_0.reg && addr <= OACEC7_1.reg); +} + +static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return addr == HALF_SLICE_CHICKEN2.reg || + (addr >= MICRO_BP0_0.reg && addr <= NOA_WRITE.reg) || + (addr >= OA_PERFCNT1_LO.reg && addr <= OA_PERFCNT2_HI.reg) || + (addr >= OA_PERFMATRIX_LO.reg && addr <= OA_PERFMATRIX_HI.reg); +} + +static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + addr == WAIT_FOR_RC6_EXIT.reg || + (addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg); +} + +static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + (addr >= 0x25100 && addr <= 0x2FF90) || + addr == 0x9ec0; +} + +static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + (addr >= 0x182300 && addr <= 0x1823A4); +} + +static uint32_t mask_reg_value(u32 reg, u32 val) +{ + /* HALF_SLICE_CHICKEN2 is programmed with a the + * WaDisableSTUnitPowerOptimization workaround. Make sure the value + * programmed by userspace doesn't change this. + */ + if (HALF_SLICE_CHICKEN2.reg == reg) + val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); + + /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function + * indicated by its name and a bunch of selection fields used by OA + * configs. + */ + if (WAIT_FOR_RC6_EXIT.reg == reg) + val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); + + return val; +} + +static struct i915_oa_reg *alloc_oa_regs(struct drm_i915_private *dev_priv, + bool (*is_valid)(struct drm_i915_private *dev_priv, u32 addr), + u32 __user *regs, + u32 n_regs) +{ + struct i915_oa_reg *oa_regs; + int err; + u32 i; + + if (!n_regs) + return NULL; + + if (!access_ok(VERIFY_READ, regs, n_regs * sizeof(u32) * 2)) + return ERR_PTR(-EFAULT); + + /* No is_valid function means we're not allowing any register to be programmed. */ + GEM_BUG_ON(!is_valid); + if (!is_valid) + return ERR_PTR(-EINVAL); + + oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL); + if (!oa_regs) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < n_regs; i++) { + u32 addr, value; + + err = get_user(addr, regs); + if (err) + goto addr_err; + + if (!is_valid(dev_priv, addr)) { + DRM_DEBUG("Invalid oa_reg address: %X\n", addr); + err = -EINVAL; + goto addr_err; + } + + err = get_user(value, regs + 1); + if (err) + goto addr_err; + + oa_regs[i].addr = _MMIO(addr); + oa_regs[i].value = mask_reg_value(addr, value); + + regs += 2; + } + + return oa_regs; + +addr_err: + kfree(oa_regs); + return ERR_PTR(err); +} + +static ssize_t show_dynamic_id(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i915_oa_config *oa_config = + container_of(attr, typeof(*oa_config), sysfs_metric_id); + + return sprintf(buf, "%d\n", oa_config->id); +} + +static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + sysfs_attr_init(&oa_config->sysfs_metric_id.attr); + oa_config->sysfs_metric_id.attr.name = "id"; + oa_config->sysfs_metric_id.attr.mode = S_IRUGO; + oa_config->sysfs_metric_id.show = show_dynamic_id; + oa_config->sysfs_metric_id.store = NULL; + + oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr; + oa_config->attrs[1] = NULL; + + oa_config->sysfs_metric.name = oa_config->uuid; + oa_config->sysfs_metric.attrs = oa_config->attrs; + + return sysfs_create_group(dev_priv->perf.metrics_kobj, + &oa_config->sysfs_metric); +} + +/** + * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config + * @dev: drm device + * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from + * userspace (unvalidated) + * @file: drm file + * + * Validates the submitted OA register to be saved into a new OA config that + * can then be used for programming the OA unit and its NOA network. + * + * Returns: A new allocated config number to be used with the perf open ioctl + * or a negative error code on failure. + */ +int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_perf_oa_config *args = data; + struct i915_oa_config *oa_config, *tmp; + int err, id; + + if (!dev_priv->perf.initialized) { + DRM_DEBUG("i915 perf interface not available for this system\n"); + return -ENOTSUPP; + } + + if (!dev_priv->perf.metrics_kobj) { + DRM_DEBUG("OA metrics weren't advertised via sysfs\n"); + return -EINVAL; + } + + if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { + DRM_DEBUG("Insufficient privileges to add i915 OA config\n"); + return -EACCES; + } + + if ((!args->mux_regs_ptr || !args->n_mux_regs) && + (!args->boolean_regs_ptr || !args->n_boolean_regs) && + (!args->flex_regs_ptr || !args->n_flex_regs)) { + DRM_DEBUG("No OA registers given\n"); + return -EINVAL; + } + + oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL); + if (!oa_config) { + DRM_DEBUG("Failed to allocate memory for the OA config\n"); + return -ENOMEM; + } + + atomic_set(&oa_config->ref_count, 1); + + if (!uuid_is_valid(args->uuid)) { + DRM_DEBUG("Invalid uuid format for OA config\n"); + err = -EINVAL; + goto reg_err; + } + + /* Last character in oa_config->uuid will be 0 because oa_config is + * kzalloc. + */ + memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid)); + + oa_config->mux_regs_len = args->n_mux_regs; + oa_config->mux_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_mux_reg, + u64_to_user_ptr(args->mux_regs_ptr), + args->n_mux_regs); + + if (IS_ERR(oa_config->mux_regs)) { + DRM_DEBUG("Failed to create OA config for mux_regs\n"); + err = PTR_ERR(oa_config->mux_regs); + goto reg_err; + } + + oa_config->b_counter_regs_len = args->n_boolean_regs; + oa_config->b_counter_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_b_counter_reg, + u64_to_user_ptr(args->boolean_regs_ptr), + args->n_boolean_regs); + + if (IS_ERR(oa_config->b_counter_regs)) { + DRM_DEBUG("Failed to create OA config for b_counter_regs\n"); + err = PTR_ERR(oa_config->b_counter_regs); + goto reg_err; + } + + if (INTEL_GEN(dev_priv) < 8) { + if (args->n_flex_regs != 0) { + err = -EINVAL; + goto reg_err; + } + } else { + oa_config->flex_regs_len = args->n_flex_regs; + oa_config->flex_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_flex_reg, + u64_to_user_ptr(args->flex_regs_ptr), + args->n_flex_regs); + + if (IS_ERR(oa_config->flex_regs)) { + DRM_DEBUG("Failed to create OA config for flex_regs\n"); + err = PTR_ERR(oa_config->flex_regs); + goto reg_err; + } + } + + err = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (err) + goto reg_err; + + /* We shouldn't have too many configs, so this iteration shouldn't be + * too costly. + */ + idr_for_each_entry(&dev_priv->perf.metrics_idr, tmp, id) { + if (!strcmp(tmp->uuid, oa_config->uuid)) { + DRM_DEBUG("OA config already exists with this uuid\n"); + err = -EADDRINUSE; + goto sysfs_err; + } + } + + err = create_dynamic_oa_sysfs_entry(dev_priv, oa_config); + if (err) { + DRM_DEBUG("Failed to create sysfs entry for OA config\n"); + goto sysfs_err; + } + + /* Config id 0 is invalid, id 1 for kernel stored test config. */ + oa_config->id = idr_alloc(&dev_priv->perf.metrics_idr, + oa_config, 2, + 0, GFP_KERNEL); + if (oa_config->id < 0) { + DRM_DEBUG("Failed to create sysfs entry for OA config\n"); + err = oa_config->id; + goto sysfs_err; + } + + mutex_unlock(&dev_priv->perf.metrics_lock); + + return oa_config->id; + +sysfs_err: + mutex_unlock(&dev_priv->perf.metrics_lock); +reg_err: + put_oa_config(dev_priv, oa_config); + DRM_DEBUG("Failed to add new OA config\n"); + return err; +} + +/** + * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config + * @dev: drm device + * @data: ioctl data (pointer to u64 integer) copied from userspace + * @file: drm file + * + * Configs can be removed while being used, the will stop appearing in sysfs + * and their content will be freed when the stream using the config is closed. + * + * Returns: 0 on success or a negative error code on failure. + */ +int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u64 *arg = data; + struct i915_oa_config *oa_config; + int ret; + + if (!dev_priv->perf.initialized) { + DRM_DEBUG("i915 perf interface not available for this system\n"); + return -ENOTSUPP; + } + + if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { + DRM_DEBUG("Insufficient privileges to remove i915 OA config\n"); + return -EACCES; + } + + ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (ret) + goto lock_err; + + oa_config = idr_find(&dev_priv->perf.metrics_idr, *arg); + if (!oa_config) { + DRM_DEBUG("Failed to remove unknown OA config\n"); + ret = -ENOENT; + goto config_err; + } + + GEM_BUG_ON(*arg != oa_config->id); + + sysfs_remove_group(dev_priv->perf.metrics_kobj, + &oa_config->sysfs_metric); + + idr_remove(&dev_priv->perf.metrics_idr, *arg); + put_oa_config(dev_priv, oa_config); + +config_err: + mutex_unlock(&dev_priv->perf.metrics_lock); +lock_err: + return ret; +} + static struct ctl_table oa_table[] = { { .procname = "perf_stream_paranoid", @@ -3010,9 +3385,14 @@ static struct ctl_table dev_root[] = { */ void i915_perf_init(struct drm_i915_private *dev_priv) { - dev_priv->perf.oa.n_builtin_sets = 0; + dev_priv->perf.oa.timestamp_frequency = 0; if (IS_HASWELL(dev_priv)) { + dev_priv->perf.oa.ops.is_valid_b_counter_reg = + gen7_is_valid_b_counter_addr; + dev_priv->perf.oa.ops.is_valid_mux_reg = + hsw_is_valid_mux_addr; + dev_priv->perf.oa.ops.is_valid_flex_reg = NULL; dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer; dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set; dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set; @@ -3025,9 +3405,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 12500000; dev_priv->perf.oa.oa_formats = hsw_oa_formats; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_hsw; } else if (i915.enable_execlists) { /* Note: that although we could theoretically also support the * legacy ringbuffer mode on BDW (and earlier iterations of @@ -3035,6 +3412,22 @@ void i915_perf_init(struct drm_i915_private *dev_priv) * worth the complexity to maintain now that BDW+ enable * execlist mode by default. */ + dev_priv->perf.oa.ops.is_valid_b_counter_reg = + gen7_is_valid_b_counter_addr; + dev_priv->perf.oa.ops.is_valid_mux_reg = + gen8_is_valid_mux_addr; + dev_priv->perf.oa.ops.is_valid_flex_reg = + gen8_is_valid_flex_addr; + + dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; + dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set; + dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable; + dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable; + dev_priv->perf.oa.ops.read = gen8_oa_read; + dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; + + dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats; if (IS_GEN8(dev_priv)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; @@ -3043,85 +3436,35 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 12500000; dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25); - - if (IS_BROADWELL(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_bdw; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_bdw; - } else if (IS_CHERRYVIEW(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_chv; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_chv; + if (IS_CHERRYVIEW(dev_priv)) { + dev_priv->perf.oa.ops.is_valid_mux_reg = + chv_is_valid_mux_addr; } } else if (IS_GEN9(dev_priv)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; - dev_priv->perf.oa.timestamp_frequency = 12000000; - dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); - if (IS_SKL_GT2(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt2; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt2; - } else if (IS_SKL_GT3(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt3; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt3; - } else if (IS_SKL_GT4(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt4; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt4; - } else if (IS_BROXTON(dev_priv)) { + switch (dev_priv->info.platform) { + case INTEL_BROXTON: + case INTEL_GEMINILAKE: dev_priv->perf.oa.timestamp_frequency = 19200000; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_bxt; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_bxt; - } else if (IS_KBL_GT2(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_kblgt2; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_kblgt2; - } else if (IS_KBL_GT3(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_kblgt3; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_kblgt3; - } else if (IS_GEMINILAKE(dev_priv)) { - dev_priv->perf.oa.timestamp_frequency = 19200000; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_glk; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_glk; + break; + case INTEL_SKYLAKE: + case INTEL_KABYLAKE: + dev_priv->perf.oa.timestamp_frequency = 12000000; + break; + default: + /* Leave timestamp_frequency to 0 so we can + * detect unsupported platforms. + */ + break; } } - - if (dev_priv->perf.oa.n_builtin_sets) { - dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; - dev_priv->perf.oa.ops.enable_metric_set = - gen8_enable_metric_set; - dev_priv->perf.oa.ops.disable_metric_set = - gen8_disable_metric_set; - dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable; - dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable; - dev_priv->perf.oa.ops.read = gen8_oa_read; - dev_priv->perf.oa.ops.oa_hw_tail_read = - gen8_oa_hw_tail_read; - - dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats; - } } - if (dev_priv->perf.oa.n_builtin_sets) { + if (dev_priv->perf.oa.timestamp_frequency) { hrtimer_init(&dev_priv->perf.oa.poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb; @@ -3135,10 +3478,23 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency / 2; dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); + mutex_init(&dev_priv->perf.metrics_lock); + idr_init(&dev_priv->perf.metrics_idr); + dev_priv->perf.initialized = true; } } +static int destroy_config(int id, void *p, void *data) +{ + struct drm_i915_private *dev_priv = data; + struct i915_oa_config *oa_config = p; + + put_oa_config(dev_priv, oa_config); + + return 0; +} + /** * i915_perf_fini - Counter part to i915_perf_init() * @dev_priv: i915 device instance @@ -3148,6 +3504,9 @@ void i915_perf_fini(struct drm_i915_private *dev_priv) if (!dev_priv->perf.initialized) return; + idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, dev_priv); + idr_destroy(&dev_priv->perf.metrics_idr); + unregister_sysctl_table(dev_priv->perf.sysctl_header); memset(&dev_priv->perf.oa.ops, 0, sizeof(dev_priv->perf.oa.ops)); diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h index 2cfe96d3e5d1..0679a58cdbae 100644 --- a/drivers/gpu/drm/i915/i915_pvinfo.h +++ b/drivers/gpu/drm/i915/i915_pvinfo.h @@ -49,12 +49,18 @@ enum vgt_g2v_type { VGT_G2V_MAX, }; +/* + * VGT capabilities type + */ +#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2) + struct vgt_if { u64 magic; /* VGT_MAGIC */ u16 version_major; u16 version_minor; u32 vgt_id; /* ID of vGT instance */ - u32 rsv1[12]; /* pad to offset 0x40 */ + u32 vgt_caps; /* VGT capabilities */ + u32 rsv1[11]; /* pad to offset 0x40 */ /* * Data structure to describe the balooning info of resources. * Each VM can only have one portion of continuous area for now. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c712d01f92ab..2eff98cdcfad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -25,6 +25,97 @@ #ifndef _I915_REG_H_ #define _I915_REG_H_ +/** + * DOC: The i915 register macro definition style guide + * + * Follow the style described here for new macros, and while changing existing + * macros. Do **not** mass change existing definitions just to update the style. + * + * Layout + * '''''' + * + * Keep helper macros near the top. For example, _PIPE() and friends. + * + * Prefix macros that generally should not be used outside of this file with + * underscore '_'. For example, _PIPE() and friends, single instances of + * registers that are defined solely for the use by function-like macros. + * + * Avoid using the underscore prefixed macros outside of this file. There are + * exceptions, but keep them to a minimum. + * + * There are two basic types of register definitions: Single registers and + * register groups. Register groups are registers which have two or more + * instances, for example one per pipe, port, transcoder, etc. Register groups + * should be defined using function-like macros. + * + * For single registers, define the register offset first, followed by register + * contents. + * + * For register groups, define the register instance offsets first, prefixed + * with underscore, followed by a function-like macro choosing the right + * instance based on the parameter, followed by register contents. + * + * Define the register contents (i.e. bit and bit field macros) from most + * significant to least significant bit. Indent the register content macros + * using two extra spaces between ``#define`` and the macro name. + * + * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field + * contents so that they are already shifted in place, and can be directly + * OR'd. For convenience, function-like macros may be used to define bit fields, + * but do note that the macros may be needed to read as well as write the + * register contents. + * + * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in + * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix + * to the name. + * + * Group the register and its contents together without blank lines, separate + * from other registers and their contents with one blank line. + * + * Indent macro values from macro names using TABs. Align values vertically. Use + * braces in macro values as needed to avoid unintended precedence after macro + * substitution. Use spaces in macro values according to kernel coding + * style. Use lower case in hexadecimal values. + * + * Naming + * '''''' + * + * Try to name registers according to the specs. If the register name changes in + * the specs from platform to another, stick to the original name. + * + * Try to re-use existing register macro definitions. Only add new macros for + * new register offsets, or when the register contents have changed enough to + * warrant a full redefinition. + * + * When a register macro changes for a new platform, prefix the new macro using + * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The + * prefix signifies the start platform/generation using the register. + * + * When a bit (field) macro changes or gets added for a new platform, while + * retaining the existing register macro, add a platform acronym or generation + * suffix to the name. For example, ``_SKL`` or ``_GEN8``. + * + * Examples + * '''''''' + * + * (Note that the values in the example are indented using spaces instead of + * TABs to avoid misalignment in generated documentation. Use TABs in the + * definitions.):: + * + * #define _FOO_A 0xf000 + * #define _FOO_B 0xf001 + * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) + * #define FOO_ENABLE (1 << 31) + * #define FOO_MODE_MASK (0xf << 16) + * #define FOO_MODE_SHIFT 16 + * #define FOO_MODE_BAR (0 << 16) + * #define FOO_MODE_BAZ (1 << 16) + * #define FOO_MODE_QUX_SNB (2 << 16) + * + * #define BAR _MMIO(0xb000) + * #define GEN8_BAR _MMIO(0xb888) + */ + typedef struct { uint32_t reg; } i915_reg_t; @@ -229,6 +320,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN8_RPCS_EU_MIN_SHIFT 0 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) +#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) +/* HSW only */ +#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 +#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) +#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) +/* HSW+ */ +#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) +#define HSW_RCS_CONTEXT_ENABLE (1 << 7) +#define HSW_RCS_INHIBIT (1 << 8) +/* Gen8 */ +#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) +#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) +#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) +#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 +#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) +#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 +#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) +#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) + #define GAM_ECOCHK _MMIO(0x4090) #define BDW_DISABLE_HDC_INVALIDATION (1<<25) #define ECOCHK_SNB_BIT (1<<10) @@ -729,119 +842,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define EU_PERF_CNTL5 _MMIO(0xe55c) #define EU_PERF_CNTL6 _MMIO(0xe65c) -#define GDT_CHICKEN_BITS _MMIO(0x9840) -#define GT_NOA_ENABLE 0x00000080 - /* * OA Boolean state */ -#define OAREPORTTRIG1 _MMIO(0x2740) -#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ - -#define OAREPORTTRIG2 _MMIO(0x2744) -#define OAREPORTTRIG2_INVERT_A_0 (1<<0) -#define OAREPORTTRIG2_INVERT_A_1 (1<<1) -#define OAREPORTTRIG2_INVERT_A_2 (1<<2) -#define OAREPORTTRIG2_INVERT_A_3 (1<<3) -#define OAREPORTTRIG2_INVERT_A_4 (1<<4) -#define OAREPORTTRIG2_INVERT_A_5 (1<<5) -#define OAREPORTTRIG2_INVERT_A_6 (1<<6) -#define OAREPORTTRIG2_INVERT_A_7 (1<<7) -#define OAREPORTTRIG2_INVERT_A_8 (1<<8) -#define OAREPORTTRIG2_INVERT_A_9 (1<<9) -#define OAREPORTTRIG2_INVERT_A_10 (1<<10) -#define OAREPORTTRIG2_INVERT_A_11 (1<<11) -#define OAREPORTTRIG2_INVERT_A_12 (1<<12) -#define OAREPORTTRIG2_INVERT_A_13 (1<<13) -#define OAREPORTTRIG2_INVERT_A_14 (1<<14) -#define OAREPORTTRIG2_INVERT_A_15 (1<<15) -#define OAREPORTTRIG2_INVERT_B_0 (1<<16) -#define OAREPORTTRIG2_INVERT_B_1 (1<<17) -#define OAREPORTTRIG2_INVERT_B_2 (1<<18) -#define OAREPORTTRIG2_INVERT_B_3 (1<<19) -#define OAREPORTTRIG2_INVERT_C_0 (1<<20) -#define OAREPORTTRIG2_INVERT_C_1 (1<<21) -#define OAREPORTTRIG2_INVERT_D_0 (1<<22) -#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) -#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) - -#define OAREPORTTRIG3 _MMIO(0x2748) -#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG4 _MMIO(0x274c) -#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 - -#define OAREPORTTRIG5 _MMIO(0x2750) -#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ - -#define OAREPORTTRIG6 _MMIO(0x2754) -#define OAREPORTTRIG6_INVERT_A_0 (1<<0) -#define OAREPORTTRIG6_INVERT_A_1 (1<<1) -#define OAREPORTTRIG6_INVERT_A_2 (1<<2) -#define OAREPORTTRIG6_INVERT_A_3 (1<<3) -#define OAREPORTTRIG6_INVERT_A_4 (1<<4) -#define OAREPORTTRIG6_INVERT_A_5 (1<<5) -#define OAREPORTTRIG6_INVERT_A_6 (1<<6) -#define OAREPORTTRIG6_INVERT_A_7 (1<<7) -#define OAREPORTTRIG6_INVERT_A_8 (1<<8) -#define OAREPORTTRIG6_INVERT_A_9 (1<<9) -#define OAREPORTTRIG6_INVERT_A_10 (1<<10) -#define OAREPORTTRIG6_INVERT_A_11 (1<<11) -#define OAREPORTTRIG6_INVERT_A_12 (1<<12) -#define OAREPORTTRIG6_INVERT_A_13 (1<<13) -#define OAREPORTTRIG6_INVERT_A_14 (1<<14) -#define OAREPORTTRIG6_INVERT_A_15 (1<<15) -#define OAREPORTTRIG6_INVERT_B_0 (1<<16) -#define OAREPORTTRIG6_INVERT_B_1 (1<<17) -#define OAREPORTTRIG6_INVERT_B_2 (1<<18) -#define OAREPORTTRIG6_INVERT_B_3 (1<<19) -#define OAREPORTTRIG6_INVERT_C_0 (1<<20) -#define OAREPORTTRIG6_INVERT_C_1 (1<<21) -#define OAREPORTTRIG6_INVERT_D_0 (1<<22) -#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) -#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) - -#define OAREPORTTRIG7 _MMIO(0x2758) -#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG8 _MMIO(0x275c) -#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 - #define OASTARTTRIG1 _MMIO(0x2710) #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff @@ -956,6 +960,112 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 +#define OAREPORTTRIG1 _MMIO(0x2740) +#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG2 _MMIO(0x2744) +#define OAREPORTTRIG2_INVERT_A_0 (1<<0) +#define OAREPORTTRIG2_INVERT_A_1 (1<<1) +#define OAREPORTTRIG2_INVERT_A_2 (1<<2) +#define OAREPORTTRIG2_INVERT_A_3 (1<<3) +#define OAREPORTTRIG2_INVERT_A_4 (1<<4) +#define OAREPORTTRIG2_INVERT_A_5 (1<<5) +#define OAREPORTTRIG2_INVERT_A_6 (1<<6) +#define OAREPORTTRIG2_INVERT_A_7 (1<<7) +#define OAREPORTTRIG2_INVERT_A_8 (1<<8) +#define OAREPORTTRIG2_INVERT_A_9 (1<<9) +#define OAREPORTTRIG2_INVERT_A_10 (1<<10) +#define OAREPORTTRIG2_INVERT_A_11 (1<<11) +#define OAREPORTTRIG2_INVERT_A_12 (1<<12) +#define OAREPORTTRIG2_INVERT_A_13 (1<<13) +#define OAREPORTTRIG2_INVERT_A_14 (1<<14) +#define OAREPORTTRIG2_INVERT_A_15 (1<<15) +#define OAREPORTTRIG2_INVERT_B_0 (1<<16) +#define OAREPORTTRIG2_INVERT_B_1 (1<<17) +#define OAREPORTTRIG2_INVERT_B_2 (1<<18) +#define OAREPORTTRIG2_INVERT_B_3 (1<<19) +#define OAREPORTTRIG2_INVERT_C_0 (1<<20) +#define OAREPORTTRIG2_INVERT_C_1 (1<<21) +#define OAREPORTTRIG2_INVERT_D_0 (1<<22) +#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG3 _MMIO(0x2748) +#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG4 _MMIO(0x274c) +#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 + +#define OAREPORTTRIG5 _MMIO(0x2750) +#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG6 _MMIO(0x2754) +#define OAREPORTTRIG6_INVERT_A_0 (1<<0) +#define OAREPORTTRIG6_INVERT_A_1 (1<<1) +#define OAREPORTTRIG6_INVERT_A_2 (1<<2) +#define OAREPORTTRIG6_INVERT_A_3 (1<<3) +#define OAREPORTTRIG6_INVERT_A_4 (1<<4) +#define OAREPORTTRIG6_INVERT_A_5 (1<<5) +#define OAREPORTTRIG6_INVERT_A_6 (1<<6) +#define OAREPORTTRIG6_INVERT_A_7 (1<<7) +#define OAREPORTTRIG6_INVERT_A_8 (1<<8) +#define OAREPORTTRIG6_INVERT_A_9 (1<<9) +#define OAREPORTTRIG6_INVERT_A_10 (1<<10) +#define OAREPORTTRIG6_INVERT_A_11 (1<<11) +#define OAREPORTTRIG6_INVERT_A_12 (1<<12) +#define OAREPORTTRIG6_INVERT_A_13 (1<<13) +#define OAREPORTTRIG6_INVERT_A_14 (1<<14) +#define OAREPORTTRIG6_INVERT_A_15 (1<<15) +#define OAREPORTTRIG6_INVERT_B_0 (1<<16) +#define OAREPORTTRIG6_INVERT_B_1 (1<<17) +#define OAREPORTTRIG6_INVERT_B_2 (1<<18) +#define OAREPORTTRIG6_INVERT_B_3 (1<<19) +#define OAREPORTTRIG6_INVERT_C_0 (1<<20) +#define OAREPORTTRIG6_INVERT_C_1 (1<<21) +#define OAREPORTTRIG6_INVERT_D_0 (1<<22) +#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG7 _MMIO(0x2758) +#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG8 _MMIO(0x275c) +#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 + /* CECX_0 */ #define OACEC_COMPARE_LESS_OR_EQUAL 6 #define OACEC_COMPARE_NOT_EQUAL 5 @@ -994,6 +1104,51 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OACEC7_0 _MMIO(0x27a8) #define OACEC7_1 _MMIO(0x27ac) +/* OA perf counters */ +#define OA_PERFCNT1_LO _MMIO(0x91B8) +#define OA_PERFCNT1_HI _MMIO(0x91BC) +#define OA_PERFCNT2_LO _MMIO(0x91C0) +#define OA_PERFCNT2_HI _MMIO(0x91C4) + +#define OA_PERFMATRIX_LO _MMIO(0x91C8) +#define OA_PERFMATRIX_HI _MMIO(0x91CC) + +/* RPM unit config (Gen8+) */ +#define RPM_CONFIG0 _MMIO(0x0D00) +#define RPM_CONFIG1 _MMIO(0x0D04) + +/* RPC unit config (Gen8+) */ +#define RPM_CONFIG _MMIO(0x0D08) + +/* NOA (Gen8+) */ +#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) + +#define MICRO_BP0_0 _MMIO(0x9800) +#define MICRO_BP0_2 _MMIO(0x9804) +#define MICRO_BP0_1 _MMIO(0x9808) + +#define MICRO_BP1_0 _MMIO(0x980C) +#define MICRO_BP1_2 _MMIO(0x9810) +#define MICRO_BP1_1 _MMIO(0x9814) + +#define MICRO_BP2_0 _MMIO(0x9818) +#define MICRO_BP2_2 _MMIO(0x981C) +#define MICRO_BP2_1 _MMIO(0x9820) + +#define MICRO_BP3_0 _MMIO(0x9824) +#define MICRO_BP3_2 _MMIO(0x9828) +#define MICRO_BP3_1 _MMIO(0x982C) + +#define MICRO_BP_TRIGGER _MMIO(0x9830) +#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) +#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) +#define MICRO_BP_FIRED_ARMED _MMIO(0x983C) + +#define GDT_CHICKEN_BITS _MMIO(0x9840) +#define GT_NOA_ENABLE 0x00000080 + +#define NOA_DATA _MMIO(0x986C) +#define NOA_WRITE _MMIO(0x9888) #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 @@ -1063,9 +1218,26 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) -/* See the PUNIT HAS v0.8 for the below bits */ -enum punit_power_well { - /* These numbers are fixed and must match the position of the pw bits */ +/* + * i915_power_well_id: + * + * Platform specific IDs used to look up power wells and - except for custom + * power wells - to define request/status register flag bit positions. As such + * the set of IDs on a given platform must be unique and except for custom + * power wells their value must stay fixed. + */ +enum i915_power_well_id { + /* + * I830 + * - custom power well + */ + I830_DISP_PW_PIPES = 0, + + /* + * VLV/CHV + * - PUNIT_REG_PWRGT_CTRL (bit: id*2), + * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) + */ PUNIT_POWER_WELL_RENDER = 0, PUNIT_POWER_WELL_MEDIA = 1, PUNIT_POWER_WELL_DISP2D = 3, @@ -1077,14 +1249,20 @@ enum punit_power_well { PUNIT_POWER_WELL_DPIO_RX0 = 10, PUNIT_POWER_WELL_DPIO_RX1 = 11, PUNIT_POWER_WELL_DPIO_CMN_D = 12, - - /* Not actual bit groups. Used as IDs for lookup_power_well() */ - PUNIT_POWER_WELL_ALWAYS_ON, -}; - -enum skl_disp_power_wells { - /* These numbers are fixed and must match the position of the pw bits */ - SKL_DISP_PW_MISC_IO, + /* - custom power well */ + CHV_DISP_PW_PIPE_A, /* 13 */ + + /* + * HSW/BDW + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) + */ + HSW_DISP_PW_GLOBAL = 15, + + /* + * GEN9+ + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) + */ + SKL_DISP_PW_MISC_IO = 0, SKL_DISP_PW_DDI_A_E, GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, @@ -1103,18 +1281,20 @@ enum skl_disp_power_wells { SKL_DISP_PW_1 = 14, SKL_DISP_PW_2, - /* Not actual bit groups. Used as IDs for lookup_power_well() */ - SKL_DISP_PW_ALWAYS_ON, + /* - custom power wells */ SKL_DISP_PW_DC_OFF, - BXT_DPIO_CMN_A, BXT_DPIO_CMN_BC, - GLK_DPIO_CMN_C, + GLK_DPIO_CMN_C, /* 19 */ + + /* + * Multiple platforms. + * Must start following the highest ID of any platform. + * - custom power wells + */ + I915_DISP_PW_ALWAYS_ON = 20, }; -#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) -#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) - #define PUNIT_REG_PWRGT_CTRL 0x60 #define PUNIT_REG_PWRGT_STATUS 0x61 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) @@ -2156,6 +2336,7 @@ enum skl_disp_power_wells { #define DONE_REG _MMIO(0x40b0) #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) +#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + index*4) #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) @@ -2192,6 +2373,7 @@ enum skl_disp_power_wells { #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28) +#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24) #if 0 #define PRB0_TAIL _MMIO(0x2030) @@ -2310,6 +2492,7 @@ enum skl_disp_power_wells { # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) #define _3D_CHICKEN3 _MMIO(0x2090) #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) +#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ @@ -2757,6 +2940,9 @@ enum skl_disp_power_wells { #define ILK_DPFC_CHICKEN _MMIO(0x43224) #define ILK_DPFC_DISABLE_DUMMY0 (1<<8) #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23) +#define GLK_SKIP_SEG_EN (1<<12) +#define GLK_SKIP_SEG_COUNT_MASK (3<<10) +#define GLK_SKIP_SEG_COUNT(x) ((x)<<10) #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID (1<<0) #define SNB_FBC_FRONT_BUFFER (1<<1) @@ -3626,6 +3812,12 @@ enum { #define PWM1_GATING_DIS (1 << 13) /* + * GEN10 clock gating regs + */ +#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) +#define SARBUNIT_CLKGATE_DIS (1 << 5) + +/* * Display engine regs */ @@ -3783,6 +3975,7 @@ enum { #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) #define EDP_PSR_ENABLE (1<<31) #define BDW_PSR_SINGLE_FRAME (1<<30) +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */ #define EDP_PSR_LINK_STANDBY (1<<27) #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) @@ -5227,6 +5420,9 @@ enum { #define _PIPE_MISC_A 0x70030 #define _PIPE_MISC_B 0x71030 +#define PIPEMISC_YUV420_ENABLE (1<<27) +#define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26) +#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11) #define PIPEMISC_DITHER_BPC_MASK (7<<5) #define PIPEMISC_DITHER_8_BPC (0<<5) #define PIPEMISC_DITHER_10_BPC (1<<5) @@ -6106,6 +6302,10 @@ enum { #define _PLANE_KEYMSK_2_A 0x70298 #define _PLANE_KEYMAX_1_A 0x701a0 #define _PLANE_KEYMAX_2_A 0x702a0 +#define _PLANE_AUX_DIST_1_A 0x701c0 +#define _PLANE_AUX_DIST_2_A 0x702c0 +#define _PLANE_AUX_OFFSET_1_A 0x701c4 +#define _PLANE_AUX_OFFSET_2_A 0x702c4 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ @@ -6212,6 +6412,24 @@ enum { #define PLANE_NV12_BUF_CFG(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +#define _PLANE_AUX_DIST_1_B 0x711c0 +#define _PLANE_AUX_DIST_2_B 0x712c0 +#define _PLANE_AUX_DIST_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) +#define _PLANE_AUX_DIST_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) +#define PLANE_AUX_DIST(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) + +#define _PLANE_AUX_OFFSET_1_B 0x711c4 +#define _PLANE_AUX_OFFSET_2_B 0x712c4 +#define _PLANE_AUX_OFFSET_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) +#define _PLANE_AUX_OFFSET_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) +#define PLANE_AUX_OFFSET(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) + #define _PLANE_COLOR_CTL_1_B 0x711CC #define _PLANE_COLOR_CTL_2_B 0x712CC #define _PLANE_COLOR_CTL_3_B 0x713CC @@ -6695,6 +6913,7 @@ enum { # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) #define CHICKEN_PAR1_1 _MMIO(0x42080) +#define SKL_RC_HASH_OUTSIDE (1 << 15) #define DPA_MASK_VBLANK_SRD (1 << 15) #define FORCE_ARB_IDLE_PLANES (1 << 14) #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) @@ -6703,12 +6922,14 @@ enum { #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) #define CHICKEN_MISC_2 _MMIO(0x42084) -#define GLK_CL0_PWR_DOWN (1 << 10) -#define GLK_CL1_PWR_DOWN (1 << 11) +#define CNL_COMP_PWR_DOWN (1 << 23) #define GLK_CL2_PWR_DOWN (1 << 12) +#define GLK_CL1_PWR_DOWN (1 << 11) +#define GLK_CL0_PWR_DOWN (1 << 10) -#define CHICKEN_MISC_2 _MMIO(0x42084) -#define COMP_PWR_DOWN (1 << 23) +#define CHICKEN_MISC_4 _MMIO(0x4208c) +#define FBC_STRIDE_OVERRIDE (1 << 13) +#define FBC_STRIDE_MASK 0x1FFF #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 @@ -6811,6 +7032,7 @@ enum { /* GEN8 chicken */ #define HDC_CHICKEN0 _MMIO(0x7300) +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) @@ -7264,6 +7486,7 @@ enum { #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) +#define CNP_PWM_CGE_GATING_DISABLE (1<<13) #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) /* CPU: FDI_TX */ @@ -7838,10 +8061,12 @@ enum { #define FLOW_CONTROL_ENABLE (1<<15) #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) #define STALL_DOP_GATING_DISABLE (1<<5) +#define THROTTLE_12_5 (7<<2) #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) #define DOP_CLOCK_GATING_DISABLE (1<<0) +#define PUSH_CONSTANT_DEREF_DISABLE (1<<8) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) @@ -7853,6 +8078,7 @@ enum { #define HSW_SAMPLE_C_PERFORMANCE (1<<9) #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) +#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4) #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) @@ -7984,12 +8210,31 @@ enum { #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) /* HSW Power Wells */ -#define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ -#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ -#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ -#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ -#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) -#define HSW_PWR_WELL_STATE_ENABLED (1<<30) +#define _HSW_PWR_WELL_CTL1 0x45400 +#define _HSW_PWR_WELL_CTL2 0x45404 +#define _HSW_PWR_WELL_CTL3 0x45408 +#define _HSW_PWR_WELL_CTL4 0x4540C + +/* + * Each power well control register contains up to 16 (request, status) HW + * flag tuples. The register index and HW flag shift is determined by the + * power well ID (see i915_power_well_id). There are 4 possible sources of + * power well requests each source having its own set of control registers: + * BIOS, DRIVER, KVMR, DEBUG. + */ +#define _HSW_PW_REG_IDX(pw) ((pw) >> 4) +#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2) +/* TODO: Add all PWR_WELL_CTL registers below for new platforms */ +#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL1)) +#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL2)) +#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3) +#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL4)) + +#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) +#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) @@ -7997,11 +8242,17 @@ enum { #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) /* SKL Fuse Status */ +enum skl_power_gate { + SKL_PG0, + SKL_PG1, + SKL_PG2, +}; + #define SKL_FUSE_STATUS _MMIO(0x42000) -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) -#define SKL_FUSE_PG0_DIST_STATUS (1<<27) -#define SKL_FUSE_PG1_DIST_STATUS (1<<26) -#define SKL_FUSE_PG2_DIST_STATUS (1<<25) +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */ +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 diff --git a/drivers/gpu/drm/i915/i915_selftest.h b/drivers/gpu/drm/i915/i915_selftest.h index 9d7d86f1733d..78e1a1b168ff 100644 --- a/drivers/gpu/drm/i915/i915_selftest.h +++ b/drivers/gpu/drm/i915/i915_selftest.h @@ -101,6 +101,4 @@ bool __igt_timeout(unsigned long timeout, const char *fmt, ...); #define igt_timeout(t, fmt, ...) \ __igt_timeout((t), KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) -#define igt_can_mi_store_dword_imm(D) (INTEL_GEN(D) > 2) - #endif /* !__I915_SELFTEST_H__ */ diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 7fcf00622c4c..d61c8727f756 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -220,7 +220,7 @@ out: return ret; } -static struct bin_attribute dpf_attrs = { +static const struct bin_attribute dpf_attrs = { .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, .read = i915_l3_read, @@ -229,7 +229,7 @@ static struct bin_attribute dpf_attrs = { .private = (void *)0 }; -static struct bin_attribute dpf_attrs_1 = { +static const struct bin_attribute dpf_attrs_1 = { .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, .read = i915_l3_read, @@ -532,7 +532,7 @@ static ssize_t error_state_write(struct file *file, struct kobject *kobj, return count; } -static struct bin_attribute error_state_attr = { +static const struct bin_attribute error_state_attr = { .attr.name = "error", .attr.mode = S_IRUSR | S_IWUSR, .size = 0, diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index b24a83d43559..92f4c5bb7aa7 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -38,7 +38,7 @@ TRACE_EVENT(intel_cpu_fifo_underrun, ); TRACE_EVENT(intel_pch_fifo_underrun, - TP_PROTO(struct drm_i915_private *dev_priv, enum transcoder pch_transcoder), + TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pch_transcoder), TP_ARGS(dev_priv, pch_transcoder), TP_STRUCT__entry( @@ -48,7 +48,7 @@ TRACE_EVENT(intel_pch_fifo_underrun, ), TP_fast_assign( - enum pipe pipe = (enum pipe)pch_transcoder; + enum pipe pipe = pch_transcoder; __entry->pipe = pipe; __entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe); __entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe)); @@ -1031,5 +1031,5 @@ TRACE_EVENT(switch_mm, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915 #include <trace/define_trace.h> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index cf7a958e4d3c..5fe9f3f39467 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -75,10 +75,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv) return; } + dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps)); + dev_priv->vgpu.active = true; DRM_INFO("Virtual GPU for Intel GVT-g detected.\n"); } +bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv) +{ + return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT; +} + struct _balloon_info_ { /* * There are up to 2 regions per mappable/unmappable graphic diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h index 3c3b2d24e830..b72bd2956b70 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.h +++ b/drivers/gpu/drm/i915/i915_vgpu.h @@ -27,6 +27,9 @@ #include "i915_pvinfo.h" void i915_check_vgpu(struct drm_i915_private *dev_priv); + +bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv); + int intel_vgt_balloon(struct drm_i915_private *dev_priv); void intel_vgt_deballoon(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 958be0a95960..02d1a5eacb00 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -597,33 +597,11 @@ static void i915_vma_destroy(struct i915_vma *vma) kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); } -void i915_vma_unlink_ctx(struct i915_vma *vma) -{ - struct i915_gem_context *ctx = vma->ctx; - - if (ctx->vma_lut.ht_size & I915_CTX_RESIZE_IN_PROGRESS) { - cancel_work_sync(&ctx->vma_lut.resize); - ctx->vma_lut.ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; - } - - __hlist_del(&vma->ctx_node); - ctx->vma_lut.ht_count--; - - if (i915_vma_is_ggtt(vma)) - vma->obj->vma_hashed = NULL; - vma->ctx = NULL; - - i915_vma_put(vma); -} - void i915_vma_close(struct i915_vma *vma) { GEM_BUG_ON(i915_vma_is_closed(vma)); vma->flags |= I915_VMA_CLOSED; - if (vma->ctx) - i915_vma_unlink_ctx(vma); - list_del(&vma->obj_link); rb_erase(&vma->obj_node, &vma->obj->vma_tree); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 20cf272c97b1..e811067c7724 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -59,6 +59,12 @@ struct i915_vma { u32 fence_size; u32 fence_alignment; + /** + * Count of the number of times this vma has been opened by different + * handles (but same file) for execbuf, i.e. the number of aliases + * that exist in the ctx->handle_vmas LUT for this vma. + */ + unsigned int open_count; unsigned int flags; /** * How many users have pinned this object in GTT space. The following @@ -112,13 +118,9 @@ struct i915_vma { /** * Used for performing relocations during execbuffer insertion. */ - struct drm_i915_gem_exec_object2 *exec_entry; + unsigned int *exec_flags; struct hlist_node exec_node; u32 exec_handle; - - struct i915_gem_context *ctx; - struct hlist_node ctx_node; - u32 ctx_handle; }; struct i915_vma * diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index ee76fab7bb6f..8e6dc159f64d 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -107,7 +107,9 @@ intel_plane_destroy_state(struct drm_plane *plane, drm_atomic_helper_plane_destroy_state(plane, state); } -int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, +int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, + struct intel_crtc_state *crtc_state, + const struct intel_plane_state *old_plane_state, struct intel_plane_state *intel_state) { struct drm_plane *plane = intel_state->base.plane; @@ -124,7 +126,7 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, * anything driver-specific we need to test in that case, so * just return success. */ - if (!intel_state->base.crtc && !plane->state->crtc) + if (!intel_state->base.crtc && !old_plane_state->base.crtc) return 0; /* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */ @@ -194,16 +196,21 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, else crtc_state->active_planes &= ~BIT(intel_plane->id); - return intel_plane_atomic_calc_changes(&crtc_state->base, state); + return intel_plane_atomic_calc_changes(old_crtc_state, + &crtc_state->base, + old_plane_state, + state); } static int intel_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_plane_state *new_plane_state) { - struct drm_crtc *crtc = state->crtc; - struct drm_crtc_state *drm_crtc_state; - - crtc = crtc ? crtc : plane->state->crtc; + struct drm_atomic_state *state = new_plane_state->state; + const struct drm_plane_state *old_plane_state = + drm_atomic_get_old_plane_state(state, plane); + struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; + const struct drm_crtc_state *old_crtc_state; + struct drm_crtc_state *new_crtc_state; /* * Both crtc and plane->crtc could be NULL if we're updating a @@ -214,29 +221,33 @@ static int intel_plane_atomic_check(struct drm_plane *plane, if (!crtc) return 0; - drm_crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); - if (WARN_ON(!drm_crtc_state)) - return -EINVAL; + old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); - return intel_plane_atomic_check_with_state(to_intel_crtc_state(drm_crtc_state), - to_intel_plane_state(state)); + return intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state), + to_intel_crtc_state(new_crtc_state), + to_intel_plane_state(old_plane_state), + to_intel_plane_state(new_plane_state)); } static void intel_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { + struct intel_atomic_state *state = to_intel_atomic_state(old_state->state); struct intel_plane *intel_plane = to_intel_plane(plane); - struct intel_plane_state *intel_state = - to_intel_plane_state(plane->state); - struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc; + const struct intel_plane_state *new_plane_state = + intel_atomic_get_new_plane_state(state, intel_plane); + struct drm_crtc *crtc = new_plane_state->base.crtc ?: old_state->crtc; + + if (new_plane_state->base.visible) { + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, to_intel_crtc(crtc)); - if (intel_state->base.visible) { trace_intel_update_plane(plane, to_intel_crtc(crtc)); intel_plane->update_plane(intel_plane, - to_intel_crtc_state(crtc->state), - intel_state); + new_crtc_state, new_plane_state); } else { trace_intel_disable_plane(plane, to_intel_crtc(crtc)); diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 82b144cdfa1d..5949750a35ee 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -452,24 +452,24 @@ parse_general_definitions(struct drm_i915_private *dev_priv, } } -static const union child_device_config * -child_device_ptr(const struct bdb_general_definitions *p_defs, int i) +static const struct child_device_config * +child_device_ptr(const struct bdb_general_definitions *defs, int i) { - return (const void *) &p_defs->devices[i * p_defs->child_dev_size]; + return (const void *) &defs->devices[i * defs->child_dev_size]; } static void parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) { - struct sdvo_device_mapping *p_mapping; - const struct bdb_general_definitions *p_defs; - const struct old_child_dev_config *child; /* legacy */ + struct sdvo_device_mapping *mapping; + const struct bdb_general_definitions *defs; + const struct child_device_config *child; int i, child_device_num, count; u16 block_size; - p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); - if (!p_defs) { + defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); + if (!defs) { DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n"); return; } @@ -479,18 +479,17 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, * device size matches that of the *legacy* child device config * struct. Thus, SDVO mapping will be skipped for newer VBT. */ - if (p_defs->child_dev_size != sizeof(*child)) { + if (defs->child_dev_size != LEGACY_CHILD_DEVICE_CONFIG_SIZE) { DRM_DEBUG_KMS("Unsupported child device size for SDVO mapping.\n"); return; } /* get the block size of general definitions */ - block_size = get_blocksize(p_defs); + block_size = get_blocksize(defs); /* get the number of child device */ - child_device_num = (block_size - sizeof(*p_defs)) / - p_defs->child_dev_size; + child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; count = 0; for (i = 0; i < child_device_num; i++) { - child = &child_device_ptr(p_defs, i)->old; + child = child_device_ptr(defs, i); if (!child->device_type) { /* skip the device block if device type is invalid */ continue; @@ -514,20 +513,20 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, child->slave_addr, (child->dvo_port == DEVICE_PORT_DVOB) ? "SDVOB" : "SDVOC"); - p_mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; - if (!p_mapping->initialized) { - p_mapping->dvo_port = child->dvo_port; - p_mapping->slave_addr = child->slave_addr; - p_mapping->dvo_wiring = child->dvo_wiring; - p_mapping->ddc_pin = child->ddc_pin; - p_mapping->i2c_pin = child->i2c_pin; - p_mapping->initialized = 1; + mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; + if (!mapping->initialized) { + mapping->dvo_port = child->dvo_port; + mapping->slave_addr = child->slave_addr; + mapping->dvo_wiring = child->dvo_wiring; + mapping->ddc_pin = child->ddc_pin; + mapping->i2c_pin = child->i2c_pin; + mapping->initialized = 1; DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", - p_mapping->dvo_port, - p_mapping->slave_addr, - p_mapping->dvo_wiring, - p_mapping->ddc_pin, - p_mapping->i2c_pin); + mapping->dvo_port, + mapping->slave_addr, + mapping->dvo_wiring, + mapping->ddc_pin, + mapping->i2c_pin); } else { DRM_DEBUG_KMS("Maybe one SDVO port is shared by " "two SDVO device.\n"); @@ -577,7 +576,7 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) { const struct bdb_edp *edp; const struct edp_power_seq *edp_pps; - const struct edp_link_params *edp_link_params; + const struct edp_fast_link_params *edp_link_params; int panel_type = dev_priv->vbt.panel_type; edp = find_section(bdb, BDB_EDP); @@ -601,7 +600,7 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) /* Get the eDP sequencing and link info */ edp_pps = &edp->power_seqs[panel_type]; - edp_link_params = &edp->link_params[panel_type]; + edp_link_params = &edp->fast_link_params[panel_type]; dev_priv->vbt.edp.pps = *edp_pps; @@ -1113,15 +1112,15 @@ static void sanitize_aux_ch(struct drm_i915_private *dev_priv, static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, const struct bdb_header *bdb) { - union child_device_config *it, *child = NULL; + struct child_device_config *it, *child = NULL; struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; uint8_t hdmi_level_shift; int i, j; bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; uint8_t aux_channel, ddc_pin; /* Each DDI port can have more than one value on the "DVO Port" field, - * so look for all the possible values for each port and abort if more - * than one is found. */ + * so look for all the possible values for each port. + */ int dvo_ports[][3] = { {DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, {DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, @@ -1130,7 +1129,10 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, }; - /* Find the child device to use, abort if more than one found. */ + /* + * Find the first child device to reference the port, report if more + * than one found. + */ for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { it = dev_priv->vbt.child_dev + i; @@ -1138,27 +1140,27 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, if (dvo_ports[port][j] == -1) break; - if (it->common.dvo_port == dvo_ports[port][j]) { + if (it->dvo_port == dvo_ports[port][j]) { if (child) { - DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n", + DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n", port_name(port)); - return; + } else { + child = it; } - child = it; } } } if (!child) return; - aux_channel = child->common.aux_channel; - ddc_pin = child->common.ddc_pin; + aux_channel = child->aux_channel; + ddc_pin = child->ddc_pin; - is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; - is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; - is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT; - is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; - is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); + is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; + is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; + is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT; + is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; + is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); info->supports_dvi = is_dvi; info->supports_hdmi = is_hdmi; @@ -1207,7 +1209,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, if (bdb->version >= 158) { /* The VBT HDMI level shift values match the table we have. */ - hdmi_level_shift = child->raw[7] & 0xF; + hdmi_level_shift = child->hdmi_level_shifter_value; DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", port_name(port), hdmi_level_shift); @@ -1215,11 +1217,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, } /* Parse the I_boost config for SKL and above */ - if (bdb->version >= 196 && child->common.iboost) { - info->dp_boost_level = translate_iboost(child->common.iboost_level & 0xF); + if (bdb->version >= 196 && child->iboost) { + info->dp_boost_level = translate_iboost(child->dp_iboost_level); DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n", port_name(port), info->dp_boost_level); - info->hdmi_boost_level = translate_iboost(child->common.iboost_level >> 4); + info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level); DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n", port_name(port), info->hdmi_boost_level); } @@ -1247,15 +1249,15 @@ static void parse_device_mapping(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) { - const struct bdb_general_definitions *p_defs; - const union child_device_config *p_child; - union child_device_config *child_dev_ptr; + const struct bdb_general_definitions *defs; + const struct child_device_config *child; + struct child_device_config *child_dev_ptr; int i, child_device_num, count; u8 expected_size; u16 block_size; - p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); - if (!p_defs) { + defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); + if (!defs) { DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); return; } @@ -1264,41 +1266,39 @@ parse_device_mapping(struct drm_i915_private *dev_priv, } else if (bdb->version < 111) { expected_size = 27; } else if (bdb->version < 195) { - BUILD_BUG_ON(sizeof(struct old_child_dev_config) != 33); - expected_size = sizeof(struct old_child_dev_config); + expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; } else if (bdb->version == 195) { expected_size = 37; } else if (bdb->version <= 197) { expected_size = 38; } else { expected_size = 38; - BUILD_BUG_ON(sizeof(*p_child) < 38); + BUILD_BUG_ON(sizeof(*child) < 38); DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n", bdb->version, expected_size); } /* Flag an error for unexpected size, but continue anyway. */ - if (p_defs->child_dev_size != expected_size) + if (defs->child_dev_size != expected_size) DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n", - p_defs->child_dev_size, expected_size, bdb->version); + defs->child_dev_size, expected_size, bdb->version); /* The legacy sized child device config is the minimum we need. */ - if (p_defs->child_dev_size < sizeof(struct old_child_dev_config)) { + if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { DRM_DEBUG_KMS("Child device config size %u is too small.\n", - p_defs->child_dev_size); + defs->child_dev_size); return; } /* get the block size of general definitions */ - block_size = get_blocksize(p_defs); + block_size = get_blocksize(defs); /* get the number of child device */ - child_device_num = (block_size - sizeof(*p_defs)) / - p_defs->child_dev_size; + child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; count = 0; /* get the number of child device that is present */ for (i = 0; i < child_device_num; i++) { - p_child = child_device_ptr(p_defs, i); - if (!p_child->common.device_type) { + child = child_device_ptr(defs, i); + if (!child->device_type) { /* skip the device block if device type is invalid */ continue; } @@ -1308,7 +1308,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv, DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); return; } - dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL); + dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL); if (!dev_priv->vbt.child_dev) { DRM_DEBUG_KMS("No memory space for child device\n"); return; @@ -1317,8 +1317,8 @@ parse_device_mapping(struct drm_i915_private *dev_priv, dev_priv->vbt.child_dev_num = count; count = 0; for (i = 0; i < child_device_num; i++) { - p_child = child_device_ptr(p_defs, i); - if (!p_child->common.device_type) { + child = child_device_ptr(defs, i); + if (!child->device_type) { /* skip the device block if device type is invalid */ continue; } @@ -1331,8 +1331,8 @@ parse_device_mapping(struct drm_i915_private *dev_priv, * (child_dev_size) of the child device. Accessing the data must * depend on VBT version. */ - memcpy(child_dev_ptr, p_child, - min_t(size_t, p_defs->child_dev_size, sizeof(*p_child))); + memcpy(child_dev_ptr, child, + min_t(size_t, defs->child_dev_size, sizeof(*child))); /* * copied full block, now init values when they are not @@ -1340,12 +1340,12 @@ parse_device_mapping(struct drm_i915_private *dev_priv, */ if (bdb->version < 196) { /* Set default values for bits added from v196 */ - child_dev_ptr->common.iboost = 0; - child_dev_ptr->common.hpd_invert = 0; + child_dev_ptr->iboost = 0; + child_dev_ptr->hpd_invert = 0; } if (bdb->version < 192) - child_dev_ptr->common.lspcon = 0; + child_dev_ptr->lspcon = 0; } return; } @@ -1556,7 +1556,7 @@ out: */ bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) { - union child_device_config *p_child; + const struct child_device_config *child; int i; if (!dev_priv->vbt.int_tv_support) @@ -1566,11 +1566,11 @@ bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) return true; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - p_child = dev_priv->vbt.child_dev + i; + child = dev_priv->vbt.child_dev + i; /* * If the device type is not TV, continue. */ - switch (p_child->old.device_type) { + switch (child->device_type) { case DEVICE_TYPE_INT_TV: case DEVICE_TYPE_TV: case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: @@ -1581,7 +1581,7 @@ bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) /* Only when the addin_offset is non-zero, it is regarded * as present. */ - if (p_child->old.addin_offset) + if (child->addin_offset) return true; } @@ -1598,14 +1598,14 @@ bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) */ bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin) { + const struct child_device_config *child; int i; if (!dev_priv->vbt.child_dev_num) return true; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - union child_device_config *uchild = dev_priv->vbt.child_dev + i; - struct old_child_dev_config *child = &uchild->old; + child = dev_priv->vbt.child_dev + i; /* If the device type is not LFP, continue. * We have to check both the new identifiers as well as the @@ -1647,6 +1647,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin) */ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port) { + const struct child_device_config *child; static const struct { u16 dp, hdmi; } port_mapping[] = { @@ -1665,12 +1666,12 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por return false; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - const union child_device_config *p_child = - &dev_priv->vbt.child_dev[i]; - if ((p_child->common.dvo_port == port_mapping[port].dp || - p_child->common.dvo_port == port_mapping[port].hdmi) && - (p_child->common.device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING | - DEVICE_TYPE_DISPLAYPORT_OUTPUT))) + child = dev_priv->vbt.child_dev + i; + + if ((child->dvo_port == port_mapping[port].dp || + child->dvo_port == port_mapping[port].hdmi) && + (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING | + DEVICE_TYPE_DISPLAYPORT_OUTPUT))) return true; } @@ -1686,7 +1687,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por */ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) { - union child_device_config *p_child; + const struct child_device_config *child; static const short port_mapping[] = { [PORT_B] = DVO_PORT_DPB, [PORT_C] = DVO_PORT_DPC, @@ -1702,10 +1703,10 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) return false; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - p_child = dev_priv->vbt.child_dev + i; + child = dev_priv->vbt.child_dev + i; - if (p_child->common.dvo_port == port_mapping[port] && - (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == + if (child->dvo_port == port_mapping[port] && + (child->device_type & DEVICE_TYPE_eDP_BITS) == (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) return true; } @@ -1713,7 +1714,7 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) return false; } -static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child, +static bool child_dev_is_dp_dual_mode(const struct child_device_config *child, enum port port) { static const struct { @@ -1732,16 +1733,16 @@ static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child, if (port == PORT_A || port >= ARRAY_SIZE(port_mapping)) return false; - if ((p_child->common.device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != + if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) return false; - if (p_child->common.dvo_port == port_mapping[port].dp) + if (child->dvo_port == port_mapping[port].dp) return true; /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ - if (p_child->common.dvo_port == port_mapping[port].hdmi && - p_child->common.aux_channel != 0) + if (child->dvo_port == port_mapping[port].hdmi && + child->aux_channel != 0) return true; return false; @@ -1750,13 +1751,13 @@ static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child, bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port) { + const struct child_device_config *child; int i; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - const union child_device_config *p_child = - &dev_priv->vbt.child_dev[i]; + child = dev_priv->vbt.child_dev + i; - if (child_dev_is_dp_dual_mode(p_child, port)) + if (child_dev_is_dp_dual_mode(child, port)) return true; } @@ -1773,17 +1774,17 @@ bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port) { - union child_device_config *p_child; + const struct child_device_config *child; u8 dvo_port; int i; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - p_child = dev_priv->vbt.child_dev + i; + child = dev_priv->vbt.child_dev + i; - if (!(p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT)) + if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) continue; - dvo_port = p_child->common.dvo_port; + dvo_port = child->dvo_port; switch (dvo_port) { case DVO_PORT_MIPIA: @@ -1813,16 +1814,19 @@ bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, enum port port) { + const struct child_device_config *child; int i; if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv))) return false; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - if (!dev_priv->vbt.child_dev[i].common.hpd_invert) + child = dev_priv->vbt.child_dev + i; + + if (!child->hpd_invert) continue; - switch (dev_priv->vbt.child_dev[i].common.dvo_port) { + switch (child->dvo_port) { case DVO_PORT_DPA: case DVO_PORT_HDMIA: if (port == PORT_A) @@ -1857,16 +1861,19 @@ bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, enum port port) { + const struct child_device_config *child; int i; if (!HAS_LSPCON(dev_priv)) return false; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { - if (!dev_priv->vbt.child_dev[i].common.lspcon) + child = dev_priv->vbt.child_dev + i; + + if (!child->lspcon) continue; - switch (dev_priv->vbt.child_dev[i].common.dvo_port) { + switch (child->dvo_port) { case DVO_PORT_DPA: case DVO_PORT_HDMIA: if (port == PORT_A) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 1241e5891b29..d32911816fc2 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -417,24 +417,21 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv, cdclk_state->cdclk = 540000; } -static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, - int max_pixclk) +static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) { int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; - int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; /* * We seem to get an unstable or solid color picture at 200MHz. * Not sure what's wrong. For now use 200MHz only when all pipes * are off. */ - if (!IS_CHERRYVIEW(dev_priv) && - max_pixclk > freq_320*limit/100) + if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) return 400000; - else if (max_pixclk > 266667*limit/100) + else if (min_cdclk > 266667) return freq_320; - else if (max_pixclk > 0) + else if (min_cdclk > 0) return 266667; else return 200000; @@ -612,13 +609,13 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); } -static int bdw_calc_cdclk(int max_pixclk) +static int bdw_calc_cdclk(int min_cdclk) { - if (max_pixclk > 540000) + if (min_cdclk > 540000) return 675000; - else if (max_pixclk > 450000) + else if (min_cdclk > 450000) return 540000; - else if (max_pixclk > 337500) + else if (min_cdclk > 337500) return 450000; else return 337500; @@ -724,23 +721,23 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, cdclk, dev_priv->cdclk.hw.cdclk); } -static int skl_calc_cdclk(int max_pixclk, int vco) +static int skl_calc_cdclk(int min_cdclk, int vco) { if (vco == 8640000) { - if (max_pixclk > 540000) + if (min_cdclk > 540000) return 617143; - else if (max_pixclk > 432000) + else if (min_cdclk > 432000) return 540000; - else if (max_pixclk > 308571) + else if (min_cdclk > 308571) return 432000; else return 308571; } else { - if (max_pixclk > 540000) + if (min_cdclk > 540000) return 675000; - else if (max_pixclk > 450000) + else if (min_cdclk > 450000) return 540000; - else if (max_pixclk > 337500) + else if (min_cdclk > 337500) return 450000; else return 337500; @@ -1075,31 +1072,25 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv) skl_set_cdclk(dev_priv, &cdclk_state); } -static int bxt_calc_cdclk(int max_pixclk) +static int bxt_calc_cdclk(int min_cdclk) { - if (max_pixclk > 576000) + if (min_cdclk > 576000) return 624000; - else if (max_pixclk > 384000) + else if (min_cdclk > 384000) return 576000; - else if (max_pixclk > 288000) + else if (min_cdclk > 288000) return 384000; - else if (max_pixclk > 144000) + else if (min_cdclk > 144000) return 288000; else return 144000; } -static int glk_calc_cdclk(int max_pixclk) +static int glk_calc_cdclk(int min_cdclk) { - /* - * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk - * as a temporary workaround. Use a higher cdclk instead. (Note that - * intel_compute_max_dotclk() limits the max pixel clock to 99% of max - * cdclk.) - */ - if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100)) + if (min_cdclk > 158400) return 316800; - else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100)) + else if (min_cdclk > 79200) return 158400; else return 79200; @@ -1420,11 +1411,11 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) bxt_set_cdclk(dev_priv, &cdclk_state); } -static int cnl_calc_cdclk(int max_pixclk) +static int cnl_calc_cdclk(int min_cdclk) { - if (max_pixclk > 336000) + if (min_cdclk > 336000) return 528000; - else if (max_pixclk > 168000) + else if (min_cdclk > 168000) return 336000; else return 168000; @@ -1732,104 +1723,119 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, dev_priv->display.set_cdclk(dev_priv, cdclk_state); } -static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, - int pixel_rate) +static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, + int pixel_rate) +{ + if (INTEL_GEN(dev_priv) >= 10) + /* + * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2) + * once DDI clock voltage requirements are + * handled correctly. + */ + return pixel_rate; + else if (IS_GEMINILAKE(dev_priv)) + /* + * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk + * as a temporary workaround. Use a higher cdclk instead. (Note that + * intel_compute_max_dotclk() limits the max pixel clock to 99% of max + * cdclk.) + */ + return DIV_ROUND_UP(pixel_rate * 100, 2 * 99); + else if (IS_GEN9(dev_priv) || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + return pixel_rate; + else if (IS_CHERRYVIEW(dev_priv)) + return DIV_ROUND_UP(pixel_rate * 100, 95); + else + return DIV_ROUND_UP(pixel_rate * 100, 90); +} + +int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); + int min_cdclk; + + if (!crtc_state->base.enable) + return 0; + + min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); + min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else * there may be audio corruption or screen corruption." This cdclk - * restriction for GLK is 316.8 MHz and since GLK can output two - * pixels per clock, the pixel rate becomes 2 * 316.8 MHz. + * restriction for GLK is 316.8 MHz. */ if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio && crtc_state->port_clock >= 540000 && crtc_state->lane_count == 4) { - if (IS_CANNONLAKE(dev_priv)) - pixel_rate = max(316800, pixel_rate); - else if (IS_GEMINILAKE(dev_priv)) - pixel_rate = max(2 * 316800, pixel_rate); - else - pixel_rate = max(432000, pixel_rate); + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { + /* Display WA #1145: glk,cnl */ + min_cdclk = max(316800, min_cdclk); + } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { + /* Display WA #1144: skl,bxt */ + min_cdclk = max(432000, min_cdclk); + } } /* According to BSpec, "The CD clock frequency must be at least twice * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. - * The check for GLK has to be adjusted as the platform can output - * two pixels per clock. */ - if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) { - if (IS_GEMINILAKE(dev_priv)) - pixel_rate = max(2 * 2 * 96000, pixel_rate); - else - pixel_rate = max(2 * 96000, pixel_rate); + if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) + min_cdclk = max(2 * 96000, min_cdclk); + + if (min_cdclk > dev_priv->max_cdclk_freq) { + DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", + min_cdclk, dev_priv->max_cdclk_freq); + return -EINVAL; } - return pixel_rate; + return min_cdclk; } -/* compute the max rate for new configuration */ -static int intel_max_pixel_rate(struct drm_atomic_state *state) +static int intel_compute_min_cdclk(struct drm_atomic_state *state) { struct intel_atomic_state *intel_state = to_intel_atomic_state(state); struct drm_i915_private *dev_priv = to_i915(state->dev); - struct drm_crtc *crtc; - struct drm_crtc_state *cstate; + struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; - unsigned int max_pixel_rate = 0, i; + int min_cdclk, i; enum pipe pipe; - memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, - sizeof(intel_state->min_pixclk)); + memcpy(intel_state->min_cdclk, dev_priv->min_cdclk, + sizeof(intel_state->min_cdclk)); - for_each_new_crtc_in_state(state, crtc, cstate, i) { - int pixel_rate; + for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { + min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); + if (min_cdclk < 0) + return min_cdclk; - crtc_state = to_intel_crtc_state(cstate); - if (!crtc_state->base.enable) { - intel_state->min_pixclk[i] = 0; - continue; - } - - pixel_rate = crtc_state->pixel_rate; - - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) - pixel_rate = - bdw_adjust_min_pipe_pixel_rate(crtc_state, - pixel_rate); - - intel_state->min_pixclk[i] = pixel_rate; + intel_state->min_cdclk[i] = min_cdclk; } + min_cdclk = 0; for_each_pipe(dev_priv, pipe) - max_pixel_rate = max(intel_state->min_pixclk[pipe], - max_pixel_rate); + min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk); - return max_pixel_rate; + return min_cdclk; } static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); - int max_pixclk = intel_max_pixel_rate(state); - struct intel_atomic_state *intel_state = - to_intel_atomic_state(state); - int cdclk; + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + int min_cdclk, cdclk; - cdclk = vlv_calc_cdclk(dev_priv, max_pixclk); + min_cdclk = intel_compute_min_cdclk(state); + if (min_cdclk < 0) + return min_cdclk; - if (cdclk > dev_priv->max_cdclk_freq) { - DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", - cdclk, dev_priv->max_cdclk_freq); - return -EINVAL; - } + cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); intel_state->cdclk.logical.cdclk = cdclk; @@ -1847,22 +1853,18 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->dev); struct intel_atomic_state *intel_state = to_intel_atomic_state(state); - int max_pixclk = intel_max_pixel_rate(state); - int cdclk; + int min_cdclk, cdclk; + + min_cdclk = intel_compute_min_cdclk(state); + if (min_cdclk < 0) + return min_cdclk; /* * FIXME should also account for plane ratio * once 64bpp pixel formats are supported. */ - cdclk = bdw_calc_cdclk(max_pixclk); - - if (cdclk > dev_priv->max_cdclk_freq) { - DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", - cdclk, dev_priv->max_cdclk_freq); - return -EINVAL; - } + cdclk = bdw_calc_cdclk(min_cdclk); intel_state->cdclk.logical.cdclk = cdclk; @@ -1880,10 +1882,13 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) { - struct intel_atomic_state *intel_state = to_intel_atomic_state(state); struct drm_i915_private *dev_priv = to_i915(state->dev); - const int max_pixclk = intel_max_pixel_rate(state); - int cdclk, vco; + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + int min_cdclk, cdclk, vco; + + min_cdclk = intel_compute_min_cdclk(state); + if (min_cdclk < 0) + return min_cdclk; vco = intel_state->cdclk.logical.vco; if (!vco) @@ -1893,13 +1898,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) * FIXME should also account for plane ratio * once 64bpp pixel formats are supported. */ - cdclk = skl_calc_cdclk(max_pixclk, vco); - - if (cdclk > dev_priv->max_cdclk_freq) { - DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", - cdclk, dev_priv->max_cdclk_freq); - return -EINVAL; - } + cdclk = skl_calc_cdclk(min_cdclk, vco); intel_state->cdclk.logical.vco = vco; intel_state->cdclk.logical.cdclk = cdclk; @@ -1920,25 +1919,21 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); - int max_pixclk = intel_max_pixel_rate(state); - struct intel_atomic_state *intel_state = - to_intel_atomic_state(state); - int cdclk, vco; + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + int min_cdclk, cdclk, vco; + + min_cdclk = intel_compute_min_cdclk(state); + if (min_cdclk < 0) + return min_cdclk; if (IS_GEMINILAKE(dev_priv)) { - cdclk = glk_calc_cdclk(max_pixclk); + cdclk = glk_calc_cdclk(min_cdclk); vco = glk_de_pll_vco(dev_priv, cdclk); } else { - cdclk = bxt_calc_cdclk(max_pixclk); + cdclk = bxt_calc_cdclk(min_cdclk); vco = bxt_de_pll_vco(dev_priv, cdclk); } - if (cdclk > dev_priv->max_cdclk_freq) { - DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", - cdclk, dev_priv->max_cdclk_freq); - return -EINVAL; - } - intel_state->cdclk.logical.vco = vco; intel_state->cdclk.logical.cdclk = cdclk; @@ -1964,19 +1959,15 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); - struct intel_atomic_state *intel_state = - to_intel_atomic_state(state); - int max_pixclk = intel_max_pixel_rate(state); - int cdclk, vco; + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + int min_cdclk, cdclk, vco; - cdclk = cnl_calc_cdclk(max_pixclk); - vco = cnl_cdclk_pll_vco(dev_priv, cdclk); + min_cdclk = intel_compute_min_cdclk(state); + if (min_cdclk < 0) + return min_cdclk; - if (cdclk > dev_priv->max_cdclk_freq) { - DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", - cdclk, dev_priv->max_cdclk_freq); - return -EINVAL; - } + cdclk = cnl_calc_cdclk(min_cdclk); + vco = cnl_cdclk_pll_vco(dev_priv, cdclk); intel_state->cdclk.logical.vco = vco; intel_state->cdclk.logical.cdclk = cdclk; @@ -1999,14 +1990,21 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) { int max_cdclk_freq = dev_priv->max_cdclk_freq; - if (IS_GEMINILAKE(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + /* + * FIXME: Allow '2 * max_cdclk_freq' + * once DDI clock voltage requirements are + * handled correctly. + */ + return max_cdclk_freq; + else if (IS_GEMINILAKE(dev_priv)) /* * FIXME: Limiting to 99% as a temporary workaround. See - * glk_calc_cdclk() for details. + * intel_min_cdclk() for details. */ return 2 * max_cdclk_freq * 99 / 100; - else if (INTEL_INFO(dev_priv)->gen >= 9 || - IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) + else if (IS_GEN9(dev_priv) || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return max_cdclk_freq; else if (IS_CHERRYVIEW(dev_priv)) return max_cdclk_freq*95/100; diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 1813d84989c9..ff9ecd211abb 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -41,6 +41,22 @@ #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256) +/* Post offset values for RGB->YCBCR conversion */ +#define POSTOFF_RGB_TO_YUV_HI 0x800 +#define POSTOFF_RGB_TO_YUV_ME 0x100 +#define POSTOFF_RGB_TO_YUV_LO 0x800 + +/* + * These values are direct register values specified in the Bspec, + * for RGB->YUV conversion matrix (colorspace BT709) + */ +#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8 +#define CSC_RGB_TO_YUV_BU 0x37e80000 +#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0 +#define CSC_RGB_TO_YUV_BY 0xb5280000 +#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 +#define CSC_RGB_TO_YUV_BV 0x1e080000 + /* * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point * format). This macro takes the coefficient we want transformed and the @@ -91,6 +107,30 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input) } } +static void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc) +{ + int pipe = intel_crtc->pipe; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + + I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); + I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); + I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); + + I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU); + I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU); + + I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY); + I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY); + + I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV); + I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV); + + I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI); + I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME); + I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO); + I915_WRITE(PIPE_CSC_MODE(pipe), 0); +} + /* Set up the pipe CSC unit. */ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) { @@ -101,7 +141,10 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) uint16_t coeffs[9] = { 0, }; struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state); - if (crtc_state->ctm) { + if (intel_crtc_state->ycbcr420) { + i9xx_load_ycbcr_conversion_matrix(intel_crtc); + return; + } else if (crtc_state->ctm) { struct drm_color_ctm *ctm = (struct drm_color_ctm *)crtc_state->ctm->data; uint64_t input[9] = { 0, }; diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 70e0ff41070c..a77dd80a97f2 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -143,7 +143,7 @@ static void hsw_crt_get_config(struct intel_encoder *encoder, /* Note: The caller is required to filter out dpms modes not supported by the * platform. */ static void intel_crt_set_dpms(struct intel_encoder *encoder, - struct intel_crtc_state *crtc_state, + const struct intel_crtc_state *crtc_state, int mode) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -194,28 +194,28 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, } static void intel_disable_crt(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); } static void pch_disable_crt(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { } static void pch_post_disable_crt(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { intel_disable_crt(encoder, old_crtc_state, old_conn_state); } static void hsw_post_disable_crt(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -228,8 +228,8 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder, } static void intel_enable_crt(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON); } diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f4fbb396054b..1da3bb2cc4b4 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -588,6 +588,67 @@ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) } } +static const struct cnl_ddi_buf_trans * +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) +{ + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + + if (voltage == VOLTAGE_INFO_0_85V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); + return cnl_ddi_translations_hdmi_0_85V; + } else if (voltage == VOLTAGE_INFO_0_95V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); + return cnl_ddi_translations_hdmi_0_95V; + } else if (voltage == VOLTAGE_INFO_1_05V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); + return cnl_ddi_translations_hdmi_1_05V; + } else + MISSING_CASE(voltage); + return NULL; +} + +static const struct cnl_ddi_buf_trans * +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) +{ + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + + if (voltage == VOLTAGE_INFO_0_85V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); + return cnl_ddi_translations_dp_0_85V; + } else if (voltage == VOLTAGE_INFO_0_95V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); + return cnl_ddi_translations_dp_0_95V; + } else if (voltage == VOLTAGE_INFO_1_05V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); + return cnl_ddi_translations_dp_1_05V; + } else + MISSING_CASE(voltage); + return NULL; +} + +static const struct cnl_ddi_buf_trans * +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) +{ + u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + + if (dev_priv->vbt.edp.low_vswing) { + if (voltage == VOLTAGE_INFO_0_85V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); + return cnl_ddi_translations_edp_0_85V; + } else if (voltage == VOLTAGE_INFO_0_95V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); + return cnl_ddi_translations_edp_0_95V; + } else if (voltage == VOLTAGE_INFO_1_05V) { + *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); + return cnl_ddi_translations_edp_1_05V; + } else + MISSING_CASE(voltage); + return NULL; + } else { + return cnl_get_buf_trans_dp(dev_priv, n_entries); + } +} + static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) { int n_hdmi_entries; @@ -599,7 +660,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por if (IS_GEN9_LP(dev_priv)) return hdmi_level; - if (IS_GEN9_BC(dev_priv)) { + if (IS_CANNONLAKE(dev_priv)) { + cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); + hdmi_default_entry = n_hdmi_entries - 1; + } else if (IS_GEN9_BC(dev_priv)) { skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); hdmi_default_entry = 8; } else if (IS_BROADWELL(dev_priv)) { @@ -688,9 +752,6 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) enum port port = intel_ddi_get_encoder_port(encoder); const struct ddi_buf_trans *ddi_translations; - if (IS_GEN9_LP(dev_priv)) - return; - switch (encoder->type) { case INTEL_OUTPUT_EDP: ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, @@ -741,9 +802,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder) enum port port = intel_ddi_get_encoder_port(encoder); const struct ddi_buf_trans *ddi_translations_hdmi; - if (IS_GEN9_LP(dev_priv)) - return; - hdmi_level = intel_ddi_hdmi_level(dev_priv, port); if (IS_GEN9_BC(dev_priv)) { @@ -785,7 +843,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); } -static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) +static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) { switch (pll->id) { case DPLL_ID_WRPLL1: @@ -1174,6 +1232,9 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) else dotclock = pipe_config->port_clock; + if (pipe_config->ycbcr420) + dotclock *= 2; + if (pipe_config->pixel_multiplier) dotclock /= pipe_config->pixel_multiplier; @@ -1818,10 +1879,17 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int n_entries; - if (encoder->type == INTEL_OUTPUT_EDP) - intel_ddi_get_buf_trans_edp(dev_priv, &n_entries); - else - intel_ddi_get_buf_trans_dp(dev_priv, &n_entries); + if (IS_CANNONLAKE(dev_priv)) { + if (encoder->type == INTEL_OUTPUT_EDP) + cnl_get_buf_trans_edp(dev_priv, &n_entries); + else + cnl_get_buf_trans_dp(dev_priv, &n_entries); + } else { + if (encoder->type == INTEL_OUTPUT_EDP) + intel_ddi_get_buf_trans_edp(dev_priv, &n_entries); + else + intel_ddi_get_buf_trans_dp(dev_priv, &n_entries); + } if (WARN_ON(n_entries < 1)) n_entries = 1; @@ -1832,90 +1900,23 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) DP_TRAIN_VOLTAGE_SWING_MASK; } -static const struct cnl_ddi_buf_trans * -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, - u32 voltage, int *n_entries) -{ - if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); - return cnl_ddi_translations_hdmi_0_85V; - } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); - return cnl_ddi_translations_hdmi_0_95V; - } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); - return cnl_ddi_translations_hdmi_1_05V; - } - return NULL; -} - -static const struct cnl_ddi_buf_trans * -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, - u32 voltage, int *n_entries) -{ - if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); - return cnl_ddi_translations_dp_0_85V; - } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); - return cnl_ddi_translations_dp_0_95V; - } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); - return cnl_ddi_translations_dp_1_05V; - } - return NULL; -} - -static const struct cnl_ddi_buf_trans * -cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, - u32 voltage, int *n_entries) -{ - if (dev_priv->vbt.edp.low_vswing) { - if (voltage == VOLTAGE_INFO_0_85V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); - return cnl_ddi_translations_dp_0_85V; - } else if (voltage == VOLTAGE_INFO_0_95V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); - return cnl_ddi_translations_edp_0_95V; - } else if (voltage == VOLTAGE_INFO_1_05V) { - *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); - return cnl_ddi_translations_edp_1_05V; - } - return NULL; - } else { - return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries); - } -} - static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, u32 level, enum port port, int type) { const struct cnl_ddi_buf_trans *ddi_translations = NULL; - u32 n_entries, val, voltage; + u32 n_entries, val; int ln; - /* - * Values for each port type are listed in - * voltage swing programming tables. - * Vccio voltage found in PORT_COMP_DW3. - */ - voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; - if (type == INTEL_OUTPUT_HDMI) { - ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, - voltage, &n_entries); + ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); } else if (type == INTEL_OUTPUT_DP) { - ddi_translations = cnl_get_buf_trans_dp(dev_priv, - voltage, &n_entries); + ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); } else if (type == INTEL_OUTPUT_EDP) { - ddi_translations = cnl_get_buf_trans_edp(dev_priv, - voltage, &n_entries); + ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); } - if (ddi_translations == NULL) { - MISSING_CASE(voltage); + if (WARN_ON(ddi_translations == NULL)) return; - } if (level >= n_entries) { DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); @@ -2051,33 +2052,46 @@ static uint32_t translate_signal_level(int signal_levels) return 0; } -uint32_t ddi_signal_levels(struct intel_dp *intel_dp) +static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp) { - struct intel_digital_port *dport = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); - struct intel_encoder *encoder = &dport->base; uint8_t train_set = intel_dp->train_set[0]; int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); + + return translate_signal_level(signal_levels); +} + +u32 bxt_signal_levels(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); + struct intel_encoder *encoder = &dport->base; enum port port = dport->port; - uint32_t level; + u32 level = intel_ddi_dp_level(intel_dp); + + if (IS_CANNONLAKE(dev_priv)) + cnl_ddi_vswing_sequence(encoder, level); + else + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); - level = translate_signal_level(signal_levels); + return 0; +} + +uint32_t ddi_signal_levels(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); + struct intel_encoder *encoder = &dport->base; + uint32_t level = intel_ddi_dp_level(intel_dp); if (IS_GEN9_BC(dev_priv)) - skl_ddi_set_iboost(encoder, level); - else if (IS_GEN9_LP(dev_priv)) - bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); - else if (IS_CANNONLAKE(dev_priv)) { - cnl_ddi_vswing_sequence(encoder, level); - /* DDI_BUF_CTL bits 27:24 are reserved on CNL */ - return 0; - } + skl_ddi_set_iboost(encoder, level); + return DDI_BUF_TRANS_SELECT(level); } static void intel_ddi_clk_select(struct intel_encoder *encoder, - struct intel_shared_dpll *pll) + const struct intel_shared_dpll *pll) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = intel_ddi_get_encoder_port(encoder); @@ -2126,6 +2140,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = intel_ddi_get_encoder_port(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); + uint32_t level = intel_ddi_dp_level(intel_dp); WARN_ON(link_mst && (port == PORT_A || port == PORT_E)); @@ -2138,7 +2153,13 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); - intel_prepare_dp_ddi_buffers(encoder); + if (IS_CANNONLAKE(dev_priv)) + cnl_ddi_vswing_sequence(encoder, level); + else if (IS_GEN9_LP(dev_priv)) + bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); + else + intel_prepare_dp_ddi_buffers(encoder); + intel_ddi_init_dp_buf_reg(encoder); intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_start_link_train(intel_dp); @@ -2147,14 +2168,14 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, } static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, - bool has_hdmi_sink, + bool has_infoframe, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, - struct intel_shared_dpll *pll) + const struct intel_shared_dpll *pll) { - struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); + struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct drm_encoder *drm_encoder = &encoder->base; enum port port = intel_ddi_get_encoder_port(encoder); int level = intel_ddi_hdmi_level(dev_priv, port); struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); @@ -2164,23 +2185,25 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); - intel_prepare_hdmi_ddi_buffers(encoder); - if (IS_GEN9_BC(dev_priv)) - skl_ddi_set_iboost(encoder, level); + if (IS_CANNONLAKE(dev_priv)) + cnl_ddi_vswing_sequence(encoder, level); else if (IS_GEN9_LP(dev_priv)) bxt_ddi_vswing_sequence(dev_priv, level, port, INTEL_OUTPUT_HDMI); - else if (IS_CANNONLAKE(dev_priv)) - cnl_ddi_vswing_sequence(encoder, level); + else + intel_prepare_hdmi_ddi_buffers(encoder); + + if (IS_GEN9_BC(dev_priv)) + skl_ddi_set_iboost(encoder, level); - intel_hdmi->set_infoframes(drm_encoder, - has_hdmi_sink, - crtc_state, conn_state); + intel_dig_port->set_infoframes(&encoder->base, + has_infoframe, + crtc_state, conn_state); } static void intel_ddi_pre_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { int type = encoder->type; @@ -2194,21 +2217,20 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder, } if (type == INTEL_OUTPUT_HDMI) { intel_ddi_pre_enable_hdmi(encoder, - pipe_config->has_hdmi_sink, + pipe_config->has_infoframe, pipe_config, conn_state, pipe_config->shared_dpll); } } static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_encoder *encoder = &intel_encoder->base; struct drm_i915_private *dev_priv = to_i915(encoder->dev); enum port port = intel_ddi_get_encoder_port(intel_encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct intel_dp *intel_dp = NULL; int type = intel_encoder->type; uint32_t val; bool wait = false; @@ -2216,7 +2238,8 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, /* old_crtc_state and old_conn_state are NULL when called from DP_MST */ if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { - intel_dp = enc_to_intel_dp(encoder); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); } @@ -2235,7 +2258,14 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, if (wait) intel_wait_ddi_buf_idle(dev_priv, port); - if (intel_dp) { + if (type == INTEL_OUTPUT_HDMI) { + dig_port->set_infoframes(encoder, false, + old_crtc_state, old_conn_state); + } + + if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + intel_edp_panel_vdd_on(intel_dp); intel_edp_panel_off(intel_dp); } @@ -2260,8 +2290,8 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, } void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); uint32_t val; @@ -2293,8 +2323,8 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, } static void intel_enable_ddi(struct intel_encoder *intel_encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_encoder *encoder = &intel_encoder->base; struct drm_i915_private *dev_priv = to_i915(encoder->dev); @@ -2325,7 +2355,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, intel_dp_stop_link_train(intel_dp); intel_edp_backlight_on(pipe_config, conn_state); - intel_psr_enable(intel_dp); + intel_psr_enable(intel_dp, pipe_config); intel_edp_drrs_enable(intel_dp, pipe_config); } @@ -2334,8 +2364,8 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, } static void intel_disable_ddi(struct intel_encoder *intel_encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_encoder *encoder = &intel_encoder->base; int type = intel_encoder->type; @@ -2353,14 +2383,14 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_edp_drrs_disable(intel_dp, old_crtc_state); - intel_psr_disable(intel_dp); + intel_psr_disable(intel_dp, old_crtc_state); intel_edp_backlight_off(old_conn_state); } } static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { uint8_t mask = pipe_config->lane_lat_optim_mask; @@ -2432,7 +2462,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; - struct intel_hdmi *intel_hdmi; + struct intel_digital_port *intel_dig_port; u32 temp, flags = 0; /* XXX: DSI transcoder paranoia */ @@ -2471,9 +2501,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, switch (temp & TRANS_DDI_MODE_SELECT_MASK) { case TRANS_DDI_MODE_SELECT_HDMI: pipe_config->has_hdmi_sink = true; - intel_hdmi = enc_to_intel_hdmi(&encoder->base); + intel_dig_port = enc_to_dig_port(&encoder->base); - if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) + if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) pipe_config->has_infoframe = true; if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) == @@ -2726,6 +2756,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); intel_encoder->cloneable = 0; + intel_infoframe_init(intel_dig_port); + if (init_dp) { if (!intel_ddi_init_dp_connector(intel_dig_port)) goto err; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 5f91ddc78c7a..b17f7045c8f8 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -412,7 +412,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) else if (INTEL_INFO(dev_priv)->gen >= 9) gen9_sseu_info_init(dev_priv); - info->has_snoop = !info->has_llc; + WARN_ON(info->has_snoop != !info->has_llc); DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask); DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask)); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3f505682963f..f780f39e0758 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -49,11 +49,6 @@ #include <linux/dma_remapping.h> #include <linux/reservation.h> -static bool is_mmio_work(struct intel_flip_work *work) -{ - return work->mmio_work.func; -} - /* Primary plane formats for gen <= 3 */ static const uint32_t i8xx_primary_formats[] = { DRM_FORMAT_C8, @@ -72,6 +67,12 @@ static const uint32_t i965_primary_formats[] = { DRM_FORMAT_XBGR2101010, }; +static const uint64_t i9xx_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint32_t skl_primary_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, @@ -87,11 +88,34 @@ static const uint32_t skl_primary_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_format_modifiers_noccs[] = { + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + +static const uint64_t skl_format_modifiers_ccs[] = { + I915_FORMAT_MOD_Yf_TILED_CCS, + I915_FORMAT_MOD_Y_TILED_CCS, + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + /* Cursor formats */ static const uint32_t intel_cursor_formats[] = { DRM_FORMAT_ARGB8888, }; +static const uint64_t cursor_format_modifiers[] = { + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static void i9xx_crtc_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); static void ironlake_pch_clock_get(struct intel_crtc *crtc, @@ -1777,7 +1801,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); - assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); + assert_fdi_rx_enabled(dev_priv, PIPE_A); /* Workaround: set timing override bit. */ val = I915_READ(TRANS_CHICKEN2(PIPE_A)); @@ -1853,16 +1877,16 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); } -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); WARN_ON(!crtc->config->has_pch_encoder); if (HAS_PCH_LPT(dev_priv)) - return TRANSCODER_A; + return PIPE_A; else - return (enum transcoder) crtc->pipe; + return crtc->pipe; } /** @@ -1901,7 +1925,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) if (crtc->config->has_pch_encoder) { /* if driving the PCH, we need FDI enabled */ assert_fdi_rx_pll_enabled(dev_priv, - (enum pipe) intel_crtc_pch_transcoder(crtc)); + intel_crtc_pch_transcoder(crtc)); assert_fdi_tx_pll_enabled(dev_priv, (enum pipe) cpu_transcoder); } @@ -1999,11 +2023,19 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) return 128; else return 512; + case I915_FORMAT_MOD_Y_TILED_CCS: + if (plane == 1) + return 128; + /* fall through */ case I915_FORMAT_MOD_Y_TILED: if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) return 128; else return 512; + case I915_FORMAT_MOD_Yf_TILED_CCS: + if (plane == 1) + return 128; + /* fall through */ case I915_FORMAT_MOD_Yf_TILED: switch (cpp) { case 1: @@ -2110,7 +2142,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, struct drm_i915_private *dev_priv = to_i915(fb->dev); /* AUX_DIST needs only 4K alignment */ - if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) + if (plane == 1) return 4096; switch (fb->modifier) { @@ -2120,6 +2152,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, if (INTEL_GEN(dev_priv) >= 9) return 256 * 1024; return 0; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: return 1 * 1024 * 1024; @@ -2162,6 +2196,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) */ intel_runtime_pm_get(dev_priv); + atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); if (IS_ERR(vma)) goto err; @@ -2189,6 +2225,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) i915_vma_get(vma); err: + atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + intel_runtime_pm_put(dev_priv); return vma; } @@ -2250,17 +2288,13 @@ void intel_add_fb_offsets(int *x, int *y, } } -/* - * Input tile dimensions and pitch must already be - * rotated to match x and y, and in pixel units. - */ -static u32 _intel_adjust_tile_offset(int *x, int *y, - unsigned int tile_width, - unsigned int tile_height, - unsigned int tile_size, - unsigned int pitch_tiles, - u32 old_offset, - u32 new_offset) +static u32 __intel_adjust_tile_offset(int *x, int *y, + unsigned int tile_width, + unsigned int tile_height, + unsigned int tile_size, + unsigned int pitch_tiles, + u32 old_offset, + u32 new_offset) { unsigned int pitch_pixels = pitch_tiles * tile_width; unsigned int tiles; @@ -2281,18 +2315,13 @@ static u32 _intel_adjust_tile_offset(int *x, int *y, return new_offset; } -/* - * Adjust the tile offset by moving the difference into - * the x/y offsets. - */ -static u32 intel_adjust_tile_offset(int *x, int *y, - const struct intel_plane_state *state, int plane, - u32 old_offset, u32 new_offset) +static u32 _intel_adjust_tile_offset(int *x, int *y, + const struct drm_framebuffer *fb, int plane, + unsigned int rotation, + u32 old_offset, u32 new_offset) { - const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); - const struct drm_framebuffer *fb = state->base.fb; + const struct drm_i915_private *dev_priv = to_i915(fb->dev); unsigned int cpp = fb->format->cpp[plane]; - unsigned int rotation = state->base.rotation; unsigned int pitch = intel_fb_pitch(fb, plane, rotation); WARN_ON(new_offset > old_offset); @@ -2311,9 +2340,9 @@ static u32 intel_adjust_tile_offset(int *x, int *y, pitch_tiles = pitch / (tile_width * cpp); } - _intel_adjust_tile_offset(x, y, tile_width, tile_height, - tile_size, pitch_tiles, - old_offset, new_offset); + __intel_adjust_tile_offset(x, y, tile_width, tile_height, + tile_size, pitch_tiles, + old_offset, new_offset); } else { old_offset += *y * pitch + *x * cpp; @@ -2325,6 +2354,19 @@ static u32 intel_adjust_tile_offset(int *x, int *y, } /* + * Adjust the tile offset by moving the difference into + * the x/y offsets. + */ +static u32 intel_adjust_tile_offset(int *x, int *y, + const struct intel_plane_state *state, int plane, + u32 old_offset, u32 new_offset) +{ + return _intel_adjust_tile_offset(x, y, state->base.fb, plane, + state->base.rotation, + old_offset, new_offset); +} + +/* * Computes the linear offset to the base tile and adjusts * x, y. bytes per pixel is assumed to be a power-of-two. * @@ -2375,9 +2417,9 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, offset = (tile_rows * pitch_tiles + tiles) * tile_size; offset_aligned = offset & ~alignment; - _intel_adjust_tile_offset(x, y, tile_width, tile_height, - tile_size, pitch_tiles, - offset, offset_aligned); + __intel_adjust_tile_offset(x, y, tile_width, tile_height, + tile_size, pitch_tiles, + offset, offset_aligned); } else { offset = *y * pitch + *x * cpp; offset_aligned = offset & ~alignment; @@ -2409,16 +2451,24 @@ u32 intel_compute_tile_offset(int *x, int *y, rotation, alignment); } -/* Convert the fb->offset[] linear offset into x/y offsets */ -static void intel_fb_offset_to_xy(int *x, int *y, - const struct drm_framebuffer *fb, int plane) +/* Convert the fb->offset[] into x/y offsets */ +static int intel_fb_offset_to_xy(int *x, int *y, + const struct drm_framebuffer *fb, int plane) { - unsigned int cpp = fb->format->cpp[plane]; - unsigned int pitch = fb->pitches[plane]; - u32 linear_offset = fb->offsets[plane]; + struct drm_i915_private *dev_priv = to_i915(fb->dev); - *y = linear_offset / pitch; - *x = linear_offset % pitch / cpp; + if (fb->modifier != DRM_FORMAT_MOD_LINEAR && + fb->offsets[plane] % intel_tile_size(dev_priv)) + return -EINVAL; + + *x = 0; + *y = 0; + + _intel_adjust_tile_offset(x, y, + fb, plane, DRM_MODE_ROTATE_0, + fb->offsets[plane], 0); + + return 0; } static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) @@ -2427,12 +2477,48 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) case I915_FORMAT_MOD_X_TILED: return I915_TILING_X; case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: return I915_TILING_Y; default: return I915_TILING_NONE; } } +static const struct drm_format_info ccs_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, +}; + +static const struct drm_format_info * +lookup_format_info(const struct drm_format_info formats[], + int num_formats, u32 format) +{ + int i; + + for (i = 0; i < num_formats; i++) { + if (formats[i].format == format) + return &formats[i]; + } + + return NULL; +} + +static const struct drm_format_info * +intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + switch (cmd->modifier[0]) { + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + return lookup_format_info(ccs_formats, + ARRAY_SIZE(ccs_formats), + cmd->pixel_format); + default: + return NULL; + } +} + static int intel_fill_fb_info(struct drm_i915_private *dev_priv, struct drm_framebuffer *fb) @@ -2449,12 +2535,50 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, unsigned int cpp, size; u32 offset; int x, y; + int ret; cpp = fb->format->cpp[i]; width = drm_framebuffer_plane_width(fb->width, fb, i); height = drm_framebuffer_plane_height(fb->height, fb, i); - intel_fb_offset_to_xy(&x, &y, fb, i); + ret = intel_fb_offset_to_xy(&x, &y, fb, i); + if (ret) { + DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", + i, fb->offsets[i]); + return ret; + } + + if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int tile_width, tile_height; + int main_x, main_y; + int ccs_x, ccs_y; + + intel_tile_dims(fb, i, &tile_width, &tile_height); + tile_width *= hsub; + tile_height *= vsub; + + ccs_x = (x * hsub) % tile_width; + ccs_y = (y * vsub) % tile_height; + main_x = intel_fb->normal[0].x % tile_width; + main_y = intel_fb->normal[0].y % tile_height; + + /* + * CCS doesn't have its own x/y offset register, so the intra CCS tile + * x/y offsets must match between CCS and the main surface. + */ + if (main_x != ccs_x || main_y != ccs_y) { + DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", + main_x, main_y, + ccs_x, ccs_y, + intel_fb->normal[0].x, + intel_fb->normal[0].y, + x, y); + return -EINVAL; + } + } /* * The fence (if used) is aligned to the start of the object @@ -2465,7 +2589,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, * fb layout agrees with the fence layout. We already check that the * fb stride matches the fence stride elsewhere. */ - if (i915_gem_object_is_tiled(intel_fb->obj) && + if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) && (x + width) * cpp > fb->pitches[i]) { DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", i, fb->offsets[i]); @@ -2528,10 +2652,10 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, * We only keep the x/y offsets, so push all of the * gtt offset into the x/y offsets. */ - _intel_adjust_tile_offset(&x, &y, - tile_width, tile_height, - tile_size, pitch_tiles, - gtt_offset_rotated * tile_size, 0); + __intel_adjust_tile_offset(&x, &y, + tile_width, tile_height, + tile_size, pitch_tiles, + gtt_offset_rotated * tile_size, 0); gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; @@ -2664,20 +2788,6 @@ out_unref_obj: return false; } -/* Update plane->state->fb to match plane->fb after driver-internal updates */ -static void -update_state_fb(struct drm_plane *plane) -{ - if (plane->fb == plane->state->fb) - return; - - if (plane->state->fb) - drm_framebuffer_unreference(plane->state->fb); - plane->state->fb = plane->fb; - if (plane->state->fb) - drm_framebuffer_reference(plane->state->fb); -} - static void intel_set_plane_visible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state, @@ -2830,6 +2940,9 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, break; } break; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + /* FIXME AUX plane? */ case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: switch (cpp) { @@ -2852,6 +2965,44 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, return 2048; } +static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, + int main_x, int main_y, u32 main_offset) +{ + const struct drm_framebuffer *fb = plane_state->base.fb; + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int aux_x = plane_state->aux.x; + int aux_y = plane_state->aux.y; + u32 aux_offset = plane_state->aux.offset; + u32 alignment = intel_surf_alignment(fb, 1); + + while (aux_offset >= main_offset && aux_y <= main_y) { + int x, y; + + if (aux_x == main_x && aux_y == main_y) + break; + + if (aux_offset == 0) + break; + + x = aux_x / hsub; + y = aux_y / vsub; + aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, + aux_offset, aux_offset - alignment); + aux_x = x * hsub + aux_x % hsub; + aux_y = y * vsub + aux_y % vsub; + } + + if (aux_x != main_x || aux_y != main_y) + return false; + + plane_state->aux.offset = aux_offset; + plane_state->aux.x = aux_x; + plane_state->aux.y = aux_y; + + return true; +} + static int skl_check_main_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->base.fb; @@ -2894,7 +3045,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) while ((x + w) * cpp > fb->pitches[0]) { if (offset == 0) { - DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); return -EINVAL; } @@ -2903,6 +3054,26 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) } } + /* + * CCS AUX surface doesn't have its own x/y offsets, we must make sure + * they match with the main surface x/y offsets. + */ + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { + while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { + if (offset == 0) + break; + + offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, + offset, offset - alignment); + } + + if (x != plane_state->aux.x || y != plane_state->aux.y) { + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); + return -EINVAL; + } + } + plane_state->main.offset = offset; plane_state->main.x = x; plane_state->main.y = y; @@ -2939,6 +3110,49 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) return 0; } +static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->base.plane); + struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); + const struct drm_framebuffer *fb = plane_state->base.fb; + int src_x = plane_state->base.src.x1 >> 16; + int src_y = plane_state->base.src.y1 >> 16; + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int x = src_x / hsub; + int y = src_y / vsub; + u32 offset; + + switch (plane->id) { + case PLANE_PRIMARY: + case PLANE_SPRITE0: + break; + default: + DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); + return -EINVAL; + } + + if (crtc->pipe == PIPE_C) { + DRM_DEBUG_KMS("No RC support on pipe C\n"); + return -EINVAL; + } + + if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { + DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", + plane_state->base.rotation); + return -EINVAL; + } + + intel_add_fb_offsets(&x, &y, plane_state, 1); + offset = intel_compute_tile_offset(&x, &y, plane_state, 1); + + plane_state->aux.offset = offset; + plane_state->aux.x = x * hsub + src_x % hsub; + plane_state->aux.y = y * vsub + src_y % vsub; + + return 0; +} + int skl_check_plane_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->base.fb; @@ -2962,6 +3176,11 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) ret = skl_check_nv12_aux_surface(plane_state); if (ret) return ret; + } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { + ret = skl_check_ccs_aux_surface(plane_state); + if (ret) + return ret; } else { plane_state->aux.offset = ~0xfff; plane_state->aux.x = 0; @@ -3268,8 +3487,12 @@ static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) return PLANE_CTL_TILED_X; case I915_FORMAT_MOD_Y_TILED: return PLANE_CTL_TILED_Y; + case I915_FORMAT_MOD_Y_TILED_CCS: + return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; case I915_FORMAT_MOD_Yf_TILED: return PLANE_CTL_TILED_YF; + case I915_FORMAT_MOD_Yf_TILED_CCS: + return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; default: MISSING_CASE(fb_modifier); } @@ -3342,6 +3565,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane, u32 plane_ctl = plane_state->ctl; unsigned int rotation = plane_state->base.rotation; u32 stride = skl_plane_stride(fb, 0, rotation); + u32 aux_stride = skl_plane_stride(fb, 1, rotation); u32 surf_addr = plane_state->main.offset; int scaler_id = plane_state->scaler_id; int src_x = plane_state->main.x; @@ -3378,6 +3602,10 @@ static void skylake_update_primary_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), + (plane_state->aux.offset - surf_addr) | aux_stride); + I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->aux.y << 16) | plane_state->aux.x); if (scaler_id >= 0) { uint32_t ps_ctrl = 0; @@ -3419,14 +3647,6 @@ static void skylake_disable_primary_plane(struct intel_plane *primary, spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -static void intel_complete_page_flips(struct drm_i915_private *dev_priv) -{ - struct intel_crtc *crtc; - - for_each_intel_crtc(&dev_priv->drm, crtc) - intel_finish_page_flip_cs(dev_priv, crtc->pipe); -} - static int __intel_display_resume(struct drm_device *dev, struct drm_atomic_state *state, @@ -3485,6 +3705,15 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) !gpu_reset_clobbers_display(dev_priv)) return; + /* We have a modeset vs reset deadlock, defensively unbreak it. */ + set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); + wake_up_all(&dev_priv->gpu_error.wait_queue); + + if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { + DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n"); + i915_gem_set_wedged(dev_priv); + } + /* * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. @@ -3535,21 +3764,14 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) if (!state) goto unlock; - /* - * Flips in the rings will be nuked by the reset, - * so complete all pending flips so that user space - * will get its events and not get stuck. - */ - intel_complete_page_flips(dev_priv); - dev_priv->modeset_restore_state = NULL; /* reset doesn't touch the display */ if (!gpu_reset_clobbers_display(dev_priv)) { /* for testing only restore the display */ ret = __intel_display_resume(dev, state, ctx); - if (ret) - DRM_ERROR("Restoring old state failed with %i\n", ret); + if (ret) + DRM_ERROR("Restoring old state failed with %i\n", ret); } else { /* * The display has been reset as well, @@ -3578,46 +3800,18 @@ unlock: drm_modeset_drop_locks(ctx); drm_modeset_acquire_fini(ctx); mutex_unlock(&dev->mode_config.mutex); -} - -static bool abort_flip_on_reset(struct intel_crtc *crtc) -{ - struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; - - if (i915_reset_backoff(error)) - return true; - - if (crtc->reset_count != i915_reset_count(error)) - return true; - - return false; -} - -static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - bool pending; - - if (abort_flip_on_reset(intel_crtc)) - return false; - - spin_lock_irq(&dev->event_lock); - pending = to_intel_crtc(crtc)->flip_work != NULL; - spin_unlock_irq(&dev->event_lock); - return pending; + clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); } -static void intel_update_pipe_config(struct intel_crtc *crtc, - struct intel_crtc_state *old_crtc_state) +static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_crtc_state *pipe_config = - to_intel_crtc_state(crtc->base.state); /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ - crtc->base.mode = crtc->base.state->mode; + crtc->base.mode = new_crtc_state->base.mode; /* * Update pipe size and adjust fitter if needed: the reason for this is @@ -3629,17 +3823,17 @@ static void intel_update_pipe_config(struct intel_crtc *crtc, */ I915_WRITE(PIPESRC(crtc->pipe), - ((pipe_config->pipe_src_w - 1) << 16) | - (pipe_config->pipe_src_h - 1)); + ((new_crtc_state->pipe_src_w - 1) << 16) | + (new_crtc_state->pipe_src_h - 1)); /* on skylake this is done by detaching scalers */ if (INTEL_GEN(dev_priv) >= 9) { skl_detach_scalers(crtc); - if (pipe_config->pch_pfit.enabled) + if (new_crtc_state->pch_pfit.enabled) skylake_pfit_enable(crtc); } else if (HAS_PCH_SPLIT(dev_priv)) { - if (pipe_config->pch_pfit.enabled) + if (new_crtc_state->pch_pfit.enabled) ironlake_pfit_enable(crtc); else if (old_crtc_state->pch_pfit.enabled) ironlake_pfit_disable(crtc, true); @@ -4163,21 +4357,22 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) { - struct intel_crtc *crtc; - - /* Note that we don't need to be called with mode_config.lock here - * as our list of CRTC objects is static for the lifetime of the - * device and so cannot disappear as we iterate. Similarly, we can - * happily treat the predicates as racy, atomic checks as userspace - * cannot claim and pin a new fb without at least acquring the - * struct_mutex and so serialising with us. - */ - for_each_intel_crtc(&dev_priv->drm, crtc) { - if (atomic_read(&crtc->unpin_work_count) == 0) + struct drm_crtc *crtc; + bool cleanup_done; + + drm_for_each_crtc(crtc, &dev_priv->drm) { + struct drm_crtc_commit *commit; + spin_lock(&crtc->commit_lock); + commit = list_first_entry_or_null(&crtc->commit_list, + struct drm_crtc_commit, commit_entry); + cleanup_done = commit ? + try_wait_for_completion(&commit->cleanup_done) : true; + spin_unlock(&crtc->commit_lock); + + if (cleanup_done) continue; - if (crtc->flip_work) - intel_wait_for_vblank(dev_priv, crtc->pipe); + drm_crtc_wait_one_vblank(crtc); return true; } @@ -4185,57 +4380,6 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) return false; } -static void page_flip_completed(struct intel_crtc *intel_crtc) -{ - struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - struct intel_flip_work *work = intel_crtc->flip_work; - - intel_crtc->flip_work = NULL; - - if (work->event) - drm_crtc_send_vblank_event(&intel_crtc->base, work->event); - - drm_crtc_vblank_put(&intel_crtc->base); - - wake_up_all(&dev_priv->pending_flip_queue); - trace_i915_flip_complete(intel_crtc->plane, - work->pending_flip_obj); - - queue_work(dev_priv->wq, &work->unpin_work); -} - -static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - long ret; - - WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); - - ret = wait_event_interruptible_timeout( - dev_priv->pending_flip_queue, - !intel_crtc_has_pending_flip(crtc), - 60*HZ); - - if (ret < 0) - return ret; - - if (ret == 0) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = intel_crtc->flip_work; - if (work && !is_mmio_work(work)) { - WARN_ONCE(1, "Removing stuck page flip\n"); - page_flip_completed(intel_crtc); - } - spin_unlock_irq(&dev->event_lock); - } - - return 0; -} - void lpt_disable_iclkip(struct drm_i915_private *dev_priv) { u32 temp; @@ -4555,7 +4699,7 @@ static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); + assert_pch_transcoder_disabled(dev_priv, PIPE_A); lpt_program_iclkip(crtc); @@ -4600,6 +4744,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, */ need_scaling = src_w != dst_w || src_h != dst_h; + if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) + need_scaling = true; + /* * Scaling/fitting not supported in IF-ID mode in GEN9+ * TODO: Interlace fetch mode doesn't support YUV420 planar formats. @@ -4970,7 +5117,8 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); struct drm_atomic_state *old_state = old_crtc_state->base.state; struct intel_crtc_state *pipe_config = - to_intel_crtc_state(crtc->base.state); + intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state), + crtc); struct drm_plane *primary = crtc->base.primary; struct drm_plane_state *old_pri_state = drm_atomic_get_existing_plane_state(old_state, primary); @@ -4982,7 +5130,8 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) if (old_pri_state) { struct intel_plane_state *primary_state = - to_intel_plane_state(primary->state); + intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), + to_intel_plane(primary)); struct intel_plane_state *old_primary_state = to_intel_plane_state(old_pri_state); @@ -5011,7 +5160,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, if (old_pri_state) { struct intel_plane_state *primary_state = - to_intel_plane_state(primary->state); + intel_atomic_get_new_plane_state(old_intel_state, + to_intel_plane(primary)); struct intel_plane_state *old_primary_state = to_intel_plane_state(old_pri_state); @@ -5323,8 +5473,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, return; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); @@ -5409,8 +5558,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, intel_wait_for_vblank(dev_priv, pipe); intel_wait_for_vblank(dev_priv, pipe); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } /* If we change the relative order between pipe/planes enabling, we need @@ -5507,8 +5655,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_disable(crtc, old_crtc_state, old_state); @@ -5536,8 +5683,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, intel_encoders_post_disable(crtc, old_crtc_state, old_state); if (old_crtc_state->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } static void i9xx_pfit_enable(struct intel_crtc *crtc) @@ -5846,8 +5992,6 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, return; if (crtc->primary->state->visible) { - WARN_ON(intel_crtc->flip_work); - intel_pre_disable_primary_noatomic(crtc); intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); @@ -5896,7 +6040,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, intel_crtc->enabled_power_domains = 0; dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); - dev_priv->min_pixclk[intel_crtc->pipe] = 0; + dev_priv->min_cdclk[intel_crtc->pipe] = 0; } /* @@ -6141,6 +6285,9 @@ retry: static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config) { + if (pipe_config->ips_force_disable) + return false; + if (pipe_config->pipe_bpp > 24) return false; @@ -6256,6 +6403,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, return -EINVAL; } + if (pipe_config->ycbcr420 && pipe_config->base.ctm) { + /* + * There is only one pipe CSC unit per pipe, and we need that + * for output conversion from RGB->YCBCR. So if CTM is already + * applied we can't support YCBCR420 output. + */ + DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); + return -EINVAL; + } + /* * Pipe horizontal size must be even in: * - DVO ganged mode @@ -8049,6 +8206,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_crtc_state *config = intel_crtc->config; if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { u32 val = 0; @@ -8074,6 +8232,12 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) if (intel_crtc->config->dither) val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; + if (config->ycbcr420) { + val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | + PIPEMISC_YUV420_ENABLE | + PIPEMISC_YUV420_MODE_FULL_BLEND; + } + I915_WRITE(PIPEMISC(intel_crtc->pipe), val); } } @@ -8401,10 +8565,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, fb->modifier = I915_FORMAT_MOD_X_TILED; break; case PLANE_CTL_TILED_Y: - fb->modifier = I915_FORMAT_MOD_Y_TILED; + if (val & PLANE_CTL_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; + else + fb->modifier = I915_FORMAT_MOD_Y_TILED; break; case PLANE_CTL_TILED_YF: - fb->modifier = I915_FORMAT_MOD_Yf_TILED; + if (val & PLANE_CTL_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; + else + fb->modifier = I915_FORMAT_MOD_Yf_TILED; break; default: MISSING_CASE(tiling); @@ -8638,7 +8808,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", pipe_name(crtc->pipe)); - I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); + I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), + "Display power well on\n"); I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); @@ -8873,7 +9044,7 @@ static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, u32 temp; temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - id = temp >> (port * 2); + id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) return; @@ -9108,12 +9279,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, u64 power_domain_mask; bool active; - if (INTEL_GEN(dev_priv) >= 9) { - intel_crtc_init_scalers(crtc, pipe_config); - - pipe_config->scaler_state.scaler_id = -1; - pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); - } + intel_crtc_init_scalers(crtc, pipe_config); power_domain = POWER_DOMAIN_PIPE(crtc->pipe); if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) @@ -9143,6 +9309,23 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; + if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) { + u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); + bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; + + if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) { + bool blend_mode_420 = tmp & + PIPEMISC_YUV420_MODE_FULL_BLEND; + + pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; + if (pipe_config->ycbcr420 != clrspace_yuv || + pipe_config->ycbcr420 != blend_mode_420) + DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); + } else if (clrspace_yuv) { + DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); + } + } + power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); @@ -9575,7 +9758,7 @@ static void i9xx_disable_cursor(struct intel_plane *plane, /* VESA 640x480x72Hz mode to set on the pipe */ -static struct drm_display_mode load_detect_mode = { +static const struct drm_display_mode load_detect_mode = { DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), }; @@ -9610,7 +9793,7 @@ intel_framebuffer_pitch_for_width(int width, int bpp) } static u32 -intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) +intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp) { u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); return PAGE_ALIGN(pitch * mode->vdisplay); @@ -9618,7 +9801,7 @@ intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) static struct drm_framebuffer * intel_framebuffer_create_for_mode(struct drm_device *dev, - struct drm_display_mode *mode, + const struct drm_display_mode *mode, int depth, int bpp) { struct drm_framebuffer *fb; @@ -9645,7 +9828,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev, static struct drm_framebuffer * mode_fits_in_fbdev(struct drm_device *dev, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { #ifdef CONFIG_DRM_FBDEV_EMULATION struct drm_i915_private *dev_priv = to_i915(dev); @@ -9678,7 +9861,7 @@ mode_fits_in_fbdev(struct drm_device *dev, static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, struct drm_crtc *crtc, - struct drm_display_mode *mode, + const struct drm_display_mode *mode, struct drm_framebuffer *fb, int x, int y) { @@ -9712,7 +9895,7 @@ static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, } int intel_get_load_detect_pipe(struct drm_connector *connector, - struct drm_display_mode *mode, + const struct drm_display_mode *mode, struct intel_load_detect_pipe *old, struct drm_modeset_acquire_ctx *ctx) { @@ -10120,849 +10303,11 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = intel_crtc->flip_work; - intel_crtc->flip_work = NULL; - spin_unlock_irq(&dev->event_lock); - - if (work) { - cancel_work_sync(&work->mmio_work); - cancel_work_sync(&work->unpin_work); - kfree(work); - } drm_crtc_cleanup(crtc); - kfree(intel_crtc); } -static void intel_unpin_work_fn(struct work_struct *__work) -{ - struct intel_flip_work *work = - container_of(__work, struct intel_flip_work, unpin_work); - struct intel_crtc *crtc = to_intel_crtc(work->crtc); - struct drm_device *dev = crtc->base.dev; - struct drm_plane *primary = crtc->base.primary; - - if (is_mmio_work(work)) - flush_work(&work->mmio_work); - - mutex_lock(&dev->struct_mutex); - intel_unpin_fb_vma(work->old_vma); - i915_gem_object_put(work->pending_flip_obj); - mutex_unlock(&dev->struct_mutex); - - i915_gem_request_put(work->flip_queued_req); - - intel_frontbuffer_flip_complete(to_i915(dev), - to_intel_plane(primary)->frontbuffer_bit); - intel_fbc_post_update(crtc); - drm_framebuffer_unreference(work->old_fb); - - BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); - atomic_dec(&crtc->unpin_work_count); - - kfree(work); -} - -/* Is 'a' after or equal to 'b'? */ -static bool g4x_flip_count_after_eq(u32 a, u32 b) -{ - return !((a - b) & 0x80000000); -} - -static bool __pageflip_finished_cs(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - - if (abort_flip_on_reset(crtc)) - return true; - - /* - * The relevant registers doen't exist on pre-ctg. - * As the flip done interrupt doesn't trigger for mmio - * flips on gmch platforms, a flip count check isn't - * really needed there. But since ctg has the registers, - * include it in the check anyway. - */ - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) - return true; - - /* - * BDW signals flip done immediately if the plane - * is disabled, even if the plane enable is already - * armed to occur at the next vblank :( - */ - - /* - * A DSPSURFLIVE check isn't enough in case the mmio and CS flips - * used the same base address. In that case the mmio flip might - * have completed, but the CS hasn't even executed the flip yet. - * - * A flip count check isn't enough as the CS might have updated - * the base address just after start of vblank, but before we - * managed to process the interrupt. This means we'd complete the - * CS flip too soon. - * - * Combining both checks should get us a good enough result. It may - * still happen that the CS flip has been executed, but has not - * yet actually completed. But in case the base address is the same - * anyway, we don't really care. - */ - return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == - crtc->flip_work->gtt_offset && - g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), - crtc->flip_work->flip_count); -} - -static bool -__pageflip_finished_mmio(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - /* - * MMIO work completes when vblank is different from - * flip_queued_vblank. - * - * Reset counter value doesn't matter, this is handled by - * i915_wait_request finishing early, so no need to handle - * reset here. - */ - return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; -} - - -static bool pageflip_finished(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - if (!atomic_read(&work->pending)) - return false; - - smp_rmb(); - - if (is_mmio_work(work)) - return __pageflip_finished_mmio(crtc, work); - else - return __pageflip_finished_cs(crtc, work); -} - -void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - unsigned long flags; - - /* Ignore early vblank irqs */ - if (!crtc) - return; - - /* - * This is called both by irq handlers and the reset code (to complete - * lost pageflips) so needs the full irqsave spinlocks. - */ - spin_lock_irqsave(&dev->event_lock, flags); - work = crtc->flip_work; - - if (work != NULL && - !is_mmio_work(work) && - pageflip_finished(crtc, work)) - page_flip_completed(crtc); - - spin_unlock_irqrestore(&dev->event_lock, flags); -} - -void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - unsigned long flags; - - /* Ignore early vblank irqs */ - if (!crtc) - return; - - /* - * This is called both by irq handlers and the reset code (to complete - * lost pageflips) so needs the full irqsave spinlocks. - */ - spin_lock_irqsave(&dev->event_lock, flags); - work = crtc->flip_work; - - if (work != NULL && - is_mmio_work(work) && - pageflip_finished(crtc, work)) - page_flip_completed(crtc); - - spin_unlock_irqrestore(&dev->event_lock, flags); -} - -static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); - - /* Ensure that the work item is consistent when activating it ... */ - smp_mb__before_atomic(); - atomic_set(&work->pending, 1); -} - -static int intel_gen2_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask, *cs; - - cs = intel_ring_begin(req, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Can't queue multiple flips, so wait for the previous - * one to finish before executing the next. - */ - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - *cs++ = MI_WAIT_FOR_EVENT | flip_mask; - *cs++ = MI_NOOP; - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = 0; /* aux display base address, unused */ - - return 0; -} - -static int intel_gen3_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask, *cs; - - cs = intel_ring_begin(req, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - *cs++ = MI_WAIT_FOR_EVENT | flip_mask; - *cs++ = MI_NOOP; - *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = MI_NOOP; - - return 0; -} - -static int intel_gen4_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 pf, pipesrc, *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* i965+ uses the linear or tiled offsets from the - * Display Registers (which do not change across a page-flip) - * so we need only reprogram the base address. - */ - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset | - intel_fb_modifier_to_tiling(fb->modifier); - - /* XXX Enabling the panel-fitter across page-flip is so far - * untested on non-native modes, so ignore it for now. - * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - *cs++ = pf | pipesrc; - - return 0; -} - -static int intel_gen6_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 pf, pipesrc, *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); - *cs++ = intel_crtc->flip_work->gtt_offset; - - /* Contrary to the suggestions in the documentation, - * "Enable Panel Fitter" does not seem to be required when page - * flipping with a non-native mode, and worse causes a normal - * modeset to fail. - * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - *cs++ = pf | pipesrc; - - return 0; -} - -static int intel_gen7_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 *cs, plane_bit = 0; - int len, ret; - - switch (intel_crtc->plane) { - case PLANE_A: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; - break; - case PLANE_B: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; - break; - case PLANE_C: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; - break; - default: - WARN_ONCE(1, "unknown plane in flip command\n"); - return -ENODEV; - } - - len = 4; - if (req->engine->id == RCS) { - len += 6; - /* - * On Gen 8, SRM is now taking an extra dword to accommodate - * 48bits addresses, and we need a NOOP for the batch size to - * stay even. - */ - if (IS_GEN8(dev_priv)) - len += 2; - } - - /* - * BSpec MI_DISPLAY_FLIP for IVB: - * "The full packet must be contained within the same cache line." - * - * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same - * cacheline, if we ever start emitting more commands before - * the MI_DISPLAY_FLIP we may need to first emit everything else, - * then do the cacheline alignment, and finally emit the - * MI_DISPLAY_FLIP. - */ - ret = intel_ring_cacheline_align(req); - if (ret) - return ret; - - cs = intel_ring_begin(req, len); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Unmask the flip-done completion message. Note that the bspec says that - * we should do this for both the BCS and RCS, and that we must not unmask - * more than one flip event at any time (or ensure that one flip message - * can be sent by waiting for flip-done prior to queueing new flips). - * Experimentation says that BCS works despite DERRMR masking all - * flip-done completion events and that unmasking all planes at once - * for the RCS also doesn't appear to drop events. Setting the DERRMR - * to zero does lead to lockups within MI_DISPLAY_FLIP. - */ - if (req->engine->id == RCS) { - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(DERRMR); - *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | - DERRMR_PIPEB_PRI_FLIP_DONE | - DERRMR_PIPEC_PRI_FLIP_DONE); - if (IS_GEN8(dev_priv)) - *cs++ = MI_STORE_REGISTER_MEM_GEN8 | - MI_SRM_LRM_GLOBAL_GTT; - else - *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; - *cs++ = i915_mmio_reg_offset(DERRMR); - *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; - if (IS_GEN8(dev_priv)) { - *cs++ = 0; - *cs++ = MI_NOOP; - } - } - - *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; - *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = MI_NOOP; - - return 0; -} - -static bool use_mmio_flip(struct intel_engine_cs *engine, - struct drm_i915_gem_object *obj) -{ - /* - * This is not being used for older platforms, because - * non-availability of flip done interrupt forces us to use - * CS flips. Older platforms derive flip done using some clever - * tricks involving the flip_pending status bits and vblank irqs. - * So using MMIO flips there would disrupt this mechanism. - */ - - if (engine == NULL) - return true; - - if (INTEL_GEN(engine->i915) < 5) - return false; - - if (i915.use_mmio_flip < 0) - return false; - else if (i915.use_mmio_flip > 0) - return true; - else if (i915.enable_execlists) - return true; - - return engine != i915_gem_object_last_write_engine(obj); -} - -static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, - unsigned int rotation, - struct intel_flip_work *work) -{ - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - const enum pipe pipe = intel_crtc->pipe; - u32 ctl, stride = skl_plane_stride(fb, 0, rotation); - - ctl = I915_READ(PLANE_CTL(pipe, 0)); - ctl &= ~PLANE_CTL_TILED_MASK; - switch (fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - break; - case I915_FORMAT_MOD_X_TILED: - ctl |= PLANE_CTL_TILED_X; - break; - case I915_FORMAT_MOD_Y_TILED: - ctl |= PLANE_CTL_TILED_Y; - break; - case I915_FORMAT_MOD_Yf_TILED: - ctl |= PLANE_CTL_TILED_YF; - break; - default: - MISSING_CASE(fb->modifier); - } - - /* - * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on - * PLANE_SURF updates, the update is then guaranteed to be atomic. - */ - I915_WRITE(PLANE_CTL(pipe, 0), ctl); - I915_WRITE(PLANE_STRIDE(pipe, 0), stride); - - I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); - POSTING_READ(PLANE_SURF(pipe, 0)); -} - -static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, - struct intel_flip_work *work) -{ - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - i915_reg_t reg = DSPCNTR(intel_crtc->plane); - u32 dspcntr; - - dspcntr = I915_READ(reg); - - if (fb->modifier == I915_FORMAT_MOD_X_TILED) - dspcntr |= DISPPLANE_TILED; - else - dspcntr &= ~DISPPLANE_TILED; - - I915_WRITE(reg, dspcntr); - - I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); - POSTING_READ(DSPSURF(intel_crtc->plane)); -} - -static void intel_mmio_flip_work_func(struct work_struct *w) -{ - struct intel_flip_work *work = - container_of(w, struct intel_flip_work, mmio_work); - struct intel_crtc *crtc = to_intel_crtc(work->crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_framebuffer *intel_fb = - to_intel_framebuffer(crtc->base.primary->fb); - struct drm_i915_gem_object *obj = intel_fb->obj; - - WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); - - intel_pipe_update_start(crtc); - - if (INTEL_GEN(dev_priv) >= 9) - skl_do_mmio_flip(crtc, work->rotation, work); - else - /* use_mmio_flip() retricts MMIO flips to ilk+ */ - ilk_do_mmio_flip(crtc, work); - - intel_pipe_update_end(crtc, work); -} - -static int intel_default_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - return -ENODEV; -} - -static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, - struct intel_crtc *intel_crtc, - struct intel_flip_work *work) -{ - u32 addr, vblank; - - if (!atomic_read(&work->pending)) - return false; - - smp_rmb(); - - vblank = intel_crtc_get_vblank_counter(intel_crtc); - if (work->flip_ready_vblank == 0) { - if (work->flip_queued_req && - !i915_gem_request_completed(work->flip_queued_req)) - return false; - - work->flip_ready_vblank = vblank; - } - - if (vblank - work->flip_ready_vblank < 3) - return false; - - /* Potential stall - if we see that the flip has happened, - * assume a missed interrupt. */ - if (INTEL_GEN(dev_priv) >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); - else - addr = I915_READ(DSPADDR(intel_crtc->plane)); - - /* There is a potential issue here with a false positive after a flip - * to the same address. We could address this by checking for a - * non-incrementing frame counter. - */ - return addr == work->gtt_offset; -} - -void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - - WARN_ON(!in_interrupt()); - - if (crtc == NULL) - return; - - spin_lock(&dev->event_lock); - work = crtc->flip_work; - - if (work != NULL && !is_mmio_work(work) && - __pageflip_stall_check_cs(dev_priv, crtc, work)) { - WARN_ONCE(1, - "Kicking stuck page flip: queued at %d, now %d\n", - work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); - page_flip_completed(crtc); - work = NULL; - } - - if (work != NULL && !is_mmio_work(work) && - intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) - intel_queue_rps_boost_for_request(work->flip_queued_req); - spin_unlock(&dev->event_lock); -} - -__maybe_unused -static int intel_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *old_fb = crtc->primary->fb; - struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_plane *primary = crtc->primary; - enum pipe pipe = intel_crtc->pipe; - struct intel_flip_work *work; - struct intel_engine_cs *engine; - bool mmio_flip; - struct drm_i915_gem_request *request; - struct i915_vma *vma; - int ret; - - /* - * drm_mode_page_flip_ioctl() should already catch this, but double - * check to be safe. In the future we may enable pageflipping from - * a disabled primary plane. - */ - if (WARN_ON(intel_fb_obj(old_fb) == NULL)) - return -EBUSY; - - /* Can't change pixel format via MI display flips. */ - if (fb->format != crtc->primary->fb->format) - return -EINVAL; - - /* - * TILEOFF/LINOFF registers can't be changed via MI display flips. - * Note that pitch changes could also affect these register. - */ - if (INTEL_GEN(dev_priv) > 3 && - (fb->offsets[0] != crtc->primary->fb->offsets[0] || - fb->pitches[0] != crtc->primary->fb->pitches[0])) - return -EINVAL; - - if (i915_terminally_wedged(&dev_priv->gpu_error)) - goto out_hang; - - work = kzalloc(sizeof(*work), GFP_KERNEL); - if (work == NULL) - return -ENOMEM; - - work->event = event; - work->crtc = crtc; - work->old_fb = old_fb; - INIT_WORK(&work->unpin_work, intel_unpin_work_fn); - - ret = drm_crtc_vblank_get(crtc); - if (ret) - goto free_work; - - /* We borrow the event spin lock for protecting flip_work */ - spin_lock_irq(&dev->event_lock); - if (intel_crtc->flip_work) { - /* Before declaring the flip queue wedged, check if - * the hardware completed the operation behind our backs. - */ - if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { - DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); - page_flip_completed(intel_crtc); - } else { - DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); - spin_unlock_irq(&dev->event_lock); - - drm_crtc_vblank_put(crtc); - kfree(work); - return -EBUSY; - } - } - intel_crtc->flip_work = work; - spin_unlock_irq(&dev->event_lock); - - if (atomic_read(&intel_crtc->unpin_work_count) >= 2) - flush_workqueue(dev_priv->wq); - - /* Reference the objects for the scheduled work. */ - drm_framebuffer_reference(work->old_fb); - - crtc->primary->fb = fb; - update_state_fb(crtc->primary); - - work->pending_flip_obj = i915_gem_object_get(obj); - - ret = i915_mutex_lock_interruptible(dev); - if (ret) - goto cleanup; - - intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); - if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) { - ret = -EIO; - goto unlock; - } - - atomic_inc(&intel_crtc->unpin_work_count); - - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) - work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; - - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - engine = dev_priv->engine[BCS]; - if (fb->modifier != old_fb->modifier) - /* vlv: DISPLAY_FLIP fails to change tiling */ - engine = NULL; - } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { - engine = dev_priv->engine[BCS]; - } else if (INTEL_GEN(dev_priv) >= 7) { - engine = i915_gem_object_last_write_engine(obj); - if (engine == NULL || engine->id != RCS) - engine = dev_priv->engine[BCS]; - } else { - engine = dev_priv->engine[RCS]; - } - - mmio_flip = use_mmio_flip(engine, obj); - - vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto cleanup_pending; - } - - work->old_vma = to_intel_plane_state(primary->state)->vma; - to_intel_plane_state(primary->state)->vma = vma; - - work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; - work->rotation = crtc->primary->state->rotation; - - /* - * There's the potential that the next frame will not be compatible with - * FBC, so we want to call pre_update() before the actual page flip. - * The problem is that pre_update() caches some information about the fb - * object, so we want to do this only after the object is pinned. Let's - * be on the safe side and do this immediately before scheduling the - * flip. - */ - intel_fbc_pre_update(intel_crtc, intel_crtc->config, - to_intel_plane_state(primary->state)); - - if (mmio_flip) { - INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); - queue_work(system_unbound_wq, &work->mmio_work); - } else { - request = i915_gem_request_alloc(engine, - dev_priv->kernel_context); - if (IS_ERR(request)) { - ret = PTR_ERR(request); - goto cleanup_unpin; - } - - ret = i915_gem_request_await_object(request, obj, false); - if (ret) - goto cleanup_request; - - ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, - page_flip_flags); - if (ret) - goto cleanup_request; - - intel_mark_page_flip_active(intel_crtc, work); - - work->flip_queued_req = i915_gem_request_get(request); - i915_add_request(request); - } - - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); - i915_gem_track_fb(intel_fb_obj(old_fb), obj, - to_intel_plane(primary)->frontbuffer_bit); - mutex_unlock(&dev->struct_mutex); - - intel_frontbuffer_flip_prepare(to_i915(dev), - to_intel_plane(primary)->frontbuffer_bit); - - trace_i915_flip_request(intel_crtc->plane, obj); - - return 0; - -cleanup_request: - i915_add_request(request); -cleanup_unpin: - to_intel_plane_state(primary->state)->vma = work->old_vma; - intel_unpin_fb_vma(vma); -cleanup_pending: - atomic_dec(&intel_crtc->unpin_work_count); -unlock: - mutex_unlock(&dev->struct_mutex); -cleanup: - crtc->primary->fb = old_fb; - update_state_fb(crtc->primary); - - i915_gem_object_put(obj); - drm_framebuffer_unreference(work->old_fb); - - spin_lock_irq(&dev->event_lock); - intel_crtc->flip_work = NULL; - spin_unlock_irq(&dev->event_lock); - - drm_crtc_vblank_put(crtc); -free_work: - kfree(work); - - if (ret == -EIO) { - struct drm_atomic_state *state; - struct drm_plane_state *plane_state; - -out_hang: - state = drm_atomic_state_alloc(dev); - if (!state) - return -ENOMEM; - state->acquire_ctx = dev->mode_config.acquire_ctx; - -retry: - plane_state = drm_atomic_get_plane_state(state, primary); - ret = PTR_ERR_OR_ZERO(plane_state); - if (!ret) { - drm_atomic_set_fb_for_plane(plane_state, fb); - - ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); - if (!ret) - ret = drm_atomic_commit(state); - } - - if (ret == -EDEADLK) { - drm_modeset_backoff(state->acquire_ctx); - drm_atomic_state_clear(state); - goto retry; - } - - drm_atomic_state_put(state); - - if (ret == 0 && event) { - spin_lock_irq(&dev->event_lock); - drm_crtc_send_vblank_event(crtc, event); - spin_unlock_irq(&dev->event_lock); - } - } - return ret; -} - - /** * intel_wm_need_update - Check whether watermarks need updating * @plane: drm plane @@ -10997,7 +10342,7 @@ static bool intel_wm_need_update(struct drm_plane *plane, return false; } -static bool needs_scaling(struct intel_plane_state *state) +static bool needs_scaling(const struct intel_plane_state *state) { int src_w = drm_rect_width(&state->base.src) >> 16; int src_h = drm_rect_height(&state->base.src) >> 16; @@ -11007,7 +10352,9 @@ static bool needs_scaling(struct intel_plane_state *state) return (src_w != dst_w || src_h != dst_h); } -int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, +int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, + struct drm_crtc_state *crtc_state, + const struct intel_plane_state *old_plane_state, struct drm_plane_state *plane_state) { struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); @@ -11016,10 +10363,8 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, struct intel_plane *plane = to_intel_plane(plane_state->plane); struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_plane_state *old_plane_state = - to_intel_plane_state(plane->base.state); bool mode_changed = needs_modeset(crtc_state); - bool was_crtc_enabled = crtc->state->active; + bool was_crtc_enabled = old_crtc_state->base.active; bool is_crtc_enabled = crtc_state->active; bool turn_off, turn_on, visible, was_visible; struct drm_framebuffer *fb = plane_state->fb; @@ -11360,6 +10705,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->fdi_lanes, &pipe_config->fdi_m_n); + if (pipe_config->ycbcr420) + DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); + if (intel_crtc_has_dp_encoder(pipe_config)) { intel_dump_m_n_config(pipe_config, "dp m_n", pipe_config->lane_count, &pipe_config->dp_m_n); @@ -11507,7 +10855,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) struct intel_dpll_hw_state dpll_hw_state; struct intel_shared_dpll *shared_dpll; struct intel_crtc_wm_state wm_state; - bool force_thru; + bool force_thru, ips_force_disable; /* FIXME: before the switch to atomic started, a new pipe_config was * kzalloc'd. Code that depends on any field being zero should be @@ -11518,6 +10866,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) shared_dpll = crtc_state->shared_dpll; dpll_hw_state = crtc_state->dpll_hw_state; force_thru = crtc_state->pch_pfit.force_thru; + ips_force_disable = crtc_state->ips_force_disable; if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) wm_state = crtc_state->wm; @@ -11531,6 +10880,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) crtc_state->shared_dpll = shared_dpll; crtc_state->dpll_hw_state = dpll_hw_state; crtc_state->pch_pfit.force_thru = force_thru; + crtc_state->ips_force_disable = ips_force_disable; if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) crtc_state->wm = wm_state; @@ -11931,6 +11281,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_I(hdmi_scrambling); PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); PIPE_CONF_CHECK_I(has_infoframe); + PIPE_CONF_CHECK_I(ycbcr420); PIPE_CONF_CHECK_I(has_audio); @@ -12772,31 +12123,7 @@ static int intel_atomic_check(struct drm_device *dev, static int intel_atomic_prepare_commit(struct drm_device *dev, struct drm_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_crtc_state *crtc_state; - struct drm_crtc *crtc; - int i, ret; - - for_each_new_crtc_in_state(state, crtc, crtc_state, i) { - if (state->legacy_cursor_update) - continue; - - ret = intel_crtc_wait_for_pending_flips(crtc); - if (ret) - return ret; - - if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) - flush_workqueue(dev_priv->wq); - } - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - ret = drm_atomic_helper_prepare_planes(dev, state); - mutex_unlock(&dev->struct_mutex); - - return ret; + return drm_atomic_helper_prepare_planes(dev, state); } u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) @@ -12886,7 +12213,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state) unsigned int cmask = drm_crtc_mask(crtc); intel_crtc = to_intel_crtc(crtc); - cstate = to_intel_crtc_state(crtc->state); + cstate = to_intel_crtc_state(new_crtc_state); pipe = intel_crtc->pipe; if (updated & cmask || !cstate->base.active) @@ -12939,6 +12266,30 @@ static void intel_atomic_helper_free_state_worker(struct work_struct *work) intel_atomic_helper_free_state(dev_priv); } +static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) +{ + struct wait_queue_entry wait_fence, wait_reset; + struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); + + init_wait_entry(&wait_fence, 0); + init_wait_entry(&wait_reset, 0); + for (;;) { + prepare_to_wait(&intel_state->commit_ready.wait, + &wait_fence, TASK_UNINTERRUPTIBLE); + prepare_to_wait(&dev_priv->gpu_error.wait_queue, + &wait_reset, TASK_UNINTERRUPTIBLE); + + + if (i915_sw_fence_done(&intel_state->commit_ready) + || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags)) + break; + + schedule(); + } + finish_wait(&intel_state->commit_ready.wait, &wait_fence); + finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset); +} + static void intel_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; @@ -12951,6 +12302,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) u64 put_domains[I915_MAX_PIPES] = {}; int i; + intel_atomic_commit_fence_wait(intel_state); + drm_atomic_helper_wait_for_dependencies(state); if (intel_state->modeset) @@ -12988,7 +12341,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_check_cpu_fifo_underruns(dev_priv); intel_check_pch_fifo_underruns(dev_priv); - if (!crtc->state->active) { + if (!new_crtc_state->active) { /* * Make sure we don't call initial_watermarks * for ILK-style watermark updates. @@ -12997,7 +12350,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) */ if (INTEL_GEN(dev_priv) >= 9) dev_priv->display.initial_watermarks(intel_state, - to_intel_crtc_state(crtc->state)); + to_intel_crtc_state(new_crtc_state)); } } } @@ -13089,9 +12442,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); } - mutex_lock(&dev->struct_mutex); drm_atomic_helper_cleanup_planes(dev, state); - mutex_unlock(&dev->struct_mutex); drm_atomic_helper_commit_cleanup_done(state); @@ -13117,10 +12468,8 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence, switch (notify) { case FENCE_COMPLETE: - if (state->base.commit_work.func) - queue_work(system_unbound_wq, &state->base.commit_work); + /* we do blocking waits in the worker, nothing to do here */ break; - case FENCE_FREE: { struct intel_atomic_helper *helper = @@ -13206,9 +12555,7 @@ static int intel_atomic_commit(struct drm_device *dev, if (ret) { i915_sw_fence_commit(&intel_state->commit_ready); - mutex_lock(&dev->struct_mutex); drm_atomic_helper_cleanup_planes(dev, state); - mutex_unlock(&dev->struct_mutex); return ret; } dev_priv->wm.distrust_bios_wm = false; @@ -13216,22 +12563,22 @@ static int intel_atomic_commit(struct drm_device *dev, intel_atomic_track_fbs(state); if (intel_state->modeset) { - memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, - sizeof(intel_state->min_pixclk)); + memcpy(dev_priv->min_cdclk, intel_state->min_cdclk, + sizeof(intel_state->min_cdclk)); dev_priv->active_crtcs = intel_state->active_crtcs; dev_priv->cdclk.logical = intel_state->cdclk.logical; dev_priv->cdclk.actual = intel_state->cdclk.actual; } drm_atomic_state_get(state); - INIT_WORK(&state->commit_work, - nonblock ? intel_atomic_commit_work : NULL); + INIT_WORK(&state->commit_work, intel_atomic_commit_work); i915_sw_fence_commit(&intel_state->commit_ready); - if (!nonblock) { - i915_sw_fence_wait(&intel_state->commit_ready); + if (nonblock) + queue_work(system_unbound_wq, &state->commit_work); + else intel_atomic_commit_tail(state); - } + return 0; } @@ -13246,6 +12593,58 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { .set_crc_source = intel_crtc_set_crc_source, }; +struct wait_rps_boost { + struct wait_queue_entry wait; + + struct drm_crtc *crtc; + struct drm_i915_gem_request *request; +}; + +static int do_rps_boost(struct wait_queue_entry *_wait, + unsigned mode, int sync, void *key) +{ + struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); + struct drm_i915_gem_request *rq = wait->request; + + gen6_rps_boost(rq, NULL); + i915_gem_request_put(rq); + + drm_crtc_vblank_put(wait->crtc); + + list_del(&wait->wait.entry); + kfree(wait); + return 1; +} + +static void add_rps_boost_after_vblank(struct drm_crtc *crtc, + struct dma_fence *fence) +{ + struct wait_rps_boost *wait; + + if (!dma_fence_is_i915(fence)) + return; + + if (INTEL_GEN(to_i915(crtc->dev)) < 6) + return; + + if (drm_crtc_vblank_get(crtc)) + return; + + wait = kmalloc(sizeof(*wait), GFP_KERNEL); + if (!wait) { + drm_crtc_vblank_put(crtc); + return; + } + + wait->request = to_request(dma_fence_get(fence)); + wait->crtc = crtc; + + wait->wait.func = do_rps_boost; + wait->wait.flags = 0; + + add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); +} + /** * intel_prepare_plane_fb - Prepare fb for usage on plane * @plane: drm plane to prepare for @@ -13272,32 +12671,6 @@ intel_prepare_plane_fb(struct drm_plane *plane, struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); int ret; - if (obj) { - if (plane->type == DRM_PLANE_TYPE_CURSOR && - INTEL_INFO(dev_priv)->cursor_needs_physical) { - const int align = intel_cursor_alignment(dev_priv); - - ret = i915_gem_object_attach_phys(obj, align); - if (ret) { - DRM_DEBUG_KMS("failed to attach phys object\n"); - return ret; - } - } else { - struct i915_vma *vma; - - vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); - if (IS_ERR(vma)) { - DRM_DEBUG_KMS("failed to pin object\n"); - return PTR_ERR(vma); - } - - to_intel_plane_state(new_state)->vma = vma; - } - } - - if (!obj && !old_obj) - return 0; - if (old_obj) { struct drm_crtc_state *crtc_state = drm_atomic_get_existing_crtc_state(new_state->state, @@ -13336,7 +12709,41 @@ intel_prepare_plane_fb(struct drm_plane *plane, if (!obj) return 0; + ret = i915_gem_object_pin_pages(obj); + if (ret) + return ret; + + ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); + if (ret) { + i915_gem_object_unpin_pages(obj); + return ret; + } + + if (plane->type == DRM_PLANE_TYPE_CURSOR && + INTEL_INFO(dev_priv)->cursor_needs_physical) { + const int align = intel_cursor_alignment(dev_priv); + + ret = i915_gem_object_attach_phys(obj, align); + } else { + struct i915_vma *vma; + + vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); + if (!IS_ERR(vma)) + to_intel_plane_state(new_state)->vma = vma; + else + ret = PTR_ERR(vma); + } + + i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); + + mutex_unlock(&dev_priv->drm.struct_mutex); + i915_gem_object_unpin_pages(obj); + if (ret) + return ret; + if (!new_state->fence) { /* implicit fencing */ + struct dma_fence *fence; + ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, obj->resv, NULL, false, I915_FENCE_TIMEOUT, @@ -13344,7 +12751,13 @@ intel_prepare_plane_fb(struct drm_plane *plane, if (ret < 0) return ret; - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); + fence = reservation_object_get_excl_rcu(obj->resv); + if (fence) { + add_rps_boost_after_vblank(new_state->crtc, fence); + dma_fence_put(fence); + } + } else { + add_rps_boost_after_vblank(new_state->crtc, new_state->fence); } return 0; @@ -13367,8 +12780,11 @@ intel_cleanup_plane_fb(struct drm_plane *plane, /* Should only be called after a successful intel_prepare_plane_fb()! */ vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); - if (vma) + if (vma) { + mutex_lock(&plane->dev->struct_mutex); intel_unpin_fb_vma(vma); + mutex_unlock(&plane->dev->struct_mutex); + } } int @@ -13458,29 +12874,29 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_crtc_state *intel_cstate = - to_intel_crtc_state(crtc->state); struct intel_crtc_state *old_intel_cstate = to_intel_crtc_state(old_crtc_state); struct intel_atomic_state *old_intel_state = to_intel_atomic_state(old_crtc_state->state); - bool modeset = needs_modeset(crtc->state); + struct intel_crtc_state *intel_cstate = + intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc); + bool modeset = needs_modeset(&intel_cstate->base); if (!modeset && (intel_cstate->base.color_mgmt_changed || intel_cstate->update_pipe)) { - intel_color_set_csc(crtc->state); - intel_color_load_luts(crtc->state); + intel_color_set_csc(&intel_cstate->base); + intel_color_load_luts(&intel_cstate->base); } /* Perform vblank evasion around commit operation */ - intel_pipe_update_start(intel_crtc); + intel_pipe_update_start(intel_cstate); if (modeset) goto out; if (intel_cstate->update_pipe) - intel_update_pipe_config(intel_crtc, old_intel_cstate); + intel_update_pipe_config(old_intel_cstate, intel_cstate); else if (INTEL_GEN(dev_priv) >= 9) skl_detach_scalers(intel_crtc); @@ -13494,8 +12910,12 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_atomic_state *old_intel_state = + to_intel_atomic_state(old_crtc_state->state); + struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc); - intel_pipe_update_end(intel_crtc, NULL); + intel_pipe_update_end(new_crtc_state); } /** @@ -13511,7 +12931,102 @@ void intel_plane_destroy(struct drm_plane *plane) kfree(to_intel_plane(plane)); } -const struct drm_plane_funcs intel_plane_funcs = { +static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_C8: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_XRGB8888: + return modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED; + default: + return false; + } +} + +static bool i965_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_C8: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + return modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED; + default: + return false; + } +} + +static bool skl_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_CCS) + return true; + /* fall through */ + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == I915_FORMAT_MOD_Yf_TILED) + return true; + /* fall through */ + case DRM_FORMAT_C8: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED || + modifier == I915_FORMAT_MOD_Y_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && + modifier != DRM_FORMAT_MOD_LINEAR) + return false; + + if (INTEL_GEN(dev_priv) >= 9) + return skl_mod_supported(format, modifier); + else if (INTEL_GEN(dev_priv) >= 4) + return i965_mod_supported(format, modifier); + else + return i8xx_mod_supported(format, modifier); + + unreachable(); +} + +static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; +} + +static struct drm_plane_funcs intel_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = intel_plane_destroy, @@ -13519,6 +13034,7 @@ const struct drm_plane_funcs intel_plane_funcs = { .atomic_set_property = intel_plane_atomic_set_property, .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_primary_plane_format_mod_supported, }; static int @@ -13537,7 +13053,7 @@ intel_legacy_cursor_update(struct drm_plane *plane, struct intel_plane *intel_plane = to_intel_plane(plane); struct drm_framebuffer *old_fb; struct drm_crtc_state *crtc_state = crtc->state; - struct i915_vma *old_vma; + struct i915_vma *old_vma, *vma; /* * When crtc is inactive or there is a modeset pending, @@ -13586,6 +13102,8 @@ intel_legacy_cursor_update(struct drm_plane *plane, new_plane_state->crtc_h = crtc_h; ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), + to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */ + to_intel_plane_state(plane->state), to_intel_plane_state(new_plane_state)); if (ret) goto out_free; @@ -13603,8 +13121,6 @@ intel_legacy_cursor_update(struct drm_plane *plane, goto out_unlock; } } else { - struct i915_vma *vma; - vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); if (IS_ERR(vma)) { DRM_DEBUG_KMS("failed to pin object\n"); @@ -13661,6 +13177,7 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = { .atomic_set_property = intel_plane_atomic_set_property, .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_cursor_plane_format_mod_supported, }; static struct intel_plane * @@ -13671,6 +13188,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) const uint32_t *intel_primary_formats; unsigned int supported_rotations; unsigned int num_formats; + const uint64_t *modifiers; int ret; primary = kzalloc(sizeof(*primary), GFP_KERNEL); @@ -13706,21 +13224,34 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); primary->check_plane = intel_check_primary_plane; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + intel_primary_formats = skl_primary_formats; + num_formats = ARRAY_SIZE(skl_primary_formats); + modifiers = skl_format_modifiers_ccs; + + primary->update_plane = skylake_update_primary_plane; + primary->disable_plane = skylake_disable_primary_plane; + } else if (INTEL_GEN(dev_priv) >= 9) { intel_primary_formats = skl_primary_formats; num_formats = ARRAY_SIZE(skl_primary_formats); + if (pipe < PIPE_C) + modifiers = skl_format_modifiers_ccs; + else + modifiers = skl_format_modifiers_noccs; primary->update_plane = skylake_update_primary_plane; primary->disable_plane = skylake_disable_primary_plane; } else if (INTEL_GEN(dev_priv) >= 4) { intel_primary_formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); + modifiers = i9xx_format_modifiers; primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; } else { intel_primary_formats = i8xx_primary_formats; num_formats = ARRAY_SIZE(i8xx_primary_formats); + modifiers = i9xx_format_modifiers; primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; @@ -13730,21 +13261,21 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "plane 1%c", pipe_name(pipe)); else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "primary %c", pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "plane %c", plane_name(primary->plane)); if (ret) @@ -13830,7 +13361,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, 0, &intel_cursor_plane_funcs, intel_cursor_formats, ARRAY_SIZE(intel_cursor_formats), - NULL, DRM_PLANE_TYPE_CURSOR, + cursor_format_modifiers, + DRM_PLANE_TYPE_CURSOR, "cursor %c", pipe_name(pipe)); if (ret) goto fail; @@ -14143,7 +13675,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) } else if (HAS_PCH_SPLIT(dev_priv)) { int found; - dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); + dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); if (has_edp_a(dev_priv)) intel_dp_init(dev_priv, DP_A, PORT_A); @@ -14186,14 +13718,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) * trust the port type the VBT declares as we've seen at least * HDMI ports that the VBT claim are DP or eDP. */ - has_edp = intel_dp_is_edp(dev_priv, PORT_B); + has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); has_port = intel_bios_is_port_present(dev_priv, PORT_B); if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); - has_edp = intel_dp_is_edp(dev_priv, PORT_C); + has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); has_port = intel_bios_is_port_present(dev_priv, PORT_C); if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); @@ -14352,10 +13884,12 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + struct drm_framebuffer *fb = &intel_fb->base; struct drm_format_name_buf format_name; - u32 pitch_limit, stride_alignment; + u32 pitch_limit; unsigned int tiling, stride; int ret = -EINVAL; + int i; i915_gem_object_lock(obj); obj->framebuffer_references++; @@ -14384,6 +13918,19 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, /* Passed in modifier sanity checking. */ switch (mode_cmd->modifier[0]) { + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + switch (mode_cmd->pixel_format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + break; + default: + DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); + goto err; + } + /* fall through */ case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: if (INTEL_GEN(dev_priv) < 9) { @@ -14488,25 +14035,46 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, if (mode_cmd->offsets[0] != 0) goto err; - drm_helper_mode_fill_fb_struct(&dev_priv->drm, - &intel_fb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); - stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0); - if (mode_cmd->pitches[0] & (stride_alignment - 1)) { - DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n", - mode_cmd->pitches[0], stride_alignment); - goto err; + for (i = 0; i < fb->format->num_planes; i++) { + u32 stride_alignment; + + if (mode_cmd->handles[i] != mode_cmd->handles[0]) { + DRM_DEBUG_KMS("bad plane %d handle\n", i); + goto err; + } + + stride_alignment = intel_fb_stride_alignment(fb, i); + + /* + * Display WA #0531: skl,bxt,kbl,glk + * + * Render decompression and plane width > 3840 + * combined with horizontal panning requires the + * plane stride to be a multiple of 4. We'll just + * require the entire fb to accommodate that to avoid + * potential runtime errors at plane configuration time. + */ + if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) + stride_alignment *= 4; + + if (fb->pitches[i] & (stride_alignment - 1)) { + DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", + i, fb->pitches[i], stride_alignment); + goto err; + } } intel_fb->obj = obj; - ret = intel_fill_fb_info(dev_priv, &intel_fb->base); + ret = intel_fill_fb_info(dev_priv, fb); if (ret) goto err; - ret = drm_framebuffer_init(obj->base.dev, - &intel_fb->base, - &intel_fb_funcs); + ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); if (ret) { DRM_ERROR("framebuffer init failed %d\n", ret); goto err; @@ -14554,6 +14122,7 @@ static void intel_atomic_state_free(struct drm_atomic_state *state) static const struct drm_mode_config_funcs intel_mode_funcs = { .fb_create = intel_user_framebuffer_create, + .get_format_info = intel_get_format_info, .output_poll_changed = intel_fbdev_output_poll_changed, .atomic_check = intel_atomic_check, .atomic_commit = intel_atomic_commit, @@ -14653,34 +14222,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.update_crtcs = skl_update_crtcs; else dev_priv->display.update_crtcs = intel_update_crtcs; - - switch (INTEL_INFO(dev_priv)->gen) { - case 2: - dev_priv->display.queue_flip = intel_gen2_queue_flip; - break; - - case 3: - dev_priv->display.queue_flip = intel_gen3_queue_flip; - break; - - case 4: - case 5: - dev_priv->display.queue_flip = intel_gen4_queue_flip; - break; - - case 6: - dev_priv->display.queue_flip = intel_gen6_queue_flip; - break; - case 7: - case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ - dev_priv->display.queue_flip = intel_gen7_queue_flip; - break; - case 9: - /* Drop through - unsupported since execlist only. */ - default: - /* Default just returns -ENODEV to indicate unsupported */ - dev_priv->display.queue_flip = intel_default_queue_flip; - } } /* @@ -15501,7 +15042,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) for_each_intel_crtc(dev, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - int pixclk = 0; + int min_cdclk = 0; memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); if (crtc_state->base.active) { @@ -15522,22 +15063,18 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) intel_crtc_compute_pixel_rate(crtc_state); - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - pixclk = crtc_state->pixel_rate; - else - WARN_ON(dev_priv->display.modeset_calc_cdclk); - - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) - pixclk = DIV_ROUND_UP(pixclk * 100, 95); + if (dev_priv->display.modeset_calc_cdclk) { + min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); + if (WARN_ON(min_cdclk < 0)) + min_cdclk = 0; + } drm_calc_timestamping_constants(&crtc->base, &crtc_state->base.adjusted_mode); update_scanline_offset(crtc); } - dev_priv->min_pixclk[crtc->pipe] = pixclk; + dev_priv->min_cdclk[crtc->pipe] = min_cdclk; intel_pipe_config_sanity_check(dev_priv, crtc_state); } @@ -15611,7 +15148,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_wm_get_hw_state(dev); vlv_wm_sanitize(dev_priv); - } else if (IS_GEN9(dev_priv)) { + } else if (INTEL_GEN(dev_priv) >= 9) { skl_wm_get_hw_state(dev); } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_wm_get_hw_state(dev); @@ -15718,6 +15255,9 @@ void intel_modeset_cleanup(struct drm_device *dev) */ drm_kms_helper_poll_fini(dev); + /* poll work can call into fbdev, hence clean that up afterwards */ + intel_fbdev_fini(dev_priv); + intel_unregister_dsm_handler(); intel_fbc_global_disable(dev_priv); @@ -15837,7 +15377,8 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) return NULL; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); + error->power_well_driver = + I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)); for_each_pipe(dev_priv, i) { error->pipe[i].power_domain_on = diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 76c8a0bd17f9..887953c0f495 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -97,16 +97,19 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000, 324000, 432000, 540000 }; static const int skl_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; +static const int cnl_rates[] = { 162000, 216000, 270000, + 324000, 432000, 540000, + 648000, 810000 }; static const int default_rates[] = { 162000, 270000, 540000 }; /** - * is_edp - is the given port attached to an eDP panel (either CPU or PCH) + * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) * @intel_dp: DP struct * * If a CPU or PCH DP output is attached to an eDP panel, this function * will return true, and false otherwise. */ -static bool is_edp(struct intel_dp *intel_dp) +bool intel_dp_is_edp(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); @@ -229,8 +232,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->port; const int *source_rates; int size; + u32 voltage; /* This should only be done once */ WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); @@ -238,6 +243,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) if (IS_GEN9_LP(dev_priv)) { source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); + } else if (IS_CANNONLAKE(dev_priv)) { + source_rates = cnl_rates; + size = ARRAY_SIZE(cnl_rates); + voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + if (port == PORT_A || port == PORT_D || + voltage == VOLTAGE_INFO_0_85V) + size -= 2; } else if (IS_GEN9_BC(dev_priv)) { source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); @@ -322,19 +334,20 @@ static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp, return 0; } -static bool intel_dp_link_params_valid(struct intel_dp *intel_dp) +static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, + uint8_t lane_count) { /* * FIXME: we need to synchronize the current link parameters with * hardware readout. Currently fast link training doesn't work on * boot-up. */ - if (intel_dp->link_rate == 0 || - intel_dp->link_rate > intel_dp->max_link_rate) + if (link_rate == 0 || + link_rate > intel_dp->max_link_rate) return false; - if (intel_dp->lane_count == 0 || - intel_dp->lane_count > intel_dp_max_lane_count(intel_dp)) + if (lane_count == 0 || + lane_count > intel_dp_max_lane_count(intel_dp)) return false; return true; @@ -375,7 +388,7 @@ intel_dp_mode_valid(struct drm_connector *connector, max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); - if (is_edp(intel_dp) && fixed_mode) { + if (intel_dp_is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay) return MODE_PANEL; @@ -584,7 +597,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); /* We should never land here with regular DP ports */ - WARN_ON(!is_edp(intel_dp)); + WARN_ON(!intel_dp_is_edp(intel_dp)); WARN_ON(intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe); @@ -631,7 +644,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); /* We should never land here with regular DP ports */ - WARN_ON(!is_edp(intel_dp)); + WARN_ON(!intel_dp_is_edp(intel_dp)); /* * TODO: BXT has 2 PPS instances. The correct port->PPS instance @@ -834,7 +847,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code, struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = to_i915(dev); - if (!is_edp(intel_dp) || code != SYS_RESTART) + if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) return 0; pps_lock(intel_dp); @@ -894,7 +907,7 @@ intel_dp_check_edp(struct intel_dp *intel_dp) struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = to_i915(dev); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { @@ -1606,6 +1619,23 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, return bpp; } +static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1, + struct drm_display_mode *m2) +{ + bool bres = false; + + if (m1 && m2) + bres = (m1->hdisplay == m2->hdisplay && + m1->hsync_start == m2->hsync_start && + m1->hsync_end == m2->hsync_end && + m1->htotal == m2->htotal && + m1->vdisplay == m2->vdisplay && + m1->vsync_start == m2->vsync_start && + m1->vsync_end == m2->vsync_end && + m1->vtotal == m2->vtotal); + return bres; +} + bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, @@ -1651,9 +1681,17 @@ intel_dp_compute_config(struct intel_encoder *encoder, else pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; - if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { - intel_fixed_panel_mode(intel_connector->panel.fixed_mode, - adjusted_mode); + if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { + struct drm_display_mode *panel_mode = + intel_connector->panel.alt_fixed_mode; + struct drm_display_mode *req_mode = &pipe_config->base.mode; + + if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) + panel_mode = intel_connector->panel.fixed_mode; + + drm_mode_debug_printmodeline(panel_mode); + + intel_fixed_panel_mode(panel_mode, adjusted_mode); if (INTEL_GEN(dev_priv) >= 9) { int ret; @@ -1677,12 +1715,18 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { int index; - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - intel_dp->compliance.test_link_rate); - if (index >= 0) - min_clock = max_clock = index; - min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; + /* Validate the compliance test data since max values + * might have changed due to link train fallback. + */ + if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, + intel_dp->compliance.test_lane_count)) { + index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + intel_dp->compliance.test_link_rate); + if (index >= 0) + min_clock = max_clock = index; + min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; + } } DRM_DEBUG_KMS("DP link computation with max lane count %i " "max bw %d pixel clock %iKHz\n", @@ -1692,7 +1736,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, /* Walk through all bpp values. Luckily they're all nicely spaced with 2 * bpc in between. */ bpp = intel_dp_compute_bpp(intel_dp, pipe_config); - if (is_edp(intel_dp)) { + if (intel_dp_is_edp(intel_dp)) { /* Get bpp from vbt only for panels that dont have bpp in edid */ if (intel_connector->base.display_info.bpc == 0 && @@ -1785,7 +1829,7 @@ found: * DPLL0 VCO may need to be adjusted to get the correct * clock for eDP. This will affect cdclk as well. */ - if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { + if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { int vco; switch (pipe_config->port_clock / 2) { @@ -1817,7 +1861,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, } static void intel_dp_prepare(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *pipe_config) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -2025,7 +2069,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return false; cancel_delayed_work(&intel_dp->panel_vdd_work); @@ -2075,7 +2119,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) { bool vdd; - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; pps_lock(intel_dp); @@ -2159,7 +2203,7 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) lockdep_assert_held(&dev_priv->pps_mutex); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", @@ -2182,7 +2226,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", @@ -2223,7 +2267,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) void intel_edp_panel_on(struct intel_dp *intel_dp) { - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; pps_lock(intel_dp); @@ -2241,7 +2285,7 @@ static void edp_panel_off(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", @@ -2272,7 +2316,7 @@ static void edp_panel_off(struct intel_dp *intel_dp) void intel_edp_panel_off(struct intel_dp *intel_dp) { - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; pps_lock(intel_dp); @@ -2316,7 +2360,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, { struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; DRM_DEBUG_KMS("\n"); @@ -2333,7 +2377,7 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp) u32 pp; i915_reg_t pp_ctrl_reg; - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; pps_lock(intel_dp); @@ -2357,7 +2401,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; DRM_DEBUG_KMS("\n"); @@ -2417,7 +2461,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) static void ironlake_edp_pll_on(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *pipe_config) { struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -2622,7 +2666,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, intel_dotclock_calculate(pipe_config->port_clock, &pipe_config->dp_m_n); - if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && + if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { /* * This is a big fat ugly hack. @@ -2644,8 +2688,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder, } static void intel_disable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -2654,7 +2698,7 @@ static void intel_disable_dp(struct intel_encoder *encoder, intel_audio_codec_disable(encoder); if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) - intel_psr_disable(intel_dp); + intel_psr_disable(intel_dp, old_crtc_state); /* Make sure the panel is off before trying to change the mode. But also * ensure that we have vdd while we switch off the panel. */ @@ -2669,8 +2713,8 @@ static void intel_disable_dp(struct intel_encoder *encoder, } static void ilk_post_disable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = dp_to_dig_port(intel_dp)->port; @@ -2683,8 +2727,8 @@ static void ilk_post_disable_dp(struct intel_encoder *encoder, } static void vlv_post_disable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); @@ -2692,8 +2736,8 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder, } static void chv_post_disable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_device *dev = encoder->base.dev; @@ -2798,7 +2842,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, } static void intel_dp_enable_port(struct intel_dp *intel_dp, - struct intel_crtc_state *old_crtc_state) + const struct intel_crtc_state *old_crtc_state) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = to_i915(dev); @@ -2822,8 +2866,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp, } static void intel_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_device *dev = encoder->base.dev; @@ -2870,26 +2914,26 @@ static void intel_enable_dp(struct intel_encoder *encoder, } static void g4x_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { intel_enable_dp(encoder, pipe_config, conn_state); intel_edp_backlight_on(pipe_config, conn_state); } static void vlv_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); intel_edp_backlight_on(pipe_config, conn_state); - intel_psr_enable(intel_dp); + intel_psr_enable(intel_dp, pipe_config); } static void g4x_pre_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = dp_to_dig_port(intel_dp)->port; @@ -2996,7 +3040,7 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) intel_dp->active_pipe = crtc->pipe; - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; /* now it's all ours */ @@ -3011,8 +3055,8 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) } static void vlv_pre_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { vlv_phy_pre_encoder_enable(encoder); @@ -3020,8 +3064,8 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder, } static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { intel_dp_prepare(encoder, pipe_config); @@ -3029,8 +3073,8 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, } static void chv_pre_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { chv_phy_pre_encoder_enable(encoder); @@ -3041,8 +3085,8 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder, } static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { intel_dp_prepare(encoder, pipe_config); @@ -3050,8 +3094,8 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, } static void chv_dp_post_pll_disable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { chv_phy_post_pll_disable(encoder); } @@ -3462,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) uint32_t signal_levels, mask = 0; uint8_t train_set = intel_dp->train_set[0]; - if (HAS_DDI(dev_priv)) { + if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) { + signal_levels = bxt_signal_levels(intel_dp); + } else if (HAS_DDI(dev_priv)) { signal_levels = ddi_signal_levels(intel_dp); - - if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) - signal_levels = 0; - else - mask = DDI_BUF_EMP_MASK; + mask = DDI_BUF_EMP_MASK; } else if (IS_CHERRYVIEW(dev_priv)) { signal_levels = chv_signal_levels(intel_dp); } else if (IS_VALLEYVIEW(dev_priv)) { @@ -3740,7 +3782,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) return false; /* Don't clobber cached eDP rates. */ - if (!is_edp(intel_dp)) { + if (!intel_dp_is_edp(intel_dp)) { intel_dp_set_sink_rates(intel_dp); intel_dp_set_common_rates(intel_dp); } @@ -3762,7 +3804,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) * downstream port information. So, an early return here saves * time from performing other operations which are not required. */ - if (!is_edp(intel_dp) && !intel_dp->sink_count) + if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count) return false; if (!drm_dp_is_branch(intel_dp->dpcd)) @@ -3963,8 +4005,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { int status = 0; - int min_lane_count = 1; - int link_rate_index, test_link_rate; + int test_link_rate; uint8_t test_lane_count, test_link_bw; /* (DP CTS 1.2) * 4.3.1.11 @@ -3978,10 +4019,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) return DP_TEST_NAK; } test_lane_count &= DP_MAX_LANE_COUNT_MASK; - /* Validate the requested lane count */ - if (test_lane_count < min_lane_count || - test_lane_count > intel_dp->max_link_lane_count) - return DP_TEST_NAK; status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, &test_link_bw); @@ -3989,12 +4026,11 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Link Rate read failed\n"); return DP_TEST_NAK; } - /* Validate the requested link rate */ test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); - link_rate_index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - test_link_rate); - if (link_rate_index < 0) + + /* Validate the requested link rate and lane count */ + if (!intel_dp_link_params_valid(intel_dp, test_link_rate, + test_lane_count)) return DP_TEST_NAK; intel_dp->compliance.test_lane_count = test_lane_count; @@ -4263,7 +4299,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) * Validate the cached values of intel_dp->link_rate and * intel_dp->lane_count before attempting to retrain. */ - if (!intel_dp_link_params_valid(intel_dp)) + if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, + intel_dp->lane_count)) return; /* Retrain if Channel EQ or CR not ok */ @@ -4357,7 +4394,7 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp) if (!intel_dp_get_dpcd(intel_dp)) return connector_status_disconnected; - if (is_edp(intel_dp)) + if (intel_dp_is_edp(intel_dp)) return connector_status_connected; /* if there's no downstream port, we're done */ @@ -4566,7 +4603,7 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, enum port port; u32 bit; - intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); + port = intel_hpd_pin_to_port(intel_encoder->hpd_pin); switch (port) { case PORT_A: bit = BXT_DE_PORT_HP_DDIA; @@ -4673,7 +4710,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector) intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain); /* Can't disconnect eDP, but you can close the lid... */ - if (is_edp(intel_dp)) + if (intel_dp_is_edp(intel_dp)) status = edp_detect(intel_dp); else if (intel_digital_port_connected(to_i915(dev), dp_to_dig_port(intel_dp))) @@ -4753,7 +4790,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector) intel_dp->aux.i2c_defer_count = 0; intel_dp_set_edid(intel_dp); - if (is_edp(intel_dp) || intel_connector->detect_edid) + if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid) status = connector_status_connected; intel_dp->detect_done = true; @@ -4837,7 +4874,7 @@ static int intel_dp_get_modes(struct drm_connector *connector) } /* if eDP has no EDID, fall back to fixed mode */ - if (is_edp(intel_attached_dp(connector)) && + if (intel_dp_is_edp(intel_attached_dp(connector)) && intel_connector->panel.fixed_mode) { struct drm_display_mode *mode; @@ -4888,8 +4925,10 @@ intel_dp_connector_destroy(struct drm_connector *connector) if (!IS_ERR_OR_NULL(intel_connector->edid)) kfree(intel_connector->edid); - /* Can't call is_edp() since the encoder may have been destroyed - * already. */ + /* + * Can't call intel_dp_is_edp() since the encoder may have been + * destroyed already. + */ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) intel_panel_fini(&intel_connector->panel); @@ -4903,7 +4942,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) struct intel_dp *intel_dp = &intel_dig_port->dp; intel_dp_mst_encoder_cleanup(intel_dig_port); - if (is_edp(intel_dp)) { + if (intel_dp_is_edp(intel_dp)) { cancel_delayed_work_sync(&intel_dp->panel_vdd_work); /* * vdd might still be enabled do to the delayed vdd off. @@ -4929,7 +4968,7 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return; /* @@ -4997,7 +5036,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) intel_dp->active_pipe = vlv_active_pipe(intel_dp); - if (is_edp(intel_dp)) { + if (intel_dp_is_edp(intel_dp)) { /* Reinit the power sequencer, in case BIOS did something with it. */ intel_dp_pps_init(encoder->dev, intel_dp); intel_edp_panel_vdd_sanitize(intel_dp); @@ -5098,7 +5137,7 @@ put_power: } /* check the VBT to see whether the eDP is on another port */ -bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port) +bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) { /* * eDP not supported on g4x. so bail out early just @@ -5121,7 +5160,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect intel_attach_force_audio_property(connector); intel_attach_broadcast_rgb_property(connector); - if (is_edp(intel_dp)) { + if (intel_dp_is_edp(intel_dp)) { u32 allowed_scalers; allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); @@ -5234,7 +5273,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev, * seems sufficient to avoid this problem. */ if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { - vbt.t11_t12 = max_t(u16, vbt.t11_t12, 800 * 10); + vbt.t11_t12 = max_t(u16, vbt.t11_t12, 900 * 10); DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n", vbt.t11_t12); } @@ -5409,7 +5448,7 @@ static void intel_dp_pps_init(struct drm_device *dev, * The caller of this function needs to take a lock on dev_priv->drrs. */ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, - struct intel_crtc_state *crtc_state, + const struct intel_crtc_state *crtc_state, int refresh_rate) { struct intel_encoder *encoder; @@ -5506,7 +5545,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, * Initializes frontbuffer_bits and drrs.dp */ void intel_edp_drrs_enable(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = to_i915(dev); @@ -5537,7 +5576,7 @@ unlock: * */ void intel_edp_drrs_disable(struct intel_dp *intel_dp, - struct intel_crtc_state *old_crtc_state) + const struct intel_crtc_state *old_crtc_state) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = to_i915(dev); @@ -5780,13 +5819,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct drm_display_mode *fixed_mode = NULL; + struct drm_display_mode *alt_fixed_mode = NULL; struct drm_display_mode *downclock_mode = NULL; bool has_dpcd; struct drm_display_mode *scan; struct edid *edid; enum pipe pipe = INVALID_PIPE; - if (!is_edp(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) return true; /* @@ -5835,13 +5875,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, } intel_connector->edid = edid; - /* prefer fixed mode from EDID if available */ + /* prefer fixed mode from EDID if available, save an alt mode also */ list_for_each_entry(scan, &connector->probed_modes, head) { if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { fixed_mode = drm_mode_duplicate(dev, scan); downclock_mode = intel_dp_drrs_init( intel_connector, fixed_mode); - break; + } else if (!alt_fixed_mode) { + alt_fixed_mode = drm_mode_duplicate(dev, scan); } } @@ -5878,7 +5919,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, pipe_name(pipe)); } - intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); + intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode, + downclock_mode); intel_connector->panel.backlight.power = intel_edp_backlight_power; intel_panel_setup_backlight(connector, pipe); @@ -5904,26 +5946,22 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port) struct intel_encoder *encoder = &intel_dig_port->base; struct intel_dp *intel_dp = &intel_dig_port->dp; + encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port); + switch (intel_dig_port->port) { case PORT_A: - encoder->hpd_pin = HPD_PORT_A; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A; break; case PORT_B: - encoder->hpd_pin = HPD_PORT_B; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B; break; case PORT_C: - encoder->hpd_pin = HPD_PORT_C; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C; break; case PORT_D: - encoder->hpd_pin = HPD_PORT_D; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; break; case PORT_E: - encoder->hpd_pin = HPD_PORT_E; - /* FIXME: Check VBT for actual wiring of PORT E */ intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; break; @@ -6004,7 +6042,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp->DP = I915_READ(intel_dp->output_reg); intel_dp->attached_connector = intel_connector; - if (intel_dp_is_edp(dev_priv, port)) + if (intel_dp_is_port_edp(dev_priv, port)) type = DRM_MODE_CONNECTOR_eDP; else type = DRM_MODE_CONNECTOR_DisplayPort; @@ -6022,7 +6060,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, /* eDP only on port B and/or C on vlv/chv */ if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && - is_edp(intel_dp) && port != PORT_B && port != PORT_C)) + intel_dp_is_edp(intel_dp) && + port != PORT_B && port != PORT_C)) return false; DRM_DEBUG_KMS("Adding %s connector on port %c\n", @@ -6050,7 +6089,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_connector->get_hw_state = intel_connector_get_hw_state; /* init MST on ports that can support it */ - if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) && + if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) && (port == PORT_B || port == PORT_C || port == PORT_D)) intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); @@ -6148,6 +6187,9 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; dev_priv->hotplug.irq_port[port] = intel_dig_port; + if (port != PORT_A) + intel_infoframe_init(intel_dig_port); + if (!intel_dp_init_connector(intel_dig_port, intel_connector)) goto err_init_connector; diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c index b25cd88fc1c5..d2830ba3162e 100644 --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -173,24 +173,6 @@ static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) return true; } -/* -* Set minimum / maximum dynamic brightness percentage. This value is expressed -* as the percentage of normal brightness in 5% increments. -*/ -static bool -intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp, - u32 min, u32 max) -{ - u8 dbc[] = { DIV_ROUND_CLOSEST(min, 5), DIV_ROUND_CLOSEST(max, 5) }; - - if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, - dbc, sizeof(dbc)) < 0) { - DRM_DEBUG_KMS("Failed to write aux DBC brightness level\n"); - return false; - } - return true; -} - static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { @@ -226,14 +208,6 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st if (intel_dp_aux_set_pwm_freq(connector)) new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; - if (i915.enable_dbc && - (intel_dp->edp_dpcd[2] & DP_EDP_DYNAMIC_BACKLIGHT_CAP)) { - if(intel_dp_aux_set_dynamic_backlight_percent(intel_dp, 0, 100)) { - new_dpcd_buf |= DP_EDP_DYNAMIC_BACKLIGHT_ENABLE; - DRM_DEBUG_KMS("Enable dynamic brightness.\n"); - } - } - if (new_dpcd_buf != dpcd_buf) { if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) { @@ -277,66 +251,15 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector) /* Check the eDP Display control capabilities registers to determine if * the panel can support backlight control over the aux channel */ - if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) && - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) { + if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP && + (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) && + !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { DRM_DEBUG_KMS("AUX Backlight Control Supported!\n"); return true; } return false; } -/* - * Heuristic function whether we should use AUX for backlight adjustment or not. - * - * We should use AUX for backlight brightness adjustment if panel doesn't this - * via PWM pin or using AUX is better than using PWM pin. - * - * The heuristic to determine that using AUX pin is better than using PWM pin is - * that the panel support any of the feature list here. - * - Regional backlight brightness adjustment - * - Backlight PWM frequency set - * - More than 8 bits resolution of brightness level - * - Backlight enablement via AUX and not by BL_ENABLE pin - * - * If all above are not true, assume that using PWM pin is better. - */ -static bool -intel_dp_aux_display_control_heuristic(struct intel_connector *connector) -{ - struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); - uint8_t reg_val; - - /* Panel doesn't support adjusting backlight brightness via PWN pin */ - if (!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) - return true; - - /* Panel supports regional backlight brightness adjustment */ - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_GENERAL_CAP_3, - ®_val) != 1) { - DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", - DP_EDP_GENERAL_CAP_3); - return false; - } - if (reg_val > 0) - return true; - - /* Panel supports backlight PWM frequency set */ - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) - return true; - - /* Panel supports more than 8 bits resolution of brightness level */ - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) - return true; - - /* Panel supports enabling backlight via AUX but not by BL_ENABLE pin */ - if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) && - !(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP)) - return true; - - return false; - -} - int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) { struct intel_panel *panel = &intel_connector->panel; @@ -347,10 +270,6 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) if (!intel_dp_aux_display_control_capable(intel_connector)) return -ENODEV; - if (i915.enable_dpcd_backlight == -1 && - !intel_dp_aux_display_control_heuristic(intel_connector)) - return -ENODEV; - panel->backlight.setup = intel_dp_aux_setup_backlight; panel->backlight.enable = intel_dp_aux_enable_backlight; panel->backlight.disable = intel_dp_aux_disable_backlight; diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index b79c1c0e404c..05907fa8a553 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -321,12 +321,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) if (!intel_dp_link_training_channel_equalization(intel_dp)) goto failure_handling; - DRM_DEBUG_KMS("Link Training Passed at Link Rate = %d, Lane count = %d", + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, intel_dp->link_rate, intel_dp->lane_count); return; failure_handling: - DRM_DEBUG_KMS("Link Training failed at link rate = %d, lane count = %d", + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, intel_dp->link_rate, intel_dp->lane_count); if (!intel_dp_get_link_train_fallback_values(intel_dp, intel_dp->link_rate, diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 58568559711a..8e3aad0ea60b 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -123,8 +123,8 @@ static int intel_dp_mst_atomic_check(struct drm_connector *connector, } static void intel_mst_disable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); struct intel_digital_port *intel_dig_port = intel_mst->primary; @@ -146,8 +146,8 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder, } static void intel_mst_post_disable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); struct intel_digital_port *intel_dig_port = intel_mst->primary; @@ -176,8 +176,8 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, } static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); struct intel_digital_port *intel_dig_port = intel_mst->primary; @@ -219,8 +219,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, } static void intel_mst_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); struct intel_digital_port *intel_dig_port = intel_mst->primary; @@ -370,6 +370,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, int bpp = 24; /* MST uses fixed bpp */ int max_rate, mode_rate, max_lanes, max_link_clock; + if (!intel_dp) + return MODE_ERROR; + max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 2f7b0e64f628..a2a3d93d67bd 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2379,6 +2379,15 @@ cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, return pll; } +static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, + struct intel_dpll_hw_state *hw_state) +{ + DRM_DEBUG_KMS("dpll_hw_state: " + "cfgcr0: 0x%x, cfgcr1: 0x%x\n", + hw_state->cfgcr0, + hw_state->cfgcr1); +} + static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { .enable = cnl_ddi_pll_enable, .disable = cnl_ddi_pll_disable, @@ -2395,7 +2404,7 @@ static const struct dpll_info cnl_plls[] = { static const struct intel_dpll_mgr cnl_pll_mgr = { .dpll_info = cnl_plls, .get_dpll = cnl_get_dpll, - .dump_hw_state = skl_dump_hw_state, + .dump_hw_state = cnl_dump_hw_state, }; /** diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 210a8c63bde8..463ed152e6b1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -220,23 +220,23 @@ struct intel_encoder { struct intel_crtc_state *, struct drm_connector_state *); void (*pre_pll_enable)(struct intel_encoder *, - struct intel_crtc_state *, - struct drm_connector_state *); + const struct intel_crtc_state *, + const struct drm_connector_state *); void (*pre_enable)(struct intel_encoder *, - struct intel_crtc_state *, - struct drm_connector_state *); + const struct intel_crtc_state *, + const struct drm_connector_state *); void (*enable)(struct intel_encoder *, - struct intel_crtc_state *, - struct drm_connector_state *); + const struct intel_crtc_state *, + const struct drm_connector_state *); void (*disable)(struct intel_encoder *, - struct intel_crtc_state *, - struct drm_connector_state *); + const struct intel_crtc_state *, + const struct drm_connector_state *); void (*post_disable)(struct intel_encoder *, - struct intel_crtc_state *, - struct drm_connector_state *); + const struct intel_crtc_state *, + const struct drm_connector_state *); void (*post_pll_disable)(struct intel_encoder *, - struct intel_crtc_state *, - struct drm_connector_state *); + const struct intel_crtc_state *, + const struct drm_connector_state *); /* Read out the current hw state of this connector, returning true if * the encoder is active. If the encoder is enabled it also set the pipe * it is connected to in the pipe parameter. */ @@ -265,6 +265,7 @@ struct intel_encoder { struct intel_panel { struct drm_display_mode *fixed_mode; + struct drm_display_mode *alt_fixed_mode; struct drm_display_mode *downclock_mode; /* backlight */ @@ -383,7 +384,8 @@ struct intel_atomic_state { unsigned int active_pipe_changes; unsigned int active_crtcs; - unsigned int min_pixclk[I915_MAX_PIPES]; + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; @@ -752,6 +754,7 @@ struct intel_crtc_state { struct intel_link_m_n fdi_m_n; bool ips_enabled; + bool ips_force_disable; bool enable_fbc; @@ -780,6 +783,9 @@ struct intel_crtc_state { /* HDMI High TMDS char rate ratio */ bool hdmi_high_tmds_clock_ratio; + + /* output format is YCBCR 4:2:0 */ + bool ycbcr420; }; struct intel_crtc { @@ -796,9 +802,6 @@ struct intel_crtc { u8 plane_ids_mask; unsigned long long enabled_power_domains; struct intel_overlay *overlay; - struct intel_flip_work *flip_work; - - atomic_t unpin_work_count; /* Display surface base address adjustement for pageflips. Note that on * gen4+ this only adjusts up to a tile, offsets within a tile are @@ -908,16 +911,6 @@ struct intel_hdmi { bool has_audio; bool rgb_quant_range_selectable; struct intel_connector *attached_connector; - void (*write_infoframe)(struct drm_encoder *encoder, - const struct intel_crtc_state *crtc_state, - enum hdmi_infoframe_type type, - const void *frame, ssize_t len); - void (*set_infoframes)(struct drm_encoder *encoder, - bool enable, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state); - bool (*infoframe_enabled)(struct drm_encoder *encoder, - const struct intel_crtc_state *pipe_config); }; struct intel_dp_mst_encoder; @@ -1068,6 +1061,17 @@ struct intel_digital_port { bool release_cl2_override; uint8_t max_lanes; enum intel_display_power_domain ddi_io_power_domain; + + void (*write_infoframe)(struct drm_encoder *encoder, + const struct intel_crtc_state *crtc_state, + enum hdmi_infoframe_type type, + const void *frame, ssize_t len); + void (*set_infoframes)(struct drm_encoder *encoder, + bool enable, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); + bool (*infoframe_enabled)(struct drm_encoder *encoder, + const struct intel_crtc_state *pipe_config); }; struct intel_dp_mst_encoder { @@ -1131,24 +1135,6 @@ intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane) return dev_priv->plane_to_crtc_mapping[plane]; } -struct intel_flip_work { - struct work_struct unpin_work; - struct work_struct mmio_work; - - struct drm_crtc *crtc; - struct i915_vma *old_vma; - struct drm_framebuffer *old_fb; - struct drm_i915_gem_object *pending_flip_obj; - struct drm_pending_vblank_event *event; - atomic_t pending; - u32 flip_count; - u32 gtt_offset; - struct drm_i915_gem_request *flip_queued_req; - u32 flip_queued_vblank; - u32 flip_ready_vblank; - unsigned int rotation; -}; - struct intel_load_detect_pipe { struct drm_atomic_state *restore_state; }; @@ -1206,27 +1192,48 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) return container_of(intel_hdmi, struct intel_digital_port, hdmi); } +static inline struct intel_plane_state * +intel_atomic_get_new_plane_state(struct intel_atomic_state *state, + struct intel_plane *plane) +{ + return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, + &plane->base)); +} + +static inline struct intel_crtc_state * +intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, + &crtc->base)); +} + +static inline struct intel_crtc_state * +intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, + &crtc->base)); +} + /* intel_fifo_underrun.c */ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable); bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable); void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe); void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder); + enum pipe pch_transcoder); void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); /* i915_irq.c */ void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); -void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask); void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); -void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); -void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); @@ -1250,9 +1257,9 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) int intel_get_crtc_scanline(struct intel_crtc *crtc); void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask); + u8 pipe_mask); void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask); + u8 pipe_mask); void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); @@ -1263,8 +1270,8 @@ void intel_crt_reset(struct drm_encoder *encoder); /* intel_ddi.c */ void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state); + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state); void hsw_fdi_link_train(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); @@ -1289,6 +1296,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, bool state); +u32 bxt_signal_levels(struct intel_dp *intel_dp); uint32_t ddi_signal_levels(struct intel_dp *intel_dp); u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); @@ -1307,6 +1315,7 @@ void intel_audio_init(struct drm_i915_private *dev_priv); void intel_audio_deinit(struct drm_i915_private *dev_priv); /* intel_cdclk.c */ +int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); void skl_init_cdclk(struct drm_i915_private *dev_priv); void skl_uninit_cdclk(struct drm_i915_private *dev_priv); void cnl_init_cdclk(struct drm_i915_private *dev_priv); @@ -1325,7 +1334,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, /* intel_display.c */ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc); +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); void intel_update_rawclk(struct drm_i915_private *dev_priv); int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); int vlv_get_cck_clock(struct drm_i915_private *dev_priv, @@ -1334,7 +1343,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, const char *name, u32 reg); void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); void lpt_disable_iclkip(struct drm_i915_private *dev_priv); -extern const struct drm_plane_funcs intel_plane_funcs; void intel_init_display_hooks(struct drm_i915_private *dev_priv); unsigned int intel_fb_xy_to_linear(int x, int y, const struct intel_plane_state *state, @@ -1395,7 +1403,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, struct intel_digital_port *dport, unsigned int expected_mask); int intel_get_load_detect_pipe(struct drm_connector *connector, - struct drm_display_mode *mode, + const struct drm_display_mode *mode, struct intel_load_detect_pipe *old, struct drm_modeset_acquire_ctx *ctx); void intel_release_load_detect_pipe(struct drm_connector *connector, @@ -1407,9 +1415,6 @@ void intel_unpin_fb_vma(struct i915_vma *vma); struct drm_framebuffer * intel_framebuffer_create(struct drm_i915_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd); -void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe); -void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe); -void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe); int intel_prepare_plane_fb(struct drm_plane *plane, struct drm_plane_state *new_state); void intel_cleanup_plane_fb(struct drm_plane *plane, @@ -1422,7 +1427,9 @@ int intel_plane_atomic_set_property(struct drm_plane *plane, struct drm_plane_state *state, struct drm_property *property, uint64_t val); -int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, +int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, + struct drm_crtc_state *crtc_state, + const struct intel_plane_state *old_plane_state, struct drm_plane_state *plane_state); void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, @@ -1520,7 +1527,8 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); -bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port); +bool intel_dp_is_edp(struct intel_dp *intel_dp); +bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd); void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, @@ -1539,9 +1547,9 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); void intel_plane_destroy(struct drm_plane *plane); void intel_edp_drrs_enable(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state); + const struct intel_crtc_state *crtc_state); void intel_edp_drrs_disable(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state); + const struct intel_crtc_state *crtc_state); void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits); void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, @@ -1596,7 +1604,8 @@ void intel_hpd_poll_init(struct drm_i915_private *dev_priv); #ifdef CONFIG_DRM_FBDEV_EMULATION extern int intel_fbdev_init(struct drm_device *dev); extern void intel_fbdev_initial_config_async(struct drm_device *dev); -extern void intel_fbdev_fini(struct drm_device *dev); +extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv); +extern void intel_fbdev_fini(struct drm_i915_private *dev_priv); extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); extern void intel_fbdev_output_poll_changed(struct drm_device *dev); extern void intel_fbdev_restore_mode(struct drm_device *dev); @@ -1610,7 +1619,11 @@ static inline void intel_fbdev_initial_config_async(struct drm_device *dev) { } -static inline void intel_fbdev_fini(struct drm_device *dev) +static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) +{ +} + +static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) { } @@ -1664,6 +1677,7 @@ void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder, bool high_tmds_clock_ratio, bool scrambling); void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); +void intel_infoframe_init(struct intel_digital_port *intel_dig_port); /* intel_lvds.c */ @@ -1695,6 +1709,7 @@ void intel_overlay_reset(struct drm_i915_private *dev_priv); /* intel_panel.c */ int intel_panel_init(struct intel_panel *panel, struct drm_display_mode *fixed_mode, + struct drm_display_mode *alt_fixed_mode, struct drm_display_mode *downclock_mode); void intel_panel_fini(struct intel_panel *panel); void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, @@ -1734,8 +1749,10 @@ static inline void intel_backlight_device_unregister(struct intel_connector *con /* intel_psr.c */ -void intel_psr_enable(struct intel_dp *intel_dp); -void intel_psr_disable(struct intel_dp *intel_dp); +void intel_psr_enable(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); +void intel_psr_disable(struct intel_dp *intel_dp, + const struct intel_crtc_state *old_crtc_state); void intel_psr_invalidate(struct drm_i915_private *dev_priv, unsigned frontbuffer_bits); void intel_psr_flush(struct drm_i915_private *dev_priv, @@ -1859,7 +1876,6 @@ void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); void gen6_rps_idle(struct drm_i915_private *dev_priv); void gen6_rps_boost(struct drm_i915_gem_request *rq, struct intel_rps_client *rps); -void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req); void g4x_wm_get_hw_state(struct drm_device *dev); void vlv_wm_get_hw_state(struct drm_device *dev); void ilk_wm_get_hw_state(struct drm_device *dev); @@ -1899,8 +1915,8 @@ struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, int plane); int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); -void intel_pipe_update_start(struct intel_crtc *crtc); -void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work); +void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state); +void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state); /* intel_tv.c */ void intel_tv_init(struct drm_i915_private *dev_priv); @@ -1972,7 +1988,9 @@ struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); void intel_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state); extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; -int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state, +int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state, + struct intel_crtc_state *crtc_state, + const struct intel_plane_state *old_plane_state, struct intel_plane_state *intel_state); /* intel_color.c */ diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index b0b3adf016f8..fc25d7d2d942 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -731,7 +731,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) } static void intel_dsi_prepare(struct intel_encoder *intel_encoder, - struct intel_crtc_state *pipe_config); + const struct intel_crtc_state *pipe_config); static void intel_dsi_unprepare(struct intel_encoder *encoder); static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) @@ -783,8 +783,8 @@ static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) */ static void intel_dsi_pre_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -878,8 +878,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, * the pre_enable hook. */ static void intel_dsi_enable_nop(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { DRM_DEBUG_KMS("\n"); } @@ -889,11 +889,9 @@ static void intel_dsi_enable_nop(struct intel_encoder *encoder, * the post_disable hook. */ static void intel_dsi_disable(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); enum port port; @@ -903,15 +901,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder, intel_panel_disable_backlight(old_conn_state); /* - * Disable Device ready before the port shutdown in order - * to avoid split screen - */ - if (IS_BROXTON(dev_priv)) { - for_each_dsi_port(port, intel_dsi->ports) - I915_WRITE(MIPI_DEVICE_READY(port), 0); - } - - /* * According to the spec we should send SHUTDOWN before * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing * has shown that the v3 sequence works for v2 VBTs too @@ -936,8 +925,8 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) } static void intel_dsi_post_disable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -1077,7 +1066,7 @@ out_put_power: } static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) + struct intel_crtc_state *pipe_config) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -1381,7 +1370,7 @@ static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) } static void intel_dsi_prepare(struct intel_encoder *intel_encoder, - struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *pipe_config) { struct drm_encoder *encoder = &intel_encoder->base; struct drm_device *dev = encoder->dev; @@ -1849,7 +1838,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv) connector->display_info.width_mm = fixed_mode->width_mm; connector->display_info.height_mm = fixed_mode->height_mm; - intel_panel_init(&intel_connector->panel, fixed_mode, NULL); + intel_panel_init(&intel_connector->panel, fixed_mode, NULL, NULL); intel_panel_setup_backlight(connector, INVALID_PIPE); intel_dsi_add_properties(intel_connector); diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c index 6e09ceb71500..150a156f3b1e 100644 --- a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c +++ b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c @@ -46,7 +46,7 @@ static u32 dcs_get_backlight(struct intel_connector *connector) struct intel_encoder *encoder = connector->encoder; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct mipi_dsi_device *dsi_device; - u8 data; + u8 data = 0; enum port port; /* FIXME: Need to take care of 16 bit brightness level */ diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c index 7158c7ce9c09..91c07b0c8db9 100644 --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c @@ -306,7 +306,7 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, if (!gpio_desc) { gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, - "panel", gpio_index, + NULL, gpio_index, value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH); diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index baf369d2de30..5c562e1f56ae 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -175,8 +175,8 @@ static void intel_dvo_get_config(struct intel_encoder *encoder, } static void intel_disable_dvo(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dvo *intel_dvo = enc_to_dvo(encoder); @@ -189,8 +189,8 @@ static void intel_disable_dvo(struct intel_encoder *encoder, } static void intel_enable_dvo(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dvo *intel_dvo = enc_to_dvo(encoder); @@ -258,8 +258,8 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder, } static void intel_dvo_pre_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); @@ -552,7 +552,7 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) */ intel_panel_init(&intel_connector->panel, intel_dvo_get_current_mode(connector), - NULL); + NULL, NULL); intel_dvo->panel_wants_dither = true; } diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 24db316e0fd1..b8e9a234af2d 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -337,9 +337,6 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) { struct drm_i915_private *dev_priv = engine->i915; - GEM_BUG_ON(!intel_engine_is_idle(engine)); - GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request)); - /* Our semaphore implementation is strictly monotonic (i.e. we proceed * so long as the semaphore value in the register/page is greater * than the sync value), so whenever we reset the seqno, @@ -1068,6 +1065,51 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) return 0; } +static int cnl_init_workarounds(struct intel_engine_cs *engine) +{ + struct drm_i915_private *dev_priv = engine->i915; + int ret; + + /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0)) + WA_SET_BIT(GAMT_CHKN_BIT_REG, + GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT); + + /* WaForceContextSaveRestoreNonCoherent:cnl */ + WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + + /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0)) + WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5); + + /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); + + /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0)) + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, + GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE); + + /* WaInPlaceDecompressionHang:cnl */ + WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); + + /* WaPushConstantDereferenceHoldDisable:cnl */ + WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); + + /* FtrEnableFastAnisoL1BankingFix: cnl */ + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); + + /* WaEnablePreemptionGranularityControlByUMD:cnl */ + ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); + if (ret) + return ret; + + return 0; +} + static int kbl_init_workarounds(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1188,6 +1230,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine) err = glk_init_workarounds(engine); else if (IS_COFFEELAKE(dev_priv)) err = cfl_init_workarounds(engine); + else if (IS_CANNONLAKE(dev_priv)) + err = cnl_init_workarounds(engine); else err = 0; if (err) @@ -1283,6 +1327,10 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) if (port_request(&engine->execlist_port[0])) return false; + /* ELSP is empty, but there are ready requests? */ + if (READ_ONCE(engine->execlist_first)) + return false; + /* Ring stopped? */ if (!ring_is_idle(engine)) return false; @@ -1334,6 +1382,21 @@ void intel_engines_mark_idle(struct drm_i915_private *i915) } } +bool intel_engine_can_store_dword(struct intel_engine_cs *engine) +{ + switch (INTEL_GEN(engine->i915)) { + case 2: + return false; /* uses physical not virtual addresses */ + case 3: + /* maybe only uses physical not virtual addresses */ + return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); + case 6: + return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ + default: + return true; + } +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/mock_engine.c" #endif diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 860b8c26d29b..58a772de6672 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -291,6 +291,19 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; + /* Display WA #0529: skl, kbl, bxt. */ + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) { + u32 val = I915_READ(CHICKEN_MISC_4); + + val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); + + if (i915_gem_object_get_tiling(params->vma->obj) != + I915_TILING_X) + val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride; + + I915_WRITE(CHICKEN_MISC_4, val); + } + dpfc_ctl = 0; if (IS_IVYBRIDGE(dev_priv)) dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane); @@ -406,9 +419,7 @@ static void intel_fbc_work_fn(struct work_struct *__work) struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe]; if (drm_crtc_vblank_get(&crtc->base)) { - DRM_ERROR("vblank not available for FBC on pipe %c\n", - pipe_name(crtc->pipe)); - + /* CRTC is now off, leave FBC deactivated */ mutex_lock(&fbc->lock); work->scheduled = false; mutex_unlock(&fbc->lock); @@ -461,6 +472,8 @@ static void intel_fbc_schedule_activation(struct intel_crtc *crtc) struct intel_fbc_work *work = &fbc->work; WARN_ON(!mutex_is_locked(&fbc->lock)); + if (WARN_ON(!fbc->enabled)) + return; if (drm_crtc_vblank_get(&crtc->base)) { DRM_ERROR("vblank not available for FBC on pipe %c\n", @@ -881,6 +894,10 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->fb.stride = cache->fb.stride; params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); + + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) + params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, + 32 * fbc->threshold) * 8; } static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1, @@ -1216,7 +1233,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work) mutex_lock(&fbc->lock); /* Maybe we were scheduled twice. */ - if (fbc->underrun_detected) + if (fbc->underrun_detected || !fbc->enabled) goto out; DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n"); diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 0986ca4f16f1..f2bb8116227c 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -206,6 +206,7 @@ static int intelfb_create(struct drm_fb_helper *helper, } mutex_lock(&dev->struct_mutex); + intel_runtime_pm_get(dev_priv); /* Pin the GGTT vma for our access via info->screen_base. * This also validates that any existing fb inherited from the @@ -269,6 +270,7 @@ static int intelfb_create(struct drm_fb_helper *helper, fb->width, fb->height, i915_ggtt_offset(vma)); ifbdev->vma = vma; + intel_runtime_pm_put(dev_priv); mutex_unlock(&dev->struct_mutex); vga_switcheroo_client_fb_set(pdev, info); return 0; @@ -276,6 +278,7 @@ static int intelfb_create(struct drm_fb_helper *helper, out_unpin: intel_unpin_fb_vma(vma); out_unlock: + intel_runtime_pm_put(dev_priv); mutex_unlock(&dev->struct_mutex); return ret; } @@ -507,8 +510,6 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev) * trying to rectify all the possible error paths leading here. */ - drm_fb_helper_unregister_fbi(&ifbdev->helper); - drm_fb_helper_fini(&ifbdev->helper); if (ifbdev->vma) { @@ -696,8 +697,10 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie) /* Due to peculiar init order wrt to hpd handling this is separate. */ if (drm_fb_helper_initial_config(&ifbdev->helper, - ifbdev->preferred_bpp)) - intel_fbdev_fini(ifbdev->helper.dev); + ifbdev->preferred_bpp)) { + intel_fbdev_unregister(to_i915(ifbdev->helper.dev)); + intel_fbdev_fini(to_i915(ifbdev->helper.dev)); + } } void intel_fbdev_initial_config_async(struct drm_device *dev) @@ -720,9 +723,8 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev) ifbdev->cookie = 0; } -void intel_fbdev_fini(struct drm_device *dev) +void intel_fbdev_unregister(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_fbdev *ifbdev = dev_priv->fbdev; if (!ifbdev) @@ -732,8 +734,17 @@ void intel_fbdev_fini(struct drm_device *dev) if (!current_is_async()) intel_fbdev_sync(ifbdev); + drm_fb_helper_unregister_fbi(&ifbdev->helper); +} + +void intel_fbdev_fini(struct drm_i915_private *dev_priv) +{ + struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev); + + if (!ifbdev) + return; + intel_fbdev_destroy(ifbdev); - dev_priv->fbdev = NULL; } void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index d484862cc7df..04689600e337 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -187,11 +187,11 @@ static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, } static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable) { struct drm_i915_private *dev_priv = to_i915(dev); - uint32_t bit = (pch_transcoder == TRANSCODER_A) ? + uint32_t bit = (pch_transcoder == PIPE_A) ? SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; if (enable) @@ -203,7 +203,7 @@ static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum transcoder pch_transcoder = (enum transcoder) crtc->pipe; + enum pipe pch_transcoder = crtc->pipe; uint32_t serr_int = I915_READ(SERR_INT); lockdep_assert_held(&dev_priv->irq_lock); @@ -215,12 +215,12 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) POSTING_READ(SERR_INT); trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); - DRM_ERROR("pch fifo underrun on pch transcoder %s\n", - transcoder_name(pch_transcoder)); + DRM_ERROR("pch fifo underrun on pch transcoder %c\n", + pipe_name(pch_transcoder)); } static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable, bool old) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -238,8 +238,8 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, if (old && I915_READ(SERR_INT) & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { - DRM_ERROR("uncleared pch fifo underrun on pch transcoder %s\n", - transcoder_name(pch_transcoder)); + DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", + pipe_name(pch_transcoder)); } } } @@ -313,11 +313,11 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, * Returns the previous state of underrun reporting. */ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable) { struct intel_crtc *crtc = - intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder); + intel_get_crtc_for_pipe(dev_priv, pch_transcoder); unsigned long flags; bool old; @@ -390,13 +390,13 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, * interrupt to avoid an irq storm. */ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder) + enum pipe pch_transcoder) { if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, false)) { trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); - DRM_ERROR("PCH transcoder %s FIFO underrun\n", - transcoder_name(pch_transcoder)); + DRM_ERROR("PCH transcoder %c FIFO underrun\n", + pipe_name(pch_transcoder)); } } diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index 9b0ece427bdc..d9d87d96fb69 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -324,7 +324,7 @@ hangcheck_get_action(struct intel_engine_cs *engine, if (engine->hangcheck.seqno != hc->seqno) return ENGINE_ACTIVE_SEQNO; - if (i915_seqno_passed(hc->seqno, intel_engine_last_submit(engine))) + if (intel_engine_is_idle(engine)) return ENGINE_IDLE; return engine_stuck(engine, hc->acthd); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index eb0c559b66c1..e6f8f30ce7bd 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -434,7 +434,7 @@ static void intel_write_infoframe(struct drm_encoder *encoder, const struct intel_crtc_state *crtc_state, union hdmi_infoframe *frame) { - struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); uint8_t buffer[VIDEO_DIP_DATA_SIZE]; ssize_t len; @@ -450,7 +450,7 @@ static void intel_write_infoframe(struct drm_encoder *encoder, buffer[3] = 0; len++; - intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); + intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); } static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, @@ -472,12 +472,18 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, return; } + if (crtc_state->ycbcr420) + frame.avi.colorspace = HDMI_COLORSPACE_YUV420; + else + frame.avi.colorspace = HDMI_COLORSPACE_RGB; + drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, crtc_state->limited_color_range ? HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL, intel_hdmi->rgb_quant_range_selectable); + /* TODO: handle pixel repetition for YCBCR420 outputs */ intel_write_infoframe(encoder, crtc_state, &frame); } @@ -939,6 +945,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); + struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); u32 tmp, flags = 0; @@ -959,7 +966,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, if (tmp & HDMI_MODE_SELECT_HDMI) pipe_config->has_hdmi_sink = true; - if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) + if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) pipe_config->has_infoframe = true; if (tmp & SDVO_AUDIO_ENABLE) @@ -985,8 +992,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, } static void intel_enable_hdmi_audio(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); @@ -997,8 +1004,8 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder, } static void g4x_enable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -1019,8 +1026,8 @@ static void g4x_enable_hdmi(struct intel_encoder *encoder, } static void ibx_enable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -1069,8 +1076,8 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, } static void cpt_enable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -1124,18 +1131,20 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, } static void vlv_enable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { } static void intel_disable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); + struct intel_digital_port *intel_dig_port = + hdmi_to_dig_port(intel_hdmi); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); u32 temp; @@ -1178,14 +1187,15 @@ static void intel_disable_hdmi(struct intel_encoder *encoder, intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } - intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state); + intel_dig_port->set_infoframes(&encoder->base, false, + old_crtc_state, old_conn_state); intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); } static void g4x_disable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder); @@ -1194,16 +1204,16 @@ static void g4x_disable_hdmi(struct intel_encoder *encoder, } static void pch_disable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder); } static void pch_post_disable_hdmi(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); } @@ -1295,6 +1305,9 @@ intel_hdmi_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) clock *= 2; + if (drm_mode_is_420_only(&connector->display_info, mode)) + clock /= 2; + /* check if we can do 8bpc */ status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); @@ -1305,7 +1318,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, return status; } -static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) +static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); @@ -1330,8 +1343,15 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) if (connector_state->crtc != crtc_state->base.crtc) continue; - if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0) - return false; + if (crtc_state->ycbcr420) { + const struct drm_hdmi_info *hdmi = &info->hdmi; + + if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) + return false; + } else { + if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36)) + return false; + } } /* Display Wa #1139 */ @@ -1342,6 +1362,36 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) return true; } +static bool +intel_hdmi_ycbcr420_config(struct drm_connector *connector, + struct intel_crtc_state *config, + int *clock_12bpc, int *clock_8bpc) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); + + if (!connector->ycbcr_420_allowed) { + DRM_ERROR("Platform doesn't support YCBCR420 output\n"); + return false; + } + + /* YCBCR420 TMDS rate requirement is half the pixel clock */ + config->port_clock /= 2; + *clock_12bpc /= 2; + *clock_8bpc /= 2; + config->ycbcr420 = true; + + /* YCBCR 420 output conversion needs a scaler */ + if (skl_update_scaler_crtc(config)) { + DRM_DEBUG_KMS("Scaler allocation for output failed\n"); + return false; + } + + intel_pch_panel_fitting(intel_crtc, config, + DRM_MODE_SCALE_FULLSCREEN); + + return true; +} + bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) @@ -1349,7 +1399,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; - struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; + struct drm_connector *connector = conn_state->connector; + struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; struct intel_digital_connector_state *intel_conn_state = to_intel_digital_connector_state(conn_state); int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; @@ -1379,6 +1430,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, clock_12bpc *= 2; } + if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { + if (!intel_hdmi_ycbcr420_config(connector, pipe_config, + &clock_12bpc, &clock_8bpc)) { + DRM_ERROR("Can't support YCBCR420 output\n"); + return false; + } + } + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) pipe_config->has_pch_encoder = true; @@ -1587,24 +1646,24 @@ static int intel_hdmi_get_modes(struct drm_connector *connector) } static void intel_hdmi_pre_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { - struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); + struct intel_digital_port *intel_dig_port = + enc_to_dig_port(&encoder->base); intel_hdmi_prepare(encoder, pipe_config); - intel_hdmi->set_infoframes(&encoder->base, - pipe_config->has_hdmi_sink, - pipe_config, conn_state); + intel_dig_port->set_infoframes(&encoder->base, + pipe_config->has_infoframe, + pipe_config, conn_state); } static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); - struct intel_hdmi *intel_hdmi = &dport->hdmi; struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -1614,9 +1673,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 0x2b247878); - intel_hdmi->set_infoframes(&encoder->base, - pipe_config->has_hdmi_sink, - pipe_config, conn_state); + dport->set_infoframes(&encoder->base, + pipe_config->has_infoframe, + pipe_config, conn_state); g4x_enable_hdmi(encoder, pipe_config, conn_state); @@ -1624,8 +1683,8 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, } static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { intel_hdmi_prepare(encoder, pipe_config); @@ -1633,8 +1692,8 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, } static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { intel_hdmi_prepare(encoder, pipe_config); @@ -1642,23 +1701,23 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, } static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { chv_phy_post_pll_disable(encoder); } static void vlv_hdmi_post_disable(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { /* Reset lanes to avoid HDMI flicker (VLV w/a) */ vlv_phy_reset_lanes(encoder); } static void chv_hdmi_post_disable(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -1672,11 +1731,10 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder, } static void chv_hdmi_pre_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); - struct intel_hdmi *intel_hdmi = &dport->hdmi; struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -1686,9 +1744,9 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder, /* Use 800mV-0dB */ chv_set_phy_signal_level(encoder, 128, 102, false); - intel_hdmi->set_infoframes(&encoder->base, - pipe_config->has_hdmi_sink, - pipe_config, conn_state); + dport->set_infoframes(&encoder->base, + pipe_config->has_infoframe, + pipe_config, conn_state); g4x_enable_hdmi(encoder, pipe_config, conn_state); @@ -1788,52 +1846,149 @@ void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, DRM_DEBUG_KMS("sink scrambling handled\n"); } -static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, - enum port port) +static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { - const struct ddi_vbt_port_info *info = - &dev_priv->vbt.ddi_port_info[port]; u8 ddc_pin; - if (info->alternate_ddc_pin) { - DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", - info->alternate_ddc_pin, port_name(port)); - return info->alternate_ddc_pin; + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_DPB; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_DPC; + break; + case PORT_D: + ddc_pin = GMBUS_PIN_DPD_CHV; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_DPB; + break; } + return ddc_pin; +} + +static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + u8 ddc_pin; switch (port) { case PORT_B: - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_1_BXT; - else - ddc_pin = GMBUS_PIN_DPB; + ddc_pin = GMBUS_PIN_1_BXT; break; case PORT_C: - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_2_BXT; - else - ddc_pin = GMBUS_PIN_DPC; + ddc_pin = GMBUS_PIN_2_BXT; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_1_BXT; + break; + } + return ddc_pin; +} + +static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_1_BXT; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_2_BXT; break; case PORT_D: - if (HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_4_CNP; - else if (IS_CHERRYVIEW(dev_priv)) - ddc_pin = GMBUS_PIN_DPD_CHV; - else - ddc_pin = GMBUS_PIN_DPD; + ddc_pin = GMBUS_PIN_4_CNP; break; default: MISSING_CASE(port); + ddc_pin = GMBUS_PIN_1_BXT; + break; + } + return ddc_pin; +} + +static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: ddc_pin = GMBUS_PIN_DPB; break; + case PORT_C: + ddc_pin = GMBUS_PIN_DPC; + break; + case PORT_D: + ddc_pin = GMBUS_PIN_DPD; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_DPB; + break; + } + return ddc_pin; +} + +static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + const struct ddi_vbt_port_info *info = + &dev_priv->vbt.ddi_port_info[port]; + u8 ddc_pin; + + if (info->alternate_ddc_pin) { + DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", + info->alternate_ddc_pin, port_name(port)); + return info->alternate_ddc_pin; } + if (IS_CHERRYVIEW(dev_priv)) + ddc_pin = chv_port_to_ddc_pin(dev_priv, port); + else if (IS_GEN9_LP(dev_priv)) + ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); + else if (HAS_PCH_CNP(dev_priv)) + ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); + else + ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); + DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", ddc_pin, port_name(port)); return ddc_pin; } +void intel_infoframe_init(struct intel_digital_port *intel_dig_port) +{ + struct drm_i915_private *dev_priv = + to_i915(intel_dig_port->base.base.dev); + + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + intel_dig_port->write_infoframe = vlv_write_infoframe; + intel_dig_port->set_infoframes = vlv_set_infoframes; + intel_dig_port->infoframe_enabled = vlv_infoframe_enabled; + } else if (IS_G4X(dev_priv)) { + intel_dig_port->write_infoframe = g4x_write_infoframe; + intel_dig_port->set_infoframes = g4x_set_infoframes; + intel_dig_port->infoframe_enabled = g4x_infoframe_enabled; + } else if (HAS_DDI(dev_priv)) { + intel_dig_port->write_infoframe = hsw_write_infoframe; + intel_dig_port->set_infoframes = hsw_set_infoframes; + intel_dig_port->infoframe_enabled = hsw_infoframe_enabled; + } else if (HAS_PCH_IBX(dev_priv)) { + intel_dig_port->write_infoframe = ibx_write_infoframe; + intel_dig_port->set_infoframes = ibx_set_infoframes; + intel_dig_port->infoframe_enabled = ibx_infoframe_enabled; + } else { + intel_dig_port->write_infoframe = cpt_write_infoframe; + intel_dig_port->set_infoframes = cpt_set_infoframes; + intel_dig_port->infoframe_enabled = cpt_infoframe_enabled; + } +} + void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector) { @@ -1860,47 +2015,14 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, connector->doublescan_allowed = 0; connector->stereo_allowed = 1; + if (IS_GEMINILAKE(dev_priv)) + connector->ycbcr_420_allowed = true; + intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); - switch (port) { - case PORT_B: - intel_encoder->hpd_pin = HPD_PORT_B; - break; - case PORT_C: - intel_encoder->hpd_pin = HPD_PORT_C; - break; - case PORT_D: - intel_encoder->hpd_pin = HPD_PORT_D; - break; - case PORT_E: - intel_encoder->hpd_pin = HPD_PORT_E; - break; - default: - MISSING_CASE(port); + if (WARN_ON(port == PORT_A)) return; - } - - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - intel_hdmi->write_infoframe = vlv_write_infoframe; - intel_hdmi->set_infoframes = vlv_set_infoframes; - intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; - } else if (IS_G4X(dev_priv)) { - intel_hdmi->write_infoframe = g4x_write_infoframe; - intel_hdmi->set_infoframes = g4x_set_infoframes; - intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; - } else if (HAS_DDI(dev_priv)) { - intel_hdmi->write_infoframe = hsw_write_infoframe; - intel_hdmi->set_infoframes = hsw_set_infoframes; - intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; - } else if (HAS_PCH_IBX(dev_priv)) { - intel_hdmi->write_infoframe = ibx_write_infoframe; - intel_hdmi->set_infoframes = ibx_set_infoframes; - intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; - } else { - intel_hdmi->write_infoframe = cpt_write_infoframe; - intel_hdmi->set_infoframes = cpt_set_infoframes; - intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; - } + intel_encoder->hpd_pin = intel_hpd_pin(port); if (HAS_DDI(dev_priv)) intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; @@ -2000,5 +2122,7 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, intel_dig_port->dp.output_reg = INVALID_MMIO_REG; intel_dig_port->max_lanes = 4; + intel_infoframe_init(intel_dig_port); + intel_hdmi_init_connector(intel_dig_port, intel_connector); } diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index f1200272a699..875d5d218d5c 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -76,26 +76,54 @@ * it will use i915_hotplug_work_func where this logic is handled. */ -bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port) +/** + * intel_hpd_port - return port hard associated with certain pin. + * @pin: the hpd pin to get associated port + * + * Return port that is associatade with @pin and PORT_NONE if no port is + * hard associated with that @pin. + */ +enum port intel_hpd_pin_to_port(enum hpd_pin pin) { switch (pin) { case HPD_PORT_A: - *port = PORT_A; - return true; + return PORT_A; case HPD_PORT_B: - *port = PORT_B; - return true; + return PORT_B; case HPD_PORT_C: - *port = PORT_C; - return true; + return PORT_C; case HPD_PORT_D: - *port = PORT_D; - return true; + return PORT_D; case HPD_PORT_E: - *port = PORT_E; - return true; + return PORT_E; + default: + return PORT_NONE; /* no port for this pin */ + } +} + +/** + * intel_hpd_pin - return pin hard associated with certain port. + * @port: the hpd port to get associated pin + * + * Return pin that is associatade with @port and HDP_NONE if no pin is + * hard associated with that @port. + */ +enum hpd_pin intel_hpd_pin(enum port port) +{ + switch (port) { + case PORT_A: + return HPD_PORT_A; + case PORT_B: + return HPD_PORT_B; + case PORT_C: + return HPD_PORT_C; + case PORT_D: + return HPD_PORT_D; + case PORT_E: + return HPD_PORT_E; default: - return false; /* no hpd */ + MISSING_CASE(port); + return HPD_NONE; } } @@ -389,8 +417,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, if (!(BIT(i) & pin_mask)) continue; - is_dig_port = intel_hpd_pin_to_port(i, &port) && - dev_priv->hotplug.irq_port[port]; + port = intel_hpd_pin_to_port(i); + is_dig_port = port != PORT_NONE && + dev_priv->hotplug.irq_port[port]; if (is_dig_port) { bool long_hpd = long_mask & BIT(i); diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 3c9e00d4ba5a..eb5827110d8f 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -592,7 +592,6 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) int ret; intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); - mutex_lock(&dev_priv->gmbus_mutex); if (bus->force_bit) { ret = i2c_bit_algo.master_xfer(adapter, msgs, num); @@ -604,7 +603,6 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) bus->force_bit |= GMBUS_FORCE_BIT_RETRY; } - mutex_unlock(&dev_priv->gmbus_mutex); intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); return ret; @@ -624,6 +622,39 @@ static const struct i2c_algorithm gmbus_algorithm = { .functionality = gmbus_func }; +static void gmbus_lock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + mutex_lock(&dev_priv->gmbus_mutex); +} + +static int gmbus_trylock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + return mutex_trylock(&dev_priv->gmbus_mutex); +} + +static void gmbus_unlock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + mutex_unlock(&dev_priv->gmbus_mutex); +} + +static const struct i2c_lock_operations gmbus_lock_ops = { + .lock_bus = gmbus_lock_bus, + .trylock_bus = gmbus_trylock_bus, + .unlock_bus = gmbus_unlock_bus, +}; + /** * intel_gmbus_setup - instantiate all Intel i2c GMBuses * @dev_priv: i915 device private @@ -665,6 +696,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) bus->dev_priv = dev_priv; bus->adapter.algo = &gmbus_algorithm; + bus->adapter.lock_ops = &gmbus_lock_ops; /* * We wish to retry with bit banging diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 699868d81de8..d89e1b8e1cc5 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1175,6 +1175,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) return -EINVAL; switch (INTEL_GEN(engine->i915)) { + case 10: + return 0; case 9: wa_bb_fn[0] = gen9_init_indirectctx_bb; wa_bb_fn[1] = gen9_init_perctx_bb; @@ -1221,6 +1223,14 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) return ret; } +static u8 gtiir[] = { + [RCS] = 0, + [BCS] = 0, + [VCS] = 1, + [VCS2] = 1, + [VECS] = 3, +}; + static int gen8_init_common_ring(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1245,9 +1255,22 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); - /* After a GPU reset, we may have requests to replay */ + GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir)); + + /* + * Clear any pending interrupt state. + * + * We do it twice out of paranoia that some of the IIR are double + * buffered, and if we only reset it once there may still be + * an interrupt pending. + */ + I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), + GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); + I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), + GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); + /* After a GPU reset, we may have requests to replay */ submit = false; for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) { if (!port_isset(&port[n])) @@ -1306,6 +1329,31 @@ static void reset_common_ring(struct intel_engine_cs *engine, { struct execlist_port *port = engine->execlist_port; struct intel_context *ce; + unsigned int n; + + /* + * Catch up with any missed context-switch interrupts. + * + * Ideally we would just read the remaining CSB entries now that we + * know the gpu is idle. However, the CSB registers are sometimes^W + * often trashed across a GPU reset! Instead we have to rely on + * guessing the missed context-switch events by looking at what + * requests were completed. + */ + if (!request) { + for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) + i915_gem_request_put(port_request(&port[n])); + memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); + return; + } + + if (request->ctx != port_request(port)->ctx) { + i915_gem_request_put(port_request(port)); + port[0] = port[1]; + memset(&port[1], 0, sizeof(port[1])); + } + + GEM_BUG_ON(request->ctx != port_request(port)->ctx); /* If the request was innocent, we leave the request in the ELSP * and will try to replay it on restarting. The context image may @@ -1317,7 +1365,7 @@ static void reset_common_ring(struct intel_engine_cs *engine, * and have to at least restore the RING register in the context * image back to the expected values to skip over the guilty request. */ - if (!request || request->fence.error != -EIO) + if (request->fence.error != -EIO) return; /* We want a simple context + ring to execute the breadcrumb update. @@ -1339,15 +1387,6 @@ static void reset_common_ring(struct intel_engine_cs *engine, request->ring->head = request->postfix; intel_ring_update_space(request->ring); - /* Catch up with any missed context-switch interrupts */ - if (request->ctx != port_request(port)->ctx) { - i915_gem_request_put(port_request(port)); - port[0] = port[1]; - memset(&port[1], 0, sizeof(port[1])); - } - - GEM_BUG_ON(request->ctx != port_request(port)->ctx); - /* Reset WaIdleLiteRestore:bdw,skl as well */ request->tail = intel_ring_wrap(request->ring, diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 52b3a1fd4059..57ef5833c427 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -63,7 +63,6 @@ enum { }; /* Logical Rings */ -void intel_logical_ring_stop(struct intel_engine_cs *engine); void intel_logical_ring_cleanup(struct intel_engine_cs *engine); int logical_render_ring_init(struct intel_engine_cs *engine); int logical_xcs_ring_init(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c index 5abef482eacf..beb9baaf2f2e 100644 --- a/drivers/gpu/drm/i915/intel_lspcon.c +++ b/drivers/gpu/drm/i915/intel_lspcon.c @@ -210,8 +210,8 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - if (!IS_GEN9(dev_priv)) { - DRM_ERROR("LSPCON is supported on GEN9 only\n"); + if (!HAS_LSPCON(dev_priv)) { + DRM_ERROR("LSPCON is not supported on this platform\n"); return false; } diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 61d557948e21..a9813aea89d8 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -229,8 +229,8 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, } static void intel_pre_enable_lvds(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -306,8 +306,8 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder, * Sets the power state for the panel. */ static void intel_enable_lvds(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_device *dev = encoder->base.dev; struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); @@ -324,8 +324,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder, } static void intel_disable_lvds(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -339,8 +339,8 @@ static void intel_disable_lvds(struct intel_encoder *encoder, } static void gmch_disable_lvds(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { intel_panel_disable_backlight(old_conn_state); @@ -349,15 +349,15 @@ static void gmch_disable_lvds(struct intel_encoder *encoder, } static void pch_disable_lvds(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { intel_panel_disable_backlight(old_conn_state); } static void pch_post_disable_lvds(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { intel_disable_lvds(encoder, old_crtc_state, old_conn_state); } @@ -1138,7 +1138,8 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) out: mutex_unlock(&dev->mode_config.mutex); - intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); + intel_panel_init(&intel_connector->panel, fixed_mode, NULL, + downclock_mode); intel_panel_setup_backlight(connector, INVALID_PIPE); lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index 2bd03001cc70..98154efcb2f4 100644 --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/drivers/gpu/drm/i915/intel_opregion.c @@ -27,6 +27,7 @@ #include <linux/acpi.h> #include <linux/dmi.h> +#include <linux/firmware.h> #include <acpi/video.h> #include <drm/drmP.h> @@ -829,6 +830,10 @@ void intel_opregion_unregister(struct drm_i915_private *dev_priv) memunmap(opregion->rvda); opregion->rvda = NULL; } + if (opregion->vbt_firmware) { + kfree(opregion->vbt_firmware); + opregion->vbt_firmware = NULL; + } opregion->header = NULL; opregion->acpi = NULL; opregion->swsci = NULL; @@ -912,6 +917,43 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = { { } }; +static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) +{ + struct intel_opregion *opregion = &dev_priv->opregion; + const struct firmware *fw = NULL; + const char *name = i915.vbt_firmware; + int ret; + + if (!name || !*name) + return -ENOENT; + + ret = request_firmware(&fw, name, &dev_priv->drm.pdev->dev); + if (ret) { + DRM_ERROR("Requesting VBT firmware \"%s\" failed (%d)\n", + name, ret); + return ret; + } + + if (intel_bios_is_valid_vbt(fw->data, fw->size)) { + opregion->vbt_firmware = kmemdup(fw->data, fw->size, GFP_KERNEL); + if (opregion->vbt_firmware) { + DRM_DEBUG_KMS("Found valid VBT firmware \"%s\"\n", name); + opregion->vbt = opregion->vbt_firmware; + opregion->vbt_size = fw->size; + ret = 0; + } else { + ret = -ENOMEM; + } + } else { + DRM_DEBUG_KMS("Invalid VBT firmware \"%s\"\n", name); + ret = -EINVAL; + } + + release_firmware(fw); + + return ret; +} + int intel_opregion_setup(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; @@ -974,6 +1016,9 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) if (mboxes & MBOX_ASLE_EXT) DRM_DEBUG_DRIVER("ASLE extension supported\n"); + if (intel_load_vbt_firmware(dev_priv) == 0) + goto out; + if (dmi_check_system(intel_no_opregion_vbt)) goto out; diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index b96aed941b97..aace22e7ccac 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -799,9 +799,13 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, if (ret != 0) return ret; + atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); + goto out_pin_section; + } ret = i915_vma_put_fence(vma); if (ret) @@ -886,6 +890,9 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, out_unpin: i915_gem_object_unpin_from_display_plane(vma); +out_pin_section: + atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + return ret; } diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 593349be8b9d..3b1c5d783ee7 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -110,7 +110,8 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc, /* Native modes don't need fitting */ if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && - adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) + adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h && + !pipe_config->ycbcr420) goto done; switch (fitting_mode) { @@ -1698,6 +1699,8 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) if (!panel->backlight.max) return -ENODEV; + panel->backlight.min = get_backlight_min_vbt(connector); + val = bxt_get_backlight(connector); val = intel_panel_compute_brightness(connector, val); panel->backlight.level = clamp(val, panel->backlight.min, @@ -1734,6 +1737,8 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused) if (!panel->backlight.max) return -ENODEV; + panel->backlight.min = get_backlight_min_vbt(connector); + val = bxt_get_backlight(connector); val = intel_panel_compute_brightness(connector, val); panel->backlight.level = clamp(val, panel->backlight.min, @@ -1919,11 +1924,13 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) int intel_panel_init(struct intel_panel *panel, struct drm_display_mode *fixed_mode, + struct drm_display_mode *alt_fixed_mode, struct drm_display_mode *downclock_mode) { intel_panel_init_backlight_funcs(panel); panel->fixed_mode = fixed_mode; + panel->alt_fixed_mode = alt_fixed_mode; panel->downclock_mode = downclock_mode; return 0; @@ -1937,6 +1944,10 @@ void intel_panel_fini(struct intel_panel *panel) if (panel->fixed_mode) drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); + if (panel->alt_fixed_mode) + drm_mode_destroy(intel_connector->base.dev, + panel->alt_fixed_mode); + if (panel->downclock_mode) drm_mode_destroy(intel_connector->base.dev, panel->downclock_mode); diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index 8fbd2bd0877f..96043a51c1bf 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -506,8 +506,8 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, return 0; } -static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, - bool enable) +static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv, + bool enable) { struct drm_device *dev = &dev_priv->drm; struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); @@ -533,10 +533,24 @@ retry: goto put_state; } - pipe_config->pch_pfit.force_thru = enable; - if (pipe_config->cpu_transcoder == TRANSCODER_EDP && - pipe_config->pch_pfit.enabled != enable) - pipe_config->base.connectors_changed = true; + if (HAS_IPS(dev_priv)) { + /* + * When IPS gets enabled, the pipe CRC changes. Since IPS gets + * enabled and disabled dynamically based on package C states, + * user space can't make reliable use of the CRCs, so let's just + * completely disable it. + */ + pipe_config->ips_force_disable = enable; + if (pipe_config->ips_enabled == enable) + pipe_config->base.connectors_changed = true; + } + + if (IS_HASWELL(dev_priv)) { + pipe_config->pch_pfit.force_thru = enable; + if (pipe_config->cpu_transcoder == TRANSCODER_EDP && + pipe_config->pch_pfit.enabled != enable) + pipe_config->base.connectors_changed = true; + } ret = drm_atomic_commit(state); @@ -570,8 +584,9 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; break; case INTEL_PIPE_CRC_SOURCE_PF: - if (IS_HASWELL(dev_priv) && pipe == PIPE_A) - hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); + if ((IS_HASWELL(dev_priv) || + IS_BROADWELL(dev_priv)) && pipe == PIPE_A) + hsw_pipe_A_crc_wa(dev_priv, true); *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; break; @@ -606,7 +621,6 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv, enum intel_pipe_crc_source source) { struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); enum intel_display_power_domain power_domain; u32 val = 0; /* shut up gcc */ int ret; @@ -643,14 +657,6 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv, goto out; } - /* - * When IPS gets enabled, the pipe CRC changes. Since IPS gets - * enabled and disabled dynamically based on package C states, - * user space can't make reliable use of the CRCs, so let's just - * completely disable it. - */ - hsw_disable_ips(crtc); - spin_lock_irq(&pipe_crc->lock); kfree(pipe_crc->entries); pipe_crc->entries = entries; @@ -691,10 +697,9 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv, g4x_undo_pipe_scramble_reset(dev_priv, pipe); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) vlv_undo_pipe_scramble_reset(dev_priv, pipe); - else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) - hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); - - hsw_enable_ips(crtc); + else if ((IS_HASWELL(dev_priv) || + IS_BROADWELL(dev_priv)) && pipe == PIPE_A) + hsw_pipe_A_crc_wa(dev_priv, false); } ret = 0; @@ -914,7 +919,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, { struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum intel_display_power_domain power_domain; enum intel_pipe_crc_source source; u32 val = 0; /* shut up gcc */ @@ -935,16 +939,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, if (ret != 0) goto out; - if (source) { - /* - * When IPS gets enabled, the pipe CRC changes. Since IPS gets - * enabled and disabled dynamically based on package C states, - * user space can't make reliable use of the CRCs, so let's just - * completely disable it. - */ - hsw_disable_ips(intel_crtc); - } - I915_WRITE(PIPE_CRC_CTL(crtc->index), val); POSTING_READ(PIPE_CRC_CTL(crtc->index)); @@ -953,10 +947,9 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, g4x_undo_pipe_scramble_reset(dev_priv, crtc->index); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) vlv_undo_pipe_scramble_reset(dev_priv, crtc->index); - else if (IS_HASWELL(dev_priv) && crtc->index == PIPE_A) - hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); - - hsw_enable_ips(intel_crtc); + else if ((IS_HASWELL(dev_priv) || + IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A) + hsw_pipe_A_crc_wa(dev_priv, false); } pipe_crc->skipped = 0; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 48785ef75d33..0201816a4229 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -62,6 +62,20 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(CHICKEN_PAR1_1, I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); + /* + * Display WA#0390: skl,bxt,kbl,glk + * + * Must match Sampler, Pixel Back End, and Media + * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31). + * + * Including bits outside the page in the hash would + * require 2 (or 4?) MiB alignment of resources. Just + * assume the defaul hashing mode which only uses bits + * within the page. + */ + I915_WRITE(CHICKEN_PAR1_1, + I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE); + I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); @@ -78,6 +92,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | ILK_DPFC_DISABLE_DUMMY0); + + if (IS_SKYLAKE(dev_priv)) { + /* WaDisableDopClockGating */ + I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) + & ~GEN7_DOP_CLOCK_GATE_ENABLE); + } } static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) @@ -105,6 +125,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) static void glk_init_clock_gating(struct drm_i915_private *dev_priv) { + u32 val; gen9_init_clock_gating(dev_priv); /* @@ -124,6 +145,11 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(CHICKEN_MISC_2, val); } + /* Display WA #1133: WaFbcSkipSegments:glk */ + val = I915_READ(ILK_DPFC_CHICKEN); + val &= ~GLK_SKIP_SEG_COUNT_MASK; + val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1); + I915_WRITE(ILK_DPFC_CHICKEN, val); } static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) @@ -1302,21 +1328,21 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) int num_active_planes = hweight32(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); const struct g4x_pipe_wm *raw; - struct intel_plane_state *plane_state; + const struct intel_plane_state *old_plane_state; + const struct intel_plane_state *new_plane_state; struct intel_plane *plane; enum plane_id plane_id; int i, level; unsigned int dirty = 0; - for_each_intel_plane_in_state(state, plane, plane_state, i) { - const struct intel_plane_state *old_plane_state = - to_intel_plane_state(plane->base.state); - - if (plane_state->base.crtc != &crtc->base && + for_each_oldnew_intel_plane_in_state(state, plane, + old_plane_state, + new_plane_state, i) { + if (new_plane_state->base.crtc != &crtc->base && old_plane_state->base.crtc != &crtc->base) continue; - if (g4x_raw_plane_wm_compute(crtc_state, plane_state)) + if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state)) dirty |= BIT(plane->id); } @@ -1811,21 +1837,21 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) int num_active_planes = hweight32(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); - struct intel_plane_state *plane_state; + const struct intel_plane_state *old_plane_state; + const struct intel_plane_state *new_plane_state; struct intel_plane *plane; enum plane_id plane_id; int level, ret, i; unsigned int dirty = 0; - for_each_intel_plane_in_state(state, plane, plane_state, i) { - const struct intel_plane_state *old_plane_state = - to_intel_plane_state(plane->base.state); - - if (plane_state->base.crtc != &crtc->base && + for_each_oldnew_intel_plane_in_state(state, plane, + old_plane_state, + new_plane_state, i) { + if (new_plane_state->base.crtc != &crtc->base && old_plane_state->base.crtc != &crtc->base) continue; - if (vlv_raw_plane_wm_compute(crtc_state, plane_state)) + if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state)) dirty |= BIT(plane->id); } @@ -1844,7 +1870,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) /* cursor changes don't warrant a FIFO recompute */ if (dirty & ~BIT(PLANE_CURSOR)) { const struct intel_crtc_state *old_crtc_state = - to_intel_crtc_state(crtc->base.state); + intel_atomic_get_old_crtc_state(state, crtc); const struct vlv_fifo_state *old_fifo_state = &old_crtc_state->wm.vlv.fifo_state; @@ -2758,7 +2784,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) static void intel_read_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[8]) { - if (IS_GEN9(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 9) { uint32_t val; int ret, i; int level, max_level = ilk_wm_max_level(dev_priv); @@ -2818,7 +2844,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, } /* - * WaWmMemoryReadLatency:skl,glk + * WaWmMemoryReadLatency:skl+,glk * * punit doesn't take into account the read latency so we need * to add 2us to the various latency levels we retrieve from the @@ -2857,6 +2883,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, wm[0] = 7; wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; + } else { + MISSING_CASE(INTEL_DEVID(dev_priv)); } } @@ -2912,7 +2940,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, * - latencies are in us on gen9. * - before then, WM1+ latency values are in 0.5us units */ - if (IS_GEN9(dev_priv)) + if (INTEL_GEN(dev_priv) >= 9) latency *= 10; else if (level > 0) latency *= 5; @@ -3530,8 +3558,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev) return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); } -#define SKL_SAGV_BLOCK_TIME 30 /* µs */ - /* * FIXME: We still don't have the proper code detect if we need to apply the WA, * so assume we'll always need it in order to avoid underruns. @@ -3549,7 +3575,8 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) static bool intel_has_sagv(struct drm_i915_private *dev_priv) { - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || + IS_CANNONLAKE(dev_priv)) return true; if (IS_SKYLAKE(dev_priv) && @@ -3655,12 +3682,13 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) struct intel_crtc_state *cstate; enum pipe pipe; int level, latency; + int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20; if (!intel_has_sagv(dev_priv)) return false; /* - * SKL workaround: bspec recommends we disable the SAGV when we have + * SKL+ workaround: bspec recommends we disable the SAGV when we have * more then one pipe enabled * * If there are no active CRTCs, no additional checks need be performed @@ -3699,11 +3727,11 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) latency += 15; /* - * If any of the planes on this pipe don't enable wm levels - * that incur memory latencies higher then 30µs we can't enable - * the SAGV + * If any of the planes on this pipe don't enable wm levels that + * incur memory latencies higher than sagv_block_time_us we + * can't enable the SAGV. */ - if (latency < SKL_SAGV_BLOCK_TIME) + if (latency < sagv_block_time_us) return false; } @@ -4071,7 +4099,9 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, /* For Non Y-tile return 8-blocks */ if (fb->modifier != I915_FORMAT_MOD_Y_TILED && - fb->modifier != I915_FORMAT_MOD_Yf_TILED) + fb->modifier != I915_FORMAT_MOD_Yf_TILED && + fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS && + fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS) return 8; /* @@ -4266,8 +4296,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, * should allow pixel_rate up to ~2 GHz which seems sufficient since max * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. */ -static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, - uint32_t latency) +static uint_fixed_16_16_t +skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate, + uint8_t cpp, uint32_t latency) { uint32_t wm_intermediate_val; uint_fixed_16_16_t ret; @@ -4277,6 +4308,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, wm_intermediate_val = latency * pixel_rate * cpp; ret = div_fixed16(wm_intermediate_val, 1000 * 512); + + if (INTEL_GEN(dev_priv) >= 10) + ret = add_fixed16_u32(ret, 1); + return ret; } @@ -4377,7 +4412,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, } y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED || - fb->modifier == I915_FORMAT_MOD_Yf_TILED; + fb->modifier == I915_FORMAT_MOD_Yf_TILED || + fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS; x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; /* Display WA #1141: kbl,cfl */ @@ -4430,9 +4467,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (y_tiled) { interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512); + + if (INTEL_GEN(dev_priv) >= 10) + interm_pbpl++; + plane_blocks_per_line = div_fixed16(interm_pbpl, y_min_scanlines); - } else if (x_tiled) { + } else if (x_tiled && INTEL_GEN(dev_priv) == 9) { interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); plane_blocks_per_line = u32_to_fixed16(interm_pbpl); } else { @@ -4440,7 +4481,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, plane_blocks_per_line = u32_to_fixed16(interm_pbpl); } - method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); + method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency); method2 = skl_wm_method2(plane_pixel_rate, cstate->base.adjusted_mode.crtc_htotal, latency, @@ -4472,6 +4513,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, res_lines = div_round_up_fixed16(selected_result, plane_blocks_per_line); + /* Display WA #1125: skl,bxt,kbl,glk */ + if (level == 0 && + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) + res_blocks += fixed16_to_u32_round_up(y_tile_minimum); + + /* Display WA #1126: skl,bxt,kbl,glk */ if (level >= 1 && level <= 7) { if (y_tiled) { res_blocks += fixed16_to_u32_round_up(y_tile_minimum); @@ -6127,6 +6175,7 @@ void gen6_rps_boost(struct drm_i915_gem_request *rq, struct intel_rps_client *rps) { struct drm_i915_private *i915 = rq->i915; + unsigned long flags; bool boost; /* This is intentionally racy! We peek at the state here, then @@ -6136,13 +6185,13 @@ void gen6_rps_boost(struct drm_i915_gem_request *rq, return; boost = false; - spin_lock_irq(&rq->lock); + spin_lock_irqsave(&rq->lock, flags); if (!rq->waitboost && !i915_gem_request_completed(rq)) { atomic_inc(&i915->rps.num_waiters); rq->waitboost = true; boost = true; } - spin_unlock_irq(&rq->lock); + spin_unlock_irqrestore(&rq->lock, flags); if (!boost) return; @@ -7938,7 +7987,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) */ } -static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv) +static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) { uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; @@ -8221,7 +8270,56 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, I915_WRITE(GEN7_MISCCPCTL, misccpctl); } -static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) +{ + if (!HAS_PCH_CNP(dev_priv)) + return; + + /* Wa #1181 */ + I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE); +} + +static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) +{ + u32 val; + cnp_init_clock_gating(dev_priv); + + /* This is not an Wa. Enable for better image quality */ + I915_WRITE(_3D_CHICKEN3, + _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE)); + + /* WaEnableChickenDCPR:cnl */ + I915_WRITE(GEN8_CHICKEN_DCPR_1, + I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); + + /* WaFbcWakeMemOn:cnl */ + I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | + DISP_FBC_MEMORY_WAKE); + + /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) + I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, + I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | + SARBUNIT_CLKGATE_DIS); + + /* Display WA #1133: WaFbcSkipSegments:cnl */ + val = I915_READ(ILK_DPFC_CHICKEN); + val &= ~GLK_SKIP_SEG_COUNT_MASK; + val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1); + I915_WRITE(ILK_DPFC_CHICKEN, val); +} + +static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) +{ + cnp_init_clock_gating(dev_priv); + gen9_init_clock_gating(dev_priv); + + /* WaFbcNukeOnHostModify:cfl */ + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | + ILK_DPFC_NUKE_ON_ANY_MODIFICATION); +} + +static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) { gen9_init_clock_gating(dev_priv); @@ -8235,12 +8333,12 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | GEN6_GAMUNIT_CLOCK_GATE_DISABLE); - /* WaFbcNukeOnHostModify:kbl,cfl */ + /* WaFbcNukeOnHostModify:kbl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); } -static void skylake_init_clock_gating(struct drm_i915_private *dev_priv) +static void skl_init_clock_gating(struct drm_i915_private *dev_priv) { gen9_init_clock_gating(dev_priv); @@ -8253,7 +8351,7 @@ static void skylake_init_clock_gating(struct drm_i915_private *dev_priv) ILK_DPFC_NUKE_ON_ANY_MODIFICATION); } -static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) +static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) { enum pipe pipe; @@ -8311,7 +8409,7 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); } -static void haswell_init_clock_gating(struct drm_i915_private *dev_priv) +static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) { ilk_init_lp_watermarks(dev_priv); @@ -8365,7 +8463,7 @@ static void haswell_init_clock_gating(struct drm_i915_private *dev_priv) lpt_init_clock_gating(dev_priv); } -static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv) +static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) { uint32_t snpcr; @@ -8462,7 +8560,7 @@ static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv) gen6_check_mch_setup(dev_priv); } -static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv) +static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) { /* WaDisableEarlyCull:vlv */ I915_WRITE(_3D_CHICKEN3, @@ -8542,7 +8640,7 @@ static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); } -static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) +static void chv_init_clock_gating(struct drm_i915_private *dev_priv) { /* WaVSRefCountFullforceMissDisable:chv */ /* WaDSRefCountFullforceMissDisable:chv */ @@ -8602,7 +8700,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) g4x_disable_trickle_feed(dev_priv); } -static void crestline_init_clock_gating(struct drm_i915_private *dev_priv) +static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv) { I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); I915_WRITE(RENCLK_GATE_D2, 0); @@ -8616,7 +8714,7 @@ static void crestline_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); } -static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv) +static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) { I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | I965_RCC_CLOCK_GATE_DISABLE | @@ -8701,34 +8799,38 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) */ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { - if (IS_SKYLAKE(dev_priv)) - dev_priv->display.init_clock_gating = skylake_init_clock_gating; - else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) - dev_priv->display.init_clock_gating = kabylake_init_clock_gating; + if (IS_CANNONLAKE(dev_priv)) + dev_priv->display.init_clock_gating = cnl_init_clock_gating; + else if (IS_COFFEELAKE(dev_priv)) + dev_priv->display.init_clock_gating = cfl_init_clock_gating; + else if (IS_SKYLAKE(dev_priv)) + dev_priv->display.init_clock_gating = skl_init_clock_gating; + else if (IS_KABYLAKE(dev_priv)) + dev_priv->display.init_clock_gating = kbl_init_clock_gating; else if (IS_BROXTON(dev_priv)) dev_priv->display.init_clock_gating = bxt_init_clock_gating; else if (IS_GEMINILAKE(dev_priv)) dev_priv->display.init_clock_gating = glk_init_clock_gating; else if (IS_BROADWELL(dev_priv)) - dev_priv->display.init_clock_gating = broadwell_init_clock_gating; + dev_priv->display.init_clock_gating = bdw_init_clock_gating; else if (IS_CHERRYVIEW(dev_priv)) - dev_priv->display.init_clock_gating = cherryview_init_clock_gating; + dev_priv->display.init_clock_gating = chv_init_clock_gating; else if (IS_HASWELL(dev_priv)) - dev_priv->display.init_clock_gating = haswell_init_clock_gating; + dev_priv->display.init_clock_gating = hsw_init_clock_gating; else if (IS_IVYBRIDGE(dev_priv)) - dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; + dev_priv->display.init_clock_gating = ivb_init_clock_gating; else if (IS_VALLEYVIEW(dev_priv)) - dev_priv->display.init_clock_gating = valleyview_init_clock_gating; + dev_priv->display.init_clock_gating = vlv_init_clock_gating; else if (IS_GEN6(dev_priv)) dev_priv->display.init_clock_gating = gen6_init_clock_gating; else if (IS_GEN5(dev_priv)) - dev_priv->display.init_clock_gating = ironlake_init_clock_gating; + dev_priv->display.init_clock_gating = ilk_init_clock_gating; else if (IS_G4X(dev_priv)) dev_priv->display.init_clock_gating = g4x_init_clock_gating; else if (IS_I965GM(dev_priv)) - dev_priv->display.init_clock_gating = crestline_init_clock_gating; + dev_priv->display.init_clock_gating = i965gm_init_clock_gating; else if (IS_I965G(dev_priv)) - dev_priv->display.init_clock_gating = broadwater_init_clock_gating; + dev_priv->display.init_clock_gating = i965g_init_clock_gating; else if (IS_GEN3(dev_priv)) dev_priv->display.init_clock_gating = gen3_init_clock_gating; else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) @@ -8831,6 +8933,7 @@ static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv) case GEN6_PCODE_SUCCESS: return 0; case GEN6_PCODE_UNIMPLEMENTED_CMD: + return -ENODEV; case GEN6_PCODE_ILLEGAL_CMD: return -ENXIO; case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: @@ -8878,7 +8981,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val */ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { - DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); + DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n", + mbox, __builtin_return_address(0)); return -EAGAIN; } @@ -8889,7 +8993,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val if (__intel_wait_for_register_fw(dev_priv, GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, 500, 0, NULL)) { - DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); + DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n", + mbox, __builtin_return_address(0)); return -ETIMEDOUT; } @@ -8902,8 +9007,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val status = gen6_check_mailbox_status(dev_priv); if (status) { - DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n", - status); + DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n", + mbox, __builtin_return_address(0), status); return status; } @@ -8923,7 +9028,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, */ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { - DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); + DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n", + val, mbox, __builtin_return_address(0)); return -EAGAIN; } @@ -8934,7 +9040,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, if (__intel_wait_for_register_fw(dev_priv, GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, 500, 0, NULL)) { - DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); + DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n", + val, mbox, __builtin_return_address(0)); return -ETIMEDOUT; } @@ -8946,8 +9053,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, status = gen6_check_mailbox_status(dev_priv); if (status) { - DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n", - status); + DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n", + val, mbox, __builtin_return_address(0), status); return status; } @@ -9085,43 +9192,6 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); } -struct request_boost { - struct work_struct work; - struct drm_i915_gem_request *req; -}; - -static void __intel_rps_boost_work(struct work_struct *work) -{ - struct request_boost *boost = container_of(work, struct request_boost, work); - struct drm_i915_gem_request *req = boost->req; - - if (!i915_gem_request_completed(req)) - gen6_rps_boost(req, NULL); - - i915_gem_request_put(req); - kfree(boost); -} - -void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req) -{ - struct request_boost *boost; - - if (req == NULL || INTEL_GEN(req->i915) < 6) - return; - - if (i915_gem_request_completed(req)) - return; - - boost = kmalloc(sizeof(*boost), GFP_ATOMIC); - if (boost == NULL) - return; - - boost->req = i915_gem_request_get(req); - - INIT_WORK(&boost->work, __intel_rps_boost_work); - queue_work(req->i915->wq, &boost->work); -} - void intel_pm_setup(struct drm_i915_private *dev_priv) { mutex_init(&dev_priv->rps.hw_lock); diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 559f1ab42bfc..f62ab05d3d62 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -103,28 +103,26 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp, POSTING_READ(ctl_reg); } -static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) +static void vlv_psr_setup_vsc(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_crtc *crtc = intel_dig_port->base.base.crtc; - enum pipe pipe = to_intel_crtc(crtc)->pipe; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); uint32_t val; /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ - val = I915_READ(VLV_VSCSDP(pipe)); + val = I915_READ(VLV_VSCSDP(crtc->pipe)); val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; - I915_WRITE(VLV_VSCSDP(pipe), val); + I915_WRITE(VLV_VSCSDP(crtc->pipe), val); } -static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) +static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { - struct edp_vsc_psr psr_vsc; struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct edp_vsc_psr psr_vsc; /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ memset(&psr_vsc, 0, sizeof(psr_vsc)); @@ -145,7 +143,8 @@ static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) intel_psr_write_vsc(intel_dp, &psr_vsc); } -static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) +static void hsw_psr_setup_vsc(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct edp_vsc_psr psr_vsc; @@ -233,16 +232,15 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) I915_WRITE(aux_ctl_reg, aux_ctl); } -static void vlv_psr_enable_source(struct intel_dp *intel_dp) +static void vlv_psr_enable_source(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = dig_port->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_crtc *crtc = dig_port->base.base.crtc; - enum pipe pipe = to_intel_crtc(crtc)->pipe; + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */ - I915_WRITE(VLV_PSRCTL(pipe), + I915_WRITE(VLV_PSRCTL(crtc->pipe), VLV_EDP_PSR_MODE_SW_TIMER | VLV_EDP_PSR_SRC_TRANSMITTER_STATE | VLV_EDP_PSR_ENABLE); @@ -315,6 +313,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TP2_SEL; + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; I915_WRITE(EDP_PSR_CTL, val); } @@ -484,16 +483,17 @@ static void intel_psr_activate(struct intel_dp *intel_dp) /** * intel_psr_enable - Enable PSR * @intel_dp: Intel DP + * @crtc_state: new CRTC state * * This function can only be called after the pipe is fully trained and enabled. */ -void intel_psr_enable(struct intel_dp *intel_dp) +void intel_psr_enable(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); - enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 chicken; if (!HAS_PSR(dev_priv)) { @@ -519,11 +519,13 @@ void intel_psr_enable(struct intel_dp *intel_dp) if (HAS_DDI(dev_priv)) { if (dev_priv->psr.psr2_support) { - skl_psr_setup_su_vsc(intel_dp); + skl_psr_setup_su_vsc(intel_dp, crtc_state); + chicken = PSR2_VSC_ENABLE_PROG_HEADER; if (dev_priv->psr.y_cord_support) chicken |= PSR2_ADD_VERTICAL_LINE_COUNT; I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); + I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP | EDP_PSR_DEBUG_MASK_HPD | @@ -532,7 +534,8 @@ void intel_psr_enable(struct intel_dp *intel_dp) EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); } else { /* set up vsc header for psr1 */ - hsw_psr_setup_vsc(intel_dp); + hsw_psr_setup_vsc(intel_dp, crtc_state); + /* * Per Spec: Avoid continuous PSR exit by masking MEMUP * and HPD. also mask LPSP to avoid dependency on other @@ -552,7 +555,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 9) intel_psr_activate(intel_dp); } else { - vlv_psr_setup_vsc(intel_dp); + vlv_psr_setup_vsc(intel_dp, crtc_state); /* Enable PSR on the panel */ vlv_psr_enable_sink(intel_dp); @@ -563,7 +566,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) * but let it on inactive state. So we might do this prior * to active transition, i.e. here. */ - vlv_psr_enable_source(intel_dp); + vlv_psr_enable_source(intel_dp, crtc_state); } /* @@ -584,37 +587,38 @@ unlock: mutex_unlock(&dev_priv->psr.lock); } -static void vlv_psr_disable(struct intel_dp *intel_dp) +static void vlv_psr_disable(struct intel_dp *intel_dp, + const struct intel_crtc_state *old_crtc_state) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = - to_intel_crtc(intel_dig_port->base.base.crtc); + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); uint32_t val; if (dev_priv->psr.active) { /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */ if (intel_wait_for_register(dev_priv, - VLV_PSRSTAT(intel_crtc->pipe), + VLV_PSRSTAT(crtc->pipe), VLV_EDP_PSR_IN_TRANS, 0, 1)) WARN(1, "PSR transition took longer than expected\n"); - val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); + val = I915_READ(VLV_PSRCTL(crtc->pipe)); val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; val &= ~VLV_EDP_PSR_ENABLE; val &= ~VLV_EDP_PSR_MODE_MASK; - I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); + I915_WRITE(VLV_PSRCTL(crtc->pipe), val); dev_priv->psr.active = false; } else { - WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); + WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe)); } } -static void hsw_psr_disable(struct intel_dp *intel_dp) +static void hsw_psr_disable(struct intel_dp *intel_dp, + const struct intel_crtc_state *old_crtc_state) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; @@ -663,10 +667,12 @@ static void hsw_psr_disable(struct intel_dp *intel_dp) /** * intel_psr_disable - Disable PSR * @intel_dp: Intel DP + * @old_crtc_state: old CRTC state * * This function needs to be called before disabling pipe. */ -void intel_psr_disable(struct intel_dp *intel_dp) +void intel_psr_disable(struct intel_dp *intel_dp, + const struct intel_crtc_state *old_crtc_state) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; @@ -680,9 +686,9 @@ void intel_psr_disable(struct intel_dp *intel_dp) /* Disable PSR on Source */ if (HAS_DDI(dev_priv)) - hsw_psr_disable(intel_dp); + hsw_psr_disable(intel_dp, old_crtc_state); else - vlv_psr_disable(intel_dp); + vlv_psr_disable(intel_dp, old_crtc_state); /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); diff --git a/drivers/gpu/drm/i915/intel_renderstate_gen9.c b/drivers/gpu/drm/i915/intel_renderstate_gen9.c index 16a7ec273bd9..7d3ac02f0177 100644 --- a/drivers/gpu/drm/i915/intel_renderstate_gen9.c +++ b/drivers/gpu/drm/i915/intel_renderstate_gen9.c @@ -20,7 +20,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * - * Generated by: intel-gpu-tools-1.8-220-g01153e7 + * Generated by: intel-gpu-tools-1.19-177-g68e2eab2 */ #include "intel_renderstate.h" @@ -873,7 +873,7 @@ static const u32 gen9_null_state_batch[] = { 0x00000000, 0x00000000, 0x78550003, - 0x00000000, + 0x0000000f, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5224b7abb8a3..cdf084ef5aae 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1712,6 +1712,9 @@ u32 *intel_ring_begin(struct drm_i915_gem_request *req, unsigned int total_bytes; u32 *cs; + /* Packets must be qword aligned. */ + GEM_BUG_ON(num_dwords & 1); + total_bytes = bytes + req->reserved_space; GEM_BUG_ON(total_bytes > ring->effective_size); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index d33c93444c0d..79c0021f3700 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -735,4 +735,6 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv); void intel_engines_mark_idle(struct drm_i915_private *i915); void intel_engines_reset_default_submission(struct drm_i915_private *i915); +bool intel_engine_can_store_dword(struct intel_engine_cs *engine); + #endif /* _INTEL_RINGBUFFER_H_ */ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index f630d632a976..a3bfb9f27e7a 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -50,10 +50,11 @@ */ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, - int power_well_id); + enum i915_power_well_id power_well_id); static struct i915_power_well * -lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id); +lookup_power_well(struct drm_i915_private *dev_priv, + enum i915_power_well_id power_well_id); const char * intel_display_power_domain_str(enum intel_display_power_domain domain) @@ -168,18 +169,6 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv, intel_power_well_disable(dev_priv, power_well); } -/* - * We should only use the power well if we explicitly asked the hardware to - * enable it, so check if it's enabled and also check if we've requested it to - * be enabled. - */ -static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - return I915_READ(HSW_PWR_WELL_DRIVER) == - (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); -} - /** * __intel_display_power_is_enabled - unlocked check for a power domain * @dev_priv: i915 device instance @@ -278,38 +267,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv, * to be enabled, and it will only be disabled if none of the registers is * requesting it to be enabled. */ -static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) -{ - struct pci_dev *pdev = dev_priv->drm.pdev; - - /* - * After we re-enable the power well, if we touch VGA register 0x3d5 - * we'll get unclaimed register interrupts. This stops after we write - * anything to the VGA MSR register. The vgacon module uses this - * register all the time, so if we unbind our driver and, as a - * consequence, bind vgacon, we'll get stuck in an infinite loop at - * console_unlock(). So make here we touch the VGA MSR register, making - * sure vgacon can keep working normally without triggering interrupts - * and error messages. - */ - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); - vga_put(pdev, VGA_RSRC_LEGACY_IO); - - if (IS_BROADWELL(dev_priv)) - gen8_irq_power_well_post_enable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); -} - -static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) -{ - if (IS_BROADWELL(dev_priv)) - gen8_irq_power_well_pre_disable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); -} - -static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, + u8 irq_pipe_mask, bool has_vga) { struct pci_dev *pdev = dev_priv->drm.pdev; @@ -323,54 +282,55 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, * sure vgacon can keep working normally without triggering interrupts * and error messages. */ - if (power_well->id == SKL_DISP_PW_2) { + if (has_vga) { vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); vga_put(pdev, VGA_RSRC_LEGACY_IO); - - gen8_irq_power_well_post_enable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); } + + if (irq_pipe_mask) + gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); } -static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, + u8 irq_pipe_mask) { - if (power_well->id == SKL_DISP_PW_2) - gen8_irq_power_well_pre_disable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); + if (irq_pipe_mask) + gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); } -static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) + +static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { - int id = power_well->id; + enum i915_power_well_id id = power_well->id; /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ WARN_ON(intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - SKL_POWER_WELL_STATE(id), - SKL_POWER_WELL_STATE(id), + HSW_PWR_WELL_CTL_DRIVER(id), + HSW_PWR_WELL_CTL_STATE(id), + HSW_PWR_WELL_CTL_STATE(id), 1)); } -static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id) +static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, + enum i915_power_well_id id) { - u32 req_mask = SKL_POWER_WELL_REQ(id); + u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); u32 ret; - ret = I915_READ(HSW_PWR_WELL_BIOS) & req_mask ? 1 : 0; - ret |= I915_READ(HSW_PWR_WELL_DRIVER) & req_mask ? 2 : 0; - ret |= I915_READ(HSW_PWR_WELL_KVMR) & req_mask ? 4 : 0; - ret |= I915_READ(HSW_PWR_WELL_DEBUG) & req_mask ? 8 : 0; + ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; return ret; } -static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { - int id = power_well->id; + enum i915_power_well_id id = power_well->id; bool disabled; u32 reqs; @@ -383,9 +343,9 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, * Skip the wait in case any of the request bits are set and print a * diagnostic message. */ - wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) & - SKL_POWER_WELL_STATE(id))) || - (reqs = gen9_power_well_requesters(dev_priv, id)), 1); + wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & + HSW_PWR_WELL_CTL_STATE(id))) || + (reqs = hsw_power_well_requesters(dev_priv, id)), 1); if (disabled) return; @@ -394,216 +354,85 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); } -static void hsw_set_power_well(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well, bool enable) +static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, + enum skl_power_gate pg) { - bool is_enabled, enable_requested; - uint32_t tmp; + /* Timeout 5us for PG#0, for other PGs 1us */ + WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, + SKL_FUSE_PG_DIST_STATUS(pg), + SKL_FUSE_PG_DIST_STATUS(pg), 1)); +} - tmp = I915_READ(HSW_PWR_WELL_DRIVER); - is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; - enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; - - if (enable) { - if (!enable_requested) - I915_WRITE(HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_ENABLE_REQUEST); - - if (!is_enabled) { - DRM_DEBUG_KMS("Enabling power well\n"); - if (intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_STATE_ENABLED, - HSW_PWR_WELL_STATE_ENABLED, - 20)) - DRM_ERROR("Timeout enabling power well\n"); - hsw_power_well_post_enable(dev_priv); - } +static void hsw_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum i915_power_well_id id = power_well->id; + bool wait_fuses = power_well->hsw.has_fuses; + enum skl_power_gate pg; + u32 val; - } else { - if (enable_requested) { - hsw_power_well_pre_disable(dev_priv); - I915_WRITE(HSW_PWR_WELL_DRIVER, 0); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Requesting to disable the power well\n"); - } + if (wait_fuses) { + pg = SKL_PW_TO_PG(id); + /* + * For PW1 we have to wait both for the PW0/PG0 fuse state + * before enabling the power well and PW1/PG1's own fuse + * state after the enabling. For all other power wells with + * fuses we only have to wait for that PW/PG's fuse state + * after the enabling. + */ + if (pg == SKL_PG1) + gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); } + + val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); + hsw_wait_for_power_well_enable(dev_priv, power_well); + + if (wait_fuses) + gen9_wait_for_power_well_fuses(dev_priv, pg); + + hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, + power_well->hsw.has_vga); } -#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) +static void hsw_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum i915_power_well_id id = power_well->id; + u32 val; -#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_GMBUS) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) + hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); -#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) -#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) -#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) -#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) + val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), + val & ~HSW_PWR_WELL_CTL_REQ(id)); + hsw_wait_for_power_well_disable(dev_priv, power_well); +} -#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) +/* + * We should only use the power well if we explicitly asked the hardware to + * enable it, so check if it's enabled and also check if we've requested it to + * be enabled. + */ +static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum i915_power_well_id id = power_well->id; + u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); + + return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; +} static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) { + enum i915_power_well_id id = SKL_DISP_PW_2; + WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), "DC9 already programmed to be enabled.\n"); WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, "DC5 still not disabled to enable DC9.\n"); - WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER) & - SKL_POWER_WELL_REQ(SKL_DISP_PW_2), + WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & + HSW_PWR_WELL_CTL_REQ(id), "Power well 2 on.\n"); WARN_ONCE(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); @@ -799,181 +628,39 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); } -static void skl_set_power_well(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well, bool enable) -{ - uint32_t tmp, fuse_status; - uint32_t req_mask, state_mask; - bool is_enabled, enable_requested, check_fuse_status = false; - - tmp = I915_READ(HSW_PWR_WELL_DRIVER); - fuse_status = I915_READ(SKL_FUSE_STATUS); - - switch (power_well->id) { - case SKL_DISP_PW_1: - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG0_DIST_STATUS, - SKL_FUSE_PG0_DIST_STATUS, - 1)) { - DRM_ERROR("PG0 not enabled\n"); - return; - } - break; - case SKL_DISP_PW_2: - if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { - DRM_ERROR("PG1 in disabled state\n"); - return; - } - break; - case SKL_DISP_PW_MISC_IO: - case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */ - case SKL_DISP_PW_DDI_B: - case SKL_DISP_PW_DDI_C: - case SKL_DISP_PW_DDI_D: - case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */ - case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */ - case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */ - case CNL_DISP_PW_AUX_D: - break; - default: - WARN(1, "Unknown power well %lu\n", power_well->id); - return; - } - - req_mask = SKL_POWER_WELL_REQ(power_well->id); - enable_requested = tmp & req_mask; - state_mask = SKL_POWER_WELL_STATE(power_well->id); - is_enabled = tmp & state_mask; - - if (!enable && enable_requested) - skl_power_well_pre_disable(dev_priv, power_well); - - if (enable) { - if (!enable_requested) { - WARN((tmp & state_mask) && - !I915_READ(HSW_PWR_WELL_BIOS), - "Invalid for power well status to be enabled, unless done by the BIOS, \ - when request is to disable!\n"); - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); - } - - if (!is_enabled) { - DRM_DEBUG_KMS("Enabling %s\n", power_well->name); - check_fuse_status = true; - } - - gen9_wait_for_power_well_enable(dev_priv, power_well); - } else { - if (enable_requested) { - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Disabling %s\n", power_well->name); - } - - gen9_wait_for_power_well_disable(dev_priv, power_well); - } - - if (check_fuse_status) { - if (power_well->id == SKL_DISP_PW_1) { - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG1_DIST_STATUS, - SKL_FUSE_PG1_DIST_STATUS, - 1)) - DRM_ERROR("PG1 distributing status timeout\n"); - } else if (power_well->id == SKL_DISP_PW_2) { - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG2_DIST_STATUS, - SKL_FUSE_PG2_DIST_STATUS, - 1)) - DRM_ERROR("PG2 distributing status timeout\n"); - } - } - - if (enable && !is_enabled) - skl_power_well_post_enable(dev_priv, power_well); -} - static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - /* Take over the request bit if set by BIOS. */ - if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) { - if (!(I915_READ(HSW_PWR_WELL_DRIVER) & - HSW_PWR_WELL_ENABLE_REQUEST)) - I915_WRITE(HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_ENABLE_REQUEST); - I915_WRITE(HSW_PWR_WELL_BIOS, 0); - } -} - -static void hsw_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - hsw_set_power_well(dev_priv, power_well, true); -} - -static void hsw_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - hsw_set_power_well(dev_priv, power_well, false); -} - -static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - uint32_t mask = SKL_POWER_WELL_REQ(power_well->id) | - SKL_POWER_WELL_STATE(power_well->id); - - return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; -} - -static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - uint32_t mask = SKL_POWER_WELL_REQ(power_well->id); - uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS); + enum i915_power_well_id id = power_well->id; + u32 mask = HSW_PWR_WELL_CTL_REQ(id); + u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); /* Take over the request bit if set by BIOS. */ if (bios_req & mask) { - uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER); + u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); if (!(drv_req & mask)) - I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask); - I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); + I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); } } -static void skl_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - skl_set_power_well(dev_priv, power_well, true); -} - -static void skl_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - skl_set_power_well(dev_priv, power_well, false); -} - static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - bxt_ddi_phy_init(dev_priv, power_well->data); + bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); } static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - bxt_ddi_phy_uninit(dev_priv, power_well->data); + bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); } static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return bxt_ddi_phy_is_enabled(dev_priv, power_well->data); + return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); } static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) @@ -982,16 +669,16 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); if (IS_GEMINILAKE(dev_priv)) { power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); } } @@ -1089,7 +776,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, static void vlv_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - enum punit_power_well power_well_id = power_well->id; + enum i915_power_well_id power_well_id = power_well->id; u32 mask; u32 state; u32 ctrl; @@ -1137,7 +824,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv, static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - int power_well_id = power_well->id; + enum i915_power_well_id power_well_id = power_well->id; bool enabled = false; u32 mask; u32 state; @@ -1324,8 +1011,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) -static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, - int power_well_id) +static struct i915_power_well * +lookup_power_well(struct drm_i915_private *dev_priv, + enum i915_power_well_id power_well_id) { struct i915_power_domains *power_domains = &dev_priv->power_domains; int i; @@ -1672,7 +1360,7 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - enum pipe pipe = power_well->id; + enum pipe pipe = PIPE_A; bool enabled; u32 state, ctrl; @@ -1702,7 +1390,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - enum pipe pipe = power_well->id; + enum pipe pipe = PIPE_A; u32 state; u32 ctrl; @@ -1735,7 +1423,7 @@ out: static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN_ON_ONCE(power_well->id != PIPE_A); + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); chv_set_pipe_power_well(dev_priv, power_well, true); @@ -1745,7 +1433,7 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN_ON_ONCE(power_well->id != PIPE_A); + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); vlv_display_power_well_deinit(dev_priv); @@ -1861,37 +1549,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, intel_runtime_pm_put(dev_priv); } -#define HSW_DISPLAY_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) - -#define BDW_DISPLAY_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ +#define I830_PIPES_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ BIT_ULL(POWER_DOMAIN_INIT)) #define VLV_DISPLAY_POWER_DOMAINS ( \ @@ -1974,13 +1638,201 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_AUX_D) | \ BIT_ULL(POWER_DOMAIN_INIT)) -#define I830_PIPES_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ +#define HSW_DISPLAY_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define BDW_DISPLAY_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_GMBUS) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) +#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) +#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) +#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { @@ -2010,6 +1862,7 @@ static struct i915_power_well i9xx_always_on_power_well[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, }; @@ -2026,11 +1879,13 @@ static struct i915_power_well i830_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "pipes", .domains = I830_PIPES_POWER_DOMAINS, .ops = &i830_pipes_power_well_ops, + .id = I830_DISP_PW_PIPES, }, }; @@ -2041,13 +1896,6 @@ static const struct i915_power_well_ops hsw_power_well_ops = { .is_enabled = hsw_power_well_enabled, }; -static const struct i915_power_well_ops skl_power_well_ops = { - .sync_hw = skl_power_well_sync_hw, - .enable = skl_power_well_enable, - .disable = skl_power_well_disable, - .is_enabled = skl_power_well_enabled, -}; - static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = gen9_dc_off_power_well_enable, @@ -2068,11 +1916,16 @@ static struct i915_power_well hsw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", .domains = HSW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, + .id = HSW_DISP_PW_GLOBAL, + { + .hsw.has_vga = true, + }, }, }; @@ -2082,11 +1935,17 @@ static struct i915_power_well bdw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", .domains = BDW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, + .id = HSW_DISP_PW_GLOBAL, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + }, }, }; @@ -2117,7 +1976,7 @@ static struct i915_power_well vlv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = PUNIT_POWER_WELL_ALWAYS_ON, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2175,6 +2034,7 @@ static struct i915_power_well chv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2184,7 +2044,7 @@ static struct i915_power_well chv_power_wells[] = { * required for any pipe to work. */ .domains = CHV_DISPLAY_POWER_DOMAINS, - .id = PIPE_A, + .id = CHV_DISP_PW_PIPE_A, .ops = &chv_pipe_power_well_ops, }, { @@ -2202,7 +2062,7 @@ static struct i915_power_well chv_power_wells[] = { }; bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, - int power_well_id) + enum i915_power_well_id power_well_id) { struct i915_power_well *power_well; bool ret; @@ -2219,20 +2079,23 @@ static struct i915_power_well skl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = SKL_DISP_PW_ALWAYS_ON, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "MISC IO power well", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_MISC_IO, }, { @@ -2244,31 +2107,36 @@ static struct i915_power_well skl_power_wells[] = { { .name = "power well 2", .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "DDI A/E IO power well", .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_A_E, }, { .name = "DDI B IO power well", .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, { .name = "DDI D IO power well", .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_D, }, }; @@ -2279,12 +2147,16 @@ static struct i915_power_well bxt_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "DC off", @@ -2295,22 +2167,31 @@ static struct i915_power_well bxt_power_wells[] = { { .name = "power well 2", .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "dpio-common-a", .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .data = DPIO_PHY1, + { + .bxt.phy = DPIO_PHY1, + }, }, { .name = "dpio-common-bc", .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .data = DPIO_PHY0, + { + .bxt.phy = DPIO_PHY0, + }, }, }; @@ -2320,13 +2201,17 @@ static struct i915_power_well glk_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "DC off", @@ -2337,64 +2222,75 @@ static struct i915_power_well glk_power_wells[] = { { .name = "power well 2", .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "dpio-common-a", .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .data = DPIO_PHY1, + { + .bxt.phy = DPIO_PHY1, + }, }, { .name = "dpio-common-b", .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .data = DPIO_PHY0, + { + .bxt.phy = DPIO_PHY0, + }, }, { .name = "dpio-common-c", .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = GLK_DPIO_CMN_C, - .data = DPIO_PHY2, + { + .bxt.phy = DPIO_PHY2, + }, }, { .name = "AUX A", .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_A, }, { .name = "AUX B", .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_B, }, { .name = "AUX C", .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_C, }, { .name = "DDI A IO power well", .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_DDI_A, }, { .name = "DDI B IO power well", .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, }; @@ -2405,36 +2301,40 @@ static struct i915_power_well cnl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "AUX A", .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_A, }, { .name = "AUX B", .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_B, }, { .name = "AUX C", .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_C, }, { .name = "AUX D", .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_D, }, { @@ -2446,31 +2346,36 @@ static struct i915_power_well cnl_power_wells[] = { { .name = "power well 2", .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "DDI A IO power well", .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_DDI_A, }, { .name = "DDI B IO power well", .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, { .name = "DDI D IO power well", .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_D, }, }; @@ -2534,6 +2439,22 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, return mask; } +static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) +{ + struct i915_power_domains *power_domains = &dev_priv->power_domains; + u64 power_well_ids; + int i; + + power_well_ids = 0; + for (i = 0; i < power_domains->power_well_count; i++) { + enum i915_power_well_id id = power_domains->power_wells[i].id; + + WARN_ON(id >= sizeof(power_well_ids) * 8); + WARN_ON(power_well_ids & BIT_ULL(id)); + power_well_ids |= BIT_ULL(id); + } +} + #define set_power_wells(power_domains, __power_wells) ({ \ (power_domains)->power_wells = (__power_wells); \ (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ @@ -2585,6 +2506,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) set_power_wells(power_domains, i9xx_always_on_power_well); } + assert_power_well_ids_unique(dev_priv); + return 0; } @@ -2784,30 +2707,67 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv) usleep_range(10, 30); /* 10 us delay per Bspec */ } -#define CNL_PROCMON_IDX(val) \ - (((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT) -#define NUM_CNL_PROCMON \ - (CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1) +enum { + PROCMON_0_85V_DOT_0, + PROCMON_0_95V_DOT_0, + PROCMON_0_95V_DOT_1, + PROCMON_1_05V_DOT_0, + PROCMON_1_05V_DOT_1, +}; static const struct cnl_procmon { u32 dw1, dw9, dw10; -} cnl_procmon_values[NUM_CNL_PROCMON] = { - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] = - { .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] = - { .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, - [CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] = - { .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, - [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] = - { .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, - [CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] = - { .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, +} cnl_procmon_values[] = { + [PROCMON_0_85V_DOT_0] = + { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, + [PROCMON_0_95V_DOT_0] = + { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, + [PROCMON_0_95V_DOT_1] = + { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, + [PROCMON_1_05V_DOT_0] = + { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, + [PROCMON_1_05V_DOT_1] = + { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, }; +static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv) +{ + const struct cnl_procmon *procmon; + u32 val; + + val = I915_READ(CNL_PORT_COMP_DW3); + switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { + default: + MISSING_CASE(val); + case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: + procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; + break; + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: + procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; + break; + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: + procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; + break; + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: + procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; + break; + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: + procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; + break; + } + + val = I915_READ(CNL_PORT_COMP_DW1); + val &= ~((0xff << 16) | 0xff); + val |= procmon->dw1; + I915_WRITE(CNL_PORT_COMP_DW1, val); + + I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9); + I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10); +} + static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) { struct i915_power_domains *power_domains = &dev_priv->power_domains; - const struct cnl_procmon *procmon; struct i915_power_well *well; u32 val; @@ -2820,21 +2780,10 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 2. Enable Comp */ val = I915_READ(CHICKEN_MISC_2); - val &= ~COMP_PWR_DOWN; + val &= ~CNL_COMP_PWR_DOWN; I915_WRITE(CHICKEN_MISC_2, val); - val = I915_READ(CNL_PORT_COMP_DW3); - procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)]; - - WARN_ON(procmon->dw10 == 0); - - val = I915_READ(CNL_PORT_COMP_DW1); - val &= ~((0xff << 16) | 0xff); - val |= procmon->dw1; - I915_WRITE(CNL_PORT_COMP_DW1, val); - - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9); - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10); + cnl_set_procmon_ref_values(dev_priv); val = I915_READ(CNL_PORT_COMP_DW0); val |= COMP_INIT; @@ -2861,9 +2810,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume gen9_dbuf_enable(dev_priv); } -#undef CNL_PROCMON_IDX -#undef NUM_CNL_PROCMON - static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) { struct i915_power_domains *power_domains = &dev_priv->power_domains; @@ -2894,7 +2840,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) /* 5. Disable Comp */ val = I915_READ(CHICKEN_MISC_2); - val |= COMP_PWR_DOWN; + val |= CNL_COMP_PWR_DOWN; I915_WRITE(CHICKEN_MISC_2, val); } diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index bea8152ae859..7437944b388f 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -201,11 +201,8 @@ to_intel_sdvo_connector(struct drm_connector *connector) return container_of(connector, struct intel_sdvo_connector, base.base); } -static struct intel_sdvo_connector_state * -to_intel_sdvo_connector_state(struct drm_connector_state *conn_state) -{ - return container_of(conn_state, struct intel_sdvo_connector_state, base.base); -} +#define to_intel_sdvo_connector_state(conn_state) \ + container_of((conn_state), struct intel_sdvo_connector_state, base.base) static bool intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); @@ -451,23 +448,24 @@ static const char * const cmd_status_names[] = { "Scaling not supported" }; -static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, - const void *args, int args_len) +static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, + const void *args, int args_len, + bool unlocked) { u8 *buf, status; struct i2c_msg *msgs; int i, ret = true; - /* Would be simpler to allocate both in one go ? */ + /* Would be simpler to allocate both in one go ? */ buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); if (!buf) return false; msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); if (!msgs) { - kfree(buf); + kfree(buf); return false; - } + } intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); @@ -498,7 +496,10 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, msgs[i+2].len = 1; msgs[i+2].buf = &status; - ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); + if (unlocked) + ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); + else + ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); if (ret < 0) { DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); ret = false; @@ -516,6 +517,12 @@ out: return ret; } +static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, + const void *args, int args_len) +{ + return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); +} + static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, void *response, int response_len) { @@ -602,13 +609,13 @@ static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjust return 4; } -static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, - u8 ddc_bus) +static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, + u8 ddc_bus) { /* This must be the immediately preceding write before the i2c xfer */ - return intel_sdvo_write_cmd(intel_sdvo, - SDVO_CMD_SET_CONTROL_BUS_SWITCH, - &ddc_bus, 1); + return __intel_sdvo_write_cmd(intel_sdvo, + SDVO_CMD_SET_CONTROL_BUS_SWITCH, + &ddc_bus, 1, false); } static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) @@ -988,7 +995,7 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, } static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, - struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *pipe_config) { uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; union hdmi_infoframe frame; @@ -1022,7 +1029,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, } static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, - struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state) { struct intel_sdvo_tv_format format; uint32_t format_map; @@ -1192,9 +1199,9 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, } while (0) static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, - struct intel_sdvo_connector_state *sdvo_state) + const struct intel_sdvo_connector_state *sdvo_state) { - struct drm_connector_state *conn_state = &sdvo_state->base.base; + const struct drm_connector_state *conn_state = &sdvo_state->base.base; struct intel_sdvo_connector *intel_sdvo_conn = to_intel_sdvo_connector(conn_state->connector); uint16_t val; @@ -1248,14 +1255,15 @@ static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, } static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, - struct intel_crtc_state *crtc_state, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; - struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(conn_state); - struct drm_display_mode *mode = &crtc_state->base.mode; + const struct intel_sdvo_connector_state *sdvo_state = + to_intel_sdvo_connector_state(conn_state); + const struct drm_display_mode *mode = &crtc_state->base.mode; struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); u32 sdvox; struct intel_sdvo_in_out_map in_out; @@ -1349,8 +1357,10 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, else sdvox |= SDVO_PIPE_SEL(crtc->pipe); - if (crtc_state->has_audio) + if (crtc_state->has_audio) { + WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4); sdvox |= SDVO_AUDIO_ENABLE; + } if (INTEL_GEN(dev_priv) >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ @@ -1480,6 +1490,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, if (sdvox & HDMI_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; + if (sdvox & SDVO_AUDIO_ENABLE) + pipe_config->has_audio = true; + if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, &val, 1)) { if (val == SDVO_ENCODE_HDMI) @@ -1492,8 +1505,8 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, } static void intel_disable_sdvo(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); @@ -1537,21 +1550,21 @@ static void intel_disable_sdvo(struct intel_encoder *encoder, } static void pch_disable_sdvo(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { } static void pch_post_disable_sdvo(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { intel_disable_sdvo(encoder, old_crtc_state, old_conn_state); } static void intel_enable_sdvo(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -2453,6 +2466,7 @@ static bool intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) { struct drm_encoder *encoder = &intel_sdvo->base.base; + struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct drm_connector *connector; struct intel_encoder *intel_encoder = to_intel_encoder(encoder); struct intel_connector *intel_connector; @@ -2488,7 +2502,9 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) encoder->encoder_type = DRM_MODE_ENCODER_TMDS; connector->connector_type = DRM_MODE_CONNECTOR_DVID; - if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { + /* gen3 doesn't do the hdmi bits in the SDVO register */ + if (INTEL_GEN(dev_priv) >= 4 && + intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; intel_sdvo->is_hdmi = true; } @@ -2924,7 +2940,7 @@ static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, { struct intel_sdvo *sdvo = adapter->algo_data; - if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) + if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) return -EIO; return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); @@ -2941,6 +2957,33 @@ static const struct i2c_algorithm intel_sdvo_ddc_proxy = { .functionality = intel_sdvo_ddc_proxy_func }; +static void proxy_lock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); +} + +static int proxy_trylock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); +} + +static void proxy_unlock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); +} + +static const struct i2c_lock_operations proxy_lock_ops = { + .lock_bus = proxy_lock_bus, + .trylock_bus = proxy_trylock_bus, + .unlock_bus = proxy_unlock_bus, +}; + static bool intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, struct drm_i915_private *dev_priv) @@ -2953,6 +2996,7 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, sdvo->ddc.dev.parent = &pdev->dev; sdvo->ddc.algo_data = sdvo; sdvo->ddc.algo = &intel_sdvo_ddc_proxy; + sdvo->ddc.lock_ops = &proxy_lock_ops; return i2c_add_adapter(&sdvo->ddc) == 0; } diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 4c6b387fa9dc..b0d6e3e28d07 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -30,6 +30,7 @@ * support. */ #include <drm/drmP.h> +#include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_fourcc.h> #include <drm/drm_rect.h> @@ -69,8 +70,7 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, /** * intel_pipe_update_start() - start update of a set of display registers - * @crtc: the crtc of which the registers are going to be updated - * @start_vbl_count: vblank counter return pointer used for error checking + * @new_crtc_state: the new crtc state * * Mark the start of an update to pipe registers that should be updated * atomically regarding vblank. If the next vblank will happens within @@ -78,18 +78,18 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, * * After a successful call to this function, interrupts will be disabled * until a subsequent call to intel_pipe_update_end(). That is done to - * avoid random delays. The value written to @start_vbl_count should be - * supplied to intel_pipe_update_end() for error checking. + * avoid random delays. */ -void intel_pipe_update_start(struct intel_crtc *crtc) +void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; + const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode; long timeout = msecs_to_jiffies_timeout(1); int scanline, min, max, vblank_start; wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && - intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI); + intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI); DEFINE_WAIT(wait); vblank_start = adjusted_mode->crtc_vblank_start; @@ -169,41 +169,35 @@ void intel_pipe_update_start(struct intel_crtc *crtc) /** * intel_pipe_update_end() - end update of a set of display registers - * @crtc: the crtc of which the registers were updated - * @start_vbl_count: start vblank counter (used for error checking) + * @new_crtc_state: the new crtc state * * Mark the end of an update started with intel_pipe_update_start(). This * re-enables interrupts and verifies the update was actually completed - * before a vblank using the value of @start_vbl_count. + * before a vblank. */ -void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) +void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); enum pipe pipe = crtc->pipe; int scanline_end = intel_get_crtc_scanline(crtc); u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); ktime_t end_vbl_time = ktime_get(); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (work) { - work->flip_queued_vblank = end_vbl_count; - smp_mb__before_atomic(); - atomic_set(&work->pending, 1); - } - trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); /* We're still in the vblank-evade critical section, this can't race. * Would be slightly nice to just grab the vblank count and arm the * event outside of the critical section - the spinlock might spin for a * while ... */ - if (crtc->base.state->event) { + if (new_crtc_state->base.event) { WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); spin_lock(&crtc->base.dev->event_lock); - drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event); + drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event); spin_unlock(&crtc->base.dev->event_lock); - crtc->base.state->event = NULL; + new_crtc_state->base.event = NULL; } local_irq_enable(); @@ -244,6 +238,7 @@ skl_update_plane(struct intel_plane *plane, u32 surf_addr = plane_state->main.offset; unsigned int rotation = plane_state->base.rotation; u32 stride = skl_plane_stride(fb, 0, rotation); + u32 aux_stride = skl_plane_stride(fb, 1, rotation); int crtc_x = plane_state->base.dst.x1; int crtc_y = plane_state->base.dst.y1; uint32_t crtc_w = drm_rect_width(&plane_state->base.dst); @@ -278,6 +273,10 @@ skl_update_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), + (plane_state->aux.offset - surf_addr) | aux_stride); + I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->aux.y << 16) | plane_state->aux.x); /* program plane scaler */ if (plane_state->scaler_id >= 0) { @@ -1038,6 +1037,12 @@ static const uint32_t g4x_plane_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t i9xx_plane_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint32_t snb_plane_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, @@ -1073,6 +1078,122 @@ static uint32_t skl_plane_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_plane_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + +static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + /* This is the same as primary plane since SKL has universal planes */ + switch (format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == I915_FORMAT_MOD_Yf_TILED) + return true; + /* fall through */ + case DRM_FORMAT_C8: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED || + modifier == I915_FORMAT_MOD_Y_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && + modifier != DRM_FORMAT_MOD_LINEAR) + return false; + + if (INTEL_GEN(dev_priv) >= 9) + return skl_sprite_plane_format_mod_supported(plane, format, modifier); + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + return vlv_sprite_plane_format_mod_supported(plane, format, modifier); + else + return g4x_sprite_plane_format_mod_supported(plane, format, modifier); + + unreachable(); +} + +static const struct drm_plane_funcs intel_sprite_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = intel_plane_destroy, + .atomic_get_property = intel_plane_atomic_get_property, + .atomic_set_property = intel_plane_atomic_set_property, + .atomic_duplicate_state = intel_plane_duplicate_state, + .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_sprite_plane_format_mod_supported, +}; + struct intel_plane * intel_sprite_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, int plane) @@ -1081,6 +1202,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, struct intel_plane_state *state = NULL; unsigned long possible_crtcs; const uint32_t *plane_formats; + const uint64_t *modifiers; unsigned int supported_rotations; int num_plane_formats; int ret; @@ -1098,7 +1220,17 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } intel_plane->base.state = &state->base; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10) { + intel_plane->can_scale = true; + state->scaler_id = -1; + + intel_plane->update_plane = skl_update_plane; + intel_plane->disable_plane = skl_disable_plane; + + plane_formats = skl_plane_formats; + num_plane_formats = ARRAY_SIZE(skl_plane_formats); + modifiers = skl_plane_format_modifiers; + } else if (INTEL_GEN(dev_priv) >= 9) { intel_plane->can_scale = true; state->scaler_id = -1; @@ -1107,6 +1239,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); + modifiers = skl_plane_format_modifiers; } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { intel_plane->can_scale = false; intel_plane->max_downscale = 1; @@ -1116,6 +1249,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = vlv_plane_formats; num_plane_formats = ARRAY_SIZE(vlv_plane_formats); + modifiers = i9xx_plane_format_modifiers; } else if (INTEL_GEN(dev_priv) >= 7) { if (IS_IVYBRIDGE(dev_priv)) { intel_plane->can_scale = true; @@ -1130,6 +1264,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = snb_plane_formats; num_plane_formats = ARRAY_SIZE(snb_plane_formats); + modifiers = i9xx_plane_format_modifiers; } else { intel_plane->can_scale = true; intel_plane->max_downscale = 16; @@ -1137,6 +1272,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = g4x_update_plane; intel_plane->disable_plane = g4x_disable_plane; + modifiers = i9xx_plane_format_modifiers; if (IS_GEN6(dev_priv)) { plane_formats = snb_plane_formats; num_plane_formats = ARRAY_SIZE(snb_plane_formats); @@ -1169,15 +1305,17 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 9) ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, - possible_crtcs, &intel_plane_funcs, + possible_crtcs, &intel_sprite_plane_funcs, plane_formats, num_plane_formats, - NULL, DRM_PLANE_TYPE_OVERLAY, + modifiers, + DRM_PLANE_TYPE_OVERLAY, "plane %d%c", plane + 2, pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, - possible_crtcs, &intel_plane_funcs, + possible_crtcs, &intel_sprite_plane_funcs, plane_formats, num_plane_formats, - NULL, DRM_PLANE_TYPE_OVERLAY, + modifiers, + DRM_PLANE_TYPE_OVERLAY, "sprite %c", sprite_name(pipe, plane)); if (ret) goto fail; diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 906893c006d8..0cc999fa09c5 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -814,8 +814,8 @@ intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) static void intel_enable_tv(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -829,8 +829,8 @@ intel_enable_tv(struct intel_encoder *encoder, static void intel_disable_tv(struct intel_encoder *encoder, - struct intel_crtc_state *old_crtc_state, - struct drm_connector_state *old_conn_state) + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -838,7 +838,7 @@ intel_disable_tv(struct intel_encoder *encoder, I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); } -static const struct tv_mode *intel_tv_mode_find(struct drm_connector_state *conn_state) +static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state) { int format = conn_state->tv.mode; @@ -976,8 +976,8 @@ static void set_color_conversion(struct drm_i915_private *dev_priv, } static void intel_tv_pre_enable(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state) + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 27e072cc96eb..0178ba42a0e5 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -94,7 +94,7 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv); } -static void guc_write_irq_trigger(struct intel_guc *guc) +static void gen8_guc_raise_irq(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); @@ -109,7 +109,7 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv) mutex_init(&guc->send_mutex); guc->send = intel_guc_send_nop; - guc->notify = guc_write_irq_trigger; + guc->notify = gen8_guc_raise_irq; } static void fetch_uc_fw(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index deb4430541cf..0529af7cfbb8 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1251,7 +1251,7 @@ static const struct register_whitelist { } whitelist[] = { { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), - .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, + .size = 8, .gen_bitmask = GEN_RANGE(4, 10) }, }; int i915_reg_read_ioctl(struct drm_device *dev, @@ -1497,7 +1497,6 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, [VECS] = GEN6_GRDOM_VECS, }; u32 hw_mask; - int ret; if (engine_mask == ALL_ENGINES) { hw_mask = GEN6_GRDOM_FULL; @@ -1509,11 +1508,7 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, hw_mask |= hw_engine_mask[engine->id]; } - ret = gen6_hw_domain_reset(dev_priv, hw_mask); - - intel_uncore_forcewake_reset(dev_priv, true); - - return ret; + return gen6_hw_domain_reset(dev_priv, hw_mask); } /** diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h index a92e7762f596..404569c9fdfc 100644 --- a/drivers/gpu/drm/i915/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h @@ -149,16 +149,19 @@ struct bdb_general_features { u8 ssc_freq:1; u8 enable_lfp_on_override:1; u8 disable_ssc_ddt:1; - u8 rsvd7:1; + u8 underscan_vga_timings:1; u8 display_clock_mode:1; - u8 rsvd8:1; /* finish byte */ + u8 vbios_hotplug_support:1; /* bits 3 */ u8 disable_smooth_vision:1; u8 single_dvi:1; - u8 rsvd9:1; + u8 rotate_180:1; /* 181 */ u8 fdi_rx_polarity_inverted:1; - u8 rsvd10:4; /* finish byte */ + u8 vbios_extended_mode:1; /* 160 */ + u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ + u8 panel_best_fit_timing:1; /* 160 */ + u8 ignore_strap_state:1; /* 160 */ /* bits 4 */ u8 legacy_monitor_detect; @@ -167,9 +170,10 @@ struct bdb_general_features { u8 int_crt_support:1; u8 int_tv_support:1; u8 int_efp_support:1; - u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ - u8 rsvd11:3; /* finish byte */ + u8 dp_ssc_dongle_supported:1; + u8 rsvd11:2; /* finish byte */ } __packed; /* pre-915 */ @@ -206,6 +210,56 @@ struct bdb_general_features { #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 +/* Add the device class for LFP, TV, HDMI */ +#define DEVICE_TYPE_INT_LFP 0x1022 +#define DEVICE_TYPE_INT_TV 0x1009 +#define DEVICE_TYPE_HDMI 0x60D2 +#define DEVICE_TYPE_DP 0x68C6 +#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 +#define DEVICE_TYPE_eDP 0x78C6 + +#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) +#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) +#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) +#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) +#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) +#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) +#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) +#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) +#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) +#define DEVICE_TYPE_LVDS_SINGALING (1 << 5) +#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) +#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) +#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) +#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) +#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) + +/* + * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the + * system, the other bits may or may not be set for eDP outputs. + */ +#define DEVICE_TYPE_eDP_BITS \ + (DEVICE_TYPE_INTERNAL_CONNECTOR | \ + DEVICE_TYPE_MIPI_OUTPUT | \ + DEVICE_TYPE_COMPOSITE_OUTPUT | \ + DEVICE_TYPE_DUAL_CHANNEL | \ + DEVICE_TYPE_LVDS_SINGALING | \ + DEVICE_TYPE_TMDS_DVI_SIGNALING | \ + DEVICE_TYPE_VIDEO_SIGNALING | \ + DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ + DEVICE_TYPE_ANALOG_OUTPUT) + +#define DEVICE_TYPE_DP_DUAL_MODE_BITS \ + (DEVICE_TYPE_INTERNAL_CONNECTOR | \ + DEVICE_TYPE_MIPI_OUTPUT | \ + DEVICE_TYPE_COMPOSITE_OUTPUT | \ + DEVICE_TYPE_LVDS_SINGALING | \ + DEVICE_TYPE_TMDS_DVI_SIGNALING | \ + DEVICE_TYPE_VIDEO_SIGNALING | \ + DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ + DEVICE_TYPE_DIGITAL_OUTPUT | \ + DEVICE_TYPE_ANALOG_OUTPUT) + #define DEVICE_CFG_NONE 0x00 #define DEVICE_CFG_12BIT_DVOB 0x01 #define DEVICE_CFG_12BIT_DVOC 0x02 @@ -226,77 +280,126 @@ struct bdb_general_features { #define DEVICE_WIRE_DVOB_MASTER 0x0d #define DEVICE_WIRE_DVOC_MASTER 0x0e +/* dvo_port pre BDB 155 */ #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ #define DEVICE_PORT_DVOB 0x01 #define DEVICE_PORT_DVOC 0x02 +/* dvo_port BDB 155+ */ +#define DVO_PORT_HDMIA 0 +#define DVO_PORT_HDMIB 1 +#define DVO_PORT_HDMIC 2 +#define DVO_PORT_HDMID 3 +#define DVO_PORT_LVDS 4 +#define DVO_PORT_TV 5 +#define DVO_PORT_CRT 6 +#define DVO_PORT_DPB 7 +#define DVO_PORT_DPC 8 +#define DVO_PORT_DPD 9 +#define DVO_PORT_DPA 10 +#define DVO_PORT_DPE 11 /* 193 */ +#define DVO_PORT_HDMIE 12 /* 193 */ +#define DVO_PORT_MIPIA 21 /* 171 */ +#define DVO_PORT_MIPIB 22 /* 171 */ +#define DVO_PORT_MIPIC 23 /* 171 */ +#define DVO_PORT_MIPID 24 /* 171 */ + +#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 + /* - * We used to keep this struct but without any version control. We should avoid - * using it in the future, but it should be safe to keep using it in the old - * code. Do not change; we rely on its size. + * The child device config, aka the display device data structure, provides a + * description of a port and its configuration on the platform. + * + * The child device config size has been increased, and fields have been added + * and their meaning has changed over time. Care must be taken when accessing + * basically any of the fields to ensure the correct interpretation for the BDB + * version in question. + * + * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve + * space for the full structure below, and initialize the tail not actually + * present in VBT to zeros. Accessing those fields is fine, as long as the + * default zero is taken into account, again according to the BDB version. + * + * BDB versions 155 and below are considered legacy, and version 155 seems to be + * a baseline for some of the VBT documentation. When adding new fields, please + * include the BDB version when the field was added, if it's above that. */ -struct old_child_dev_config { +struct child_device_config { u16 handle; - u16 device_type; - u8 device_id[10]; /* ascii string */ - u16 addin_offset; - u8 dvo_port; /* See Device_PORT_* above */ - u8 i2c_pin; - u8 slave_addr; - u8 ddc_pin; - u16 edid_ptr; - u8 dvo_cfg; /* See DEVICE_CFG_* above */ - u8 dvo2_port; - u8 i2c2_pin; - u8 slave2_addr; - u8 ddc2_pin; - u8 capabilities; - u8 dvo_wiring;/* See DEVICE_WIRE_* above */ - u8 dvo2_wiring; - u16 extended_type; - u8 dvo_function; -} __packed; + u16 device_type; /* See DEVICE_TYPE_* above */ + + union { + u8 device_id[10]; /* ascii string */ + struct { + u8 i2c_speed; + u8 dp_onboard_redriver; /* 158 */ + u8 dp_ondock_redriver; /* 158 */ + u8 hdmi_level_shifter_value:4; /* 169 */ + u8 hdmi_max_data_rate:4; /* 204 */ + u16 dtd_buf_ptr; /* 161 */ + u8 edidless_efp:1; /* 161 */ + u8 compression_enable:1; /* 198 */ + u8 compression_method:1; /* 198 */ + u8 ganged_edp:1; /* 202 */ + u8 reserved0:4; + u8 compression_structure_index:4; /* 198 */ + u8 reserved1:4; + u8 slave_port; /* 202 */ + u8 reserved2; + } __packed; + } __packed; -/* This one contains field offsets that are known to be common for all BDB - * versions. Notice that the meaning of the contents contents may still change, - * but at least the offsets are consistent. */ - -struct common_child_dev_config { - u16 handle; - u16 device_type; - u8 not_common1[12]; - u8 dvo_port; - u8 not_common2[2]; + u16 addin_offset; + u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ + u8 i2c_pin; + u8 slave_addr; u8 ddc_pin; u16 edid_ptr; u8 dvo_cfg; /* See DEVICE_CFG_* above */ - u8 efp_routed:1; - u8 lane_reversal:1; - u8 lspcon:1; - u8 iboost:1; - u8 hpd_invert:1; - u8 flag_reserved:3; - u8 hdmi_support:1; - u8 dp_support:1; - u8 tmds_support:1; - u8 support_reserved:5; - u8 aux_channel; - u8 not_common3[11]; - u8 iboost_level; -} __packed; + union { + struct { + u8 dvo2_port; + u8 i2c2_pin; + u8 slave2_addr; + u8 ddc2_pin; + } __packed; + struct { + u8 efp_routed:1; /* 158 */ + u8 lane_reversal:1; /* 184 */ + u8 lspcon:1; /* 192 */ + u8 iboost:1; /* 196 */ + u8 hpd_invert:1; /* 196 */ + u8 flag_reserved:3; + u8 hdmi_support:1; /* 158 */ + u8 dp_support:1; /* 158 */ + u8 tmds_support:1; /* 158 */ + u8 support_reserved:5; + u8 aux_channel; + u8 dongle_detect; + } __packed; + } __packed; + + u8 pipe_cap:2; + u8 sdvo_stall:1; /* 158 */ + u8 hpd_status:2; + u8 integrated_encoder:1; + u8 capabilities_reserved:2; + u8 dvo_wiring; /* See DEVICE_WIRE_* above */ + + union { + u8 dvo2_wiring; + u8 mipi_bridge_type; /* 171 */ + } __packed; -/* This field changes depending on the BDB version, so the most reliable way to - * read it is by checking the BDB version and reading the raw pointer. */ -union child_device_config { - /* This one is safe to be used anywhere, but the code should still check - * the BDB version. */ - u8 raw[33]; - /* This one should only be kept for legacy code. */ - struct old_child_dev_config old; - /* This one should also be safe to use anywhere, even without version - * checks. */ - struct common_child_dev_config common; + u16 extended_type; + u8 dvo_function; + u8 dp_usb_type_c:1; /* 195 */ + u8 flags2_reserved:7; /* 195 */ + u8 dp_gpio_index; /* 195 */ + u16 dp_gpio_pin_num; /* 195 */ + u8 dp_iboost_level:4; /* 196 */ + u8 hdmi_iboost_level:4; /* 196 */ } __packed; struct bdb_general_definitions { @@ -585,23 +688,38 @@ struct bdb_driver_features { #define EDP_VSWING_1_2V 3 -struct edp_link_params { +struct edp_fast_link_params { u8 rate:4; u8 lanes:4; u8 preemphasis:4; u8 vswing:4; } __packed; +struct edp_pwm_delays { + u16 pwm_on_to_backlight_enable; + u16 backlight_disable_to_pwm_off; +} __packed; + +struct edp_full_link_params { + u8 preemphasis:4; + u8 vswing:4; +} __packed; + struct bdb_edp { struct edp_power_seq power_seqs[16]; u32 color_depth; - struct edp_link_params link_params[16]; + struct edp_fast_link_params fast_link_params[16]; u32 sdrrs_msa_timing_delay; /* ith bit indicates enabled/disabled for (i+1)th panel */ - u16 edp_s3d_feature; - u16 edp_t3_optimization; - u64 edp_vswing_preemph; /* v173 */ + u16 edp_s3d_feature; /* 162 */ + u16 edp_t3_optimization; /* 165 */ + u64 edp_vswing_preemph; /* 173 */ + u16 fast_link_training; /* 182 */ + u16 dpcd_600h_write_required; /* 185 */ + struct edp_pwm_delays pwm_delays[16]; /* 186 */ + u16 full_link_params_provided; /* 199 */ + struct edp_full_link_params full_link_params[16]; /* 199 */ } __packed; struct psr_table { @@ -745,81 +863,6 @@ struct bdb_psr { #define SWF14_APM_STANDBY 0x1 #define SWF14_APM_RESTORE 0x0 -/* Add the device class for LFP, TV, HDMI */ -#define DEVICE_TYPE_INT_LFP 0x1022 -#define DEVICE_TYPE_INT_TV 0x1009 -#define DEVICE_TYPE_HDMI 0x60D2 -#define DEVICE_TYPE_DP 0x68C6 -#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 -#define DEVICE_TYPE_eDP 0x78C6 - -#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) -#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) -#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) -#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) -#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) -#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) -#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) -#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) -#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) -#define DEVICE_TYPE_LVDS_SINGALING (1 << 5) -#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) -#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) -#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) -#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) -#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) - -/* - * Bits we care about when checking for DEVICE_TYPE_eDP - * Depending on the system, the other bits may or may not - * be set for eDP outputs. - */ -#define DEVICE_TYPE_eDP_BITS \ - (DEVICE_TYPE_INTERNAL_CONNECTOR | \ - DEVICE_TYPE_MIPI_OUTPUT | \ - DEVICE_TYPE_COMPOSITE_OUTPUT | \ - DEVICE_TYPE_DUAL_CHANNEL | \ - DEVICE_TYPE_LVDS_SINGALING | \ - DEVICE_TYPE_TMDS_DVI_SIGNALING | \ - DEVICE_TYPE_VIDEO_SIGNALING | \ - DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ - DEVICE_TYPE_ANALOG_OUTPUT) - -#define DEVICE_TYPE_DP_DUAL_MODE_BITS \ - (DEVICE_TYPE_INTERNAL_CONNECTOR | \ - DEVICE_TYPE_MIPI_OUTPUT | \ - DEVICE_TYPE_COMPOSITE_OUTPUT | \ - DEVICE_TYPE_LVDS_SINGALING | \ - DEVICE_TYPE_TMDS_DVI_SIGNALING | \ - DEVICE_TYPE_VIDEO_SIGNALING | \ - DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ - DEVICE_TYPE_DIGITAL_OUTPUT | \ - DEVICE_TYPE_ANALOG_OUTPUT) - -/* define the DVO port for HDMI output type */ -#define DVO_B 1 -#define DVO_C 2 -#define DVO_D 3 - -/* Possible values for the "DVO Port" field for versions >= 155: */ -#define DVO_PORT_HDMIA 0 -#define DVO_PORT_HDMIB 1 -#define DVO_PORT_HDMIC 2 -#define DVO_PORT_HDMID 3 -#define DVO_PORT_LVDS 4 -#define DVO_PORT_TV 5 -#define DVO_PORT_CRT 6 -#define DVO_PORT_DPB 7 -#define DVO_PORT_DPC 8 -#define DVO_PORT_DPD 9 -#define DVO_PORT_DPA 10 -#define DVO_PORT_DPE 11 -#define DVO_PORT_HDMIE 12 -#define DVO_PORT_MIPIA 21 -#define DVO_PORT_MIPIB 22 -#define DVO_PORT_MIPIC 23 -#define DVO_PORT_MIPID 24 - /* Block 52 contains MIPI configuration block * 6 * bdb_mipi_config, followed by 6 pps data block * block below diff --git a/drivers/gpu/drm/i915/selftests/huge_gem_object.c b/drivers/gpu/drm/i915/selftests/huge_gem_object.c index caf76af36aba..c5c7e8efbdd3 100644 --- a/drivers/gpu/drm/i915/selftests/huge_gem_object.c +++ b/drivers/gpu/drm/i915/selftests/huge_gem_object.c @@ -111,6 +111,7 @@ huge_gem_object(struct drm_i915_private *i915, dma_addr_t dma_size) { struct drm_i915_gem_object *obj; + unsigned int cache_level; GEM_BUG_ON(!phys_size || phys_size > dma_size); GEM_BUG_ON(!IS_ALIGNED(phys_size, PAGE_SIZE)); @@ -128,9 +129,8 @@ huge_gem_object(struct drm_i915_private *i915, obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); obj->scratch = phys_size; return obj; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c index 95d4aebc0181..35d778d70626 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c @@ -241,7 +241,7 @@ static bool always_valid(struct drm_i915_private *i915) static bool needs_mi_store_dword(struct drm_i915_private *i915) { - return igt_can_mi_store_dword_imm(i915); + return intel_engine_can_store_dword(i915->engine[RCS]); } static const struct igt_coherency_mode { diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 12b85b3278cd..fb0a58fc8348 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -38,8 +38,6 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value) u32 *cmd; int err; - GEM_BUG_ON(!igt_can_mi_store_dword_imm(vma->vm->i915)); - size = (4 * count + 1) * sizeof(u32); size = round_up(size, PAGE_SIZE); obj = i915_gem_object_create_internal(vma->vm->i915, size); @@ -123,6 +121,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj, int err; GEM_BUG_ON(obj->base.size > vm->total); + GEM_BUG_ON(!intel_engine_can_store_dword(engine)); vma = i915_vma_instance(obj, vm, NULL); if (IS_ERR(vma)) @@ -359,6 +358,9 @@ static int igt_ctx_exec(void *arg) } for_each_engine(engine, i915, id) { + if (!intel_engine_can_store_dword(engine)) + continue; + if (!obj) { obj = create_test_object(ctx, file, &objects); if (IS_ERR(obj)) { diff --git a/drivers/gpu/drm/i915/selftests/i915_random.c b/drivers/gpu/drm/i915/selftests/i915_random.c index d044bf9a6feb..222c511bea49 100644 --- a/drivers/gpu/drm/i915/selftests/i915_random.c +++ b/drivers/gpu/drm/i915/selftests/i915_random.c @@ -62,7 +62,7 @@ unsigned int *i915_random_order(unsigned int count, struct rnd_state *state) { unsigned int *order, i; - order = kmalloc_array(count, sizeof(*order), GFP_TEMPORARY); + order = kmalloc_array(count, sizeof(*order), GFP_KERNEL); if (!order) return order; diff --git a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c index 7276194c04f7..828904b7d468 100644 --- a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c @@ -117,12 +117,12 @@ static int igt_random_insert_remove(void *arg) mock_engine_reset(engine); - waiters = kvmalloc_array(count, sizeof(*waiters), GFP_TEMPORARY); + waiters = kvmalloc_array(count, sizeof(*waiters), GFP_KERNEL); if (!waiters) goto out_engines; bitmap = kcalloc(DIV_ROUND_UP(count, BITS_PER_LONG), sizeof(*bitmap), - GFP_TEMPORARY); + GFP_KERNEL); if (!bitmap) goto out_waiters; @@ -187,12 +187,12 @@ static int igt_insert_complete(void *arg) mock_engine_reset(engine); - waiters = kvmalloc_array(count, sizeof(*waiters), GFP_TEMPORARY); + waiters = kvmalloc_array(count, sizeof(*waiters), GFP_KERNEL); if (!waiters) goto out_engines; bitmap = kcalloc(DIV_ROUND_UP(count, BITS_PER_LONG), sizeof(*bitmap), - GFP_TEMPORARY); + GFP_KERNEL); if (!bitmap) goto out_waiters; @@ -368,7 +368,7 @@ static int igt_wakeup(void *arg) mock_engine_reset(engine); - waiters = kvmalloc_array(count, sizeof(*waiters), GFP_TEMPORARY); + waiters = kvmalloc_array(count, sizeof(*waiters), GFP_KERNEL); if (!waiters) goto out_engines; diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 7096c3911cd3..02e52a146ed8 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -22,8 +22,13 @@ * */ +#include <linux/kthread.h> + #include "../i915_selftest.h" +#include "mock_context.h" +#include "mock_drm.h" + struct hang { struct drm_i915_private *i915; struct drm_i915_gem_object *hws; @@ -248,9 +253,6 @@ static int igt_hang_sanitycheck(void *arg) /* Basic check that we can execute our hanging batch */ - if (!igt_can_mi_store_dword_imm(i915)) - return 0; - mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); if (err) @@ -259,6 +261,9 @@ static int igt_hang_sanitycheck(void *arg) for_each_engine(engine, i915, id) { long timeout; + if (!intel_engine_can_store_dword(engine)) + continue; + rq = hang_create_request(&h, engine, i915->kernel_context); if (IS_ERR(rq)) { err = PTR_ERR(rq); @@ -292,6 +297,37 @@ unlock: return err; } +static void global_reset_lock(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags)) + wait_event(i915->gpu_error.reset_queue, + !test_bit(I915_RESET_BACKOFF, + &i915->gpu_error.flags)); + + for_each_engine(engine, i915, id) { + while (test_and_set_bit(I915_RESET_ENGINE + id, + &i915->gpu_error.flags)) + wait_on_bit(&i915->gpu_error.flags, + I915_RESET_ENGINE + id, + TASK_UNINTERRUPTIBLE); + } +} + +static void global_reset_unlock(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + for_each_engine(engine, i915, id) + clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags); + + clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + wake_up_all(&i915->gpu_error.reset_queue); +} + static int igt_global_reset(void *arg) { struct drm_i915_private *i915 = arg; @@ -300,13 +336,13 @@ static int igt_global_reset(void *arg) /* Check that we can issue a global GPU reset */ - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); set_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags); mutex_lock(&i915->drm.struct_mutex); reset_count = i915_reset_count(&i915->gpu_error); - i915_reset(i915); + i915_reset(i915, I915_RESET_QUIET); if (i915_reset_count(&i915->gpu_error) == reset_count) { pr_err("No GPU reset recorded!\n"); @@ -315,8 +351,7 @@ static int igt_global_reset(void *arg) mutex_unlock(&i915->drm.struct_mutex); GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags)); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) err = -EIO; @@ -343,7 +378,7 @@ static int igt_reset_engine(void *arg) reset_engine_count = i915_reset_engine_count(&i915->gpu_error, engine); - err = i915_reset_engine(engine); + err = i915_reset_engine(engine, I915_RESET_QUIET); if (err) { pr_err("i915_reset_engine failed\n"); break; @@ -372,6 +407,164 @@ static int igt_reset_engine(void *arg) return err; } +static int active_engine(void *data) +{ + struct intel_engine_cs *engine = data; + struct drm_i915_gem_request *rq[2] = {}; + struct i915_gem_context *ctx[2]; + struct drm_file *file; + unsigned long count = 0; + int err = 0; + + file = mock_file(engine->i915); + if (IS_ERR(file)) + return PTR_ERR(file); + + mutex_lock(&engine->i915->drm.struct_mutex); + ctx[0] = live_context(engine->i915, file); + mutex_unlock(&engine->i915->drm.struct_mutex); + if (IS_ERR(ctx[0])) { + err = PTR_ERR(ctx[0]); + goto err_file; + } + + mutex_lock(&engine->i915->drm.struct_mutex); + ctx[1] = live_context(engine->i915, file); + mutex_unlock(&engine->i915->drm.struct_mutex); + if (IS_ERR(ctx[1])) { + err = PTR_ERR(ctx[1]); + i915_gem_context_put(ctx[0]); + goto err_file; + } + + while (!kthread_should_stop()) { + unsigned int idx = count++ & 1; + struct drm_i915_gem_request *old = rq[idx]; + struct drm_i915_gem_request *new; + + mutex_lock(&engine->i915->drm.struct_mutex); + new = i915_gem_request_alloc(engine, ctx[idx]); + if (IS_ERR(new)) { + mutex_unlock(&engine->i915->drm.struct_mutex); + err = PTR_ERR(new); + break; + } + + rq[idx] = i915_gem_request_get(new); + i915_add_request(new); + mutex_unlock(&engine->i915->drm.struct_mutex); + + if (old) { + i915_wait_request(old, 0, MAX_SCHEDULE_TIMEOUT); + i915_gem_request_put(old); + } + } + + for (count = 0; count < ARRAY_SIZE(rq); count++) + i915_gem_request_put(rq[count]); + +err_file: + mock_file_free(engine->i915, file); + return err; +} + +static int igt_reset_active_engines(void *arg) +{ + struct drm_i915_private *i915 = arg; + struct intel_engine_cs *engine, *active; + enum intel_engine_id id, tmp; + int err = 0; + + /* Check that issuing a reset on one engine does not interfere + * with any other engine. + */ + + if (!intel_has_reset_engine(i915)) + return 0; + + for_each_engine(engine, i915, id) { + struct task_struct *threads[I915_NUM_ENGINES]; + unsigned long resets[I915_NUM_ENGINES]; + unsigned long global = i915_reset_count(&i915->gpu_error); + IGT_TIMEOUT(end_time); + + memset(threads, 0, sizeof(threads)); + for_each_engine(active, i915, tmp) { + struct task_struct *tsk; + + if (active == engine) + continue; + + resets[tmp] = i915_reset_engine_count(&i915->gpu_error, + active); + + tsk = kthread_run(active_engine, active, + "igt/%s", active->name); + if (IS_ERR(tsk)) { + err = PTR_ERR(tsk); + goto unwind; + } + + threads[tmp] = tsk; + get_task_struct(tsk); + } + + set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags); + do { + err = i915_reset_engine(engine, I915_RESET_QUIET); + if (err) { + pr_err("i915_reset_engine(%s) failed, err=%d\n", + engine->name, err); + break; + } + } while (time_before(jiffies, end_time)); + clear_bit(I915_RESET_ENGINE + engine->id, + &i915->gpu_error.flags); + +unwind: + for_each_engine(active, i915, tmp) { + int ret; + + if (!threads[tmp]) + continue; + + ret = kthread_stop(threads[tmp]); + if (ret) { + pr_err("kthread for active engine %s failed, err=%d\n", + active->name, ret); + if (!err) + err = ret; + } + put_task_struct(threads[tmp]); + + if (resets[tmp] != i915_reset_engine_count(&i915->gpu_error, + active)) { + pr_err("Innocent engine %s was reset (count=%ld)\n", + active->name, + i915_reset_engine_count(&i915->gpu_error, + active) - resets[tmp]); + err = -EIO; + } + } + + if (global != i915_reset_count(&i915->gpu_error)) { + pr_err("Global reset (count=%ld)!\n", + i915_reset_count(&i915->gpu_error) - global); + err = -EIO; + } + + if (err) + break; + + cond_resched(); + } + + if (i915_terminally_wedged(&i915->gpu_error)) + err = -EIO; + + return err; +} + static u32 fake_hangcheck(struct drm_i915_gem_request *rq) { u32 reset_count; @@ -406,9 +599,12 @@ static int igt_wait_reset(void *arg) long timeout; int err; + if (!intel_engine_can_store_dword(i915->engine[RCS])) + return 0; + /* Check that we detect a stuck waiter and issue a reset */ - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); @@ -453,8 +649,7 @@ fini: hang_fini(&h); unlock: mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) return -EIO; @@ -472,10 +667,8 @@ static int igt_reset_queue(void *arg) /* Check that we replay pending requests following a hang */ - if (!igt_can_mi_store_dword_imm(i915)) - return 0; + global_reset_lock(i915); - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); if (err) @@ -486,6 +679,9 @@ static int igt_reset_queue(void *arg) IGT_TIMEOUT(end_time); unsigned int count; + if (!intel_engine_can_store_dword(engine)) + continue; + prev = hang_create_request(&h, engine, i915->kernel_context); if (IS_ERR(prev)) { err = PTR_ERR(prev); @@ -522,7 +718,7 @@ static int igt_reset_queue(void *arg) reset_count = fake_hangcheck(prev); - i915_reset(i915); + i915_reset(i915, I915_RESET_QUIET); GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags)); @@ -569,8 +765,7 @@ fini: hang_fini(&h); unlock: mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) return -EIO; @@ -578,21 +773,23 @@ unlock: return err; } -static int igt_render_engine_reset_fallback(void *arg) +static int igt_handle_error(void *arg) { struct drm_i915_private *i915 = arg; struct intel_engine_cs *engine = i915->engine[RCS]; struct hang h; struct drm_i915_gem_request *rq; - unsigned int reset_count, reset_engine_count; - int err = 0; + struct i915_gpu_state *error; + int err; /* Check that we can issue a global GPU and engine reset */ if (!intel_has_reset_engine(i915)) return 0; - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + if (!intel_engine_can_store_dword(i915->engine[RCS])) + return 0; + mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); @@ -608,71 +805,31 @@ static int igt_render_engine_reset_fallback(void *arg) i915_gem_request_get(rq); __i915_add_request(rq, true); - /* make reset engine fail */ - rq->fence.error = -EIO; - if (!wait_for_hang(&h, rq)) { pr_err("Failed to start request %x\n", rq->fence.seqno); err = -EIO; goto err_request; } - reset_engine_count = i915_reset_engine_count(&i915->gpu_error, engine); - reset_count = fake_hangcheck(rq); - - /* unlock since we'll call handle_error */ mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); - i915_handle_error(i915, intel_engine_flag(engine), "live test"); + /* Temporarily disable error capture */ + error = xchg(&i915->gpu_error.first_error, (void *)-1); - if (i915_reset_engine_count(&i915->gpu_error, engine) != - reset_engine_count) { - pr_err("render engine reset recorded! (full reset expected)\n"); - err = -EINVAL; - goto out_rq; - } + engine->hangcheck.stalled = true; + engine->hangcheck.seqno = intel_engine_get_seqno(engine); - if (i915_reset_count(&i915->gpu_error) == reset_count) { - pr_err("No full GPU reset recorded!\n"); - err = -EINVAL; - goto out_rq; - } + i915_handle_error(i915, intel_engine_flag(engine), "%s", __func__); - /* - * by using fence.error = -EIO, full reset sets the wedged flag, do one - * more full reset to re-enable the hw. - */ - if (i915_terminally_wedged(&i915->gpu_error)) { - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - rq->fence.error = 0; - - mutex_lock(&i915->drm.struct_mutex); - set_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags); - i915_reset(i915); - GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, - &i915->gpu_error.flags)); - mutex_unlock(&i915->drm.struct_mutex); - - if (i915_reset_count(&i915->gpu_error) == reset_count) { - pr_err("No full GPU reset recorded!\n"); - err = -EINVAL; - goto out_rq; - } - } - -out_rq: - i915_gem_request_put(rq); - hang_fini(&h); -out_backoff: - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + xchg(&i915->gpu_error.first_error, error); - if (i915_terminally_wedged(&i915->gpu_error)) - return -EIO; + mutex_lock(&i915->drm.struct_mutex); - return err; + if (rq->fence.error != -EIO) { + pr_err("Guilty request not identified!\n"); + err = -EINVAL; + goto err_request; + } err_request: i915_gem_request_put(rq); @@ -680,7 +837,7 @@ err_fini: hang_fini(&h); err_unlock: mutex_unlock(&i915->drm.struct_mutex); - goto out_backoff; + return err; } int intel_hangcheck_live_selftests(struct drm_i915_private *i915) @@ -689,9 +846,10 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) SUBTEST(igt_hang_sanitycheck), SUBTEST(igt_global_reset), SUBTEST(igt_reset_engine), + SUBTEST(igt_reset_active_engines), SUBTEST(igt_wait_reset), SUBTEST(igt_reset_queue), - SUBTEST(igt_render_engine_reset_fallback), + SUBTEST(igt_handle_error), }; if (!intel_has_gpu_reset(i915)) diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c index 2d0fef2cfca6..3cac22eb47ce 100644 --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c @@ -127,7 +127,7 @@ static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_pri return 0; valid = kzalloc(BITS_TO_LONGS(FW_RANGE) * sizeof(*valid), - GFP_TEMPORARY); + GFP_KERNEL); if (!valid) return -ENOMEM; diff --git a/drivers/gpu/drm/i915/selftests/mock_context.c b/drivers/gpu/drm/i915/selftests/mock_context.c index 9c7c68181f82..098ce643ad07 100644 --- a/drivers/gpu/drm/i915/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/selftests/mock_context.c @@ -40,18 +40,13 @@ mock_context(struct drm_i915_private *i915, INIT_LIST_HEAD(&ctx->link); ctx->i915 = i915; - ctx->vma_lut.ht_bits = VMA_HT_BITS; - ctx->vma_lut.ht_size = BIT(VMA_HT_BITS); - ctx->vma_lut.ht = kcalloc(ctx->vma_lut.ht_size, - sizeof(*ctx->vma_lut.ht), - GFP_KERNEL); - if (!ctx->vma_lut.ht) - goto err_free; + INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); + INIT_LIST_HEAD(&ctx->handles_list); ret = ida_simple_get(&i915->contexts.hw_ida, 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); if (ret < 0) - goto err_vma_ht; + goto err_handles; ctx->hw_id = ret; if (name) { @@ -66,9 +61,7 @@ mock_context(struct drm_i915_private *i915, return ctx; -err_vma_ht: - kvfree(ctx->vma_lut.ht); -err_free: +err_handles: kfree(ctx); return NULL; @@ -95,3 +88,11 @@ void mock_init_contexts(struct drm_i915_private *i915) INIT_WORK(&i915->contexts.free_work, contexts_free_worker); init_llist_head(&i915->contexts.free_list); } + +struct i915_gem_context * +live_context(struct drm_i915_private *i915, struct drm_file *file) +{ + lockdep_assert_held(&i915->drm.struct_mutex); + + return i915_gem_create_context(i915, file->driver_priv); +} diff --git a/drivers/gpu/drm/i915/selftests/mock_context.h b/drivers/gpu/drm/i915/selftests/mock_context.h index 383941a61124..2f432c03d413 100644 --- a/drivers/gpu/drm/i915/selftests/mock_context.h +++ b/drivers/gpu/drm/i915/selftests/mock_context.h @@ -33,4 +33,7 @@ mock_context(struct drm_i915_private *i915, void mock_context_close(struct i915_gem_context *ctx); +struct i915_gem_context * +live_context(struct drm_i915_private *i915, struct drm_file *file); + #endif /* !__MOCK_CONTEXT_H */ diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c index 5b18a2dc19a8..fc0fd7498689 100644 --- a/drivers/gpu/drm/i915/selftests/mock_engine.c +++ b/drivers/gpu/drm/i915/selftests/mock_engine.c @@ -123,10 +123,12 @@ static struct intel_ring *mock_ring(struct intel_engine_cs *engine) } struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, - const char *name) + const char *name, + int id) { struct mock_engine *engine; - static int id; + + GEM_BUG_ON(id >= I915_NUM_ENGINES); engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL); if (!engine) @@ -141,7 +143,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, /* minimal engine setup for requests */ engine->base.i915 = i915; snprintf(engine->base.name, sizeof(engine->base.name), "%s", name); - engine->base.id = id++; + engine->base.id = id; engine->base.status_page.page_addr = (void *)(engine + 1); engine->base.context_pin = mock_context_pin; diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.h b/drivers/gpu/drm/i915/selftests/mock_engine.h index e5e240216ba3..133d0c21790d 100644 --- a/drivers/gpu/drm/i915/selftests/mock_engine.h +++ b/drivers/gpu/drm/i915/selftests/mock_engine.h @@ -40,7 +40,8 @@ struct mock_engine { }; struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, - const char *name); + const char *name, + int id); void mock_engine_flush(struct intel_engine_cs *engine); void mock_engine_reset(struct intel_engine_cs *engine); void mock_engine_free(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 2f1844c50e7d..678723430d78 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -22,6 +22,7 @@ * */ +#include <linux/pm_domain.h> #include <linux/pm_runtime.h> #include "mock_engine.h" @@ -53,11 +54,12 @@ static void mock_device_release(struct drm_device *dev) mutex_lock(&i915->drm.struct_mutex); mock_device_flush(i915); + i915_gem_contexts_lost(i915); mutex_unlock(&i915->drm.struct_mutex); cancel_delayed_work_sync(&i915->gt.retire_work); cancel_delayed_work_sync(&i915->gt.idle_work); - flush_workqueue(i915->wq); + i915_gem_drain_workqueue(i915); mutex_lock(&i915->drm.struct_mutex); for_each_engine(engine, i915, id) @@ -109,6 +111,23 @@ static void mock_idle_work_handler(struct work_struct *work) { } +static int pm_domain_resume(struct device *dev) +{ + return pm_generic_runtime_resume(dev); +} + +static int pm_domain_suspend(struct device *dev) +{ + return pm_generic_runtime_suspend(dev); +} + +static struct dev_pm_domain pm_domain = { + .ops = { + .runtime_suspend = pm_domain_suspend, + .runtime_resume = pm_domain_resume, + }, +}; + struct drm_i915_private *mock_gem_device(void) { struct drm_i915_private *i915; @@ -127,8 +146,10 @@ struct drm_i915_private *mock_gem_device(void) dev_set_name(&pdev->dev, "mock"); dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + dev_pm_domain_set(&pdev->dev, &pm_domain); + pm_runtime_enable(&pdev->dev); pm_runtime_dont_use_autosuspend(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); + WARN_ON(pm_runtime_get_sync(&pdev->dev)); i915 = (struct drm_i915_private *)(pdev + 1); pci_set_drvdata(pdev, i915); @@ -205,7 +226,7 @@ struct drm_i915_private *mock_gem_device(void) mutex_unlock(&i915->drm.struct_mutex); mkwrite_device_info(i915)->ring_mask = BIT(0); - i915->engine[RCS] = mock_engine(i915, "mock"); + i915->engine[RCS] = mock_engine(i915, "mock", RCS); if (!i915->engine[RCS]) goto err_priorities; diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c index 82e1c500ec20..247c60e6bed2 100644 --- a/drivers/gpu/drm/imx/ipuv3-plane.c +++ b/drivers/gpu/drm/imx/ipuv3-plane.c @@ -497,6 +497,27 @@ static int ipu_chan_assign_axi_id(int ipu_chan) } } +static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride, + u8 *burstsize, u8 *num_bursts) +{ + const unsigned int width_bytes = width * cpp; + unsigned int npb, bursts; + + /* Maximum number of pixels per burst without overshooting stride */ + for (npb = 64 / cpp; npb > 0; --npb) { + if (round_up(width_bytes, npb * cpp) <= stride) + break; + } + *burstsize = npb; + + /* Maximum number of consecutive bursts without overshooting stride */ + for (bursts = 8; bursts > 1; bursts /= 2) { + if (round_up(width_bytes, npb * cpp * bursts) <= stride) + break; + } + *num_bursts = bursts; +} + static void ipu_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { @@ -510,6 +531,9 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, unsigned long alpha_eba = 0; enum ipu_color_space ics; unsigned int axi_id = 0; + const struct drm_format_info *info; + u8 burstsize, num_bursts; + u32 width, height; int active; if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG) @@ -526,8 +550,8 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id, drm_rect_width(&state->src) >> 16, drm_rect_height(&state->src) >> 16, - state->fb->pitches[0], - state->fb->format->format, &eba); + fb->pitches[0], + fb->format->format, &eba); } if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) { @@ -546,19 +570,17 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, return; } + ics = ipu_drm_fourcc_to_colorspace(fb->format->format); switch (ipu_plane->dp_flow) { case IPU_DP_FLOW_SYNC_BG: - ipu_dp_setup_channel(ipu_plane->dp, - IPUV3_COLORSPACE_RGB, - IPUV3_COLORSPACE_RGB); + ipu_dp_setup_channel(ipu_plane->dp, ics, IPUV3_COLORSPACE_RGB); ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); break; case IPU_DP_FLOW_SYNC_FG: - ics = ipu_drm_fourcc_to_colorspace(state->fb->format->format); ipu_dp_setup_channel(ipu_plane->dp, ics, IPUV3_COLORSPACE_UNKNOWN); /* Enable local alpha on partial plane */ - switch (state->fb->format->format) { + switch (fb->format->format) { case DRM_FORMAT_ARGB1555: case DRM_FORMAT_ABGR1555: case DRM_FORMAT_RGBA5551: @@ -584,15 +606,21 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, ipu_dmfc_config_wait4eot(ipu_plane->dmfc, drm_rect_width(dst)); + width = drm_rect_width(&state->src) >> 16; + height = drm_rect_height(&state->src) >> 16; + info = drm_format_info(fb->format->format); + ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0], + &burstsize, &num_bursts); + ipu_cpmem_zero(ipu_plane->ipu_ch); - ipu_cpmem_set_resolution(ipu_plane->ipu_ch, - drm_rect_width(&state->src) >> 16, - drm_rect_height(&state->src) >> 16); - ipu_cpmem_set_fmt(ipu_plane->ipu_ch, state->fb->format->format); + ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height); + ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format); + ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize); ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); - ipu_cpmem_set_stride(ipu_plane->ipu_ch, state->fb->pitches[0]); + ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]); ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id); + switch (fb->format->format) { case DRM_FORMAT_YUV420: case DRM_FORMAT_YVU420: @@ -632,6 +660,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, case DRM_FORMAT_RGBX8888_A8: case DRM_FORMAT_BGRX8888_A8: alpha_eba = drm_plane_state_to_eba(state, 1); + num_bursts = 0; dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d", eba, alpha_eba, state->src.x1 >> 16, state->src.y1 >> 16); @@ -645,8 +674,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8); ipu_cpmem_set_high_priority(ipu_plane->alpha_ch); ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1); - ipu_cpmem_set_stride(ipu_plane->alpha_ch, - state->fb->pitches[1]); + ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]); ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16); ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba); ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba); @@ -658,6 +686,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, } ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba); ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba); + ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts); ipu_plane_enable(ipu_plane); } diff --git a/drivers/gpu/drm/lib/drm_random.c b/drivers/gpu/drm/lib/drm_random.c index 7b12a68c3b54..a78c4b483e8d 100644 --- a/drivers/gpu/drm/lib/drm_random.c +++ b/drivers/gpu/drm/lib/drm_random.c @@ -28,7 +28,7 @@ unsigned int *drm_random_order(unsigned int count, struct rnd_state *state) { unsigned int *order, i; - order = kmalloc_array(count, sizeof(*order), GFP_TEMPORARY); + order = kmalloc_array(count, sizeof(*order), GFP_KERNEL); if (!order) return order; diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 0e3828ed1e46..7791313405b5 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -486,8 +486,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) adreno_gpu = &a3xx_gpu->base; gpu = &adreno_gpu->base; - a3xx_gpu->pdev = pdev; - gpu->perfcntrs = perfcntrs; gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs); diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h index 85ff66cbddd6..ab60dc9e344e 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h @@ -28,7 +28,6 @@ struct a3xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; /* if OCMEM is used for GMEM: */ uint32_t ocmem_base; diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 19abf229b08d..58341ef6f15b 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -568,8 +568,6 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) adreno_gpu = &a4xx_gpu->base; gpu = &adreno_gpu->base; - a4xx_gpu->pdev = pdev; - gpu->perfcntrs = NULL; gpu->num_perfcntrs = 0; diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.h b/drivers/gpu/drm/msm/adreno/a4xx_gpu.h index 01247204ac92..f757184328a3 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.h @@ -23,7 +23,6 @@ struct a4xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; /* if OCMEM is used for GMEM: */ uint32_t ocmem_base; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index f9eae03aa1dc..17c59d839e6f 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -284,28 +284,14 @@ static int a5xx_me_init(struct msm_gpu *gpu) static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu, const struct firmware *fw, u64 *iova) { - struct drm_device *drm = gpu->dev; struct drm_gem_object *bo; void *ptr; - bo = msm_gem_new_locked(drm, fw->size - 4, MSM_BO_UNCACHED); - if (IS_ERR(bo)) - return bo; + ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, + MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); - ptr = msm_gem_get_vaddr(bo); - if (!ptr) { - drm_gem_object_unreference(bo); - return ERR_PTR(-ENOMEM); - } - - if (iova) { - int ret = msm_gem_get_iova(bo, gpu->aspace, iova); - - if (ret) { - drm_gem_object_unreference(bo); - return ERR_PTR(ret); - } - } + if (IS_ERR(ptr)) + return ERR_CAST(ptr); memcpy(ptr, &fw->data[4], fw->size - 4); @@ -372,8 +358,7 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) { static bool loaded; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); - struct platform_device *pdev = a5xx_gpu->pdev; + struct platform_device *pdev = gpu->pdev; int ret; /* @@ -410,6 +395,7 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \ A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW | \ A5XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ + A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT | \ A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) @@ -812,6 +798,27 @@ static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n"); } +static void a5xx_fault_detect_irq(struct msm_gpu *gpu) +{ + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + + dev_err(dev->dev, "gpu fault fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", + gpu->funcs->last_fence(gpu), + gpu_read(gpu, REG_A5XX_RBBM_STATUS), + gpu_read(gpu, REG_A5XX_CP_RB_RPTR), + gpu_read(gpu, REG_A5XX_CP_RB_WPTR), + gpu_read64(gpu, REG_A5XX_CP_IB1_BASE, REG_A5XX_CP_IB1_BASE_HI), + gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), + gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI), + gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); + + /* Turn off the hangcheck timer to keep it from bothering us */ + del_timer(&gpu->hangcheck_timer); + + queue_work(priv->wq, &gpu->recover_work); +} + #define RBBM_ERROR_MASK \ (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \ A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \ @@ -838,6 +845,9 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu) if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR) a5xx_cp_err_irq(gpu); + if (status & A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT) + a5xx_fault_detect_irq(gpu); + if (status & A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) a5xx_uche_err_irq(gpu); @@ -1015,7 +1025,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) adreno_gpu = &a5xx_gpu->base; gpu = &adreno_gpu->base; - a5xx_gpu->pdev = pdev; adreno_gpu->registers = a5xx_registers; adreno_gpu->reg_offsets = a5xx_register_offsets; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h index 1137092241d5..e94451685bf8 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -23,7 +23,6 @@ struct a5xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; struct drm_gem_object *pm4_bo; uint64_t pm4_iova; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index 87af6eea0483..04aab1dcae2b 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -294,16 +294,10 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) */ bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2; - a5xx_gpu->gpmu_bo = msm_gem_new_locked(drm, bosize, MSM_BO_UNCACHED); - if (IS_ERR(a5xx_gpu->gpmu_bo)) - goto err; - - if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->aspace, - &a5xx_gpu->gpmu_iova)) - goto err; - - ptr = msm_gem_get_vaddr(a5xx_gpu->gpmu_bo); - if (!ptr) + ptr = msm_gem_kernel_new_locked(drm, bosize, + MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, + &a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova); + if (IS_ERR(ptr)) goto err; while (cmds_size > 0) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 7414c6bbd582..c8b4ac254bb5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -337,11 +337,6 @@ void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords) DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name); } -static const char *iommu_ports[] = { - "gfx3d_user", "gfx3d_priv", - "gfx3d1_user", "gfx3d1_priv", -}; - int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs) { @@ -373,15 +368,15 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.ringsz = RB_SIZE; + pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, adreno_gpu->info->name, &adreno_gpu_config); if (ret) return ret; - pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); - ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev); if (ret) { dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n", @@ -396,37 +391,17 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, return ret; } - if (gpu->aspace && gpu->aspace->mmu) { - struct msm_mmu *mmu = gpu->aspace->mmu; - ret = mmu->funcs->attach(mmu, iommu_ports, - ARRAY_SIZE(iommu_ports)); - if (ret) - return ret; - } + adreno_gpu->memptrs = msm_gem_kernel_new(drm, + sizeof(*adreno_gpu->memptrs), MSM_BO_UNCACHED, gpu->aspace, + &adreno_gpu->memptrs_bo, &adreno_gpu->memptrs_iova); - adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs), - MSM_BO_UNCACHED); - if (IS_ERR(adreno_gpu->memptrs_bo)) { - ret = PTR_ERR(adreno_gpu->memptrs_bo); - adreno_gpu->memptrs_bo = NULL; - dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); - return ret; - } - - adreno_gpu->memptrs = msm_gem_get_vaddr(adreno_gpu->memptrs_bo); if (IS_ERR(adreno_gpu->memptrs)) { - dev_err(drm->dev, "could not vmap memptrs\n"); - return -ENOMEM; - } - - ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->aspace, - &adreno_gpu->memptrs_iova); - if (ret) { - dev_err(drm->dev, "could not map memptrs: %d\n", ret); - return ret; + ret = PTR_ERR(adreno_gpu->memptrs); + adreno_gpu->memptrs = NULL; + dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); } - return 0; + return ret; } void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) @@ -446,10 +421,4 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) release_firmware(adreno_gpu->pfp); msm_gpu_cleanup(gpu); - - if (gpu->aspace) { - gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, - iommu_ports, ARRAY_SIZE(iommu_ports)); - msm_gem_address_space_put(gpu->aspace); - } } diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 311c1c1e7d6c..98742d7af6dc 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -161,12 +161,17 @@ static const struct of_device_id dt_match[] = { {} }; +static const struct dev_pm_ops dsi_pm_ops = { + SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, NULL) +}; + static struct platform_driver dsi_driver = { .probe = dsi_dev_probe, .remove = dsi_dev_remove, .driver = { .name = "msm_dsi", .of_match_table = dt_match, + .pm = &dsi_pm_ops, }, }; diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 9e6017387efb..2302046197a8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -179,6 +179,8 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host); int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct drm_device *dev); int msm_dsi_host_init(struct msm_dsi *msm_dsi); +int msm_dsi_runtime_suspend(struct device *dev); +int msm_dsi_runtime_resume(struct device *dev); /* dsi phy */ struct msm_dsi_phy; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index c7b612c3d771..dbb31a014419 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -135,7 +135,6 @@ struct msm_dsi_host { struct completion video_comp; struct mutex dev_mutex; struct mutex cmd_mutex; - struct mutex clk_mutex; spinlock_t intr_lock; /* Protect interrupt ctrl register */ u32 err_work_state; @@ -221,6 +220,8 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( goto put_gdsc; } + pm_runtime_get_sync(dev); + ret = regulator_enable(gdsc_reg); if (ret) { pr_err("%s: unable to enable gdsc\n", __func__); @@ -247,6 +248,7 @@ disable_clks: clk_disable_unprepare(ahb_clk); disable_gdsc: regulator_disable(gdsc_reg); + pm_runtime_put_autosuspend(dev); put_clk: clk_put(ahb_clk); put_gdsc: @@ -455,6 +457,34 @@ static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->bus_clks[i]); } +int msm_dsi_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); + struct mipi_dsi_host *host = msm_dsi->host; + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + if (!msm_host->cfg_hnd) + return 0; + + dsi_bus_clk_disable(msm_host); + + return 0; +} + +int msm_dsi_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); + struct mipi_dsi_host *host = msm_dsi->host; + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + if (!msm_host->cfg_hnd) + return 0; + + return dsi_bus_clk_enable(msm_host); +} + static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) { int ret; @@ -596,35 +626,6 @@ static void dsi_link_clk_disable(struct msm_dsi_host *msm_host) } } -static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable) -{ - int ret = 0; - - mutex_lock(&msm_host->clk_mutex); - if (enable) { - ret = dsi_bus_clk_enable(msm_host); - if (ret) { - pr_err("%s: Can not enable bus clk, %d\n", - __func__, ret); - goto unlock_ret; - } - ret = dsi_link_clk_enable(msm_host); - if (ret) { - pr_err("%s: Can not enable link clk, %d\n", - __func__, ret); - dsi_bus_clk_disable(msm_host); - goto unlock_ret; - } - } else { - dsi_link_clk_disable(msm_host); - dsi_bus_clk_disable(msm_host); - } - -unlock_ret: - mutex_unlock(&msm_host->clk_mutex); - return ret; -} - static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host) { struct drm_display_mode *mode = msm_host->mode; @@ -1699,6 +1700,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) } msm_host->pdev = pdev; + msm_dsi->host = &msm_host->base; ret = dsi_host_parse_dt(msm_host); if (ret) { @@ -1713,6 +1715,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } + pm_runtime_enable(&pdev->dev); + msm_host->cfg_hnd = dsi_get_config(msm_host); if (!msm_host->cfg_hnd) { ret = -EINVAL; @@ -1753,7 +1757,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) init_completion(&msm_host->video_comp); mutex_init(&msm_host->dev_mutex); mutex_init(&msm_host->cmd_mutex); - mutex_init(&msm_host->clk_mutex); spin_lock_init(&msm_host->intr_lock); /* setup workqueue */ @@ -1761,7 +1764,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) INIT_WORK(&msm_host->err_work, dsi_err_worker); INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); - msm_dsi->host = &msm_host->base; msm_dsi->id = msm_host->id; DBG("Dsi Host %d initialized", msm_host->id); @@ -1783,9 +1785,10 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host) msm_host->workqueue = NULL; } - mutex_destroy(&msm_host->clk_mutex); mutex_destroy(&msm_host->cmd_mutex); mutex_destroy(&msm_host->dev_mutex); + + pm_runtime_disable(&msm_host->pdev->dev); } int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, @@ -1881,7 +1884,8 @@ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, * mdss interrupt is generated in mdp core clock domain * mdp clock need to be enabled to receive dsi interrupt */ - dsi_clk_ctrl(msm_host, 1); + pm_runtime_get_sync(&msm_host->pdev->dev); + dsi_link_clk_enable(msm_host); /* TODO: vote for bus bandwidth */ @@ -1911,7 +1915,8 @@ void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, /* TODO: unvote for bus bandwidth */ - dsi_clk_ctrl(msm_host, 0); + dsi_link_clk_disable(msm_host); + pm_runtime_put_autosuspend(&msm_host->pdev->dev); } int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, @@ -2160,8 +2165,11 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host) * and only turned on before MDP START. * This part of code should be enabled once mdp driver support it. */ - /* if (msm_panel->mode == MSM_DSI_CMD_MODE) - dsi_clk_ctrl(msm_host, 0); */ + /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { + * dsi_link_clk_disable(msm_host); + * pm_runtime_put_autosuspend(&msm_host->pdev->dev); + * } + */ return 0; } @@ -2217,9 +2225,11 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, goto unlock_ret; } - ret = dsi_clk_ctrl(msm_host, 1); + pm_runtime_get_sync(&msm_host->pdev->dev); + ret = dsi_link_clk_enable(msm_host); if (ret) { - pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret); + pr_err("%s: failed to enable link clocks. ret=%d\n", + __func__, ret); goto fail_disable_reg; } @@ -2243,7 +2253,8 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, return 0; fail_disable_clk: - dsi_clk_ctrl(msm_host, 0); + dsi_link_clk_disable(msm_host); + pm_runtime_put_autosuspend(&msm_host->pdev->dev); fail_disable_reg: dsi_host_regulator_disable(msm_host); unlock_ret: @@ -2268,7 +2279,8 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host) pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); - dsi_clk_ctrl(msm_host, 0); + dsi_link_clk_disable(msm_host); + pm_runtime_put_autosuspend(&msm_host->pdev->dev); dsi_host_regulator_disable(msm_host); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 0c2eb9c9a1fc..7c9bf91bc22b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -373,7 +373,7 @@ static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) { clk_disable_unprepare(phy->ahb_clk); - pm_runtime_put_sync(&phy->pdev->dev); + pm_runtime_put_autosuspend(&phy->pdev->dev); } static const struct of_device_id dsi_phy_dt_match[] = { diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index a968cad509c2..17e069a133a4 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -239,6 +239,8 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev) hdmi->pwr_clks[i] = clk; } + pm_runtime_enable(&pdev->dev); + hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0); hdmi->i2c = msm_hdmi_i2c_init(hdmi); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c index 13ac822dee5d..7e357077ed26 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -35,6 +35,8 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge) const struct hdmi_platform_config *config = hdmi->config; int i, ret; + pm_runtime_get_sync(&hdmi->pdev->dev); + for (i = 0; i < config->pwr_reg_cnt; i++) { ret = regulator_enable(hdmi->pwr_regs[i]); if (ret) { @@ -84,6 +86,8 @@ static void power_off(struct drm_bridge *bridge) config->pwr_reg_names[i], ret); } } + + pm_runtime_put_autosuspend(&hdmi->pdev->dev); } #define AVI_IFRAME_LINE_NUMBER 1 diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c index 71536d9c7fe8..c0848dfedd50 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c @@ -137,6 +137,36 @@ err: return ret; } +static void enable_hpd_clocks(struct hdmi *hdmi, bool enable) +{ + const struct hdmi_platform_config *config = hdmi->config; + struct device *dev = &hdmi->pdev->dev; + int i, ret; + + if (enable) { + for (i = 0; i < config->hpd_clk_cnt; i++) { + if (config->hpd_freq && config->hpd_freq[i]) { + ret = clk_set_rate(hdmi->hpd_clks[i], + config->hpd_freq[i]); + if (ret) + dev_warn(dev, + "failed to set clk %s (%d)\n", + config->hpd_clk_names[i], ret); + } + + ret = clk_prepare_enable(hdmi->hpd_clks[i]); + if (ret) { + dev_err(dev, + "failed to enable hpd clk: %s (%d)\n", + config->hpd_clk_names[i], ret); + } + } + } else { + for (i = config->hpd_clk_cnt - 1; i >= 0; i--) + clk_disable_unprepare(hdmi->hpd_clks[i]); + } +} + static int hpd_enable(struct hdmi_connector *hdmi_connector) { struct hdmi *hdmi = hdmi_connector->hdmi; @@ -167,22 +197,8 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) goto fail; } - for (i = 0; i < config->hpd_clk_cnt; i++) { - if (config->hpd_freq && config->hpd_freq[i]) { - ret = clk_set_rate(hdmi->hpd_clks[i], - config->hpd_freq[i]); - if (ret) - dev_warn(dev, "failed to set clk %s (%d)\n", - config->hpd_clk_names[i], ret); - } - - ret = clk_prepare_enable(hdmi->hpd_clks[i]); - if (ret) { - dev_err(dev, "failed to enable hpd clk: %s (%d)\n", - config->hpd_clk_names[i], ret); - goto fail; - } - } + pm_runtime_get_sync(dev); + enable_hpd_clocks(hdmi, true); msm_hdmi_set_mode(hdmi, false); msm_hdmi_phy_reset(hdmi); @@ -225,8 +241,8 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector) msm_hdmi_set_mode(hdmi, false); - for (i = 0; i < config->hpd_clk_cnt; i++) - clk_disable_unprepare(hdmi->hpd_clks[i]); + enable_hpd_clocks(hdmi, false); + pm_runtime_put_autosuspend(dev); ret = gpio_config(hdmi, false); if (ret) @@ -285,7 +301,16 @@ void msm_hdmi_connector_irq(struct drm_connector *connector) static enum drm_connector_status detect_reg(struct hdmi *hdmi) { - uint32_t hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); + uint32_t hpd_int_status; + + pm_runtime_get_sync(&hdmi->pdev->dev); + enable_hpd_clocks(hdmi, true); + + hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); + + enable_hpd_clocks(hdmi, false); + pm_runtime_put_autosuspend(&hdmi->pdev->dev); + return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ? connector_status_connected : connector_status_disconnected; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c index aa7402e03f67..60790df91bfa 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c @@ -192,6 +192,7 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, { struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder); struct mdp5_kms *mdp5_kms; + struct device *dev; int intf_num; u32 data = 0; @@ -214,14 +215,16 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, /* Smart Panel, Sync mode */ data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL; + dev = &mdp5_kms->pdev->dev; + /* Make sure clocks are on when connectors calling this function. */ - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, MDP5_SPLIT_DPL_LOWER_SMART_PANEL); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 3a81e26629c7..6fcb58ab718c 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -415,6 +415,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); struct mdp5_kms *mdp5_kms = get_kms(crtc); + struct device *dev = &mdp5_kms->pdev->dev; DBG("%s", crtc->name); @@ -425,7 +426,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); mdp5_crtc->enabled = false; } @@ -436,13 +437,17 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); struct mdp5_kms *mdp5_kms = get_kms(crtc); + struct device *dev = &mdp5_kms->pdev->dev; DBG("%s", crtc->name); if (WARN_ON(mdp5_crtc->enabled)) return; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); + + mdp5_crtc_mode_set_nofb(crtc); + mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); if (mdp5_cstate->cmd_mode) @@ -533,7 +538,7 @@ static bool is_fullscreen(struct drm_crtc_state *cstate, ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); } -enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, +static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, struct drm_crtc_state *new_crtc_state, struct drm_plane_state *bpstate) { @@ -727,6 +732,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; struct drm_device *dev = crtc->dev; struct mdp5_kms *mdp5_kms = get_kms(crtc); + struct platform_device *pdev = mdp5_kms->pdev; struct msm_kms *kms = &mdp5_kms->base.base; struct drm_gem_object *cursor_bo, *old_bo = NULL; uint32_t blendcfg, stride; @@ -755,7 +761,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, if (!handle) { DBG("Cursor off"); cursor_enable = false; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(&pdev->dev); goto set_cursor; } @@ -770,6 +776,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, lm = mdp5_cstate->pipeline.mixer->lm; stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0); + pm_runtime_get_sync(&pdev->dev); + spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); old_bo = mdp5_crtc->cursor.scanout_bo; @@ -779,8 +787,6 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, get_roi(crtc, &roi_w, &roi_h); - mdp5_enable(mdp5_kms); - mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); @@ -798,6 +804,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); + pm_runtime_put_autosuspend(&pdev->dev); + set_cursor: ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); if (ret) { @@ -809,7 +817,7 @@ set_cursor: crtc_flush(crtc, flush_mask); end: - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(&pdev->dev); if (old_bo) { drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo); /* enable vblank to complete cursor work: */ @@ -842,7 +850,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) get_roi(crtc, &roi_w, &roi_h); - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(&mdp5_kms->pdev->dev); spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), @@ -855,7 +863,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) crtc_flush(crtc, flush_mask); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(&mdp5_kms->pdev->dev); return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index 70bef51245af..5b851380d3f2 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c @@ -297,6 +297,10 @@ static void mdp5_encoder_enable(struct drm_encoder *encoder) { struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); struct mdp5_interface *intf = mdp5_encoder->intf; + /* this isn't right I think */ + struct drm_crtc_state *cstate = encoder->crtc->state; + + mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode); if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND) mdp5_cmd_encoder_enable(encoder); @@ -320,7 +324,6 @@ static int mdp5_encoder_atomic_check(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = { - .mode_set = mdp5_encoder_mode_set, .disable = mdp5_encoder_disable, .enable = mdp5_encoder_enable, .atomic_check = mdp5_encoder_atomic_check, @@ -350,6 +353,7 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder); struct mdp5_kms *mdp5_kms; + struct device *dev; int intf_num; u32 data = 0; @@ -369,8 +373,10 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, else return -EINVAL; + dev = &mdp5_kms->pdev->dev; /* Make sure clocks are on when connectors calling this function. */ - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); + /* Dumb Panel, Sync mode */ mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); @@ -378,7 +384,7 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c index 3ce8b9dec9c1..bb5deb00c899 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c @@ -49,16 +49,19 @@ static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) void mdp5_irq_preinstall(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - mdp5_enable(mdp5_kms); + struct device *dev = &mdp5_kms->pdev->dev; + + pm_runtime_get_sync(dev); mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } int mdp5_irq_postinstall(struct msm_kms *kms) { struct mdp_kms *mdp_kms = to_mdp_kms(kms); struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); + struct device *dev = &mdp5_kms->pdev->dev; struct mdp_irq *error_handler = &mdp5_kms->error_handler; error_handler->irq = mdp5_irq_error_handler; @@ -67,9 +70,9 @@ int mdp5_irq_postinstall(struct msm_kms *kms) MDP5_IRQ_INTF2_UNDER_RUN | MDP5_IRQ_INTF3_UNDER_RUN; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp_irq_register(mdp_kms, error_handler); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } @@ -77,9 +80,11 @@ int mdp5_irq_postinstall(struct msm_kms *kms) void mdp5_irq_uninstall(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - mdp5_enable(mdp5_kms); + struct device *dev = &mdp5_kms->pdev->dev; + + pm_runtime_get_sync(dev); mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } irqreturn_t mdp5_irq(struct msm_kms *kms) @@ -109,11 +114,12 @@ irqreturn_t mdp5_irq(struct msm_kms *kms) int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp_update_vblank_mask(to_mdp_kms(kms), mdp5_crtc_vblank(crtc), true); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } @@ -121,9 +127,10 @@ int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp_update_vblank_mask(to_mdp_kms(kms), mdp5_crtc_vblank(crtc), false); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index 1c603aef3c59..f7c0698fec40 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -30,11 +30,10 @@ static const char *iommu_ports[] = { static int mdp5_hw_init(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - struct platform_device *pdev = mdp5_kms->pdev; + struct device *dev = &mdp5_kms->pdev->dev; unsigned long flags; - pm_runtime_get_sync(&pdev->dev); - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); /* Magic unknown register writes: * @@ -66,8 +65,7 @@ static int mdp5_hw_init(struct msm_kms *kms) mdp5_ctlm_hw_reset(mdp5_kms->ctlm); - mdp5_disable(mdp5_kms); - pm_runtime_put_sync(&pdev->dev); + pm_runtime_put_sync(dev); return 0; } @@ -111,8 +109,9 @@ static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state) static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); if (mdp5_kms->smp) mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp); @@ -121,11 +120,12 @@ static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *st static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; if (mdp5_kms->smp) mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, @@ -249,6 +249,9 @@ int mdp5_disable(struct mdp5_kms *mdp5_kms) { DBG(""); + mdp5_kms->enable_count--; + WARN_ON(mdp5_kms->enable_count < 0); + clk_disable_unprepare(mdp5_kms->ahb_clk); clk_disable_unprepare(mdp5_kms->axi_clk); clk_disable_unprepare(mdp5_kms->core_clk); @@ -262,6 +265,8 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms) { DBG(""); + mdp5_kms->enable_count++; + clk_prepare_enable(mdp5_kms->ahb_clk); clk_prepare_enable(mdp5_kms->axi_clk); clk_prepare_enable(mdp5_kms->core_clk); @@ -486,11 +491,12 @@ fail: static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, u32 *major, u32 *minor) { + struct device *dev = &mdp5_kms->pdev->dev; u32 version; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); *major = FIELD(version, MDP5_HW_VERSION_MAJOR); *minor = FIELD(version, MDP5_HW_VERSION_MINOR); @@ -643,7 +649,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) * have left things on, in which case we'll start getting faults if * we don't disable): */ - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(&pdev->dev); for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || !config->hw->intf.base[i]) @@ -652,7 +658,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); } - mdp5_disable(mdp5_kms); mdelay(16); if (config->platform.iommu) { @@ -678,6 +683,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) aspace = NULL;; } + pm_runtime_put_autosuspend(&pdev->dev); + ret = modeset_init(mdp5_kms); if (ret) { dev_err(&pdev->dev, "modeset_init failed: %d\n", ret); @@ -1005,6 +1012,30 @@ static int mdp5_dev_remove(struct platform_device *pdev) return 0; } +static __maybe_unused int mdp5_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); + + DBG(""); + + return mdp5_disable(mdp5_kms); +} + +static __maybe_unused int mdp5_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); + + DBG(""); + + return mdp5_enable(mdp5_kms); +} + +static const struct dev_pm_ops mdp5_pm_ops = { + SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) +}; + static const struct of_device_id mdp5_dt_match[] = { { .compatible = "qcom,mdp5", }, /* to support downstream DT files */ @@ -1019,6 +1050,7 @@ static struct platform_driver mdp5_driver = { .driver = { .name = "msm_mdp", .of_match_table = mdp5_dt_match, + .pm = &mdp5_pm_ops, }, }; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 17caa0e8c8ae..9b3fe01089d1 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -76,6 +76,8 @@ struct mdp5_kms { bool rpm_enabled; struct mdp_irq error_handler; + + int enable_count; }; #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) @@ -167,11 +169,13 @@ struct mdp5_encoder { static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) { + WARN_ON(mdp5_kms->enable_count <= 0); msm_writel(data, mdp5_kms->mmio + reg); } static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) { + WARN_ON(mdp5_kms->enable_count <= 0); return msm_readl(mdp5_kms->mmio + reg); } @@ -255,9 +259,6 @@ static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer) return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp; } -int mdp5_disable(struct mdp5_kms *mdp5_kms); -int mdp5_enable(struct mdp5_kms *mdp5_kms); - void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t old_irqmask); void mdp5_irq_preinstall(struct msm_kms *kms); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c index 9c34d7824988..f2a0db7a8a03 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c @@ -31,6 +31,10 @@ struct msm_mdss { struct regulator *vdd; + struct clk *ahb_clk; + struct clk *axi_clk; + struct clk *vsync_clk; + struct { volatile unsigned long enabled_mask; struct irq_domain *domain; @@ -140,6 +144,51 @@ static int mdss_irq_domain_init(struct msm_mdss *mdss) return 0; } +int msm_mdss_enable(struct msm_mdss *mdss) +{ + DBG(""); + + clk_prepare_enable(mdss->ahb_clk); + if (mdss->axi_clk) + clk_prepare_enable(mdss->axi_clk); + if (mdss->vsync_clk) + clk_prepare_enable(mdss->vsync_clk); + + return 0; +} + +int msm_mdss_disable(struct msm_mdss *mdss) +{ + DBG(""); + + if (mdss->vsync_clk) + clk_disable_unprepare(mdss->vsync_clk); + if (mdss->axi_clk) + clk_disable_unprepare(mdss->axi_clk); + clk_disable_unprepare(mdss->ahb_clk); + + return 0; +} + +static int msm_mdss_get_clocks(struct msm_mdss *mdss) +{ + struct platform_device *pdev = to_platform_device(mdss->dev->dev); + + mdss->ahb_clk = msm_clk_get(pdev, "iface"); + if (IS_ERR(mdss->ahb_clk)) + mdss->ahb_clk = NULL; + + mdss->axi_clk = msm_clk_get(pdev, "bus"); + if (IS_ERR(mdss->axi_clk)) + mdss->axi_clk = NULL; + + mdss->vsync_clk = msm_clk_get(pdev, "vsync"); + if (IS_ERR(mdss->vsync_clk)) + mdss->vsync_clk = NULL; + + return 0; +} + void msm_mdss_destroy(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -153,8 +202,6 @@ void msm_mdss_destroy(struct drm_device *dev) regulator_disable(mdss->vdd); - pm_runtime_put_sync(dev->dev); - pm_runtime_disable(dev->dev); } @@ -190,6 +237,12 @@ int msm_mdss_init(struct drm_device *dev) goto fail; } + ret = msm_mdss_get_clocks(mdss); + if (ret) { + dev_err(dev->dev, "failed to get clocks: %d\n", ret); + goto fail; + } + /* Regulator to enable GDSCs in downstream kernels */ mdss->vdd = devm_regulator_get(dev->dev, "vdd"); if (IS_ERR(mdss->vdd)) { @@ -221,12 +274,6 @@ int msm_mdss_init(struct drm_device *dev) pm_runtime_enable(dev->dev); - /* - * TODO: This is needed as the MDSS GDSC is only tied to MDSS's power - * domain. Remove this once runtime PM is adapted for all the devices. - */ - pm_runtime_get_sync(dev->dev); - return 0; fail_irq: regulator_disable(mdss->vdd); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c index 58f712d37e7f..ae4983d9d0a5 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c @@ -28,6 +28,13 @@ struct mdp5_smp { int blk_cnt; int blk_size; + + /* register cache */ + u32 alloc_w[22]; + u32 alloc_r[22]; + u32 pipe_reqprio_fifo_wm0[SSPP_MAX]; + u32 pipe_reqprio_fifo_wm1[SSPP_MAX]; + u32 pipe_reqprio_fifo_wm2[SSPP_MAX]; }; static inline @@ -98,16 +105,15 @@ static int smp_request_block(struct mdp5_smp *smp, static void set_fifo_thresholds(struct mdp5_smp *smp, enum mdp5_pipe pipe, int nblks) { - struct mdp5_kms *mdp5_kms = get_kms(smp); u32 smp_entries_per_blk = smp->blk_size / (128 / BITS_PER_BYTE); u32 val; /* 1/4 of SMP pool that is being fetched */ val = (nblks * smp_entries_per_blk) / 4; - mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), val * 1); - mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), val * 2); - mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), val * 3); + smp->pipe_reqprio_fifo_wm0[pipe] = val * 1; + smp->pipe_reqprio_fifo_wm1[pipe] = val * 2; + smp->pipe_reqprio_fifo_wm2[pipe] = val * 3; } /* @@ -222,7 +228,6 @@ void mdp5_smp_release(struct mdp5_smp *smp, struct mdp5_smp_state *state, static unsigned update_smp_state(struct mdp5_smp *smp, u32 cid, mdp5_smp_state_t *assigned) { - struct mdp5_kms *mdp5_kms = get_kms(smp); int cnt = smp->blk_cnt; unsigned nblks = 0; u32 blk, val; @@ -231,7 +236,7 @@ static unsigned update_smp_state(struct mdp5_smp *smp, int idx = blk / 3; int fld = blk % 3; - val = mdp5_read(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx)); + val = smp->alloc_w[idx]; switch (fld) { case 0: @@ -248,8 +253,8 @@ static unsigned update_smp_state(struct mdp5_smp *smp, break; } - mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx), val); - mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(idx), val); + smp->alloc_w[idx] = val; + smp->alloc_r[idx] = val; nblks++; } @@ -257,6 +262,39 @@ static unsigned update_smp_state(struct mdp5_smp *smp, return nblks; } +static void write_smp_alloc_regs(struct mdp5_smp *smp) +{ + struct mdp5_kms *mdp5_kms = get_kms(smp); + int i, num_regs; + + num_regs = smp->blk_cnt / 3 + 1; + + for (i = 0; i < num_regs; i++) { + mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(i), + smp->alloc_w[i]); + mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(i), + smp->alloc_r[i]); + } +} + +static void write_smp_fifo_regs(struct mdp5_smp *smp) +{ + struct mdp5_kms *mdp5_kms = get_kms(smp); + int i; + + for (i = 0; i < mdp5_kms->num_hwpipes; i++) { + struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; + enum mdp5_pipe pipe = hwpipe->pipe; + + mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), + smp->pipe_reqprio_fifo_wm0[pipe]); + mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), + smp->pipe_reqprio_fifo_wm1[pipe]); + mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), + smp->pipe_reqprio_fifo_wm2[pipe]); + } +} + void mdp5_smp_prepare_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state) { enum mdp5_pipe pipe; @@ -277,6 +315,9 @@ void mdp5_smp_prepare_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state) set_fifo_thresholds(smp, pipe, nblks); } + write_smp_alloc_regs(smp); + write_smp_fifo_regs(smp); + state->assigned = 0; } @@ -289,6 +330,8 @@ void mdp5_smp_complete_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state set_fifo_thresholds(smp, pipe, 0); } + write_smp_fifo_regs(smp); + state->released = 0; } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index b0129e7b29e3..606df7bea97b 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -73,6 +73,10 @@ bool dumpstate = false; MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); module_param(dumpstate, bool, 0600); +static bool modeset = true; +MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); +module_param(modeset, bool, 0600); + /* * Util/helpers: */ @@ -878,8 +882,37 @@ static int msm_pm_resume(struct device *dev) } #endif +#ifdef CONFIG_PM +static int msm_runtime_suspend(struct device *dev) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct msm_drm_private *priv = ddev->dev_private; + + DBG(""); + + if (priv->mdss) + return msm_mdss_disable(priv->mdss); + + return 0; +} + +static int msm_runtime_resume(struct device *dev) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct msm_drm_private *priv = ddev->dev_private; + + DBG(""); + + if (priv->mdss) + return msm_mdss_enable(priv->mdss); + + return 0; +} +#endif + static const struct dev_pm_ops msm_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) + SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL) }; /* @@ -1103,6 +1136,9 @@ static struct platform_driver msm_platform_driver = { static int __init msm_drm_register(void) { + if (!modeset) + return -EINVAL; + DBG("init"); msm_mdp_register(); msm_dsi_register(); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index fc8d24f7c084..5e8109c07560 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -55,8 +55,6 @@ struct msm_fence_cb; struct msm_gem_address_space; struct msm_gem_vma; -#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ - struct msm_file_private { /* currently we don't do anything useful with this.. but when * per-context address spaces are supported we'd keep track of @@ -237,6 +235,12 @@ struct drm_gem_object *msm_gem_new(struct drm_device *dev, uint32_t size, uint32_t flags); struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, uint32_t size, uint32_t flags); +void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova); +void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova); struct drm_gem_object *msm_gem_import(struct drm_device *dev, struct dma_buf *dmabuf, struct sg_table *sgt); @@ -248,10 +252,10 @@ uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, struct msm_gem_address_space *aspace, int plane); struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); -struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); +struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, + int w, int h, int p, uint32_t format); struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); void msm_fbdev_free(struct drm_device *dev); diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index 6ecb7b170316..fc175e724ad6 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -20,6 +20,7 @@ #include "msm_drv.h" #include "msm_kms.h" +#include "msm_gem.h" struct msm_framebuffer { struct drm_framebuffer base; @@ -28,6 +29,8 @@ struct msm_framebuffer { }; #define to_msm_framebuffer(x) container_of(x, struct msm_framebuffer, base) +static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, + const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); static int msm_framebuffer_create_handle(struct drm_framebuffer *fb, struct drm_file *file_priv, @@ -161,7 +164,7 @@ out_unref: return ERR_PTR(ret); } -struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, +static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos) { struct msm_drm_private *priv = dev->dev_private; @@ -237,3 +240,43 @@ fail: return ERR_PTR(ret); } + +struct drm_framebuffer * +msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format) +{ + struct drm_mode_fb_cmd2 mode_cmd = { + .pixel_format = format, + .width = w, + .height = h, + .pitches = { p }, + }; + struct drm_gem_object *bo; + struct drm_framebuffer *fb; + int size; + + /* allocate backing bo */ + size = mode_cmd.pitches[0] * mode_cmd.height; + DBG("allocating %d bytes for fb %d", size, dev->primary->index); + bo = msm_gem_new(dev, size, MSM_BO_SCANOUT | MSM_BO_WC | MSM_BO_STOLEN); + if (IS_ERR(bo)) { + dev_warn(dev->dev, "could not allocate stolen bo\n"); + /* try regular bo: */ + bo = msm_gem_new(dev, size, MSM_BO_SCANOUT | MSM_BO_WC); + } + if (IS_ERR(bo)) { + dev_err(dev->dev, "failed to allocate buffer object\n"); + return ERR_CAST(bo); + } + + fb = msm_framebuffer_init(dev, &mode_cmd, &bo); + if (IS_ERR(fb)) { + dev_err(dev->dev, "failed to allocate fb\n"); + /* note: if fb creation failed, we can't rely on fb destroy + * to unref the bo: + */ + drm_gem_object_unreference_unlocked(bo); + return ERR_CAST(fb); + } + + return fb; +} diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c index 9c00fedfc741..c178563fcd4d 100644 --- a/drivers/gpu/drm/msm/msm_fbdev.c +++ b/drivers/gpu/drm/msm/msm_fbdev.c @@ -19,7 +19,6 @@ #include <drm/drm_fb_helper.h> #include "msm_drv.h" -#include "msm_gem.h" #include "msm_kms.h" extern int msm_gem_mmap_obj(struct drm_gem_object *obj, @@ -35,7 +34,6 @@ static int msm_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma); struct msm_fbdev { struct drm_fb_helper base; struct drm_framebuffer *fb; - struct drm_gem_object *bo; }; static struct fb_ops msm_fb_ops = { @@ -57,16 +55,16 @@ static int msm_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) { struct drm_fb_helper *helper = (struct drm_fb_helper *)info->par; struct msm_fbdev *fbdev = to_msm_fbdev(helper); - struct drm_gem_object *drm_obj = fbdev->bo; + struct drm_gem_object *bo = msm_framebuffer_bo(fbdev->fb, 0); int ret = 0; - ret = drm_gem_mmap_obj(drm_obj, drm_obj->size, vma); + ret = drm_gem_mmap_obj(bo, bo->size, vma); if (ret) { pr_err("%s:drm_gem_mmap_obj fail\n", __func__); return ret; } - return msm_gem_mmap_obj(drm_obj, vma); + return msm_gem_mmap_obj(bo, vma); } static int msm_fbdev_create(struct drm_fb_helper *helper, @@ -76,47 +74,30 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, struct drm_device *dev = helper->dev; struct msm_drm_private *priv = dev->dev_private; struct drm_framebuffer *fb = NULL; + struct drm_gem_object *bo; struct fb_info *fbi = NULL; - struct drm_mode_fb_cmd2 mode_cmd = {0}; uint64_t paddr; - int ret, size; + uint32_t format; + int ret, pitch; + + format = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth); DBG("create fbdev: %dx%d@%d (%dx%d)", sizes->surface_width, sizes->surface_height, sizes->surface_bpp, sizes->fb_width, sizes->fb_height); - mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, - sizes->surface_depth); - - mode_cmd.width = sizes->surface_width; - mode_cmd.height = sizes->surface_height; - - mode_cmd.pitches[0] = align_pitch( - mode_cmd.width, sizes->surface_bpp); + pitch = align_pitch(sizes->surface_width, sizes->surface_bpp); + fb = msm_alloc_stolen_fb(dev, sizes->surface_width, + sizes->surface_height, pitch, format); - /* allocate backing bo */ - size = mode_cmd.pitches[0] * mode_cmd.height; - DBG("allocating %d bytes for fb %d", size, dev->primary->index); - fbdev->bo = msm_gem_new(dev, size, MSM_BO_SCANOUT | - MSM_BO_WC | MSM_BO_STOLEN); - if (IS_ERR(fbdev->bo)) { - ret = PTR_ERR(fbdev->bo); - fbdev->bo = NULL; - dev_err(dev->dev, "failed to allocate buffer object: %d\n", ret); - goto fail; - } - - fb = msm_framebuffer_init(dev, &mode_cmd, &fbdev->bo); if (IS_ERR(fb)) { dev_err(dev->dev, "failed to allocate fb\n"); - /* note: if fb creation failed, we can't rely on fb destroy - * to unref the bo: - */ - drm_gem_object_unreference_unlocked(fbdev->bo); ret = PTR_ERR(fb); goto fail; } + bo = msm_framebuffer_bo(fb, 0); + mutex_lock(&dev->struct_mutex); /* @@ -124,7 +105,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, * in panic (ie. lock-safe, etc) we could avoid pinning the * buffer now: */ - ret = msm_gem_get_iova(fbdev->bo, priv->kms->aspace, &paddr); + ret = msm_gem_get_iova(bo, priv->kms->aspace, &paddr); if (ret) { dev_err(dev->dev, "failed to get buffer obj iova: %d\n", ret); goto fail_unlock; @@ -152,14 +133,14 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, dev->mode_config.fb_base = paddr; - fbi->screen_base = msm_gem_get_vaddr(fbdev->bo); + fbi->screen_base = msm_gem_get_vaddr(bo); if (IS_ERR(fbi->screen_base)) { ret = PTR_ERR(fbi->screen_base); goto fail_unlock; } - fbi->screen_size = fbdev->bo->size; + fbi->screen_size = bo->size; fbi->fix.smem_start = paddr; - fbi->fix.smem_len = fbdev->bo->size; + fbi->fix.smem_len = bo->size; DBG("par=%p, %dx%d", fbi->par, fbi->var.xres, fbi->var.yres); DBG("allocated %dx%d fb", fbdev->fb->width, fbdev->fb->height); @@ -241,7 +222,9 @@ void msm_fbdev_free(struct drm_device *dev) /* this will free the backing object */ if (fbdev->fb) { - msm_gem_put_vaddr(fbdev->bo); + struct drm_gem_object *bo = + msm_framebuffer_bo(fbdev->fb, 0); + msm_gem_put_vaddr(bo); drm_framebuffer_remove(fbdev->fb); } diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index a0c60e738db8..f15821a0d900 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -1024,3 +1024,49 @@ fail: drm_gem_object_unreference_unlocked(obj); return ERR_PTR(ret); } + +static void *_msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova, bool locked) +{ + void *vaddr; + struct drm_gem_object *obj = _msm_gem_new(dev, size, flags, locked); + int ret; + + if (IS_ERR(obj)) + return ERR_CAST(obj); + + if (iova) { + ret = msm_gem_get_iova(obj, aspace, iova); + if (ret) { + drm_gem_object_unreference(obj); + return ERR_PTR(ret); + } + } + + vaddr = msm_gem_get_vaddr(obj); + if (!vaddr) { + msm_gem_put_iova(obj, aspace); + drm_gem_object_unreference(obj); + return ERR_PTR(-ENOMEM); + } + + if (bo) + *bo = obj; + + return vaddr; +} + +void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova) +{ + return _msm_gem_kernel_new(dev, size, flags, aspace, bo, iova, false); +} + +void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova) +{ + return _msm_gem_kernel_new(dev, size, flags, aspace, bo, iova, true); +} diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 8a75c0bd8a78..5d0a75d4b249 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -40,7 +40,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev, if (sz > SIZE_MAX) return NULL; - submit = kmalloc(sz, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); + submit = kmalloc(sz, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); if (!submit) return NULL; diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 9f3dbc236ab3..ffbff27600e0 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -562,11 +562,49 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) return 0; } +static struct msm_gem_address_space * +msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, + uint64_t va_start, uint64_t va_end) +{ + struct iommu_domain *iommu; + struct msm_gem_address_space *aspace; + int ret; + + /* + * Setup IOMMU.. eventually we will (I think) do this once per context + * and have separate page tables per context. For now, to keep things + * simple and to get something working, just use a single address space: + */ + iommu = iommu_domain_alloc(&platform_bus_type); + if (!iommu) + return NULL; + + iommu->geometry.aperture_start = va_start; + iommu->geometry.aperture_end = va_end; + + dev_info(gpu->dev->dev, "%s: using IOMMU\n", gpu->name); + + aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu"); + if (IS_ERR(aspace)) { + dev_err(gpu->dev->dev, "failed to init iommu: %ld\n", + PTR_ERR(aspace)); + iommu_domain_free(iommu); + return ERR_CAST(aspace); + } + + ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); + if (ret) { + msm_gem_address_space_put(aspace); + return ERR_PTR(ret); + } + + return aspace; +} + int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, const char *name, struct msm_gpu_config *config) { - struct iommu_domain *iommu; int ret; if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) @@ -636,28 +674,19 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, if (IS_ERR(gpu->gpu_cx)) gpu->gpu_cx = NULL; - /* Setup IOMMU.. eventually we will (I think) do this once per context - * and have separate page tables per context. For now, to keep things - * simple and to get something working, just use a single address space: - */ - iommu = iommu_domain_alloc(&platform_bus_type); - if (iommu) { - iommu->geometry.aperture_start = config->va_start; - iommu->geometry.aperture_end = config->va_end; - - dev_info(drm->dev, "%s: using IOMMU\n", name); - gpu->aspace = msm_gem_address_space_create(&pdev->dev, - iommu, "gpu"); - if (IS_ERR(gpu->aspace)) { - ret = PTR_ERR(gpu->aspace); - dev_err(drm->dev, "failed to init iommu: %d\n", ret); - gpu->aspace = NULL; - iommu_domain_free(iommu); - goto fail; - } + gpu->pdev = pdev; + platform_set_drvdata(pdev, gpu); + + bs_init(gpu); - } else { + gpu->aspace = msm_gpu_create_address_space(gpu, pdev, + config->va_start, config->va_end); + + if (gpu->aspace == NULL) dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); + else if (IS_ERR(gpu->aspace)) { + ret = PTR_ERR(gpu->aspace); + goto fail; } /* Create ringbuffer: */ @@ -669,14 +698,10 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, goto fail; } - gpu->pdev = pdev; - platform_set_drvdata(pdev, gpu); - - bs_init(gpu); - return 0; fail: + platform_set_drvdata(pdev, NULL); return ret; } @@ -693,7 +718,9 @@ void msm_gpu_cleanup(struct msm_gpu *gpu) msm_gem_put_iova(gpu->rb->bo, gpu->aspace); msm_ringbuffer_destroy(gpu->rb); } - - if (gpu->fctx) - msm_fence_context_free(gpu->fctx); + if (gpu->aspace) { + gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, + NULL, 0); + msm_gem_address_space_put(gpu->aspace); + } } diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index a8f2ba5e5f07..17d5824417ad 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -99,5 +99,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev); struct msm_kms *mdp5_kms_init(struct drm_device *dev); int msm_mdss_init(struct drm_device *dev); void msm_mdss_destroy(struct drm_device *dev); +int msm_mdss_enable(struct msm_mdss *mdss); +int msm_mdss_disable(struct msm_mdss *mdss); #endif /* __MSM_KMS_H__ */ diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 791bca3c6a9c..bf065a540130 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -33,16 +33,14 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int size) } ring->gpu = gpu; - ring->bo = msm_gem_new(gpu->dev, size, MSM_BO_WC); - if (IS_ERR(ring->bo)) { - ret = PTR_ERR(ring->bo); - ring->bo = NULL; - goto fail; - } - ring->start = msm_gem_get_vaddr(ring->bo); + /* Pass NULL for the iova pointer - we will map it later */ + ring->start = msm_gem_kernel_new(gpu->dev, size, MSM_BO_WC, + gpu->aspace, &ring->bo, NULL); + if (IS_ERR(ring->start)) { ret = PTR_ERR(ring->start); + ring->start = 0; goto fail; } ring->end = ring->start + (size / 4); diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 8f689f1f6122..6aa6ee16dcbd 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -1096,6 +1096,38 @@ static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { .disable = nv_crtc_disable, }; +static const uint32_t modeset_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB1555, +}; + +static struct drm_plane * +create_primary_plane(struct drm_device *dev) +{ + struct drm_plane *primary; + int ret; + + primary = kzalloc(sizeof(*primary), GFP_KERNEL); + if (primary == NULL) { + DRM_DEBUG_KMS("Failed to allocate primary plane\n"); + return NULL; + } + + /* possible_crtc's will be filled in later by crtc_init */ + ret = drm_universal_plane_init(dev, primary, 0, + &drm_primary_helper_funcs, + modeset_formats, + ARRAY_SIZE(modeset_formats), NULL, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) { + kfree(primary); + primary = NULL; + } + + return primary; +} + int nv04_crtc_create(struct drm_device *dev, int crtc_num) { @@ -1114,7 +1146,9 @@ nv04_crtc_create(struct drm_device *dev, int crtc_num) nv_crtc->save = nv_crtc_save; nv_crtc->restore = nv_crtc_restore; - drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); + drm_crtc_init_with_planes(dev, &nv_crtc->base, + create_primary_plane(dev), NULL, + &nv04_crtc_funcs, NULL); drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index e54944d23268..c8c2333f24ee 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -63,6 +63,7 @@ static uint32_t formats[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12, + DRM_FORMAT_NV21, }; /* Sine can be approximated with @@ -90,6 +91,26 @@ cos_mul(int degrees, int factor) } static int +verify_scaling(const struct drm_framebuffer *fb, uint8_t shift, + uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, + uint32_t crtc_w, uint32_t crtc_h) +{ + if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { + DRM_DEBUG_KMS("Unsuitable framebuffer scaling: %dx%d -> %dx%d\n", + src_w, src_h, crtc_w, crtc_h); + return -ERANGE; + } + + if (src_x != 0 || src_y != 0) { + DRM_DEBUG_KMS("Unsuitable framebuffer offset: %d,%d\n", + src_x, src_y); + return -ERANGE; + } + + return 0; +} + +static int nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, @@ -107,7 +128,9 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool flip = nv_plane->flip; int soff = NV_PCRTC0_SIZE * nv_crtc->index; int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index; - int format, ret; + unsigned shift = drm->client.device.info.chipset >= 0x30 ? 1 : 3; + unsigned format = 0; + int ret; /* Source parameters given in 16.16 fixed point, ignore fractional. */ src_x >>= 16; @@ -115,18 +138,9 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, src_w >>= 16; src_h >>= 16; - format = ALIGN(src_w * 4, 0x100); - - if (format > 0xffff) - return -ERANGE; - - if (drm->client.device.info.chipset >= 0x30) { - if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) - return -ERANGE; - } else { - if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3)) - return -ERANGE; - } + ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); + if (ret) + return ret; ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false); if (ret) @@ -146,21 +160,23 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, nvif_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); - if (fb->format->format != DRM_FORMAT_UYVY) + if (fb->format->format == DRM_FORMAT_YUYV || + fb->format->format == DRM_FORMAT_NV12) format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; - if (fb->format->format == DRM_FORMAT_NV12) + if (fb->format->format == DRM_FORMAT_NV12 || + fb->format->format == DRM_FORMAT_NV21) format |= NV_PVIDEO_FORMAT_PLANAR; if (nv_plane->iturbt_709) format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; if (nv_plane->colorkey & (1 << 24)) format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; - if (fb->format->format == DRM_FORMAT_NV12) { + if (format & NV_PVIDEO_FORMAT_PLANAR) { nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset + fb->offsets[1]); } - nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format); + nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format | fb->pitches[0]); nvif_wr32(dev, NV_PVIDEO_STOP, 0); /* TODO: wait for vblank? */ nvif_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1); @@ -357,7 +373,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct nouveau_bo *cur = nv_plane->cur; uint32_t overlay = 1; int brightness = (nv_plane->brightness - 512) * 62 / 512; - int pitch, ret, i; + int ret, i; /* Source parameters given in 16.16 fixed point, ignore fractional. */ src_x >>= 16; @@ -365,17 +381,9 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, src_w >>= 16; src_h >>= 16; - pitch = ALIGN(src_w * 4, 0x100); - - if (pitch > 0xffff) - return -ERANGE; - - /* TODO: Compute an offset? Not sure how to do this for YUYV. */ - if (src_x != 0 || src_y != 0) - return -ERANGE; - - if (crtc_w < src_w || crtc_h < src_h) - return -ERANGE; + ret = verify_scaling(fb, 0, src_x, src_y, src_w, src_h, crtc_w, crtc_h); + if (ret) + return ret; ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false); if (ret) @@ -389,8 +397,9 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, for (i = 0; i < 2; i++) { nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i, - nv_fb->nvbo->bo.offset); - nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch); + nv_fb->nvbo->bo.offset); + nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, + fb->pitches[0]); nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0); } nvif_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h index e8e77ee24776..deb477282dde 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h @@ -18,6 +18,7 @@ enum dcb_connector_type { DCB_CONNECTOR_HDMI_C = 0x63, DCB_CONNECTOR_DMS59_DP0 = 0x64, DCB_CONNECTOR_DMS59_DP1 = 0x65, + DCB_CONNECTOR_WFD = 0x70, DCB_CONNECTOR_NONE = 0xff }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h index 4892a65ddd48..903d117603d8 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h @@ -6,6 +6,7 @@ enum dcb_output_type { DCB_OUTPUT_TMDS = 0x2, DCB_OUTPUT_LVDS = 0x3, DCB_OUTPUT_DP = 0x6, + DCB_OUTPUT_WFD = 0x8, DCB_OUTPUT_EOL = 0xe, DCB_OUTPUT_UNUSED = 0xf, DCB_OUTPUT_ANY = -1, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h index b268b96faece..1bfd93b85575 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -96,4 +96,5 @@ int g84_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gt215_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gf119_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gm107_therm_new(struct nvkm_device *, int, struct nvkm_therm **); +int gm200_therm_new(struct nvkm_device *, int, struct nvkm_therm **); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index b998c33af18a..dd6fba55ad5d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -351,11 +351,8 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) struct lvdstableheader lth; if (bios->fp.fptablepointer == 0x0) { - /* Apple cards don't have the fp table; the laptops use DDC */ - /* The table is also missing on some x86 IGPs */ -#ifndef __powerpc__ - NV_ERROR(drm, "Pointer to flat panel table invalid\n"); -#endif + /* Most laptop cards lack an fp table. They use DDC. */ + NV_DEBUG(drm, "Pointer to flat panel table invalid\n"); bios->digital_min_front_porch = 0x4b; return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 5137155bf3c0..70d8e0d69ad5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -1184,6 +1184,7 @@ drm_conntype_from_dcb(enum dcb_connector_type dcb) case DCB_CONNECTOR_HDMI_0 : case DCB_CONNECTOR_HDMI_1 : case DCB_CONNECTOR_HDMI_C : return DRM_MODE_CONNECTOR_HDMIA; + case DCB_CONNECTOR_WFD : return DRM_MODE_CONNECTOR_VIRTUAL; default: break; } diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index d66640047913..2e7785f49e6d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -231,9 +231,30 @@ nouveau_framebuffer_new(struct drm_device *dev, struct nouveau_bo *nvbo, struct nouveau_framebuffer **pfb) { + struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_framebuffer *fb; int ret; + /* YUV overlays have special requirements pre-NV50 */ + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA && + + (mode_cmd->pixel_format == DRM_FORMAT_YUYV || + mode_cmd->pixel_format == DRM_FORMAT_UYVY || + mode_cmd->pixel_format == DRM_FORMAT_NV12 || + mode_cmd->pixel_format == DRM_FORMAT_NV21) && + (mode_cmd->pitches[0] & 0x3f || /* align 64 */ + mode_cmd->pitches[0] >= 0x10000 || /* at most 64k pitch */ + (mode_cmd->pitches[1] && /* pitches for planes must match */ + mode_cmd->pitches[0] != mode_cmd->pitches[1]))) { + struct drm_format_name_buf format_name; + DRM_DEBUG_KMS("Unsuitable framebuffer: format: %s; pitches: 0x%x\n 0x%x\n", + drm_get_format_name(mode_cmd->pixel_format, + &format_name), + mode_cmd->pitches[0], + mode_cmd->pitches[1]); + return -EINVAL; + } + if (!(fb = *pfb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index df7e2037031a..595630d1fb9e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -585,18 +585,18 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) nouveau_led_suspend(dev); if (dev->mode_config.num_crtc) { - NV_INFO(drm, "suspending console...\n"); + NV_DEBUG(drm, "suspending console...\n"); nouveau_fbcon_set_suspend(dev, 1); - NV_INFO(drm, "suspending display...\n"); + NV_DEBUG(drm, "suspending display...\n"); ret = nouveau_display_suspend(dev, runtime); if (ret) return ret; } - NV_INFO(drm, "evicting buffers...\n"); + NV_DEBUG(drm, "evicting buffers...\n"); ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); - NV_INFO(drm, "waiting for kernel channels to go idle...\n"); + NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); if (drm->cechan) { ret = nouveau_channel_idle(drm->cechan); if (ret) @@ -609,7 +609,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) goto fail_display; } - NV_INFO(drm, "suspending fence...\n"); + NV_DEBUG(drm, "suspending fence...\n"); if (drm->fence && nouveau_fence(drm)->suspend) { if (!nouveau_fence(drm)->suspend(drm)) { ret = -ENOMEM; @@ -617,7 +617,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) } } - NV_INFO(drm, "suspending object tree...\n"); + NV_DEBUG(drm, "suspending object tree...\n"); ret = nvif_client_suspend(&drm->client.base); if (ret) goto fail_client; @@ -630,7 +630,7 @@ fail_client: fail_display: if (dev->mode_config.num_crtc) { - NV_INFO(drm, "resuming display...\n"); + NV_DEBUG(drm, "resuming display...\n"); nouveau_display_resume(dev, runtime); } return ret; @@ -641,19 +641,19 @@ nouveau_do_resume(struct drm_device *dev, bool runtime) { struct nouveau_drm *drm = nouveau_drm(dev); - NV_INFO(drm, "resuming object tree...\n"); + NV_DEBUG(drm, "resuming object tree...\n"); nvif_client_resume(&drm->client.base); - NV_INFO(drm, "resuming fence...\n"); + NV_DEBUG(drm, "resuming fence...\n"); if (drm->fence && nouveau_fence(drm)->resume) nouveau_fence(drm)->resume(drm); nouveau_run_vbios_init(dev); if (dev->mode_config.num_crtc) { - NV_INFO(drm, "resuming display...\n"); + NV_DEBUG(drm, "resuming display...\n"); nouveau_display_resume(dev, runtime); - NV_INFO(drm, "resuming console...\n"); + NV_DEBUG(drm, "resuming console...\n"); nouveau_fbcon_set_suspend(dev, 0); } diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 999c35a25498..b0ad7fcefcf5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -179,7 +179,8 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, } static void -nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) +nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, + struct drm_printer *printer) { } @@ -252,7 +253,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, } static void -nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) +nv04_gart_manager_debug(struct ttm_mem_type_manager *man, + struct drm_printer *printer) { } diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index f7b4326a4641..2dbf62a2ac41 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -3141,7 +3141,7 @@ nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, mstc->connector.funcs->reset(&mstc->connector); nouveau_conn_attach_properties(&mstc->connector); - for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++) + for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); @@ -4451,11 +4451,13 @@ nv50_display_create(struct drm_device *dev) /* create crtc objects to represent the hw heads */ if (disp->disp->oclass >= GF110_DISP) - crtcs = nvif_rd32(&device->object, 0x022448); + crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; else - crtcs = 2; + crtcs = 0x3; - for (i = 0; i < crtcs; i++) { + for (i = 0; i < fls(crtcs); i++) { + if (!(crtcs & (1 << i))) + continue; ret = nv50_head_create(dev, i); if (ret) goto out; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7bdc7a5ae723..e096a5d9c292 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2043,6 +2043,7 @@ nv120_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2077,6 +2078,7 @@ nv124_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2111,6 +2113,7 @@ nv126_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2321,6 +2324,35 @@ nv137_chipset = { }; static const struct nvkm_device_chip +nv138_chipset = { + .name = "GP108", + .bar = gf100_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp102_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .pmu = gp102_pmu_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp102_ce_new, + .ce[1] = gp102_ce_new, + .ce[2] = gp102_ce_new, + .ce[3] = gp102_ce_new, + .disp = gp102_disp_new, + .dma = gf119_dma_new, + .fifo = gp100_fifo_new, +}; + +static const struct nvkm_device_chip nv13b_chipset = { .name = "GP10B", .bar = gk20a_bar_new, @@ -2782,6 +2814,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, case 0x134: device->chip = &nv134_chipset; break; case 0x136: device->chip = &nv136_chipset; break; case 0x137: device->chip = &nv137_chipset; break; + case 0x138: device->chip = &nv138_chipset; break; case 0x13b: device->chip = &nv13b_chipset; break; default: nvdev_error(device, "unknown chipset (%08x)\n", boot0); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index 88582af8bd89..93a75e5b2791 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -285,6 +285,10 @@ nvkm_disp_oneinit(struct nvkm_engine *engine) case DCB_OUTPUT_DP: ret = nvkm_dp_new(disp, i, &dcbE, &outp); break; + case DCB_OUTPUT_WFD: + /* No support for WFD yet. */ + ret = -ENODEV; + continue; default: nvkm_warn(subdev, "dcb %d type %d unknown\n", i, dcbE.type); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c index b33552757647..9fd7ae331308 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c @@ -92,5 +92,8 @@ gf119_head = { int gf119_head_new(struct nvkm_disp *disp, int id) { + struct nvkm_device *device = disp->engine.subdev.device; + if (!(nvkm_rd32(device, 0x612004) & (0x00000001 << id))) + return 0; return nvkm_head_new_(&gf119_head, disp, id); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 8a8895246d26..7fea7d45202f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -124,6 +124,8 @@ nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) static bool nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) { + struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg); + struct nvkm_subdev *subdev = &mpeg->engine.subdev; u32 inst = data << 4; u32 dma0 = nvkm_rd32(device, 0x700000 + inst); u32 dma1 = nvkm_rd32(device, 0x700004 + inst); @@ -132,8 +134,11 @@ nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) u32 size = dma1 + 1; /* only allow linear DMA objects */ - if (!(dma0 & 0x00002000)) + if (!(dma0 & 0x00002000)) { + nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n", + inst, dma0, dma1, dma2); return false; + } if (mthd == 0x0190) { /* DMA_CMD */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c index 16de5bd94b14..b5ec7c504dc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c @@ -31,6 +31,8 @@ bool nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) { struct nvkm_instmem *imem = device->imem; + struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg); + struct nvkm_subdev *subdev = &mpeg->engine.subdev; u32 inst = data << 4; u32 dma0 = nvkm_instmem_rd32(imem, inst + 0); u32 dma1 = nvkm_instmem_rd32(imem, inst + 4); @@ -39,8 +41,11 @@ nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) u32 size = dma1 + 1; /* only allow linear DMA objects */ - if (!(dma0 & 0x00002000)) + if (!(dma0 & 0x00002000)) { + nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n", + inst, dma0, dma1, dma2); return false; + } if (mthd == 0x0190) { /* DMA_CMD */ diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c index d45d7947a964..77273b53672c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c @@ -251,7 +251,7 @@ cmd_write(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_hdr *cmd, struct nvkm_msgqueue_queue *queue) { const struct nvkm_subdev *subdev = priv->falcon->owner; - static unsigned long timeout = ~0; + static unsigned timeout = 2000; unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); int ret = -EAGAIN; bool commit = true; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index 6d8f21290aa2..676c167c95b9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -24,6 +24,7 @@ #include "gf100.h" #include <core/gpuobj.h> +#include <core/option.h> #include <subdev/fb.h> #include <subdev/mmu.h> @@ -59,6 +60,8 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm, return ret; bar_len = device->func->resource_size(device, bar_nr); + if (bar_nr == 3 && bar->bar2_halve) + bar_len >>= 1; ret = nvkm_vm_new(device, 0, bar_len, 0, key, &vm); if (ret) @@ -129,6 +132,8 @@ gf100_bar_init(struct nvkm_bar *base) if (bar->bar[0].mem) { addr = nvkm_memory_addr(bar->bar[0].mem) >> 12; + if (bar->bar2_halve) + addr |= 0x40000000; nvkm_wr32(device, 0x001714, 0x80000000 | addr); } @@ -161,6 +166,7 @@ gf100_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) return -ENOMEM; nvkm_bar_ctor(func, device, index, &bar->base); + bar->bar2_halve = nvkm_boolopt(device->cfgopt, "NvBar2Halve", false); *pbar = &bar->base; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h index f7dea69640d8..20a5255362ba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h @@ -11,6 +11,7 @@ struct gf100_bar_vm { struct gf100_bar { struct nvkm_bar base; + bool bar2_halve; struct gf100_bar_vm bar[2]; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index 3841ad6be99e..a239e73562c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -60,12 +60,12 @@ gf100_fb_oneinit(struct nvkm_fb *base) size = min(size, 0x1000); ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000, - false, &fb->base.mmu_rd); + true, &fb->base.mmu_rd); if (ret) return ret; ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000, - false, &fb->base.mmu_wr); + true, &fb->base.mmu_wr); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 4a57defc99b3..1399d923d446 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -171,7 +171,7 @@ nvkm_gpio_fini(struct nvkm_subdev *subdev, bool suspend) return 0; } -static struct dmi_system_id gpio_reset_ids[] = { +static const struct dmi_system_id gpio_reset_ids[] = { { .ident = "Apple Macbook 10,1", .matches = { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index d2c4d6033abb..f93766418056 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c @@ -27,6 +27,7 @@ static const struct nvkm_mc_map gf100_mc_reset[] = { { 0x00020000, NVKM_ENGINE_MSPDEC }, { 0x00008000, NVKM_ENGINE_MSVLD }, + { 0x00002000, NVKM_SUBDEV_PMU, true }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, { 0x00000080, NVKM_ENGINE_CE1 }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c index eb9b278198b2..a4cb82495cee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c @@ -192,6 +192,10 @@ nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device, } } +#ifdef __BIG_ENDIAN + pci->msi = false; +#endif + pci->msi = nvkm_boolopt(device->cfgopt, "NvMSI", pci->msi); if (pci->msi && func->msi_rearm) { pci->msi = pci_enable_msi(pci->pdev) == 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index 3306f9fe7140..ce70a193caa7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -75,7 +75,7 @@ nvkm_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; - if (!(nvkm_rd32(device, 0x000200) & 0x00002000)) + if (!pmu->func->enabled(pmu)) return 0; /* Inhibit interrupts, and wait for idle. */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c index 0e36d4cb7201..0b458656e870 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c @@ -24,13 +24,30 @@ #include "priv.h" #include "fuc/gf100.fuc3.h" +#include <subdev/mc.h> + +void +gf100_pmu_reset(struct nvkm_pmu *pmu) +{ + struct nvkm_device *device = pmu->subdev.device; + nvkm_mc_disable(device, NVKM_SUBDEV_PMU); + nvkm_mc_enable(device, NVKM_SUBDEV_PMU); +} + +bool +gf100_pmu_enabled(struct nvkm_pmu *pmu) +{ + return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU); +} + static const struct nvkm_pmu_func gf100_pmu = { .code.data = gf100_pmu_code, .code.size = sizeof(gf100_pmu_code), .data.data = gf100_pmu_data, .data.size = sizeof(gf100_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c index 0e4ba4248b15..3dfa79d4fb13 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c @@ -30,7 +30,8 @@ gf119_pmu = { .code.size = sizeof(gf119_pmu_code), .data.data = gf119_pmu_data, .data.size = sizeof(gf119_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c index 2ad858d825ac..8f7ec10fd2a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c @@ -109,7 +109,8 @@ gk104_pmu = { .code.size = sizeof(gk104_pmu_code), .data.data = gk104_pmu_data, .data.size = sizeof(gk104_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c index fc4b8ecfdaeb..345741d55a56 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c @@ -88,7 +88,8 @@ gk110_pmu = { .code.size = sizeof(gk110_pmu_code), .data.data = gk110_pmu_data, .data.size = sizeof(gk110_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c index e9a91277683a..e4acf7876ea1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c @@ -30,7 +30,8 @@ gk208_pmu = { .code.size = sizeof(gk208_pmu_code), .data.data = gk208_pmu_data, .data.size = sizeof(gk208_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index 978aae3c1001..05e81855c367 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -196,9 +196,10 @@ gk20a_dvfs_data= { static const struct nvkm_pmu_func gk20a_pmu = { + .enabled = gf100_pmu_enabled, .init = gk20a_pmu_init, .fini = gk20a_pmu_fini, - .reset = gt215_pmu_reset, + .reset = gf100_pmu_reset, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c index 9a248ed75f09..459df1ef9e70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c @@ -32,7 +32,8 @@ gm107_pmu = { .code.size = sizeof(gm107_pmu_code), .data.data = gm107_pmu_data, .data.size = sizeof(gm107_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 44bef22bce52..31c843145c7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -38,6 +38,7 @@ gm20b_pmu_recv(struct nvkm_pmu *pmu) static const struct nvkm_pmu_func gm20b_pmu = { + .enabled = gf100_pmu_enabled, .intr = gt215_pmu_intr, .recv = gm20b_pmu_recv, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c index 6c41c20c85a7..e210cd6af816 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c @@ -25,7 +25,8 @@ static const struct nvkm_pmu_func gp100_pmu = { - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c index f017352206c9..98c7a2a8afc4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c @@ -31,8 +31,15 @@ gp102_pmu_reset(struct nvkm_pmu *pmu) nvkm_mask(device, 0x10a3c0, 0x00000001, 0x00000000); } +static bool +gp102_pmu_enabled(struct nvkm_pmu *pmu) +{ + return !(nvkm_rd32(pmu->subdev.device, 0x10a3c0) & 0x00000001); +} + static const struct nvkm_pmu_func gp102_pmu = { + .enabled = gp102_pmu_enabled, .reset = gp102_pmu_reset, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c index 90d428b3be97..e04216daea58 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c @@ -180,13 +180,19 @@ gt215_pmu_fini(struct nvkm_pmu *pmu) nvkm_wr32(pmu->subdev.device, 0x10a014, 0x00000060); } -void +static void gt215_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; - nvkm_mask(device, 0x000200, 0x00002000, 0x00000000); - nvkm_mask(device, 0x000200, 0x00002000, 0x00002000); - nvkm_rd32(device, 0x000200); + nvkm_mask(device, 0x022210, 0x00000001, 0x00000000); + nvkm_mask(device, 0x022210, 0x00000001, 0x00000001); + nvkm_rd32(device, 0x022210); +} + +static bool +gt215_pmu_enabled(struct nvkm_pmu *pmu) +{ + return nvkm_rd32(pmu->subdev.device, 0x022210) & 0x00000001; } int @@ -241,6 +247,7 @@ gt215_pmu = { .code.size = sizeof(gt215_pmu_code), .data.data = gt215_pmu_data, .data.size = sizeof(gt215_pmu_data), + .enabled = gt215_pmu_enabled, .reset = gt215_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index 096cba069f72..a4c48a10cd47 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -20,6 +20,7 @@ struct nvkm_pmu_func { u32 size; } data; + bool (*enabled)(struct nvkm_pmu *); void (*reset)(struct nvkm_pmu *); int (*init)(struct nvkm_pmu *); void (*fini)(struct nvkm_pmu *); @@ -30,12 +31,14 @@ struct nvkm_pmu_func { void (*pgob)(struct nvkm_pmu *, bool); }; -void gt215_pmu_reset(struct nvkm_pmu *); int gt215_pmu_init(struct nvkm_pmu *); void gt215_pmu_fini(struct nvkm_pmu *); void gt215_pmu_intr(struct nvkm_pmu *); void gt215_pmu_recv(struct nvkm_pmu *); int gt215_pmu_send(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); +bool gf100_pmu_enabled(struct nvkm_pmu *); +void gf100_pmu_reset(struct nvkm_pmu *); + void gk110_pmu_pgob(struct nvkm_pmu *, bool); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild index 135758ba3e28..2bafcc1d1818 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild @@ -11,3 +11,4 @@ nvkm-y += nvkm/subdev/therm/g84.o nvkm-y += nvkm/subdev/therm/gt215.o nvkm-y += nvkm/subdev/therm/gf119.o nvkm-y += nvkm/subdev/therm/gm107.o +nvkm-y += nvkm/subdev/therm/gm200.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c index 86e81930d8ee..96f8da40ac82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c @@ -203,7 +203,7 @@ g84_therm_fini(struct nvkm_therm *therm) nvkm_wr32(device, 0x1100, 0x10000); /* PBUS */ } -static void +void g84_therm_init(struct nvkm_therm *therm) { g84_sensor_setup(therm); diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c index 9ef96aab3f24..73dc78093d5d 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2017 Karol Herbst * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,16 +19,21 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: Karol Herbst */ +#include "priv.h" -#ifndef _EVENTINIT_H_ -#define _EVENTINIT_H_ +static const struct nvkm_therm_func +gm200_therm = { + .init = g84_therm_init, + .fini = g84_therm_fini, + .temp_get = g84_temp_get, + .program_alarms = nvkm_therm_program_alarms_polling, +}; -#define PEM_CURRENT_POWERPLAY_FEATURE_VERSION 4 - -void pem_init_feature_info(struct pp_eventmgr *eventmgr); -void pem_uninit_featureInfo(struct pp_eventmgr *eventmgr); -int pem_register_interrupts(struct pp_eventmgr *eventmgr); -int pem_unregister_interrupts(struct pp_eventmgr *eventmgr); - -#endif /* _EVENTINIT_H_ */ +int +gm200_therm_new(struct nvkm_device *device, int index, + struct nvkm_therm **ptherm) +{ + return nvkm_therm_new_(&gm200_therm, device, index, ptherm); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h index 235a5d8daff6..1f46e371d7c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h @@ -111,6 +111,7 @@ void g84_therm_fini(struct nvkm_therm *); int gt215_therm_fan_sense(struct nvkm_therm *); +void g84_therm_init(struct nvkm_therm *); void gf119_therm_init(struct nvkm_therm *); int nvkm_fanpwm_create(struct nvkm_therm *, struct dcb_gpio_func *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c index e93b2410c38b..ddb2b2c600ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c @@ -83,7 +83,7 @@ nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs, { struct nvkm_subdev *subdev = &therm->subdev; bool active; - const char *thresolds[] = { + static const char * const thresholds[] = { "fanboost", "downclock", "critical", "shutdown" }; int temperature = therm->func->temp_get(therm); @@ -94,10 +94,10 @@ nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs, if (dir == NVKM_THERM_THRS_FALLING) nvkm_info(subdev, "temperature (%i C) went below the '%s' threshold\n", - temperature, thresolds[thrs]); + temperature, thresholds[thrs]); else nvkm_info(subdev, "temperature (%i C) hit the '%s' threshold\n", - temperature, thresolds[thrs]); + temperature, thresholds[thrs]); active = (dir == NVKM_THERM_THRS_RISING); switch (thrs) { diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index 085486024089..ed465572491e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -185,6 +185,9 @@ struct dss_pll_hw { bool has_freqsel; bool has_selfreqdco; bool has_refsel; + + /* DRA7 errata i886: use high N & M to avoid jitter */ + bool errata_i886; }; struct dss_pll { diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c index 5e221302768b..9d9d9d42009b 100644 --- a/drivers/gpu/drm/omapdrm/dss/pll.c +++ b/drivers/gpu/drm/omapdrm/dss/pll.c @@ -215,8 +215,8 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, dss_pll_calc_func func, void *data) { const struct dss_pll_hw *hw = pll->hw; - int n, n_min, n_max; - int m, m_min, m_max; + int n, n_start, n_stop, n_inc; + int m, m_start, m_stop, m_inc; unsigned long fint, clkdco; unsigned long pll_hw_max; unsigned long fint_hw_min, fint_hw_max; @@ -226,22 +226,33 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, fint_hw_min = hw->fint_min; fint_hw_max = hw->fint_max; - n_min = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); - n_max = min((unsigned)(clkin / fint_hw_min), hw->n_max); + n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); + n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max); + n_inc = 1; + + if (hw->errata_i886) { + swap(n_start, n_stop); + n_inc = -1; + } pll_max = pll_max ? pll_max : ULONG_MAX; - /* Try to find high N & M to avoid jitter (DRA7 errata i886) */ - for (n = n_max; n >= n_min; --n) { + for (n = n_start; n != n_stop; n += n_inc) { fint = clkin / n; - m_min = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), + m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), 1ul); - m_max = min3((unsigned)(pll_max / fint / 2), + m_stop = min3((unsigned)(pll_max / fint / 2), (unsigned)(pll_hw_max / fint / 2), hw->m_max); + m_inc = 1; + + if (hw->errata_i886) { + swap(m_start, m_stop); + m_inc = -1; + } - for (m = m_max; m >= m_min; --m) { + for (m = m_start; m != m_stop; m += m_inc) { clkdco = 2 * m * fint; if (func(n, m, fint, clkdco, data)) diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c index 5bd7788357b2..d58da6f32693 100644 --- a/drivers/gpu/drm/omapdrm/dss/venc.c +++ b/drivers/gpu/drm/omapdrm/dss/venc.c @@ -263,6 +263,12 @@ static const struct venc_config venc_config_pal_bdghi = { .fid_ext_start_y__fid_ext_offset_y = 0x01380005, }; +enum venc_videomode { + VENC_MODE_UNKNOWN, + VENC_MODE_PAL, + VENC_MODE_NTSC, +}; + static const struct videomode omap_dss_pal_vm = { .hactive = 720, .vactive = 574, @@ -297,6 +303,24 @@ static const struct videomode omap_dss_ntsc_vm = { DISPLAY_FLAGS_SYNC_NEGEDGE, }; +static enum venc_videomode venc_get_videomode(const struct videomode *vm) +{ + if (!(vm->flags & DISPLAY_FLAGS_INTERLACED)) + return VENC_MODE_UNKNOWN; + + if (vm->pixelclock == omap_dss_pal_vm.pixelclock && + vm->hactive == omap_dss_pal_vm.hactive && + vm->vactive == omap_dss_pal_vm.vactive) + return VENC_MODE_PAL; + + if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock && + vm->hactive == omap_dss_ntsc_vm.hactive && + vm->vactive == omap_dss_ntsc_vm.vactive) + return VENC_MODE_NTSC; + + return VENC_MODE_UNKNOWN; +} + static struct { struct platform_device *pdev; void __iomem *base; @@ -423,14 +447,14 @@ static void venc_runtime_put(void) static const struct venc_config *venc_timings_to_config(struct videomode *vm) { - if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0) + switch (venc_get_videomode(vm)) { + default: + WARN_ON_ONCE(1); + case VENC_MODE_PAL: return &venc_config_pal_trm; - - if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0) + case VENC_MODE_NTSC: return &venc_config_ntsc_trm; - - BUG(); - return NULL; + } } static int venc_power_on(struct omap_dss_device *dssdev) @@ -541,15 +565,28 @@ static void venc_display_disable(struct omap_dss_device *dssdev) static void venc_set_timings(struct omap_dss_device *dssdev, struct videomode *vm) { + struct videomode actual_vm; + DSSDBG("venc_set_timings\n"); mutex_lock(&venc.venc_lock); + switch (venc_get_videomode(vm)) { + default: + WARN_ON_ONCE(1); + case VENC_MODE_PAL: + actual_vm = omap_dss_pal_vm; + break; + case VENC_MODE_NTSC: + actual_vm = omap_dss_ntsc_vm; + break; + } + /* Reset WSS data when the TV standard changes. */ - if (memcmp(&venc.vm, vm, sizeof(*vm))) + if (memcmp(&venc.vm, &actual_vm, sizeof(actual_vm))) venc.wss_data = 0; - venc.vm = *vm; + venc.vm = actual_vm; dispc_set_tv_pclk(13500000); @@ -561,13 +598,13 @@ static int venc_check_timings(struct omap_dss_device *dssdev, { DSSDBG("venc_check_timings\n"); - if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0) + switch (venc_get_videomode(vm)) { + case VENC_MODE_PAL: + case VENC_MODE_NTSC: return 0; - - if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0) - return 0; - - return -EINVAL; + default: + return -EINVAL; + } } static void venc_get_timings(struct omap_dss_device *dssdev, diff --git a/drivers/gpu/drm/omapdrm/dss/video-pll.c b/drivers/gpu/drm/omapdrm/dss/video-pll.c index f7ea02a88b1a..38a239cc5e04 100644 --- a/drivers/gpu/drm/omapdrm/dss/video-pll.c +++ b/drivers/gpu/drm/omapdrm/dss/video-pll.c @@ -130,6 +130,8 @@ static const struct dss_pll_hw dss_dra7_video_pll_hw = { .mX_lsb[3] = 5, .has_refsel = true, + + .errata_i886 = true, }; struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 9b3c36b48356..cdf5b0601eba 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -84,23 +84,36 @@ static void omap_atomic_commit_tail(struct drm_atomic_state *old_state) /* Apply the atomic update. */ drm_atomic_helper_commit_modeset_disables(dev, old_state); - /* With the current dss dispc implementation we have to enable - * the new modeset before we can commit planes. The dispc ovl - * configuration relies on the video mode configuration been - * written into the HW when the ovl configuration is - * calculated. - * - * This approach is not ideal because after a mode change the - * plane update is executed only after the first vblank - * interrupt. The dispc implementation should be fixed so that - * it is able use uncommitted drm state information. - */ - drm_atomic_helper_commit_modeset_enables(dev, old_state); - omap_atomic_wait_for_completion(dev, old_state); - - drm_atomic_helper_commit_planes(dev, old_state, 0); - - drm_atomic_helper_commit_hw_done(old_state); + if (priv->omaprev != 0x3430) { + /* With the current dss dispc implementation we have to enable + * the new modeset before we can commit planes. The dispc ovl + * configuration relies on the video mode configuration been + * written into the HW when the ovl configuration is + * calculated. + * + * This approach is not ideal because after a mode change the + * plane update is executed only after the first vblank + * interrupt. The dispc implementation should be fixed so that + * it is able use uncommitted drm state information. + */ + drm_atomic_helper_commit_modeset_enables(dev, old_state); + omap_atomic_wait_for_completion(dev, old_state); + + drm_atomic_helper_commit_planes(dev, old_state, 0); + + drm_atomic_helper_commit_hw_done(old_state); + } else { + /* + * OMAP3 DSS seems to have issues with the work-around above, + * resulting in endless sync losts if a crtc is enabled without + * a plane. For now, skip the WA for OMAP3. + */ + drm_atomic_helper_commit_planes(dev, old_state, 0); + + drm_atomic_helper_commit_modeset_enables(dev, old_state); + + drm_atomic_helper_commit_hw_done(old_state); + } /* * Wait for completion of the page flips to ensure that old buffers diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 14c5613b4388..afbf50d0c08f 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -509,23 +509,25 @@ static void qxl_primary_atomic_update(struct drm_plane *plane, .y2 = qfb->base.height }; - if (!old_state->fb) { - qxl_io_log(qdev, - "create primary fb: %dx%d,%d,%d\n", - bo->surf.width, bo->surf.height, - bo->surf.stride, bo->surf.format); + if (old_state->fb) { + qfb_old = to_qxl_framebuffer(old_state->fb); + bo_old = gem_to_qxl_bo(qfb_old->obj); + } else { + bo_old = NULL; + } - qxl_io_create_primary(qdev, 0, bo); - bo->is_primary = true; + if (bo == bo_old) return; - } else { - qfb_old = to_qxl_framebuffer(old_state->fb); - bo_old = gem_to_qxl_bo(qfb_old->obj); + if (bo_old && bo_old->is_primary) { + qxl_io_destroy_primary(qdev); bo_old->is_primary = false; } - bo->is_primary = true; + if (!bo->is_primary) { + qxl_io_create_primary(qdev, 0, bo); + bo->is_primary = true; + } qxl_draw_dirty_fb(qdev, qfb, bo, 0, 0, &norect, 1, 1); } @@ -534,13 +536,15 @@ static void qxl_primary_atomic_disable(struct drm_plane *plane, { struct qxl_device *qdev = plane->dev->dev_private; - if (old_state->fb) - { struct qxl_framebuffer *qfb = + if (old_state->fb) { + struct qxl_framebuffer *qfb = to_qxl_framebuffer(old_state->fb); struct qxl_bo *bo = gem_to_qxl_bo(qfb->obj); - qxl_io_destroy_primary(qdev); - bo->is_primary = false; + if (bo->is_primary) { + qxl_io_destroy_primary(qdev); + bo->is_primary = false; + } } } @@ -698,14 +702,15 @@ static void qxl_plane_cleanup_fb(struct drm_plane *plane, struct drm_gem_object *obj; struct qxl_bo *user_bo; - if (!plane->state->fb) { - /* we never executed prepare_fb, so there's nothing to + if (!old_state->fb) { + /* + * we never executed prepare_fb, so there's nothing to * unpin. */ return; } - obj = to_qxl_framebuffer(plane->state->fb)->obj; + obj = to_qxl_framebuffer(old_state->fb)->obj; user_bo = gem_to_qxl_bo(obj); qxl_bo_unpin(user_bo); } diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 4acbb944bcd2..be16c6390216 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -109,5 +109,3 @@ radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o radeon-$(CONFIG_ACPI) += radeon_acpi.o obj-$(CONFIG_DRM_RADEON)+= radeon.o - -CFLAGS_radeon_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index e82a99cb2459..ab32830c4e23 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -58,7 +58,7 @@ enum r600_hdmi_iec_status_bits { static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) { - struct r600_audio_pin status; + struct r600_audio_pin status = {}; uint32_t value; value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index ec63bc5e9de7..8cbaeec090c9 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -924,7 +924,7 @@ struct radeon_vm_id { struct radeon_vm { struct mutex mutex; - struct rb_root va; + struct rb_root_cached va; /* protecting invalidated and freed */ spinlock_t status_lock; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 997131d58c7f..ffc10cadcf34 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1663,7 +1663,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, radeon_agp_suspend(rdev); pci_save_state(dev->pdev); - if (freeze && rdev->family >= CHIP_CEDAR) { + if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) { rdev->asic->asic_reset(rdev, true); pci_restore_state(dev->pdev); } else if (suspend) { diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index fd25361ac681..2fcf805d3a16 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -322,10 +322,10 @@ static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfb if (rfb->obj) { radeonfb_destroy_pinned_object(rfb->obj); rfb->obj = NULL; + drm_framebuffer_unregister_private(&rfb->base); + drm_framebuffer_cleanup(&rfb->base); } drm_fb_helper_fini(&rfbdev->helper); - drm_framebuffer_unregister_private(&rfb->base); - drm_framebuffer_cleanup(&rfb->base); return 0; } diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index a2ab6dcdf4a2..a2ac8ac0930d 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -58,6 +58,10 @@ static uint64_t get_vmem_size(struct kgd_dev *kgd); static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd); + +static int alloc_pasid(unsigned int bits); +static void free_pasid(unsigned int pasid); + static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); /* @@ -75,12 +79,14 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); @@ -110,6 +116,8 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_vmem_size = get_vmem_size, .get_gpu_clock_counter = get_gpu_clock_counter, .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, + .alloc_pasid = alloc_pasid, + .free_pasid = free_pasid, .program_sh_mem_settings = kgd_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, .init_pipeline = kgd_init_pipeline, @@ -339,6 +347,31 @@ static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd) return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100; } +/* + * PASID manager + */ +static DEFINE_IDA(pasid_ida); + +int alloc_pasid(unsigned int bits) +{ + int pasid = -EINVAL; + + for (bits = min(bits, 31U); bits > 0; bits--) { + pasid = ida_simple_get(&pasid_ida, + 1U << (bits - 1), 1U << bits, + GFP_KERNEL); + if (pasid != -ENOSPC) + break; + } + + return pasid; +} + +void free_pasid(unsigned int pasid) +{ + ida_simple_remove(&pasid_ida, pasid); +} + static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd) { return (struct radeon_device *)kgd; @@ -482,7 +515,9 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) } static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm) { uint32_t wptr_shadow, is_wptr_shadow_valid; struct cik_mqd *m; @@ -636,7 +671,7 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) return false; } -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id) { @@ -785,7 +820,8 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, unsigned int watch_point_id, unsigned int reg_offset) { - return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; + return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset] + / 4; } static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid) diff --git a/drivers/gpu/drm/radeon/radeon_mn.c b/drivers/gpu/drm/radeon/radeon_mn.c index 896f2cf51e4e..1d62288b7ee3 100644 --- a/drivers/gpu/drm/radeon/radeon_mn.c +++ b/drivers/gpu/drm/radeon/radeon_mn.c @@ -50,7 +50,7 @@ struct radeon_mn { /* objects protected by lock */ struct mutex lock; - struct rb_root objects; + struct rb_root_cached objects; }; struct radeon_mn_node { @@ -75,8 +75,8 @@ static void radeon_mn_destroy(struct work_struct *work) mutex_lock(&rdev->mn_lock); mutex_lock(&rmn->lock); hash_del(&rmn->node); - rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects, - it.rb) { + rbtree_postorder_for_each_entry_safe(node, next_node, + &rmn->objects.rb_root, it.rb) { interval_tree_remove(&node->it, &rmn->objects); list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { @@ -205,7 +205,7 @@ static struct radeon_mn *radeon_mn_get(struct radeon_device *rdev) rmn->mm = mm; rmn->mn.ops = &radeon_mn_ops; mutex_init(&rmn->lock); - rmn->objects = RB_ROOT; + rmn->objects = RB_ROOT_CACHED; r = __mmu_notifier_register(&rmn->mn, mm); if (r) diff --git a/drivers/gpu/drm/radeon/radeon_trace.h b/drivers/gpu/drm/radeon/radeon_trace.h index fdce4062901f..815eaa8c394b 100644 --- a/drivers/gpu/drm/radeon/radeon_trace.h +++ b/drivers/gpu/drm/radeon/radeon_trace.h @@ -204,5 +204,5 @@ DEFINE_EVENT(radeon_semaphore_request, radeon_semaphore_wait, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/radeon #include <trace/define_trace.h> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 50f60a587648..8032da57e409 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -725,8 +725,6 @@ static int radeon_ttm_tt_populate(struct ttm_tt *ttm) { struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); struct radeon_device *rdev; - unsigned i; - int r; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); if (ttm->state != tt_unpopulated) @@ -762,33 +760,13 @@ static int radeon_ttm_tt_populate(struct ttm_tt *ttm) } #endif - r = ttm_pool_populate(ttm); - if (r) { - return r; - } - - for (i = 0; i < ttm->num_pages; i++) { - gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], - 0, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { - while (i--) { - pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - gtt->ttm.dma_address[i] = 0; - } - ttm_pool_unpopulate(ttm); - return -EFAULT; - } - } - return 0; + return ttm_populate_and_map_pages(rdev->dev, >t->ttm); } static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) { struct radeon_device *rdev; struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); - unsigned i; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); if (gtt && gtt->userptr) { @@ -815,14 +793,7 @@ static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) } #endif - for (i = 0; i < ttm->num_pages; i++) { - if (gtt->ttm.dma_address[i]) { - pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - } - } - - ttm_pool_unpopulate(ttm); + ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); } int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, @@ -1030,19 +1001,17 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma) static int radeon_mm_dump_table(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *)m->private; - unsigned ttm_pl = *(int *)node->info_ent->data; + unsigned ttm_pl = *(int*)node->info_ent->data; struct drm_device *dev = node->minor->dev; struct radeon_device *rdev = dev->dev_private; - struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; - struct ttm_bo_global *glob = rdev->mman.bdev.glob; + struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl]; struct drm_printer p = drm_seq_file_printer(m); - spin_lock(&glob->lru_lock); - drm_mm_print(mm, &p); - spin_unlock(&glob->lru_lock); + man->func->debug(man, &p); return 0; } + static int ttm_pl_vram = TTM_PL_VRAM; static int ttm_pl_tt = TTM_PL_TT; diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index 5e82b408d522..e5c0e635e371 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c @@ -1185,7 +1185,7 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm) vm->ids[i].last_id_use = NULL; } mutex_init(&vm->mutex); - vm->va = RB_ROOT; + vm->va = RB_ROOT_CACHED; spin_lock_init(&vm->status_lock); INIT_LIST_HEAD(&vm->invalidated); INIT_LIST_HEAD(&vm->freed); @@ -1232,10 +1232,11 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm) struct radeon_bo_va *bo_va, *tmp; int i, r; - if (!RB_EMPTY_ROOT(&vm->va)) { + if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { dev_err(rdev->dev, "still active bo inside vm\n"); } - rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) { + rbtree_postorder_for_each_entry_safe(bo_va, tmp, + &vm->va.rb_root, it.rb) { interval_tree_remove(&bo_va->it, &vm->va); r = radeon_bo_reserve(bo_va->bo, false); if (!r) { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 83cfcfefedce..76d63de5921d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -270,11 +270,15 @@ static void rockchip_drm_fb_resume(struct drm_device *drm) static int rockchip_drm_sys_suspend(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); - struct rockchip_drm_private *priv = drm->dev_private; + struct rockchip_drm_private *priv; + + if (!drm) + return 0; drm_kms_helper_poll_disable(drm); rockchip_drm_fb_suspend(drm); + priv = drm->dev_private; priv->state = drm_atomic_helper_suspend(drm); if (IS_ERR(priv->state)) { rockchip_drm_fb_resume(drm); @@ -288,8 +292,12 @@ static int rockchip_drm_sys_suspend(struct device *dev) static int rockchip_drm_sys_resume(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); - struct rockchip_drm_private *priv = drm->dev_private; + struct rockchip_drm_private *priv; + + if (!drm) + return 0; + priv = drm->dev_private; drm_atomic_helper_resume(drm, priv->state); rockchip_drm_fb_resume(drm); drm_kms_helper_poll_enable(drm); diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c b/drivers/gpu/drm/selftests/test-drm_mm.c index dfdd858eda0a..86eb4c185a28 100644 --- a/drivers/gpu/drm/selftests/test-drm_mm.c +++ b/drivers/gpu/drm/selftests/test-drm_mm.c @@ -1627,7 +1627,7 @@ static int igt_topdown(void *ignored) goto err; bitmap = kzalloc(count / BITS_PER_LONG * sizeof(unsigned long), - GFP_TEMPORARY); + GFP_KERNEL); if (!bitmap) goto err_nodes; @@ -1741,7 +1741,7 @@ static int igt_bottomup(void *ignored) goto err; bitmap = kzalloc(count / BITS_PER_LONG * sizeof(unsigned long), - GFP_TEMPORARY); + GFP_KERNEL); if (!bitmap) goto err_nodes; diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index 5bcad8f5fb4f..882d85db9053 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -13,17 +13,26 @@ config DRM_SUN4I Display Engine. If M is selected the module will be called sun4i-drm. +if DRM_SUN4I + config DRM_SUN4I_HDMI tristate "Allwinner A10 HDMI Controller Support" - depends on DRM_SUN4I default DRM_SUN4I help Choose this option if you have an Allwinner SoC with an HDMI controller. +config DRM_SUN4I_HDMI_CEC + bool "Allwinner A10 HDMI CEC Support" + depends on DRM_SUN4I_HDMI + select CEC_CORE + select CEC_PIN + help + Choose this option if you have an Allwinner SoC with an HDMI + controller and want to use CEC. + config DRM_SUN4I_BACKEND tristate "Support for Allwinner A10 Display Engine Backend" - depends on DRM_SUN4I default DRM_SUN4I help Choose this option if you have an Allwinner SoC with the @@ -33,10 +42,11 @@ config DRM_SUN4I_BACKEND config DRM_SUN8I_MIXER tristate "Support for Allwinner Display Engine 2.0 Mixer" - depends on DRM_SUN4I default MACH_SUN8I help Choose this option if you have an Allwinner SoC with the Allwinner Display Engine 2.0, which has a mixer to do some graphics mixture and feed graphics to TCON, If M is selected the module will be called sun8i-mixer. + +endif diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index e29fd3a2ba9c..43c753cafc88 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -2,6 +2,7 @@ sun4i-drm-y += sun4i_drv.o sun4i-drm-y += sun4i_framebuffer.o sun4i-drm-hdmi-y += sun4i_hdmi_enc.o +sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index cf480218daa5..ec5943627aa5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -312,7 +312,7 @@ static int sun4i_backend_of_get_id(struct device_node *node) struct device_node *remote; u32 reg; - remote = of_parse_phandle(ep, "remote-endpoint", 0); + remote = of_graph_get_remote_endpoint(ep); if (!remote) continue; diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 6eddb8086075..a2012638d5f7 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -25,12 +25,20 @@ #include "sun4i_framebuffer.h" #include "sun4i_tcon.h" +static void sun4i_drv_lastclose(struct drm_device *dev) +{ + struct sun4i_drv *drv = dev->dev_private; + + drm_fbdev_cma_restore_mode(drv->fbdev); +} + DEFINE_DRM_GEM_CMA_FOPS(sun4i_drv_fops); static struct drm_driver sun4i_drv_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC, /* Generic Operations */ + .lastclose = sun4i_drv_lastclose, .fops = &sun4i_drv_fops, .name = "sun4i-drm", .desc = "Allwinner sun4i Display Engine", diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h index 2f2f2ff1ea63..a1f8cba251a2 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h @@ -15,6 +15,8 @@ #include <drm/drm_connector.h> #include <drm/drm_encoder.h> +#include <media/cec-pin.h> + #define SUN4I_HDMI_CTRL_REG 0x004 #define SUN4I_HDMI_CTRL_ENABLE BIT(31) @@ -86,6 +88,11 @@ #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21 +#define SUN4I_HDMI_CEC 0x214 +#define SUN4I_HDMI_CEC_ENABLE BIT(11) +#define SUN4I_HDMI_CEC_TX BIT(9) +#define SUN4I_HDMI_CEC_RX BIT(8) + #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n))) #define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4)) @@ -96,6 +103,7 @@ #define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) #define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) +#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8) #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8) #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0) @@ -105,14 +113,34 @@ #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff) +#define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c +#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7) +#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6) +#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5) +#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4) +#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3) +#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2) +#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1) +#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0) + #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510 #define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) +#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4) +#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4) +#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1) +#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf) +#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0) +#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1) #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518 + #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c +#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1) #define SUN4I_HDMI_DDC_CMD_REG 0x520 #define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6 +#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5 +#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3 #define SUN4I_HDMI_DDC_CLK_REG 0x528 #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3) @@ -146,12 +174,16 @@ struct sun4i_hdmi { struct clk *ddc_clk; struct clk *tmds_clk; + struct i2c_adapter *i2c; + struct sun4i_drv *drv; bool hdmi_monitor; + struct cec_adapter *cec_adap; }; int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk); int sun4i_tmds_create(struct sun4i_hdmi *hdmi); +int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi); #endif /* _SUN4I_HDMI_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c index f5d0d6bd1084..9ea6cd5a1370 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c @@ -29,8 +29,6 @@ #include "sun4i_hdmi.h" #include "sun4i_tcon.h" -#define DDC_SEGMENT_ADDR 0x30 - static inline struct sun4i_hdmi * drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) { @@ -184,93 +182,13 @@ static const struct drm_encoder_funcs sun4i_hdmi_funcs = { .destroy = drm_encoder_cleanup, }; -static int sun4i_hdmi_read_sub_block(struct sun4i_hdmi *hdmi, - unsigned int blk, unsigned int offset, - u8 *buf, unsigned int count) -{ - unsigned long reg; - int i; - - reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK; - writel(reg | SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ, - hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - - writel(SUN4I_HDMI_DDC_ADDR_SEGMENT(offset >> 8) | - SUN4I_HDMI_DDC_ADDR_EDDC(DDC_SEGMENT_ADDR << 1) | - SUN4I_HDMI_DDC_ADDR_OFFSET(offset) | - SUN4I_HDMI_DDC_ADDR_SLAVE(DDC_ADDR), - hdmi->base + SUN4I_HDMI_DDC_ADDR_REG); - - reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); - writel(reg | SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR, - hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); - - writel(count, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG); - writel(SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ, - hdmi->base + SUN4I_HDMI_DDC_CMD_REG); - - reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD, - hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - - if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg, - !(reg & SUN4I_HDMI_DDC_CTRL_START_CMD), - 100, 100000)) - return -EIO; - - for (i = 0; i < count; i++) - buf[i] = readb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG); - - return 0; -} - -static int sun4i_hdmi_read_edid_block(void *data, u8 *buf, unsigned int blk, - size_t length) -{ - struct sun4i_hdmi *hdmi = data; - int retry = 2, i; - - do { - for (i = 0; i < length; i += SUN4I_HDMI_DDC_FIFO_SIZE) { - unsigned char offset = blk * EDID_LENGTH + i; - unsigned int count = min((unsigned int)SUN4I_HDMI_DDC_FIFO_SIZE, - length - i); - int ret; - - ret = sun4i_hdmi_read_sub_block(hdmi, blk, offset, - buf + i, count); - if (ret) - return ret; - } - } while (!drm_edid_block_valid(buf, blk, true, NULL) && (retry--)); - - return 0; -} - static int sun4i_hdmi_get_modes(struct drm_connector *connector) { struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); - unsigned long reg; struct edid *edid; int ret; - /* Reset i2c controller */ - writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET, - hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg, - !(reg & SUN4I_HDMI_DDC_CTRL_RESET), - 100, 2000)) - return -EIO; - - writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE | - SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE, - hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG); - - clk_prepare_enable(hdmi->ddc_clk); - clk_set_rate(hdmi->ddc_clk, 100000); - - edid = drm_do_get_edid(connector, sun4i_hdmi_read_edid_block, hdmi); + edid = drm_get_edid(connector, hdmi->i2c); if (!edid) return 0; @@ -279,11 +197,10 @@ static int sun4i_hdmi_get_modes(struct drm_connector *connector) hdmi->hdmi_monitor ? "an HDMI" : "a DVI"); drm_mode_connector_update_edid_property(connector, edid); + cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); ret = drm_add_edid_modes(connector, edid); kfree(edid); - clk_disable_unprepare(hdmi->ddc_clk); - return ret; } @@ -299,8 +216,10 @@ sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, reg & SUN4I_HDMI_HPD_HIGH, - 0, 500000)) + 0, 500000)) { + cec_phys_addr_invalidate(hdmi->cec_adap); return connector_status_disconnected; + } return connector_status_connected; } @@ -314,6 +233,40 @@ static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, }; +#ifdef CONFIG_DRM_SUN4I_HDMI_CEC +static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) +{ + struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); + + return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; +} + +static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) +{ + struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); + + /* Start driving the CEC pin low */ + writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); +} + +static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) +{ + struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); + + /* + * Stop driving the CEC pin, the pull up will take over + * unless another CEC device is driving the pin low. + */ + writel(0, hdmi->base + SUN4I_HDMI_CEC); +} + +static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { + .read = sun4i_hdmi_cec_pin_read, + .low = sun4i_hdmi_cec_pin_low, + .high = sun4i_hdmi_cec_pin_high, +}; +#endif + static int sun4i_hdmi_bind(struct device *dev, struct device *master, void *data) { @@ -406,9 +359,9 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master, SUN4I_HDMI_PLL_CTRL_PLL_EN; writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); - ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk); + ret = sun4i_hdmi_i2c_create(dev, hdmi); if (ret) { - dev_err(dev, "Couldn't create the DDC clock\n"); + dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); return ret; } @@ -421,13 +374,26 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master, NULL); if (ret) { dev_err(dev, "Couldn't initialise the HDMI encoder\n"); - return ret; + goto err_del_i2c_adapter; } hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); - if (!hdmi->encoder.possible_crtcs) - return -EPROBE_DEFER; + if (!hdmi->encoder.possible_crtcs) { + ret = -EPROBE_DEFER; + goto err_del_i2c_adapter; + } + +#ifdef CONFIG_DRM_SUN4I_HDMI_CEC + hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, + hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS | + CEC_CAP_PASSTHROUGH | CEC_CAP_RC); + ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); + if (ret < 0) + goto err_cleanup_connector; + writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, + hdmi->base + SUN4I_HDMI_CEC); +#endif drm_connector_helper_add(&hdmi->connector, &sun4i_hdmi_connector_helper_funcs); @@ -444,12 +410,18 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master, hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; + ret = cec_register_adapter(hdmi->cec_adap, dev); + if (ret < 0) + goto err_cleanup_connector; drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); return 0; err_cleanup_connector: + cec_delete_adapter(hdmi->cec_adap); drm_encoder_cleanup(&hdmi->encoder); +err_del_i2c_adapter: + i2c_del_adapter(hdmi->i2c); return ret; } @@ -458,8 +430,10 @@ static void sun4i_hdmi_unbind(struct device *dev, struct device *master, { struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); + cec_unregister_adapter(hdmi->cec_adap); drm_connector_cleanup(&hdmi->connector); drm_encoder_cleanup(&hdmi->encoder); + i2c_del_adapter(hdmi->i2c); } static const struct component_ops sun4i_hdmi_ops = { diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file mode 100644 index 000000000000..2e42d09ab42e --- /dev/null +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * Copyright (C) 2017 Jonathan Liu <net147@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <linux/clk.h> +#include <linux/i2c.h> +#include <linux/iopoll.h> + +#include "sun4i_hdmi.h" + +#define SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ( \ + SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR \ +) + +/* FIFO request bit is set when FIFO level is above RX_THRESHOLD during read */ +#define RX_THRESHOLD SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX +/* FIFO request bit is set when FIFO level is below TX_THRESHOLD during write */ +#define TX_THRESHOLD 1 + +static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) +{ + /* + * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz + * clock. As clock rate is fixed, just round it up to 100 us. + */ + const unsigned long byte_time_ns = 100; + const u32 mask = SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK | + SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST | + SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE; + u32 reg; + + /* Limit transfer length by FIFO threshold */ + len = min_t(int, len, read ? (RX_THRESHOLD + 1) : + (SUN4I_HDMI_DDC_FIFO_SIZE - TX_THRESHOLD + 1)); + + /* Wait until error, FIFO request bit set or transfer complete */ + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG, reg, + reg & mask, len * byte_time_ns, 100000)) + return -ETIMEDOUT; + + if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) + return -EIO; + + if (read) + readsb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len); + else + writesb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len); + + /* Clear FIFO request bit */ + writel(SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST, + hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG); + + return len; +} + +static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg) +{ + int i, len; + u32 reg; + + /* Set FIFO direction */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK; + reg |= (msg->flags & I2C_M_RD) ? + SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ : + SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE; + writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + + /* Set I2C address */ + writel(SUN4I_HDMI_DDC_ADDR_SLAVE(msg->addr), + hdmi->base + SUN4I_HDMI_DDC_ADDR_REG); + + /* Set FIFO RX/TX thresholds and clear FIFO */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); + reg |= SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR; + reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK; + reg |= SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(RX_THRESHOLD); + reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK; + reg |= SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(TX_THRESHOLD); + writel(reg, hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG, + reg, + !(reg & SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR), + 100, 2000)) + return -EIO; + + /* Set transfer length */ + writel(msg->len, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG); + + /* Set command */ + writel(msg->flags & I2C_M_RD ? + SUN4I_HDMI_DDC_CMD_IMPLICIT_READ : + SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE, + hdmi->base + SUN4I_HDMI_DDC_CMD_REG); + + /* Clear interrupt status bits */ + writel(SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK | + SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST | + SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE, + hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG); + + /* Start command */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD, + hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + + /* Transfer bytes */ + for (i = 0; i < msg->len; i += len) { + len = fifo_transfer(hdmi, msg->buf + i, msg->len - i, + msg->flags & I2C_M_RD); + if (len <= 0) + return len; + } + + /* Wait for command to finish */ + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, + reg, + !(reg & SUN4I_HDMI_DDC_CTRL_START_CMD), + 100, 100000)) + return -EIO; + + /* Check for errors */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG); + if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) || + !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) { + return -EIO; + } + + return 0; +} + +static int sun4i_hdmi_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct sun4i_hdmi *hdmi = i2c_get_adapdata(adap); + u32 reg; + int err, i, ret = num; + + for (i = 0; i < num; i++) { + if (!msgs[i].len) + return -EINVAL; + if (msgs[i].len > SUN4I_HDMI_DDC_BYTE_COUNT_MAX) + return -EINVAL; + } + + /* Reset I2C controller */ + writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET, + hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg, + !(reg & SUN4I_HDMI_DDC_CTRL_RESET), + 100, 2000)) + return -EIO; + + writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE | + SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE, + hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG); + + clk_prepare_enable(hdmi->ddc_clk); + clk_set_rate(hdmi->ddc_clk, 100000); + + for (i = 0; i < num; i++) { + err = xfer_msg(hdmi, &msgs[i]); + if (err) { + ret = err; + break; + } + } + + clk_disable_unprepare(hdmi->ddc_clk); + return ret; +} + +static u32 sun4i_hdmi_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm sun4i_hdmi_i2c_algorithm = { + .master_xfer = sun4i_hdmi_i2c_xfer, + .functionality = sun4i_hdmi_i2c_func, +}; + +int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi) +{ + struct i2c_adapter *adap; + int ret = 0; + + ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk); + if (ret) + return ret; + + adap = devm_kzalloc(dev, sizeof(*adap), GFP_KERNEL); + if (!adap) + return -ENOMEM; + + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_DDC; + adap->algo = &sun4i_hdmi_i2c_algorithm; + strlcpy(adap->name, "sun4i_hdmi_i2c adapter", sizeof(adap->name)); + i2c_set_adapdata(adap, hdmi); + + ret = i2c_add_adapter(adap); + if (ret) + return ret; + + hdmi->i2c = adap; + + return ret; +} diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index d45f3a1a0a29..7bddf12548d3 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -25,12 +25,6 @@ struct sun4i_plane_desc { uint32_t nformats; }; -static int sun4i_backend_layer_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) -{ - return 0; -} - static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state) { @@ -52,8 +46,7 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane, sun4i_backend_layer_enable(backend, layer->id, true); } -static struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = { - .atomic_check = sun4i_backend_layer_atomic_check, +static const struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = { .atomic_disable = sun4i_backend_layer_atomic_disable, .atomic_update = sun4i_backend_layer_atomic_update, }; diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c index 42a238bbb899..7cd7090ad63a 100644 --- a/drivers/gpu/drm/sun4i/sun4i_rgb.c +++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c @@ -127,13 +127,6 @@ static const struct drm_connector_funcs sun4i_rgb_con_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, }; -static int sun4i_rgb_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - return 0; -} - static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder) { struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder); @@ -181,7 +174,6 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder, } static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = { - .atomic_check = sun4i_rgb_atomic_check, .mode_set = sun4i_rgb_encoder_mode_set, .disable = sun4i_rgb_encoder_disable, .enable = sun4i_rgb_encoder_enable, diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index 924c345820c0..5a219d1ccc26 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -197,8 +197,6 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel); void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable); /* Mode Related Controls */ -void sun4i_tcon_switch_interlace(struct sun4i_tcon *tcon, - bool enable); void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, struct drm_encoder *encoder); void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c index 4edf15e299ab..050cfd43c7a0 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tv.c +++ b/drivers/gpu/drm/sun4i/sun4i_tv.c @@ -341,13 +341,6 @@ static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode, mode->vtotal = mode->vsync_end + tv_mode->vback_porch; } -static int sun4i_tv_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - return 0; -} - static void sun4i_tv_disable(struct drm_encoder *encoder) { struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder); @@ -489,7 +482,6 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder, } static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = { - .atomic_check = sun4i_tv_atomic_check, .disable = sun4i_tv_disable, .enable = sun4i_tv_enable, .mode_set = sun4i_tv_mode_set, diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig index 2db29d67193d..dc58ab140151 100644 --- a/drivers/gpu/drm/tegra/Kconfig +++ b/drivers/gpu/drm/tegra/Kconfig @@ -3,6 +3,7 @@ config DRM_TEGRA depends on ARCH_TEGRA || (ARM && COMPILE_TEST) depends on COMMON_CLK depends on DRM + depends on OF select DRM_KMS_HELPER select DRM_MIPI_DSI select DRM_PANEL diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 6af3a9ad6565..8927784396e8 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -17,4 +17,6 @@ tegra-drm-y := \ falcon.o \ vic.o +tegra-drm-y += trace.o + obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index 2fde44c3a1b3..e4da041ba89b 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -25,6 +25,7 @@ #include "dpaux.h" #include "drm.h" +#include "trace.h" static DEFINE_MUTEX(dpaux_lock); static LIST_HEAD(dpaux_list); @@ -65,14 +66,19 @@ static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work) } static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, - unsigned long offset) + unsigned int offset) { - return readl(dpaux->regs + (offset << 2)); + u32 value = readl(dpaux->regs + (offset << 2)); + + trace_dpaux_readl(dpaux->dev, offset, value); + + return value; } static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, - u32 value, unsigned long offset) + u32 value, unsigned int offset) { + trace_dpaux_writel(dpaux->dev, offset, value); writel(value, dpaux->regs + (offset << 2)); } diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 224ce1dbb1cb..597d563d636a 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -306,8 +306,6 @@ host1x_bo_lookup(struct drm_file *file, u32 handle) if (!gem) return NULL; - drm_gem_object_unreference_unlocked(gem); - bo = to_tegra_bo(gem); return &bo->base; } @@ -396,8 +394,10 @@ int tegra_drm_submit(struct tegra_drm_context *context, (void __user *)(uintptr_t)args->waitchks; struct drm_tegra_syncpt syncpt; struct host1x *host1x = dev_get_drvdata(drm->dev->parent); + struct drm_gem_object **refs; struct host1x_syncpt *sp; struct host1x_job *job; + unsigned int num_refs; int err; /* We don't yet support other than one syncpt_incr struct per submit */ @@ -419,6 +419,21 @@ int tegra_drm_submit(struct tegra_drm_context *context, job->class = context->client->base.class; job->serialize = true; + /* + * Track referenced BOs so that they can be unreferenced after the + * submission is complete. + */ + num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks; + + refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); + if (!refs) { + err = -ENOMEM; + goto put; + } + + /* reuse as an iterator later */ + num_refs = 0; + while (num_cmdbufs) { struct drm_tegra_cmdbuf cmdbuf; struct host1x_bo *bo; @@ -447,6 +462,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); obj = host1x_to_tegra_bo(bo); + refs[num_refs++] = &obj->gem; /* * Gather buffer base address must be 4-bytes aligned, @@ -476,6 +492,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, reloc = &job->relocarray[num_relocs]; obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); + refs[num_refs++] = &obj->gem; /* * The unaligned cmdbuf offset will cause an unaligned write @@ -489,6 +506,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, } obj = host1x_to_tegra_bo(reloc->target.bo); + refs[num_refs++] = &obj->gem; if (reloc->target.offset >= obj->gem.size) { err = -EINVAL; @@ -508,6 +526,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, goto fail; obj = host1x_to_tegra_bo(wait->bo); + refs[num_refs++] = &obj->gem; /* * The unaligned offset will cause an unaligned write during @@ -547,17 +566,20 @@ int tegra_drm_submit(struct tegra_drm_context *context, goto fail; err = host1x_job_submit(job); - if (err) - goto fail_submit; + if (err) { + host1x_job_unpin(job); + goto fail; + } args->fence = job->syncpt_end; - host1x_job_put(job); - return 0; - -fail_submit: - host1x_job_unpin(job); fail: + while (num_refs--) + drm_gem_object_put_unlocked(refs[num_refs]); + + kfree(refs); + +put: host1x_job_put(job); return err; } @@ -593,7 +615,7 @@ static int tegra_gem_mmap(struct drm_device *drm, void *data, args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -860,7 +882,7 @@ static int tegra_gem_set_tiling(struct drm_device *drm, void *data, bo->tiling.mode = mode; bo->tiling.value = value; - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -900,7 +922,7 @@ static int tegra_gem_get_tiling(struct drm_device *drm, void *data, break; } - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return err; } @@ -925,7 +947,7 @@ static int tegra_gem_set_flags(struct drm_device *drm, void *data, if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) bo->flags |= TEGRA_BO_BOTTOM_UP; - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -947,7 +969,7 @@ static int tegra_gem_get_flags(struct drm_device *drm, void *data, if (bo->flags & TEGRA_BO_BOTTOM_UP) args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -955,20 +977,34 @@ static int tegra_gem_get_flags(struct drm_device *drm, void *data, static const struct drm_ioctl_desc tegra_drm_ioctls[] = { #ifdef CONFIG_DRM_TEGRA_STAGING - DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), - DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), - DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, + DRM_UNLOCKED | DRM_RENDER_ALLOW), #endif }; @@ -1035,9 +1071,11 @@ static int tegra_debugfs_iova(struct seq_file *s, void *data) struct tegra_drm *tegra = drm->dev_private; struct drm_printer p = drm_seq_file_printer(s); - mutex_lock(&tegra->mm_lock); - drm_mm_print(&tegra->mm, &p); - mutex_unlock(&tegra->mm_lock); + if (tegra->domain) { + mutex_lock(&tegra->mm_lock); + drm_mm_print(&tegra->mm, &p); + mutex_unlock(&tegra->mm_lock); + } return 0; } @@ -1057,7 +1095,7 @@ static int tegra_debugfs_init(struct drm_minor *minor) static struct drm_driver tegra_drm_driver = { .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | - DRIVER_ATOMIC, + DRIVER_ATOMIC | DRIVER_RENDER, .load = tegra_drm_load, .unload = tegra_drm_unload, .open = tegra_drm_open, diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 6d6da01282f3..063f5d397526 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -23,6 +23,7 @@ #include <drm/drm_fixed.h> #include "gem.h" +#include "trace.h" struct reset_control; @@ -172,14 +173,19 @@ static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) } static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, - unsigned long offset) + unsigned int offset) { + trace_dc_writel(dc->dev, offset, value); writel(value, dc->regs + (offset << 2)); } -static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned long offset) +static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) { - return readl(dc->regs + (offset << 2)); + u32 value = readl(dc->regs + (offset << 2)); + + trace_dc_readl(dc->dev, offset, value); + + return value; } struct tegra_dc_window { diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index e4b5aedfdbd4..046649ec9441 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -28,6 +28,7 @@ #include "drm.h" #include "dsi.h" #include "mipi-phy.h" +#include "trace.h" struct tegra_dsi_state { struct drm_connector_state base; @@ -105,15 +106,20 @@ static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) return to_dsi_state(dsi->output.connector.state); } -static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg) +static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) { - return readl(dsi->regs + (reg << 2)); + u32 value = readl(dsi->regs + (offset << 2)); + + trace_dsi_readl(dsi->dev, offset, value); + + return value; } static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, - unsigned long reg) + unsigned int offset) { - writel(value, dsi->regs + (reg << 2)); + trace_dsi_writel(dsi->dev, offset, value); + writel(value, dsi->regs + (offset << 2)); } static int tegra_dsi_show_regs(struct seq_file *s, void *data) diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 25acb73ee728..80540c1c66dc 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -88,7 +88,7 @@ static void tegra_fb_destroy(struct drm_framebuffer *framebuffer) if (bo->pages) vunmap(bo->vaddr); - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); } } @@ -195,7 +195,7 @@ struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, unreference: while (i--) - drm_gem_object_unreference_unlocked(&planes[i]->gem); + drm_gem_object_put_unlocked(&planes[i]->gem); return ERR_PTR(err); } @@ -242,7 +242,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper, info = drm_fb_helper_alloc_fbi(helper); if (IS_ERR(info)) { dev_err(drm->dev, "failed to allocate framebuffer info\n"); - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); return PTR_ERR(info); } @@ -251,7 +251,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper, err = PTR_ERR(fbdev->fb); dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n", err); - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); return PTR_ERR(fbdev->fb); } diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c index c6079affe642..ab1e53d434e8 100644 --- a/drivers/gpu/drm/tegra/gem.c +++ b/drivers/gpu/drm/tegra/gem.c @@ -24,7 +24,7 @@ static void tegra_bo_put(struct host1x_bo *bo) { struct tegra_bo *obj = host1x_to_tegra_bo(bo); - drm_gem_object_unreference_unlocked(&obj->gem); + drm_gem_object_put_unlocked(&obj->gem); } static dma_addr_t tegra_bo_pin(struct host1x_bo *bo, struct sg_table **sgt) @@ -95,7 +95,7 @@ static struct host1x_bo *tegra_bo_get(struct host1x_bo *bo) { struct tegra_bo *obj = host1x_to_tegra_bo(bo); - drm_gem_object_reference(&obj->gem); + drm_gem_object_get(&obj->gem); return bo; } @@ -325,7 +325,7 @@ struct tegra_bo *tegra_bo_create_with_handle(struct drm_file *file, return ERR_PTR(err); } - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); return bo; } @@ -460,30 +460,28 @@ const struct vm_operations_struct tegra_bo_vm_ops = { .close = drm_gem_vm_close, }; -int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma) +static int tegra_gem_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { - struct drm_gem_object *gem; - struct tegra_bo *bo; - int ret; - - ret = drm_gem_mmap(file, vma); - if (ret) - return ret; - - gem = vma->vm_private_data; - bo = to_tegra_bo(gem); + struct tegra_bo *bo = to_tegra_bo(gem); if (!bo->pages) { unsigned long vm_pgoff = vma->vm_pgoff; + int err; + /* + * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), + * and set the vm_pgoff (used as a fake buffer offset by DRM) + * to 0 as we want to map the whole buffer. + */ vma->vm_flags &= ~VM_PFNMAP; vma->vm_pgoff = 0; - ret = dma_mmap_wc(gem->dev->dev, vma, bo->vaddr, bo->paddr, + err = dma_mmap_wc(gem->dev->dev, vma, bo->vaddr, bo->paddr, gem->size); - if (ret) { + if (err < 0) { drm_gem_vm_close(vma); - return ret; + return err; } vma->vm_pgoff = vm_pgoff; @@ -499,6 +497,20 @@ int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma) return 0; } +int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct drm_gem_object *gem; + int err; + + err = drm_gem_mmap(file, vma); + if (err < 0) + return err; + + gem = vma->vm_private_data; + + return tegra_gem_mmap(gem, vma); +} + static struct sg_table * tegra_gem_prime_map_dma_buf(struct dma_buf_attachment *attach, enum dma_data_direction dir) @@ -582,7 +594,14 @@ static void tegra_gem_prime_kunmap(struct dma_buf *buf, unsigned long page, static int tegra_gem_prime_mmap(struct dma_buf *buf, struct vm_area_struct *vma) { - return -EINVAL; + struct drm_gem_object *gem = buf->priv; + int err; + + err = drm_gem_mmap_obj(gem, gem->size, vma); + if (err < 0) + return err; + + return tegra_gem_mmap(gem, vma); } static void *tegra_gem_prime_vmap(struct dma_buf *buf) @@ -633,7 +652,7 @@ struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm, struct drm_gem_object *gem = buf->priv; if (gem->dev == drm) { - drm_gem_object_reference(gem); + drm_gem_object_get(gem); return gem; } } diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index a621b0da4092..5b9d83b71943 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -24,6 +24,7 @@ #include "hdmi.h" #include "drm.h" #include "dc.h" +#include "trace.h" #define HDMI_ELD_BUFFER_SIZE 96 @@ -100,14 +101,19 @@ enum { }; static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, - unsigned long offset) + unsigned int offset) { - return readl(hdmi->regs + (offset << 2)); + u32 value = readl(hdmi->regs + (offset << 2)); + + trace_hdmi_readl(hdmi->dev, offset, value); + + return value; } static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, - unsigned long offset) + unsigned int offset) { + trace_hdmi_writel(hdmi->dev, offset, value); writel(value, hdmi->regs + (offset << 2)); } diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index e0642d05a8d3..7ab1d1dc7cd7 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -26,6 +26,7 @@ #include "dc.h" #include "drm.h" #include "sor.h" +#include "trace.h" #define SOR_REKEY 0x38 @@ -232,14 +233,19 @@ static inline struct tegra_sor *to_sor(struct tegra_output *output) return container_of(output, struct tegra_sor, output); } -static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) +static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) { - return readl(sor->regs + (offset << 2)); + u32 value = readl(sor->regs + (offset << 2)); + + trace_sor_readl(sor->dev, offset, value); + + return value; } static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, - unsigned long offset) + unsigned int offset) { + trace_sor_writel(sor->dev, offset, value); writel(value, sor->regs + (offset << 2)); } diff --git a/drivers/gpu/drm/tegra/trace.c b/drivers/gpu/drm/tegra/trace.c new file mode 100644 index 000000000000..006f65c72a34 --- /dev/null +++ b/drivers/gpu/drm/tegra/trace.c @@ -0,0 +1,2 @@ +#define CREATE_TRACE_POINTS +#include "trace.h" diff --git a/drivers/gpu/drm/tegra/trace.h b/drivers/gpu/drm/tegra/trace.h new file mode 100644 index 000000000000..5a1ab4046e92 --- /dev/null +++ b/drivers/gpu/drm/tegra/trace.h @@ -0,0 +1,68 @@ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM tegra + +#if !defined(DRM_TEGRA_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define DRM_TEGRA_TRACE_H 1 + +#include <linux/device.h> +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(register_access, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value), + TP_STRUCT__entry( + __field(struct device *, dev) + __field(unsigned int, offset) + __field(u32, value) + ), + TP_fast_assign( + __entry->dev = dev; + __entry->offset = offset; + __entry->value = value; + ), + TP_printk("%s %04x %08x", dev_name(__entry->dev), __entry->offset, + __entry->value) +); + +DEFINE_EVENT(register_access, dc_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, dc_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, hdmi_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, hdmi_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, dsi_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, dsi_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, dpaux_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, dpaux_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, sor_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, sor_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +#endif /* DRM_TEGRA_TRACE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/tegra +#define TRACE_INCLUDE_FILE trace +#include <trace/define_trace.h> diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index 47cb1aaa58b1..2448229fa653 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -258,12 +258,16 @@ static const struct tegra_drm_client_ops vic_ops = { .submit = tegra_drm_submit, }; +#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin" + static const struct vic_config vic_t124_config = { - .firmware = "nvidia/tegra124/vic03_ucode.bin", + .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, }; +#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" + static const struct vic_config vic_t210_config = { - .firmware = "nvidia/tegra210/vic04_ucode.bin", + .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, }; static const struct of_device_id vic_match[] = { @@ -394,3 +398,10 @@ struct platform_driver tegra_vic_driver = { .probe = vic_probe, .remove = vic_remove, }; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) +MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE); +#endif +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE); +#endif diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 22b57020790d..d79607a1187c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -70,6 +70,7 @@ static inline int ttm_mem_type_from_place(const struct ttm_place *place, static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type) { struct ttm_mem_type_manager *man = &bdev->man[mem_type]; + struct drm_printer p = drm_debug_printer(TTM_PFX); pr_err(" has_type: %d\n", man->has_type); pr_err(" use_type: %d\n", man->use_type); @@ -79,7 +80,7 @@ static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type) pr_err(" available_caching: 0x%08X\n", man->available_caching); pr_err(" default_caching: 0x%08X\n", man->default_caching); if (mem_type != TTM_PL_SYSTEM) - (*man->func->debug)(man, TTM_PFX); + (*man->func->debug)(man, &p); } static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, @@ -108,8 +109,8 @@ static ssize_t ttm_bo_global_show(struct kobject *kobj, struct ttm_bo_global *glob = container_of(kobj, struct ttm_bo_global, kobj); - return snprintf(buffer, PAGE_SIZE, "%lu\n", - (unsigned long) atomic_read(&glob->bo_count)); + return snprintf(buffer, PAGE_SIZE, "%d\n", + atomic_read(&glob->bo_count)); } static struct attribute *ttm_bo_global_attrs[] = { @@ -394,14 +395,33 @@ static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo) ww_mutex_unlock (&bo->resv->lock); } +static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) +{ + int r; + + if (bo->resv == &bo->ttm_resv) + return 0; + + reservation_object_init(&bo->ttm_resv); + BUG_ON(!reservation_object_trylock(&bo->ttm_resv)); + + r = reservation_object_copy_fences(&bo->ttm_resv, bo->resv); + if (r) { + reservation_object_unlock(&bo->ttm_resv); + reservation_object_fini(&bo->ttm_resv); + } + + return r; +} + static void ttm_bo_flush_all_fences(struct ttm_buffer_object *bo) { struct reservation_object_list *fobj; struct dma_fence *fence; int i; - fobj = reservation_object_get_list(bo->resv); - fence = reservation_object_get_excl(bo->resv); + fobj = reservation_object_get_list(&bo->ttm_resv); + fence = reservation_object_get_excl(&bo->ttm_resv); if (fence && !fence->ops->signaled) dma_fence_enable_sw_signaling(fence); @@ -420,18 +440,30 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) struct ttm_bo_global *glob = bo->glob; int ret; + ret = ttm_bo_individualize_resv(bo); + if (ret) { + /* Last resort, if we fail to allocate memory for the + * fences block for the BO to become idle + */ + reservation_object_wait_timeout_rcu(bo->resv, true, false, + 30 * HZ); + spin_lock(&glob->lru_lock); + goto error; + } + spin_lock(&glob->lru_lock); ret = __ttm_bo_reserve(bo, false, true, NULL); - if (!ret) { - if (!ttm_bo_wait(bo, false, true)) { + if (reservation_object_test_signaled_rcu(&bo->ttm_resv, true)) { ttm_bo_del_from_lru(bo); spin_unlock(&glob->lru_lock); + if (bo->resv != &bo->ttm_resv) + reservation_object_unlock(&bo->ttm_resv); ttm_bo_cleanup_memtype_use(bo); - return; - } else - ttm_bo_flush_all_fences(bo); + } + + ttm_bo_flush_all_fences(bo); /* * Make NO_EVICT bos immediately available to @@ -445,7 +477,10 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) __ttm_bo_unreserve(bo); } + if (bo->resv != &bo->ttm_resv) + reservation_object_unlock(&bo->ttm_resv); +error: kref_get(&bo->list_kref); list_add_tail(&bo->ddestroy, &bdev->ddestroy); spin_unlock(&glob->lru_lock); @@ -471,17 +506,25 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, bool no_wait_gpu) { struct ttm_bo_global *glob = bo->glob; + struct reservation_object *resv; int ret; - ret = ttm_bo_wait(bo, false, true); + if (unlikely(list_empty(&bo->ddestroy))) + resv = bo->resv; + else + resv = &bo->ttm_resv; + + if (reservation_object_test_signaled_rcu(resv, true)) + ret = 0; + else + ret = -EBUSY; if (ret && !no_wait_gpu) { long lret; ww_mutex_unlock(&bo->resv->lock); spin_unlock(&glob->lru_lock); - lret = reservation_object_wait_timeout_rcu(bo->resv, - true, + lret = reservation_object_wait_timeout_rcu(resv, true, interruptible, 30 * HZ); @@ -505,13 +548,6 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, spin_unlock(&glob->lru_lock); return 0; } - - /* - * remove sync_obj with ttm_bo_wait, the wait should be - * finished, and no new wait object should have been added. - */ - ret = ttm_bo_wait(bo, false, true); - WARN_ON(ret); } if (ret || unlikely(list_empty(&bo->ddestroy))) { @@ -521,6 +557,8 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, } ttm_bo_del_from_lru(bo); + if (!list_empty(&bo->ddestroy) && (bo->resv != &bo->ttm_resv)) + reservation_object_fini(&bo->ttm_resv); list_del_init(&bo->ddestroy); kref_put(&bo->list_kref, ttm_bo_ref_bug); diff --git a/drivers/gpu/drm/ttm/ttm_bo_manager.c b/drivers/gpu/drm/ttm/ttm_bo_manager.c index 90a6c0b03afc..a7c232dc39cb 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_manager.c +++ b/drivers/gpu/drm/ttm/ttm_bo_manager.c @@ -136,13 +136,12 @@ static int ttm_bo_man_takedown(struct ttm_mem_type_manager *man) } static void ttm_bo_man_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { struct ttm_range_manager *rman = (struct ttm_range_manager *) man->priv; - struct drm_printer p = drm_debug_printer(prefix); spin_lock(&rman->lock); - drm_mm_print(&rman->mm, &p); + drm_mm_print(&rman->mm, printer); spin_unlock(&rman->lock); } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index d0459b392e5e..78cb99be7146 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -469,6 +469,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, * TODO: Explicit member copy would probably be better here. */ + atomic_inc(&bo->glob->bo_count); INIT_LIST_HEAD(&fbo->ddestroy); INIT_LIST_HEAD(&fbo->lru); INIT_LIST_HEAD(&fbo->swap); @@ -586,7 +587,6 @@ int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long offset, size; int ret; - BUG_ON(!list_empty(&bo->swap)); map->virtual = NULL; map->bo = bo; if (num_pages > bo->num_pages) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index a01e5c90fd87..c8ebb757e36b 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -39,6 +39,7 @@ #include <linux/rbtree.h> #include <linux/module.h> #include <linux/uaccess.h> +#include <linux/mem_encrypt.h> #define TTM_BO_VM_NUM_PREFAULT 16 @@ -230,9 +231,11 @@ static int ttm_bo_vm_fault(struct vm_fault *vmf) * first page. */ for (i = 0; i < TTM_BO_VM_NUM_PREFAULT; ++i) { - if (bo->mem.bus.is_iomem) + if (bo->mem.bus.is_iomem) { + /* Iomem should not be marked encrypted */ + cvma.vm_page_prot = pgprot_decrypted(cvma.vm_page_prot); pfn = bdev->driver->io_mem_pfn(bo, page_offset); - else { + } else { page = ttm->pages[page_offset]; if (unlikely(!page && i == 0)) { retval = VM_FAULT_OOM; diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index eeddc1e48409..052e1f102113 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -615,7 +615,7 @@ static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool, } else { pr_err("Failed to fill pool (%p)\n", pool); /* If we have any pages left put them to the pool. */ - list_for_each_entry(p, &pool->list, lru) { + list_for_each_entry(p, &new_pages, lru) { ++cpages; } list_splice(&new_pages, &pool->list); @@ -920,6 +920,49 @@ void ttm_pool_unpopulate(struct ttm_tt *ttm) } EXPORT_SYMBOL(ttm_pool_unpopulate); +#if defined(CONFIG_SWIOTLB) || defined(CONFIG_INTEL_IOMMU) +int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt) +{ + unsigned i; + int r; + + r = ttm_pool_populate(&tt->ttm); + if (r) + return r; + + for (i = 0; i < tt->ttm.num_pages; i++) { + tt->dma_address[i] = dma_map_page(dev, tt->ttm.pages[i], + 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(dev, tt->dma_address[i])) { + while (i--) { + dma_unmap_page(dev, tt->dma_address[i], + PAGE_SIZE, DMA_BIDIRECTIONAL); + tt->dma_address[i] = 0; + } + ttm_pool_unpopulate(&tt->ttm); + return -EFAULT; + } + } + return 0; +} +EXPORT_SYMBOL(ttm_populate_and_map_pages); + +void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt) +{ + unsigned i; + + for (i = 0; i < tt->ttm.num_pages; i++) { + if (tt->dma_address[i]) { + dma_unmap_page(dev, tt->dma_address[i], + PAGE_SIZE, DMA_BIDIRECTIONAL); + } + } + ttm_pool_unpopulate(&tt->ttm); +} +EXPORT_SYMBOL(ttm_unmap_and_unpopulate_pages); +#endif + int ttm_page_alloc_debugfs(struct seq_file *m, void *data) { struct ttm_page_pool *p; diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c index 90ddbdca93bd..06bc14b55e66 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c @@ -60,22 +60,15 @@ #define NUM_PAGES_TO_ALLOC (PAGE_SIZE/sizeof(struct page *)) #define SMALL_ALLOCATION 4 #define FREE_ALL_PAGES (~0U) -/* times are in msecs */ -#define IS_UNDEFINED (0) -#define IS_WC (1<<1) -#define IS_UC (1<<2) -#define IS_CACHED (1<<3) -#define IS_DMA32 (1<<4) enum pool_type { - POOL_IS_UNDEFINED, - POOL_IS_WC = IS_WC, - POOL_IS_UC = IS_UC, - POOL_IS_CACHED = IS_CACHED, - POOL_IS_WC_DMA32 = IS_WC | IS_DMA32, - POOL_IS_UC_DMA32 = IS_UC | IS_DMA32, - POOL_IS_CACHED_DMA32 = IS_CACHED | IS_DMA32, + IS_UNDEFINED = 0, + IS_WC = 1 << 1, + IS_UC = 1 << 2, + IS_CACHED = 1 << 3, + IS_DMA32 = 1 << 4 }; + /* * The pool structure. There are usually six pools: * - generic (not restricted to DMA32): @@ -86,11 +79,9 @@ enum pool_type { * The other ones can be shrunk by the shrinker API if neccessary. * @pools: The 'struct device->dma_pools' link. * @type: Type of the pool - * @lock: Protects the inuse_list and free_list from concurrnet access. Must be + * @lock: Protects the free_list from concurrnet access. Must be * used with irqsave/irqrestore variants because pool allocator maybe called * from delayed work. - * @inuse_list: Pool of pages that are in use. The order is very important and - * it is in the order that the TTM pages that are put back are in. * @free_list: Pool of pages that are free to be used. No order requirements. * @dev: The device that is associated with these pools. * @size: Size used during DMA allocation. @@ -107,7 +98,6 @@ struct dma_pool { struct list_head pools; /* The 'struct device->dma_pools link */ enum pool_type type; spinlock_t lock; - struct list_head inuse_list; struct list_head free_list; struct device *dev; unsigned size; @@ -609,7 +599,6 @@ static struct dma_pool *ttm_dma_pool_init(struct device *dev, gfp_t flags, sec_pool->pool = pool; INIT_LIST_HEAD(&pool->free_list); - INIT_LIST_HEAD(&pool->inuse_list); INIT_LIST_HEAD(&pool->pools); spin_lock_init(&pool->lock); pool->dev = dev; @@ -882,22 +871,23 @@ int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev) struct dma_pool *pool; enum pool_type type; unsigned i; - gfp_t gfp_flags; int ret; if (ttm->state != tt_unpopulated) return 0; type = ttm_to_type(ttm->page_flags, ttm->caching_state); - if (ttm->page_flags & TTM_PAGE_FLAG_DMA32) - gfp_flags = GFP_USER | GFP_DMA32; - else - gfp_flags = GFP_HIGHUSER; - if (ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC) - gfp_flags |= __GFP_ZERO; - pool = ttm_dma_find_pool(dev, type); if (!pool) { + gfp_t gfp_flags; + + if (ttm->page_flags & TTM_PAGE_FLAG_DMA32) + gfp_flags = GFP_USER | GFP_DMA32; + else + gfp_flags = GFP_HIGHUSER; + if (ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC) + gfp_flags |= __GFP_ZERO; + pool = ttm_dma_pool_init(dev, gfp_flags, type); if (IS_ERR_OR_NULL(pool)) { return -ENOMEM; diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c index b7ca90db4e80..b5b335c9b2bb 100644 --- a/drivers/gpu/drm/udl/udl_fb.c +++ b/drivers/gpu/drm/udl/udl_fb.c @@ -14,6 +14,7 @@ #include <linux/slab.h> #include <linux/fb.h> #include <linux/dma-buf.h> +#include <linux/mem_encrypt.h> #include <drm/drmP.h> #include <drm/drm_crtc.h> @@ -169,6 +170,9 @@ static int udl_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) pr_notice("mmap() framebuffer addr:%lu size:%lu\n", pos, size); + /* We don't want the framebuffer to be mapped encrypted */ + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + while (size > 0) { page = vmalloc_to_pfn((void *)pos); if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED)) diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c index e695d74eaa9f..cd389c5eaef5 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ttm.c +++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c @@ -192,7 +192,7 @@ static int ttm_bo_man_takedown(struct ttm_mem_type_manager *man) } static void ttm_bo_man_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c index 86178796de6c..c706ad30411b 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c @@ -51,6 +51,7 @@ struct vmw_cmdbuf_context { struct list_head hw_submitted; struct list_head preempted; unsigned num_hw_submitted; + bool block_submission; }; /** @@ -60,6 +61,9 @@ struct vmw_cmdbuf_context { * kernel command submissions, @cur. * @space_mutex: Mutex to protect against starvation when we allocate * main pool buffer space. + * @error_mutex: Mutex to serialize the work queue error handling. + * Note this is not needed if the same workqueue handler + * can't race with itself... * @work: A struct work_struct implementeing command buffer error handling. * Immutable. * @dev_priv: Pointer to the device private struct. Immutable. @@ -85,7 +89,6 @@ struct vmw_cmdbuf_context { * Internal protection. * @dheaders: Pool of DMA memory for device command buffer headers with trailing * space for inline data. Internal protection. - * @tasklet: Tasklet struct for irq processing. Immutable. * @alloc_queue: Wait queue for processes waiting to allocate command buffer * space. * @idle_queue: Wait queue for processes waiting for command buffer idle. @@ -102,6 +105,7 @@ struct vmw_cmdbuf_context { struct vmw_cmdbuf_man { struct mutex cur_mutex; struct mutex space_mutex; + struct mutex error_mutex; struct work_struct work; struct vmw_private *dev_priv; struct vmw_cmdbuf_context ctx[SVGA_CB_CONTEXT_MAX]; @@ -117,7 +121,6 @@ struct vmw_cmdbuf_man { spinlock_t lock; struct dma_pool *headers; struct dma_pool *dheaders; - struct tasklet_struct tasklet; wait_queue_head_t alloc_queue; wait_queue_head_t idle_queue; bool irq_on; @@ -181,12 +184,13 @@ struct vmw_cmdbuf_alloc_info { }; /* Loop over each context in the command buffer manager. */ -#define for_each_cmdbuf_ctx(_man, _i, _ctx) \ +#define for_each_cmdbuf_ctx(_man, _i, _ctx) \ for (_i = 0, _ctx = &(_man)->ctx[0]; (_i) < SVGA_CB_CONTEXT_MAX; \ ++(_i), ++(_ctx)) -static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man, bool enable); - +static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man, u32 context, + bool enable); +static int vmw_cmdbuf_preempt(struct vmw_cmdbuf_man *man, u32 context); /** * vmw_cmdbuf_cur_lock - Helper to lock the cur_mutex. @@ -278,9 +282,9 @@ void vmw_cmdbuf_header_free(struct vmw_cmdbuf_header *header) vmw_cmdbuf_header_inline_free(header); return; } - spin_lock_bh(&man->lock); + spin_lock(&man->lock); __vmw_cmdbuf_header_free(header); - spin_unlock_bh(&man->lock); + spin_unlock(&man->lock); } @@ -331,7 +335,8 @@ static void vmw_cmdbuf_ctx_submit(struct vmw_cmdbuf_man *man, struct vmw_cmdbuf_context *ctx) { while (ctx->num_hw_submitted < man->max_hw_submitted && - !list_empty(&ctx->submitted)) { + !list_empty(&ctx->submitted) && + !ctx->block_submission) { struct vmw_cmdbuf_header *entry; SVGACBStatus status; @@ -386,12 +391,17 @@ static void vmw_cmdbuf_ctx_process(struct vmw_cmdbuf_man *man, __vmw_cmdbuf_header_free(entry); break; case SVGA_CB_STATUS_COMMAND_ERROR: - case SVGA_CB_STATUS_CB_HEADER_ERROR: + entry->cb_header->status = SVGA_CB_STATUS_NONE; list_add_tail(&entry->list, &man->error); schedule_work(&man->work); break; case SVGA_CB_STATUS_PREEMPTED: - list_add(&entry->list, &ctx->preempted); + entry->cb_header->status = SVGA_CB_STATUS_NONE; + list_add_tail(&entry->list, &ctx->preempted); + break; + case SVGA_CB_STATUS_CB_HEADER_ERROR: + WARN_ONCE(true, "Command buffer header error.\n"); + __vmw_cmdbuf_header_free(entry); break; default: WARN_ONCE(true, "Undefined command buffer status.\n"); @@ -468,20 +478,17 @@ static void vmw_cmdbuf_ctx_add(struct vmw_cmdbuf_man *man, } /** - * vmw_cmdbuf_man_tasklet - The main part of the command buffer interrupt - * handler implemented as a tasklet. + * vmw_cmdbuf_irqthread - The main part of the command buffer interrupt + * handler implemented as a threaded irq task. * - * @data: Tasklet closure. A pointer to the command buffer manager cast to - * an unsigned long. + * @man: Pointer to the command buffer manager. * - * The bottom half (tasklet) of the interrupt handler simply calls into the + * The bottom half of the interrupt handler simply calls into the * command buffer processor to free finished buffers and submit any * queued buffers to hardware. */ -static void vmw_cmdbuf_man_tasklet(unsigned long data) +void vmw_cmdbuf_irqthread(struct vmw_cmdbuf_man *man) { - struct vmw_cmdbuf_man *man = (struct vmw_cmdbuf_man *) data; - spin_lock(&man->lock); vmw_cmdbuf_man_process(man); spin_unlock(&man->lock); @@ -502,24 +509,112 @@ static void vmw_cmdbuf_work_func(struct work_struct *work) container_of(work, struct vmw_cmdbuf_man, work); struct vmw_cmdbuf_header *entry, *next; uint32_t dummy; - bool restart = false; + bool restart[SVGA_CB_CONTEXT_MAX]; + bool send_fence = false; + struct list_head restart_head[SVGA_CB_CONTEXT_MAX]; + int i; + struct vmw_cmdbuf_context *ctx; - spin_lock_bh(&man->lock); + for_each_cmdbuf_ctx(man, i, ctx) { + INIT_LIST_HEAD(&restart_head[i]); + restart[i] = false; + } + + mutex_lock(&man->error_mutex); + spin_lock(&man->lock); list_for_each_entry_safe(entry, next, &man->error, list) { - restart = true; - DRM_ERROR("Command buffer error.\n"); + SVGACBHeader *cb_hdr = entry->cb_header; + SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) + (entry->cmd + cb_hdr->errorOffset); + u32 error_cmd_size, new_start_offset; + const char *cmd_name; + + list_del_init(&entry->list); + restart[entry->cb_context] = true; + + if (!vmw_cmd_describe(header, &error_cmd_size, &cmd_name)) { + DRM_ERROR("Unknown command causing device error.\n"); + DRM_ERROR("Command buffer offset is %lu\n", + (unsigned long) cb_hdr->errorOffset); + __vmw_cmdbuf_header_free(entry); + send_fence = true; + continue; + } - list_del(&entry->list); - __vmw_cmdbuf_header_free(entry); - wake_up_all(&man->idle_queue); + DRM_ERROR("Command \"%s\" causing device error.\n", cmd_name); + DRM_ERROR("Command buffer offset is %lu\n", + (unsigned long) cb_hdr->errorOffset); + DRM_ERROR("Command size is %lu\n", + (unsigned long) error_cmd_size); + + new_start_offset = cb_hdr->errorOffset + error_cmd_size; + + if (new_start_offset >= cb_hdr->length) { + __vmw_cmdbuf_header_free(entry); + send_fence = true; + continue; + } + + if (man->using_mob) + cb_hdr->ptr.mob.mobOffset += new_start_offset; + else + cb_hdr->ptr.pa += (u64) new_start_offset; + + entry->cmd += new_start_offset; + cb_hdr->length -= new_start_offset; + cb_hdr->errorOffset = 0; + cb_hdr->offset = 0; + list_add_tail(&entry->list, &restart_head[entry->cb_context]); + man->ctx[entry->cb_context].block_submission = true; + } + spin_unlock(&man->lock); + + /* Preempt all contexts with errors */ + for_each_cmdbuf_ctx(man, i, ctx) { + if (ctx->block_submission && vmw_cmdbuf_preempt(man, i)) + DRM_ERROR("Failed preempting command buffer " + "context %u.\n", i); + } + + spin_lock(&man->lock); + for_each_cmdbuf_ctx(man, i, ctx) { + if (!ctx->block_submission) + continue; + + /* Move preempted command buffers to the preempted queue. */ + vmw_cmdbuf_ctx_process(man, ctx, &dummy); + + /* + * Add the preempted queue after the command buffer + * that caused an error. + */ + list_splice_init(&ctx->preempted, restart_head[i].prev); + + /* + * Finally add all command buffers first in the submitted + * queue, to rerun them. + */ + list_splice_init(&restart_head[i], &ctx->submitted); + + ctx->block_submission = false; } - spin_unlock_bh(&man->lock); - if (restart && vmw_cmdbuf_startstop(man, true)) - DRM_ERROR("Failed restarting command buffer context 0.\n"); + vmw_cmdbuf_man_process(man); + spin_unlock(&man->lock); + + for_each_cmdbuf_ctx(man, i, ctx) { + if (restart[i] && vmw_cmdbuf_startstop(man, i, true)) + DRM_ERROR("Failed restarting command buffer " + "context %u.\n", i); + } /* Send a new fence in case one was removed */ - vmw_fifo_send_fence(man->dev_priv, &dummy); + if (send_fence) { + vmw_fifo_send_fence(man->dev_priv, &dummy); + wake_up_all(&man->idle_queue); + } + + mutex_unlock(&man->error_mutex); } /** @@ -536,7 +631,7 @@ static bool vmw_cmdbuf_man_idle(struct vmw_cmdbuf_man *man, bool idle = false; int i; - spin_lock_bh(&man->lock); + spin_lock(&man->lock); vmw_cmdbuf_man_process(man); for_each_cmdbuf_ctx(man, i, ctx) { if (!list_empty(&ctx->submitted) || @@ -548,7 +643,7 @@ static bool vmw_cmdbuf_man_idle(struct vmw_cmdbuf_man *man, idle = list_empty(&man->error); out_unlock: - spin_unlock_bh(&man->lock); + spin_unlock(&man->lock); return idle; } @@ -571,7 +666,7 @@ static void __vmw_cmdbuf_cur_flush(struct vmw_cmdbuf_man *man) if (!cur) return; - spin_lock_bh(&man->lock); + spin_lock(&man->lock); if (man->cur_pos == 0) { __vmw_cmdbuf_header_free(cur); goto out_unlock; @@ -580,7 +675,7 @@ static void __vmw_cmdbuf_cur_flush(struct vmw_cmdbuf_man *man) man->cur->cb_header->length = man->cur_pos; vmw_cmdbuf_ctx_add(man, man->cur, SVGA_CB_CONTEXT_0); out_unlock: - spin_unlock_bh(&man->lock); + spin_unlock(&man->lock); man->cur = NULL; man->cur_pos = 0; } @@ -673,14 +768,14 @@ static bool vmw_cmdbuf_try_alloc(struct vmw_cmdbuf_man *man, return true; memset(info->node, 0, sizeof(*info->node)); - spin_lock_bh(&man->lock); + spin_lock(&man->lock); ret = drm_mm_insert_node(&man->mm, info->node, info->page_size); if (ret) { vmw_cmdbuf_man_process(man); ret = drm_mm_insert_node(&man->mm, info->node, info->page_size); } - spin_unlock_bh(&man->lock); + spin_unlock(&man->lock); info->done = !ret; return info->done; @@ -801,9 +896,9 @@ static int vmw_cmdbuf_space_pool(struct vmw_cmdbuf_man *man, return 0; out_no_cb_header: - spin_lock_bh(&man->lock); + spin_lock(&man->lock); drm_mm_remove_node(&header->node); - spin_unlock_bh(&man->lock); + spin_unlock(&man->lock); return ret; } @@ -1023,18 +1118,6 @@ void vmw_cmdbuf_commit(struct vmw_cmdbuf_man *man, size_t size, vmw_cmdbuf_cur_unlock(man); } -/** - * vmw_cmdbuf_tasklet_schedule - Schedule the interrupt handler bottom half. - * - * @man: The command buffer manager. - */ -void vmw_cmdbuf_tasklet_schedule(struct vmw_cmdbuf_man *man) -{ - if (!man) - return; - - tasklet_schedule(&man->tasklet); -} /** * vmw_cmdbuf_send_device_command - Send a command through the device context. @@ -1059,9 +1142,9 @@ static int vmw_cmdbuf_send_device_command(struct vmw_cmdbuf_man *man, memcpy(cmd, command, size); header->cb_header->length = size; header->cb_context = SVGA_CB_CONTEXT_DEVICE; - spin_lock_bh(&man->lock); + spin_lock(&man->lock); status = vmw_cmdbuf_header_submit(header); - spin_unlock_bh(&man->lock); + spin_unlock(&man->lock); vmw_cmdbuf_header_free(header); if (status != SVGA_CB_STATUS_COMPLETED) { @@ -1074,6 +1157,29 @@ static int vmw_cmdbuf_send_device_command(struct vmw_cmdbuf_man *man, } /** + * vmw_cmdbuf_preempt - Send a preempt command through the device + * context. + * + * @man: The command buffer manager. + * + * Synchronously sends a preempt command. + */ +static int vmw_cmdbuf_preempt(struct vmw_cmdbuf_man *man, u32 context) +{ + struct { + uint32 id; + SVGADCCmdPreempt body; + } __packed cmd; + + cmd.id = SVGA_DC_CMD_PREEMPT; + cmd.body.context = SVGA_CB_CONTEXT_0 + context; + cmd.body.ignoreIDZero = 0; + + return vmw_cmdbuf_send_device_command(man, &cmd, sizeof(cmd)); +} + + +/** * vmw_cmdbuf_startstop - Send a start / stop command through the device * context. * @@ -1082,7 +1188,7 @@ static int vmw_cmdbuf_send_device_command(struct vmw_cmdbuf_man *man, * * Synchronously sends a device start / stop context command. */ -static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man, +static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man, u32 context, bool enable) { struct { @@ -1092,7 +1198,7 @@ static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man, cmd.id = SVGA_DC_CMD_START_STOP_CONTEXT; cmd.body.enable = (enable) ? 1 : 0; - cmd.body.context = SVGA_CB_CONTEXT_0; + cmd.body.context = SVGA_CB_CONTEXT_0 + context; return vmw_cmdbuf_send_device_command(man, &cmd, sizeof(cmd)); } @@ -1191,7 +1297,7 @@ struct vmw_cmdbuf_man *vmw_cmdbuf_man_create(struct vmw_private *dev_priv) { struct vmw_cmdbuf_man *man; struct vmw_cmdbuf_context *ctx; - int i; + unsigned int i; int ret; if (!(dev_priv->capabilities & SVGA_CAP_COMMAND_BUFFERS)) @@ -1226,8 +1332,7 @@ struct vmw_cmdbuf_man *vmw_cmdbuf_man_create(struct vmw_private *dev_priv) spin_lock_init(&man->lock); mutex_init(&man->cur_mutex); mutex_init(&man->space_mutex); - tasklet_init(&man->tasklet, vmw_cmdbuf_man_tasklet, - (unsigned long) man); + mutex_init(&man->error_mutex); man->default_size = VMW_CMDBUF_INLINE_SIZE; init_waitqueue_head(&man->alloc_queue); init_waitqueue_head(&man->idle_queue); @@ -1236,11 +1341,14 @@ struct vmw_cmdbuf_man *vmw_cmdbuf_man_create(struct vmw_private *dev_priv) INIT_WORK(&man->work, &vmw_cmdbuf_work_func); vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ERROR, &dev_priv->error_waiters); - ret = vmw_cmdbuf_startstop(man, true); - if (ret) { - DRM_ERROR("Failed starting command buffer context 0.\n"); - vmw_cmdbuf_man_destroy(man); - return ERR_PTR(ret); + for_each_cmdbuf_ctx(man, i, ctx) { + ret = vmw_cmdbuf_startstop(man, i, true); + if (ret) { + DRM_ERROR("Failed starting command buffer " + "context %u.\n", i); + vmw_cmdbuf_man_destroy(man); + return ERR_PTR(ret); + } } return man; @@ -1290,18 +1398,24 @@ void vmw_cmdbuf_remove_pool(struct vmw_cmdbuf_man *man) */ void vmw_cmdbuf_man_destroy(struct vmw_cmdbuf_man *man) { + struct vmw_cmdbuf_context *ctx; + unsigned int i; + WARN_ON_ONCE(man->has_pool); (void) vmw_cmdbuf_idle(man, false, 10*HZ); - if (vmw_cmdbuf_startstop(man, false)) - DRM_ERROR("Failed stopping command buffer context 0.\n"); + + for_each_cmdbuf_ctx(man, i, ctx) + if (vmw_cmdbuf_startstop(man, i, false)) + DRM_ERROR("Failed stopping command buffer " + "context %u.\n", i); vmw_generic_waiter_remove(man->dev_priv, SVGA_IRQFLAG_ERROR, &man->dev_priv->error_waiters); - tasklet_kill(&man->tasklet); (void) cancel_work_sync(&man->work); dma_pool_destroy(man->dheaders); dma_pool_destroy(man->headers); mutex_destroy(&man->cur_mutex); mutex_destroy(&man->space_mutex); + mutex_destroy(&man->error_mutex); kfree(man); } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index 8be26509a9aa..e84fee3ec4f3 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c @@ -36,7 +36,6 @@ #include <drm/ttm/ttm_module.h> #include <linux/dma_remapping.h> -#define VMWGFX_DRIVER_NAME "vmwgfx" #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" #define VMWGFX_CHIP_SVGAII 0 #define VMW_FB_RESERVATION 0 @@ -825,7 +824,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) } if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { - ret = drm_irq_install(dev, dev->pdev->irq); + ret = vmw_irq_install(dev, dev->pdev->irq); if (ret != 0) { DRM_ERROR("Failed installing irq: %d\n", ret); goto out_no_irq; @@ -937,7 +936,7 @@ out_no_bdev: vmw_fence_manager_takedown(dev_priv->fman); out_no_fman: if (dev_priv->capabilities & SVGA_CAP_IRQMASK) - drm_irq_uninstall(dev_priv->dev); + vmw_irq_uninstall(dev_priv->dev); out_no_irq: if (dev_priv->stealth) pci_release_region(dev->pdev, 2); @@ -990,7 +989,7 @@ static void vmw_driver_unload(struct drm_device *dev) vmw_release_device_late(dev_priv); vmw_fence_manager_takedown(dev_priv->fman); if (dev_priv->capabilities & SVGA_CAP_IRQMASK) - drm_irq_uninstall(dev_priv->dev); + vmw_irq_uninstall(dev_priv->dev); if (dev_priv->stealth) pci_release_region(dev->pdev, 2); else @@ -1516,10 +1515,6 @@ static struct drm_driver driver = { .load = vmw_driver_load, .unload = vmw_driver_unload, .lastclose = vmw_lastclose, - .irq_preinstall = vmw_irq_preinstall, - .irq_postinstall = vmw_irq_postinstall, - .irq_uninstall = vmw_irq_uninstall, - .irq_handler = vmw_irq_handler, .get_vblank_counter = vmw_get_vblank_counter, .enable_vblank = vmw_enable_vblank, .disable_vblank = vmw_disable_vblank, diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index 4b948fba9eec..7e5f30e234b1 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h @@ -40,10 +40,12 @@ #include <drm/ttm/ttm_execbuf_util.h> #include <drm/ttm/ttm_module.h> #include "vmwgfx_fence.h" +#include <linux/sync_file.h> -#define VMWGFX_DRIVER_DATE "20170607" +#define VMWGFX_DRIVER_NAME "vmwgfx" +#define VMWGFX_DRIVER_DATE "20170612" #define VMWGFX_DRIVER_MAJOR 2 -#define VMWGFX_DRIVER_MINOR 13 +#define VMWGFX_DRIVER_MINOR 14 #define VMWGFX_DRIVER_PATCHLEVEL 0 #define VMWGFX_FILE_PAGE_OFFSET 0x00100000 #define VMWGFX_FIFO_STATIC_SIZE (1024*1024) @@ -351,6 +353,12 @@ struct vmw_otable_batch { struct ttm_buffer_object *otable_bo; }; +enum { + VMW_IRQTHREAD_FENCE, + VMW_IRQTHREAD_CMDBUF, + VMW_IRQTHREAD_MAX +}; + struct vmw_private { struct ttm_bo_device bdev; struct ttm_bo_global_ref bo_global_ref; @@ -529,6 +537,7 @@ struct vmw_private { struct vmw_otable_batch otable_batch; struct vmw_cmdbuf_man *cman; + DECLARE_BITMAP(irqthread_pending, VMW_IRQTHREAD_MAX); }; static inline struct vmw_surface *vmw_res_to_srf(struct vmw_resource *res) @@ -561,24 +570,21 @@ static inline struct vmw_master *vmw_master(struct drm_master *master) static inline void vmw_write(struct vmw_private *dev_priv, unsigned int offset, uint32_t value) { - unsigned long irq_flags; - - spin_lock_irqsave(&dev_priv->hw_lock, irq_flags); + spin_lock(&dev_priv->hw_lock); outl(offset, dev_priv->io_start + VMWGFX_INDEX_PORT); outl(value, dev_priv->io_start + VMWGFX_VALUE_PORT); - spin_unlock_irqrestore(&dev_priv->hw_lock, irq_flags); + spin_unlock(&dev_priv->hw_lock); } static inline uint32_t vmw_read(struct vmw_private *dev_priv, unsigned int offset) { - unsigned long irq_flags; u32 val; - spin_lock_irqsave(&dev_priv->hw_lock, irq_flags); + spin_lock(&dev_priv->hw_lock); outl(offset, dev_priv->io_start + VMWGFX_INDEX_PORT); val = inl(dev_priv->io_start + VMWGFX_VALUE_PORT); - spin_unlock_irqrestore(&dev_priv->hw_lock, irq_flags); + spin_unlock(&dev_priv->hw_lock); return val; } @@ -821,7 +827,8 @@ extern int vmw_execbuf_process(struct drm_file *file_priv, uint32_t dx_context_handle, struct drm_vmw_fence_rep __user *user_fence_rep, - struct vmw_fence_obj **out_fence); + struct vmw_fence_obj **out_fence, + uint32_t flags); extern void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv, struct vmw_fence_obj *fence); extern void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv); @@ -836,23 +843,23 @@ extern void vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, struct drm_vmw_fence_rep __user *user_fence_rep, struct vmw_fence_obj *fence, - uint32_t fence_handle); + uint32_t fence_handle, + int32_t out_fence_fd, + struct sync_file *sync_file); extern int vmw_validate_single_buffer(struct vmw_private *dev_priv, struct ttm_buffer_object *bo, bool interruptible, bool validate_as_mob); - +bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd); /** * IRQs and wating - vmwgfx_irq.c */ -extern irqreturn_t vmw_irq_handler(int irq, void *arg); extern int vmw_wait_seqno(struct vmw_private *dev_priv, bool lazy, uint32_t seqno, bool interruptible, unsigned long timeout); -extern void vmw_irq_preinstall(struct drm_device *dev); -extern int vmw_irq_postinstall(struct drm_device *dev); +extern int vmw_irq_install(struct drm_device *dev, int irq); extern void vmw_irq_uninstall(struct drm_device *dev); extern bool vmw_seqno_passed(struct vmw_private *dev_priv, uint32_t seqno); @@ -1150,13 +1157,13 @@ extern void *vmw_cmdbuf_reserve(struct vmw_cmdbuf_man *man, size_t size, extern void vmw_cmdbuf_commit(struct vmw_cmdbuf_man *man, size_t size, struct vmw_cmdbuf_header *header, bool flush); -extern void vmw_cmdbuf_tasklet_schedule(struct vmw_cmdbuf_man *man); extern void *vmw_cmdbuf_alloc(struct vmw_cmdbuf_man *man, size_t size, bool interruptible, struct vmw_cmdbuf_header **p_header); extern void vmw_cmdbuf_header_free(struct vmw_cmdbuf_header *header); extern int vmw_cmdbuf_cur_flush(struct vmw_cmdbuf_man *man, bool interruptible); +extern void vmw_cmdbuf_irqthread(struct vmw_cmdbuf_man *man); /** diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index 2cfb3c93f42a..21c62a34e558 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c @@ -24,6 +24,7 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. * **************************************************************************/ +#include <linux/sync_file.h> #include "vmwgfx_drv.h" #include "vmwgfx_reg.h" @@ -112,11 +113,12 @@ struct vmw_cmd_entry { bool user_allow; bool gb_disable; bool gb_enable; + const char *cmd_name; }; #define VMW_CMD_DEF(_cmd, _func, _user_allow, _gb_disable, _gb_enable) \ [(_cmd) - SVGA_3D_CMD_BASE] = {(_func), (_user_allow),\ - (_gb_disable), (_gb_enable)} + (_gb_disable), (_gb_enable), #_cmd} static int vmw_resource_context_res_add(struct vmw_private *dev_priv, struct vmw_sw_context *sw_context, @@ -3302,6 +3304,8 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = { true, false, true), VMW_CMD_DEF(SVGA_3D_CMD_NOP, &vmw_cmd_ok, true, false, true), + VMW_CMD_DEF(SVGA_3D_CMD_NOP_ERROR, &vmw_cmd_ok, + true, false, true), VMW_CMD_DEF(SVGA_3D_CMD_ENABLE_GART, &vmw_cmd_invalid, false, false, true), VMW_CMD_DEF(SVGA_3D_CMD_DISABLE_GART, &vmw_cmd_invalid, @@ -3469,6 +3473,51 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = { true, false, true), }; +bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd) +{ + u32 cmd_id = ((u32 *) buf)[0]; + + if (cmd_id >= SVGA_CMD_MAX) { + SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf; + const struct vmw_cmd_entry *entry; + + *size = header->size + sizeof(SVGA3dCmdHeader); + cmd_id = header->id; + if (cmd_id >= SVGA_3D_CMD_MAX) + return false; + + cmd_id -= SVGA_3D_CMD_BASE; + entry = &vmw_cmd_entries[cmd_id]; + *cmd = entry->cmd_name; + return true; + } + + switch (cmd_id) { + case SVGA_CMD_UPDATE: + *cmd = "SVGA_CMD_UPDATE"; + *size = sizeof(u32) + sizeof(SVGAFifoCmdUpdate); + break; + case SVGA_CMD_DEFINE_GMRFB: + *cmd = "SVGA_CMD_DEFINE_GMRFB"; + *size = sizeof(u32) + sizeof(SVGAFifoCmdDefineGMRFB); + break; + case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: + *cmd = "SVGA_CMD_BLIT_GMRFB_TO_SCREEN"; + *size = sizeof(u32) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); + break; + case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: + *cmd = "SVGA_CMD_BLIT_SCREEN_TO_GMRFB"; + *size = sizeof(u32) + sizeof(SVGAFifoCmdBlitGMRFBToScreen); + break; + default: + *cmd = "UNKNOWN"; + *size = 0; + return false; + } + + return true; +} + static int vmw_cmd_check(struct vmw_private *dev_priv, struct vmw_sw_context *sw_context, void *buf, uint32_t *size) @@ -3781,6 +3830,8 @@ int vmw_execbuf_fence_commands(struct drm_file *file_priv, * which the information should be copied. * @fence: Pointer to the fenc object. * @fence_handle: User-space fence handle. + * @out_fence_fd: exported file descriptor for the fence. -1 if not used + * @sync_file: Only used to clean up in case of an error in this function. * * This function copies fence information to user-space. If copying fails, * The user-space struct drm_vmw_fence_rep::error member is hopefully @@ -3796,7 +3847,9 @@ vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, int ret, struct drm_vmw_fence_rep __user *user_fence_rep, struct vmw_fence_obj *fence, - uint32_t fence_handle) + uint32_t fence_handle, + int32_t out_fence_fd, + struct sync_file *sync_file) { struct drm_vmw_fence_rep fence_rep; @@ -3806,6 +3859,7 @@ vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, memset(&fence_rep, 0, sizeof(fence_rep)); fence_rep.error = ret; + fence_rep.fd = out_fence_fd; if (ret == 0) { BUG_ON(fence == NULL); @@ -3828,6 +3882,14 @@ vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, * and unreference the handle. */ if (unlikely(ret != 0) && (fence_rep.error == 0)) { + if (sync_file) + fput(sync_file->file); + + if (fence_rep.fd != -1) { + put_unused_fd(fence_rep.fd); + fence_rep.fd = -1; + } + ttm_ref_object_base_unref(vmw_fp->tfile, fence_handle, TTM_REF_USAGE); DRM_ERROR("Fence copy error. Syncing.\n"); @@ -4003,7 +4065,8 @@ int vmw_execbuf_process(struct drm_file *file_priv, uint64_t throttle_us, uint32_t dx_context_handle, struct drm_vmw_fence_rep __user *user_fence_rep, - struct vmw_fence_obj **out_fence) + struct vmw_fence_obj **out_fence, + uint32_t flags) { struct vmw_sw_context *sw_context = &dev_priv->ctx; struct vmw_fence_obj *fence = NULL; @@ -4013,20 +4076,33 @@ int vmw_execbuf_process(struct drm_file *file_priv, struct ww_acquire_ctx ticket; uint32_t handle; int ret; + int32_t out_fence_fd = -1; + struct sync_file *sync_file = NULL; + + + if (flags & DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD) { + out_fence_fd = get_unused_fd_flags(O_CLOEXEC); + if (out_fence_fd < 0) { + DRM_ERROR("Failed to get a fence file descriptor.\n"); + return out_fence_fd; + } + } if (throttle_us) { ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue, throttle_us); if (ret) - return ret; + goto out_free_fence_fd; } kernel_commands = vmw_execbuf_cmdbuf(dev_priv, user_commands, kernel_commands, command_size, &header); - if (IS_ERR(kernel_commands)) - return PTR_ERR(kernel_commands); + if (IS_ERR(kernel_commands)) { + ret = PTR_ERR(kernel_commands); + goto out_free_fence_fd; + } ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex); if (ret) { @@ -4162,8 +4238,32 @@ int vmw_execbuf_process(struct drm_file *file_priv, __vmw_execbuf_release_pinned_bo(dev_priv, fence); vmw_clear_validations(sw_context); + + /* + * If anything fails here, give up trying to export the fence + * and do a sync since the user mode will not be able to sync + * the fence itself. This ensures we are still functionally + * correct. + */ + if (flags & DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD) { + + sync_file = sync_file_create(&fence->base); + if (!sync_file) { + DRM_ERROR("Unable to create sync file for fence\n"); + put_unused_fd(out_fence_fd); + out_fence_fd = -1; + + (void) vmw_fence_obj_wait(fence, false, false, + VMW_FENCE_WAIT_TIMEOUT); + } else { + /* Link the fence with the FD created earlier */ + fd_install(out_fence_fd, sync_file->file); + } + } + vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret, - user_fence_rep, fence, handle); + user_fence_rep, fence, handle, + out_fence_fd, sync_file); /* Don't unreference when handing fence out */ if (unlikely(out_fence != NULL)) { @@ -4214,6 +4314,9 @@ out_unlock: out_free_header: if (header) vmw_cmdbuf_header_free(header); +out_free_fence_fd: + if (out_fence_fd >= 0) + put_unused_fd(out_fence_fd); return ret; } @@ -4366,6 +4469,7 @@ int vmw_execbuf_ioctl(struct drm_device *dev, unsigned long data, static const size_t copy_offset[] = { offsetof(struct drm_vmw_execbuf_arg, context_handle), sizeof(struct drm_vmw_execbuf_arg)}; + struct dma_fence *in_fence = NULL; if (unlikely(size < copy_offset[0])) { DRM_ERROR("Invalid command size, ioctl %d\n", @@ -4401,15 +4505,25 @@ int vmw_execbuf_ioctl(struct drm_device *dev, unsigned long data, arg.context_handle = (uint32_t) -1; break; case 2: - if (arg.pad64 != 0) { - DRM_ERROR("Unused IOCTL data not set to zero.\n"); - return -EINVAL; - } - break; default: break; } + + /* If imported a fence FD from elsewhere, then wait on it */ + if (arg.flags & DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD) { + in_fence = sync_file_get_fence(arg.imported_fence_fd); + + if (!in_fence) { + DRM_ERROR("Cannot get imported fence\n"); + return -EINVAL; + } + + ret = vmw_wait_dma_fence(dev_priv->fman, in_fence); + if (ret) + goto out; + } + ret = ttm_read_lock(&dev_priv->reservation_sem, true); if (unlikely(ret != 0)) return ret; @@ -4419,12 +4533,16 @@ int vmw_execbuf_ioctl(struct drm_device *dev, unsigned long data, NULL, arg.command_size, arg.throttle_us, arg.context_handle, (void __user *)(unsigned long)arg.fence_rep, - NULL); + NULL, + arg.flags); ttm_read_unlock(&dev_priv->reservation_sem); if (unlikely(ret != 0)) - return ret; + goto out; vmw_kms_cursor_post_execbuf(dev_priv); - return 0; +out: + if (in_fence) + dma_fence_put(in_fence); + return ret; } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c index b8bc5bc7de7e..3bbad22b3748 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c @@ -114,12 +114,11 @@ static void vmw_fence_obj_destroy(struct dma_fence *f) container_of(f, struct vmw_fence_obj, base); struct vmw_fence_manager *fman = fman_from_fence(fence); - unsigned long irq_flags; - spin_lock_irqsave(&fman->lock, irq_flags); + spin_lock(&fman->lock); list_del_init(&fence->head); --fman->num_fence_objects; - spin_unlock_irqrestore(&fman->lock, irq_flags); + spin_unlock(&fman->lock); fence->destroy(fence); } @@ -252,10 +251,10 @@ static void vmw_fence_work_func(struct work_struct *work) INIT_LIST_HEAD(&list); mutex_lock(&fman->goal_irq_mutex); - spin_lock_irq(&fman->lock); + spin_lock(&fman->lock); list_splice_init(&fman->cleanup_list, &list); seqno_valid = fman->seqno_valid; - spin_unlock_irq(&fman->lock); + spin_unlock(&fman->lock); if (!seqno_valid && fman->goal_irq_on) { fman->goal_irq_on = false; @@ -305,15 +304,14 @@ struct vmw_fence_manager *vmw_fence_manager_init(struct vmw_private *dev_priv) void vmw_fence_manager_takedown(struct vmw_fence_manager *fman) { - unsigned long irq_flags; bool lists_empty; (void) cancel_work_sync(&fman->work); - spin_lock_irqsave(&fman->lock, irq_flags); + spin_lock(&fman->lock); lists_empty = list_empty(&fman->fence_list) && list_empty(&fman->cleanup_list); - spin_unlock_irqrestore(&fman->lock, irq_flags); + spin_unlock(&fman->lock); BUG_ON(!lists_empty); kfree(fman); @@ -323,7 +321,6 @@ static int vmw_fence_obj_init(struct vmw_fence_manager *fman, struct vmw_fence_obj *fence, u32 seqno, void (*destroy) (struct vmw_fence_obj *fence)) { - unsigned long irq_flags; int ret = 0; dma_fence_init(&fence->base, &vmw_fence_ops, &fman->lock, @@ -331,7 +328,7 @@ static int vmw_fence_obj_init(struct vmw_fence_manager *fman, INIT_LIST_HEAD(&fence->seq_passed_actions); fence->destroy = destroy; - spin_lock_irqsave(&fman->lock, irq_flags); + spin_lock(&fman->lock); if (unlikely(fman->fifo_down)) { ret = -EBUSY; goto out_unlock; @@ -340,7 +337,7 @@ static int vmw_fence_obj_init(struct vmw_fence_manager *fman, ++fman->num_fence_objects; out_unlock: - spin_unlock_irqrestore(&fman->lock, irq_flags); + spin_unlock(&fman->lock); return ret; } @@ -489,11 +486,9 @@ rerun: void vmw_fences_update(struct vmw_fence_manager *fman) { - unsigned long irq_flags; - - spin_lock_irqsave(&fman->lock, irq_flags); + spin_lock(&fman->lock); __vmw_fences_update(fman); - spin_unlock_irqrestore(&fman->lock, irq_flags); + spin_unlock(&fman->lock); } bool vmw_fence_obj_signaled(struct vmw_fence_obj *fence) @@ -650,6 +645,51 @@ out_no_object: /** + * vmw_wait_dma_fence - Wait for a dma fence + * + * @fman: pointer to a fence manager + * @fence: DMA fence to wait on + * + * This function handles the case when the fence is actually a fence + * array. If that's the case, it'll wait on each of the child fence + */ +int vmw_wait_dma_fence(struct vmw_fence_manager *fman, + struct dma_fence *fence) +{ + struct dma_fence_array *fence_array; + int ret = 0; + int i; + + + if (dma_fence_is_signaled(fence)) + return 0; + + if (!dma_fence_is_array(fence)) + return dma_fence_wait(fence, true); + + /* From i915: Note that if the fence-array was created in + * signal-on-any mode, we should *not* decompose it into its individual + * fences. However, we don't currently store which mode the fence-array + * is operating in. Fortunately, the only user of signal-on-any is + * private to amdgpu and we should not see any incoming fence-array + * from sync-file being in signal-on-any mode. + */ + + fence_array = to_dma_fence_array(fence); + for (i = 0; i < fence_array->num_fences; i++) { + struct dma_fence *child = fence_array->fences[i]; + + ret = dma_fence_wait(child, true); + + if (ret < 0) + return ret; + } + + return 0; +} + + +/** * vmw_fence_fifo_down - signal all unsignaled fence objects. */ @@ -663,14 +703,14 @@ void vmw_fence_fifo_down(struct vmw_fence_manager *fman) * restart when we've released the fman->lock. */ - spin_lock_irq(&fman->lock); + spin_lock(&fman->lock); fman->fifo_down = true; while (!list_empty(&fman->fence_list)) { struct vmw_fence_obj *fence = list_entry(fman->fence_list.prev, struct vmw_fence_obj, head); dma_fence_get(&fence->base); - spin_unlock_irq(&fman->lock); + spin_unlock(&fman->lock); ret = vmw_fence_obj_wait(fence, false, false, VMW_FENCE_WAIT_TIMEOUT); @@ -686,18 +726,16 @@ void vmw_fence_fifo_down(struct vmw_fence_manager *fman) BUG_ON(!list_empty(&fence->head)); dma_fence_put(&fence->base); - spin_lock_irq(&fman->lock); + spin_lock(&fman->lock); } - spin_unlock_irq(&fman->lock); + spin_unlock(&fman->lock); } void vmw_fence_fifo_up(struct vmw_fence_manager *fman) { - unsigned long irq_flags; - - spin_lock_irqsave(&fman->lock, irq_flags); + spin_lock(&fman->lock); fman->fifo_down = false; - spin_unlock_irqrestore(&fman->lock, irq_flags); + spin_unlock(&fman->lock); } @@ -812,9 +850,9 @@ int vmw_fence_obj_signaled_ioctl(struct drm_device *dev, void *data, arg->signaled = vmw_fence_obj_signaled(fence); arg->signaled_flags = arg->flags; - spin_lock_irq(&fman->lock); + spin_lock(&fman->lock); arg->passed_seqno = dev_priv->last_read_seqno; - spin_unlock_irq(&fman->lock); + spin_unlock(&fman->lock); ttm_base_object_unref(&base); @@ -841,8 +879,7 @@ int vmw_fence_obj_unref_ioctl(struct drm_device *dev, void *data, * * This function is called when the seqno of the fence where @action is * attached has passed. It queues the event on the submitter's event list. - * This function is always called from atomic context, and may be called - * from irq context. + * This function is always called from atomic context. */ static void vmw_event_fence_action_seq_passed(struct vmw_fence_action *action) { @@ -851,13 +888,13 @@ static void vmw_event_fence_action_seq_passed(struct vmw_fence_action *action) struct drm_device *dev = eaction->dev; struct drm_pending_event *event = eaction->event; struct drm_file *file_priv; - unsigned long irq_flags; + if (unlikely(event == NULL)) return; file_priv = event->file_priv; - spin_lock_irqsave(&dev->event_lock, irq_flags); + spin_lock_irq(&dev->event_lock); if (likely(eaction->tv_sec != NULL)) { struct timeval tv; @@ -869,7 +906,7 @@ static void vmw_event_fence_action_seq_passed(struct vmw_fence_action *action) drm_send_event_locked(dev, eaction->event); eaction->event = NULL; - spin_unlock_irqrestore(&dev->event_lock, irq_flags); + spin_unlock_irq(&dev->event_lock); } /** @@ -904,11 +941,10 @@ static void vmw_fence_obj_add_action(struct vmw_fence_obj *fence, struct vmw_fence_action *action) { struct vmw_fence_manager *fman = fman_from_fence(fence); - unsigned long irq_flags; bool run_update = false; mutex_lock(&fman->goal_irq_mutex); - spin_lock_irqsave(&fman->lock, irq_flags); + spin_lock(&fman->lock); fman->pending_actions[action->type]++; if (dma_fence_is_signaled_locked(&fence->base)) { @@ -927,7 +963,7 @@ static void vmw_fence_obj_add_action(struct vmw_fence_obj *fence, run_update = vmw_fence_goal_check_locked(fence); } - spin_unlock_irqrestore(&fman->lock, irq_flags); + spin_unlock(&fman->lock); if (run_update) { if (!fman->goal_irq_on) { @@ -1114,7 +1150,7 @@ int vmw_fence_event_ioctl(struct drm_device *dev, void *data, } vmw_execbuf_copy_fence_user(dev_priv, vmw_fp, 0, user_fence_rep, fence, - handle); + handle, -1, NULL); vmw_fence_obj_unreference(&fence); return 0; out_no_create: diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h index d9d85aa6ed20..20224dba9d8e 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h @@ -28,6 +28,7 @@ #ifndef _VMWGFX_FENCE_H_ #include <linux/dma-fence.h> +#include <linux/dma-fence-array.h> #define VMW_FENCE_WAIT_TIMEOUT (5*HZ) @@ -102,6 +103,9 @@ extern int vmw_user_fence_create(struct drm_file *file_priv, struct vmw_fence_obj **p_fence, uint32_t *p_handle); +extern int vmw_wait_dma_fence(struct vmw_fence_manager *fman, + struct dma_fence *fence); + extern void vmw_fence_fifo_up(struct vmw_fence_manager *fman); extern void vmw_fence_fifo_down(struct vmw_fence_manager *fman); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c b/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c index d2b03d4a3c86..f2f9d88131f2 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c @@ -157,9 +157,9 @@ static int vmw_gmrid_man_takedown(struct ttm_mem_type_manager *man) } static void vmw_gmrid_man_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { - pr_info("%s: No debug info available for the GMR id manager\n", prefix); + drm_printf(printer, "No debug info available for the GMR id manager\n"); } const struct ttm_mem_type_manager_func vmw_gmrid_manager_func = { diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c index 0c7e1723292c..b9239ba067c4 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c @@ -30,11 +30,56 @@ #define VMW_FENCE_WRAP (1 << 24) -irqreturn_t vmw_irq_handler(int irq, void *arg) +/** + * vmw_thread_fn - Deferred (process context) irq handler + * + * @irq: irq number + * @arg: Closure argument. Pointer to a struct drm_device cast to void * + * + * This function implements the deferred part of irq processing. + * The function is guaranteed to run at least once after the + * vmw_irq_handler has returned with IRQ_WAKE_THREAD. + * + */ +static irqreturn_t vmw_thread_fn(int irq, void *arg) +{ + struct drm_device *dev = (struct drm_device *)arg; + struct vmw_private *dev_priv = vmw_priv(dev); + irqreturn_t ret = IRQ_NONE; + + if (test_and_clear_bit(VMW_IRQTHREAD_FENCE, + dev_priv->irqthread_pending)) { + vmw_fences_update(dev_priv->fman); + wake_up_all(&dev_priv->fence_queue); + ret = IRQ_HANDLED; + } + + if (test_and_clear_bit(VMW_IRQTHREAD_CMDBUF, + dev_priv->irqthread_pending)) { + vmw_cmdbuf_irqthread(dev_priv->cman); + ret = IRQ_HANDLED; + } + + return ret; +} + +/** + * vmw_irq_handler irq handler + * + * @irq: irq number + * @arg: Closure argument. Pointer to a struct drm_device cast to void * + * + * This function implements the quick part of irq processing. + * The function performs fast actions like clearing the device interrupt + * flags and also reasonably quick actions like waking processes waiting for + * FIFO space. Other IRQ actions are deferred to the IRQ thread. + */ +static irqreturn_t vmw_irq_handler(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; struct vmw_private *dev_priv = vmw_priv(dev); uint32_t status, masked_status; + irqreturn_t ret = IRQ_HANDLED; status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); masked_status = status & READ_ONCE(dev_priv->irq_mask); @@ -45,20 +90,21 @@ irqreturn_t vmw_irq_handler(int irq, void *arg) if (!status) return IRQ_NONE; - if (masked_status & (SVGA_IRQFLAG_ANY_FENCE | - SVGA_IRQFLAG_FENCE_GOAL)) { - vmw_fences_update(dev_priv->fman); - wake_up_all(&dev_priv->fence_queue); - } - if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS) wake_up_all(&dev_priv->fifo_queue); - if (masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER | - SVGA_IRQFLAG_ERROR)) - vmw_cmdbuf_tasklet_schedule(dev_priv->cman); + if ((masked_status & (SVGA_IRQFLAG_ANY_FENCE | + SVGA_IRQFLAG_FENCE_GOAL)) && + !test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending)) + ret = IRQ_WAKE_THREAD; - return IRQ_HANDLED; + if ((masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER | + SVGA_IRQFLAG_ERROR)) && + !test_and_set_bit(VMW_IRQTHREAD_CMDBUF, + dev_priv->irqthread_pending)) + ret = IRQ_WAKE_THREAD; + + return ret; } static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) @@ -281,23 +327,15 @@ int vmw_wait_seqno(struct vmw_private *dev_priv, return ret; } -void vmw_irq_preinstall(struct drm_device *dev) +static void vmw_irq_preinstall(struct drm_device *dev) { struct vmw_private *dev_priv = vmw_priv(dev); uint32_t status; - if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) - return; - status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); } -int vmw_irq_postinstall(struct drm_device *dev) -{ - return 0; -} - void vmw_irq_uninstall(struct drm_device *dev) { struct vmw_private *dev_priv = vmw_priv(dev); @@ -306,8 +344,41 @@ void vmw_irq_uninstall(struct drm_device *dev) if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) return; + if (!dev->irq_enabled) + return; + vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); + + dev->irq_enabled = false; + free_irq(dev->irq, dev); +} + +/** + * vmw_irq_install - Install the irq handlers + * + * @dev: Pointer to the drm device. + * @irq: The irq number. + * Return: Zero if successful. Negative number otherwise. + */ +int vmw_irq_install(struct drm_device *dev, int irq) +{ + int ret; + + if (dev->irq_enabled) + return -EBUSY; + + vmw_irq_preinstall(dev); + + ret = request_threaded_irq(irq, vmw_irq_handler, vmw_thread_fn, + IRQF_SHARED, VMWGFX_DRIVER_NAME, dev); + if (ret < 0) + return ret; + + dev->irq_enabled = true; + dev->irq = irq; + + return ret; } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 36dd7930bf5f..b850562fbdd6 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -1566,10 +1566,34 @@ vmw_kms_atomic_check_modeset(struct drm_device *dev, } +/** + * vmw_kms_atomic_commit - Perform an atomic state commit + * + * @dev: DRM device + * @state: the driver state object + * @nonblock: Whether nonblocking behaviour is requested + * + * This is a simple wrapper around drm_atomic_helper_commit() for + * us to clear the nonblocking value. + * + * Nonblocking commits currently cause synchronization issues + * for vmwgfx. + * + * RETURNS + * Zero for success or negative error code on failure. + */ +int vmw_kms_atomic_commit(struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock) +{ + return drm_atomic_helper_commit(dev, state, false); +} + + static const struct drm_mode_config_funcs vmw_kms_funcs = { .fb_create = vmw_kms_fb_create, .atomic_check = vmw_kms_atomic_check_modeset, - .atomic_commit = drm_atomic_helper_commit, + .atomic_commit = vmw_kms_atomic_commit, }; static int vmw_kms_generic_present(struct vmw_private *dev_priv, @@ -2494,7 +2518,7 @@ void vmw_kms_helper_buffer_finish(struct vmw_private *dev_priv, if (file_priv) vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret, user_fence_rep, fence, - handle); + handle, -1, NULL); if (out_fence) *out_fence = fence; else |