diff options
| author | Eric Anholt <eric@anholt.net> | 2016-02-15 17:31:41 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2016-02-26 17:42:47 -0800 |
| commit | a7c5047d1ce178dd2b1fa577fc8909ad663d56d5 (patch) | |
| tree | a817f72b9d1334c67e92392bf0e9d426c14aab81 /drivers/gpu/drm/vc4 | |
| parent | c31806fbdda910d337b60896040afa708bdfa2bd (diff) | |
drm/vc4: Fix setting of vertical timings in the CRTC.
It looks like when I went to add the interlaced bits, I just took the
existing PV_VERT* block and indented it, instead of copy and pasting
it first. Without this, changing resolution never worked.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/vc4')
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_crtc.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 5e84be2e97d0..93d53c278486 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -212,6 +212,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) PV_HORZB_HFP) | VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE)); + CRTC_WRITE(PV_VERTA, + VC4_SET_FIELD(mode->vtotal - mode->vsync_end, + PV_VERTA_VBP) | + VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, + PV_VERTA_VSYNC)); + CRTC_WRITE(PV_VERTB, + VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, + PV_VERTB_VFP) | + VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE)); + if (interlace) { CRTC_WRITE(PV_VERTA_EVEN, VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1, |