diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-06-05 16:16:23 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-09 12:02:48 +0200 |
| commit | a4263fed284282665c24ca1f3335bddde3a76d57 (patch) | |
| tree | 1c7a21534a0152b456837b28042e94bb4e1f6047 /drivers/gpu/drm/tegra/sor.c | |
| parent | 7890b576eda75c0b412ca41470366138e1b19cfc (diff) | |
drm/tegra: sor - Do not hardcode link speed
Use the speed probed from the link at runtime rather than relying on a
hardcoded default.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/sor.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index ff025aa786e8..4e354ee4b203 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -658,10 +658,10 @@ static int tegra_output_sor_enable(struct tegra_output *output) usleep_range(250, 1000); } - /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */ + /* set link bandwidth */ value = tegra_sor_readl(sor, SOR_CLK_CNTRL); value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; - value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; + value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; tegra_sor_writel(sor, value, SOR_CLK_CNTRL); /* set linkctl */ |