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author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2020-06-02 20:42:33 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2020-06-03 15:33:06 -0400 |
commit | a24eaa5c51255b344d5a321f1eeb3205f2775498 (patch) | |
tree | 09b01fccb8fab27ba877bfec26bee48c63c69b97 /drivers/gpu/drm/tegra/hda.h | |
parent | b7f839d292948142eaab77cedd031aad0bfec872 (diff) |
drm/amd/display: Revalidate bandwidth before commiting DC updates
[Why]
Whenever we switch between tiled formats without also switching pixel
formats or doing anything else that recreates the DC plane state we
can run into underflow or hangs since we're not updating the
DML parameters before committing to the hardware.
[How]
If the update type is FULL then call validate_bandwidth again to update
the DML parmeters before committing the state.
This is basically just a workaround and protective measure against
update types being added DC where we could run into this issue in
the future.
We can only fully validate the state in advance before applying it to
the hardware if we recreate all the plane and stream states since
we can't modify what's currently in use.
The next step is to update DM to ensure that we're creating the plane
and stream states for whatever could potentially be a full update in
DC to pre-emptively recreate the state for DC global validation.
The workaround can stay until this has been fixed in DM.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/hda.h')
0 files changed, 0 insertions, 0 deletions