diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2014-10-13 11:35:06 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-10-13 11:35:06 -0400 |
| commit | 1db7802418596880b51d78408f10f25e6fbd8656 (patch) | |
| tree | 81c27f4680629a9ebae0f86e0a47d74891103560 /drivers/gpu/drm/radeon | |
| parent | 60779143b5451095b4bbfb021d39955cb4794913 (diff) | |
Revert "drm/radeon/dpm: drop clk/voltage dependency filters for SI"
This reverts commit 186b1b2ba2a0684e3d2d3703427a993a3b35b16d.
There are still some stability problems on some SI boards so bring
this back.
Diffstat (limited to 'drivers/gpu/drm/radeon')
| -rw-r--r-- | drivers/gpu/drm/radeon/si_dpm.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 9e4d5d7d348f..70e61ffeace2 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -2916,6 +2916,7 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, bool disable_sclk_switching = false; u32 mclk, sclk; u16 vddc, vddci; + u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; int i; if ((rdev->pm.dpm.new_active_crtc_count > 1) || @@ -2949,6 +2950,29 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, } } + /* limit clocks to max supported clocks based on voltage dependency tables */ + btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, + &max_sclk_vddc); + btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, + &max_mclk_vddci); + btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, + &max_mclk_vddc); + + for (i = 0; i < ps->performance_level_count; i++) { + if (max_sclk_vddc) { + if (ps->performance_levels[i].sclk > max_sclk_vddc) + ps->performance_levels[i].sclk = max_sclk_vddc; + } + if (max_mclk_vddci) { + if (ps->performance_levels[i].mclk > max_mclk_vddci) + ps->performance_levels[i].mclk = max_mclk_vddci; + } + if (max_mclk_vddc) { + if (ps->performance_levels[i].mclk > max_mclk_vddc) + ps->performance_levels[i].mclk = max_mclk_vddc; + } + } + /* XXX validate the min clocks required for display */ if (disable_mclk_switching) { |