diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2016-12-14 17:02:49 +0900 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2017-02-17 15:14:32 +1000 |
| commit | 64a94ded890a2e4e5701ac34868180c2d895874a (patch) | |
| tree | f254fac58a95890f53e87d104a25939a44ce5d0c /drivers/gpu/drm/nouveau/nvkm/subdev/secboot | |
| parent | 45ef8450098fbb243ad65f590b965db1247d2d7e (diff) | |
drm/nouveau/secboot: fix WPR descriptor generation
Generate the WPR descriptor closer to what RM does. In particular, set
the expected masks, and only set the ucode members on Tegra.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/secboot')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 82e325bb1431..d4f04239b124 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -496,19 +496,22 @@ acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, { struct nvkm_gpuobj *ls_blob = acr->ls_blob; - desc->ucode_blob_base = ls_blob->addr; - desc->ucode_blob_size = ls_blob->size; - - desc->wpr_offset = 0; - /* WPR region information if WPR is not fixed */ if (sb->wpr_size == 0) { + u32 wpr_start = ls_blob->addr; + u32 wpr_end = wpr_start + ls_blob->size; + desc->wpr_region_id = 1; - desc->regions.no_regions = 1; + desc->regions.no_regions = 2; + desc->regions.region_props[0].start_addr = wpr_start >> 8; + desc->regions.region_props[0].end_addr = wpr_end >> 8; desc->regions.region_props[0].region_id = 1; - desc->regions.region_props[0].start_addr = ls_blob->addr >> 8; - desc->regions.region_props[0].end_addr = - (ls_blob->addr + ls_blob->size) >> 8; + desc->regions.region_props[0].read_mask = 0xf; + desc->regions.region_props[0].write_mask = 0xc; + desc->regions.region_props[0].client_mask = 0x2; + } else { + desc->ucode_blob_base = ls_blob->addr; + desc->ucode_blob_size = ls_blob->size; } } |