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authorBen Skeggs <bskeggs@redhat.com>2019-02-12 22:28:13 +1000
committerBen Skeggs <bskeggs@redhat.com>2019-02-20 08:59:59 +1000
commitfdad518362505f0bf09b323ee6c46f18b81f3e62 (patch)
treef8204ff521cae826e896523085e97eb2e4d3ae41 /drivers/gpu/drm/nouveau/include
parent1a346934909b2ec90a19ce453c68eb2186580e0e (diff)
drm/nouveau/sec2: utilise engine PRI address from TOP
Turing has its SEC2 instance in an alternate location, and this avoids needing to duplicate the code here for it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include')
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
index f7d89822b905..66684456daf7 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
@@ -5,6 +5,8 @@
struct nvkm_sec2 {
struct nvkm_engine engine;
+ u32 addr;
+
struct nvkm_falcon *falcon;
struct nvkm_msgqueue *queue;
struct work_struct work;