diff options
| author | Sharat Masetty <smasetty@codeaurora.org> | 2018-09-27 22:16:22 +0530 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-10-03 20:24:54 -0400 |
| commit | 9fb4bfd0be010371d3fdd2280e9d99f315382379 (patch) | |
| tree | 0f9aa5738480512e3593cfd321869bf70e8bc133 /drivers/gpu/drm/msm | |
| parent | b689a830f5264e3a53307ba468e376e9f95f15e0 (diff) | |
drm/msm/a6xx: Send the right perf index value to GMU
The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index bbb8126ec5c5..bfa3f468a31c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -70,7 +70,7 @@ static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, - ((index << 24) & 0xff) | (3 & 0xf)); + ((3 & 0xf) << 28) | index); /* * Send an invalid index as a vote for the bus bandwidth and let the |