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authorNicholas Mc Guire <hofrat@osadl.org>2015-04-04 04:39:08 +0200
committerRob Clark <robdclark@gmail.com>2015-06-11 13:11:02 -0400
commit84c3b87b8b669e2d42209ba9fc9ddeffb90b3f17 (patch)
tree47f14633e99a687857d02180425df24e63c299f8 /drivers/gpu/drm/msm/edp/edp_aux.c
parent9f68ef90aa383c01e143889989f20577605ca4f6 (diff)
drm/msm: fix HZ dependency of timeout
The timeout is passed as a constant which makes it HZ dependent because jiffies are expected so it should be converted to jiffies. The actual value is not clear from the code - my best guess is that this should be 300 milliseconds given that other timeouts are in milliseconds based on looking at other drm drivers (e.g. exynos_drm_dsi.c:356 300ms, tegra/dpaux.c:188 250ms) - this needs to be confirmed by someone who knows the details of the driver. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/edp/edp_aux.c')
-rw-r--r--drivers/gpu/drm/msm/edp/edp_aux.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/edp/edp_aux.c b/drivers/gpu/drm/msm/edp/edp_aux.c
index 5f77bf0adf1d..d950839edf91 100644
--- a/drivers/gpu/drm/msm/edp/edp_aux.c
+++ b/drivers/gpu/drm/msm/edp/edp_aux.c
@@ -148,7 +148,8 @@ ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg)
goto unlock_exit;
DBG("wait_for_completion");
- time_left = wait_for_completion_timeout(&aux->msg_comp, 300);
+ time_left = wait_for_completion_timeout(&aux->msg_comp,
+ msecs_to_jiffies(300));
if (!time_left) {
/*
* Clear GO and reset AUX channel