diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2020-03-04 11:40:51 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2020-03-10 10:51:24 +0100 |
| commit | e5fab2ec9ca4f7db47aaf1d7f39e43a13b03a4b7 (patch) | |
| tree | 5a2daba4dfa69c5e7ad2b7e1b127436c8da99bf0 /drivers/gpu/drm/meson/meson_venc_cvbs.c | |
| parent | 64db601a9561778b41add87270daf512c9bf0433 (diff) | |
drm/meson: vclk: add support for YUV420 setup
This patch adds clocking support for the YUV420 output from the
Amlogic Meson SoCs Video Processing Unit to the HDMI Controller.
The YUV420 is obtained by generating a YUV444 pixel stream like
the classic HDMI display modes, but then the Video Encoder output
can be configured to down-sample the YUV444 pixel stream to a YUV420
stream.
This mode needs a different clock generation scheme since the TMDS PHY
clock must match the 10x ratio with the YUV420 pixel clock, but
the video encoder must run at 2x the pixel clock.
This patch adds the TMDS PHY clock value in all the video clock setup
in order to better support these specific uses cases and switch
to the Common Clock framework for clocks handling in the future.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jernej Škrabec <jernej.skrabec@siol.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20200304104052.17196-11-narmstrong@baylibre.com
Diffstat (limited to 'drivers/gpu/drm/meson/meson_venc_cvbs.c')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_venc_cvbs.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c index 1bd6b6d15ffb..541f9eb2a135 100644 --- a/drivers/gpu/drm/meson/meson_venc_cvbs.c +++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c @@ -213,8 +213,10 @@ static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder, meson_venci_cvbs_mode_set(priv, meson_mode->enci); /* Setup 27MHz vclk2 for ENCI and VDAC */ - meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, MESON_VCLK_CVBS, - MESON_VCLK_CVBS, MESON_VCLK_CVBS, true); + meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, + MESON_VCLK_CVBS, MESON_VCLK_CVBS, + MESON_VCLK_CVBS, MESON_VCLK_CVBS, + true); } } |