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authorLinus Walleij <linus.walleij@linaro.org>2018-02-06 10:35:38 +0100
committerLinus Walleij <linus.walleij@linaro.org>2018-02-07 09:08:40 +0100
commiteedd6033b4c88d559afd7c8ac8a76fefcd9834a6 (patch)
tree2e276f18b5ce5ef45461abe4481318feb20367fd /drivers/gpu/drm/meson/meson_vclk.h
parent6470b7ddec69dc2edd4bcb01eab3cf71ead5f794 (diff)
drm/pl111: Support variants with broken clock divider
The early Integrator CLCD synthesized in the Integrator CP and IM-PD1 FPGAs are broken: their clock dividers do not work properly. Support disabling the clock divider and drive the clock directly from the parent under these circumstances. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-3-linus.walleij@linaro.org
Diffstat (limited to 'drivers/gpu/drm/meson/meson_vclk.h')
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