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authorXiaoguang Chen <xiaoguang.chen@intel.com>2016-11-24 13:13:00 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2016-11-24 14:08:58 +0800
commit550dd77ebb6360120269d9a7102ae2c0cea41290 (patch)
tree1e8dd484023b881537acfc948376c459af4a21ef /drivers/gpu/drm/i915
parente992faee1f82cebf39c65b340d7591ab1aa8c742 (diff)
drm/i915/gvt: fix getting 64bit bar size error
For 64bit bar while reading the higher 32bit the value should be returned directly. In the current implementation the higher 32bit value was discarded and not written to the cfg space of vgpu which lead to an incorrect bar size. Signed-off-by: Xiaoguang Chen <xiaoguang.chen@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/gvt/gvt.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 3d4223e8ebe3..b1a7c8dd4b5f 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -361,6 +361,8 @@ static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
* leave the bit 3 - bit 0 unchanged.
*/
*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
+ } else {
+ *pval = val;
}
}