diff options
| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2019-04-18 11:06:34 +0100 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2019-04-30 10:16:18 +0300 |
| commit | 9628e15ca9d5f7595ba886173e98a139d0a56cd1 (patch) | |
| tree | 10198b36a3e5dd91f2c828f8784ceb95b6ca0d3e /drivers/gpu/drm/i915/intel_vdsc.c | |
| parent | 879a4e70f96a26a9368a3caed2f552aa67105852 (diff) | |
drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Remove the workaround and whitelist the register to allow any userspace
configure the behaviour to their liking.
v2:
* Remove the workaround apart from adding the whitelist.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: kevin.ma@intel.com
Cc: xiaogang.li@intel.com
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190418100634.984-1-tvrtko.ursulin@linux.intel.com
Fixes: f63c7b4880aa ("drm/i915/icl: WaEnableStateCacheRedirectToCS")
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
[tursulin: Anuj reported no GPU hangs or performance regressions with old
Mesa on patched kernel.]
(cherry picked from commit 0fc2273b9ab7f07cdef448e99525e481535e1ab0)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_vdsc.c')
0 files changed, 0 insertions, 0 deletions