diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-01-22 22:56:30 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-01-26 15:41:24 +0200 |
| commit | 47a14955106f71e9d6cb2a807bd30dacd403a3fe (patch) | |
| tree | 0f213d213a0bf15ff2169431796e8367ac89f485 /drivers/gpu/drm/i915/intel_pm.h | |
| parent | 96dc6ed879439d6c12fd6c4ec2fbb62dd4e85998 (diff) | |
drm/i915: Add pipe ddb entries into the dbuf state
The dbuf state will be where we collect all the inter-pipe dbuf
allocation stuff. Start by adding the actual per-pipe ddb entries
there.
Originally the plan was to move them there outright, but that no longer
works as we're no longer guaranteed to have a dbuf state when it comes
time to sanity check the ddb overlaps in skl_commit_modeset_enables().
I think when I wrote this originally we did the watermark/ddb
calculation last, and so we couldn't have any crtcs in the state w/o
also having the dbuf state. But that has since changed and we do the
watermark/ddb calculation much earlier, and thus it is now possible
to commit crtcs w/o a dbuf state. So we keep another copy of the
information in the crtc state.
v2: Rebase
v3: Duplicate the entries instead of moving
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-6-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 00910bc01407..724204bb8442 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -9,8 +9,10 @@ #include <linux/types.h> #include "display/intel_bw.h" +#include "display/intel_display.h" #include "display/intel_global_state.h" +#include "i915_drv.h" #include "i915_reg.h" struct drm_device; @@ -68,6 +70,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); struct intel_dbuf_state { struct intel_global_state base; + struct skl_ddb_entry ddb[I915_MAX_PIPES]; + u8 enabled_slices; u8 active_pipes; }; |