diff options
author | Shashank Sharma <shashank.sharma@intel.com> | 2015-09-23 23:27:17 +0530 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-10-02 14:44:41 +0200 |
commit | 11b8e4f58e1baa94e44400a076b1a3757612ea55 (patch) | |
tree | 0c70c85e08569c7ca6c3c457d992691d61f96706 /drivers/gpu/drm/i915/intel_dsi_pll.c | |
parent | 37ab0810c9b7e06ec3904c186c46e9c540b3793b (diff) |
drm/i915/bxt: Program Tx Rx and Dphy clocks
BXT DSI clocks are different than previous platforms. So adding a
new function to program following clocks and dividers:
1. Program variable divider to generate input to Tx clock divider
(Output value must be < 39.5Mhz)
2. Select divide by 2 option to get < 20Mhz for Tx clock
3. Program 8by3 divider to generate Rx clock
v2: Fixed Jani's review comments. Adjusted the Macro definition as
per convention. Simplified the logic for bit definitions for
MIPI PORT A and PORT C in same registers.
v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
Jani's suggestion.
v4: Addressed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi_pll.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dsi_pll.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index f335e6cd4431..386336281997 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -384,6 +384,42 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) return pclk; } +/* Program BXT Mipi clocks and dividers */ +static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) +{ + u32 tmp; + u32 divider; + u32 dsi_rate; + u32 pll_ratio; + struct drm_i915_private *dev_priv = dev->dev_private; + + /* Clear old configurations */ + tmp = I915_READ(BXT_MIPI_CLOCK_CTL); + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); + tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); + tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); + tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); + + /* Get the current DSI rate(actual) */ + pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & + BXT_DSI_PLL_RATIO_MASK; + dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; + + /* Max possible output of clock is 39.5 MHz, program value -1 */ + divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; + tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); + + /* + * Tx escape clock must be as close to 20MHz possible, but should + * not exceed it. Hence select divide by 2 + */ + tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port); + + tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port); + + I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); +} + static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; @@ -435,6 +471,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) static void bxt_enable_dsi_pll(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + enum port port; u32 val; DRM_DEBUG_KMS("\n"); @@ -453,6 +491,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder) return; } + /* Program TX, RX, Dphy clocks */ + for_each_dsi_port(port, intel_dsi->ports) + bxt_dsi_program_clocks(encoder->base.dev, port); + /* Enable DSI PLL */ val = I915_READ(BXT_DSI_PLL_ENABLE); val |= BXT_DSI_PLL_DO_ENABLE; |