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author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-06-05 10:07:09 +0200 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-06-12 19:25:46 +0200 |
commit | 7cf4160148136deb31ee5f2802857dd935a38529 (patch) | |
tree | a6b8cc7e267b0e5a08b83fe0432474fc21a6892d /drivers/gpu/drm/i915/intel_drv.h | |
parent | 534b5a5341cb7e16a98d44623d8fce9464ebf22c (diff) |
drm/i915: clear up backlight #define confusion on gen4+
- Regroup definitions for BLC_PWM_CTL so that they're all together and
and ordered according to the bitfields.
- Add all missing definitions for BLC_PWM_CTL2.
- Use the BLM_ (for backlight modulation) prefix consistently.
- Note that combination mode (i.e. also taking the legacy backlight
control value from pci config space into account) is gen4 only.
- Move the new registers for PCH-split machines up, they're an almost
match for the gen4 defitions. Prefix the special PCH-only bits with
BLM_PCH_. Also add the pipe C select bit for ivb.
- Rip out the second pair of PCH polarity definitions - they're only
valid on early (pre-production) ilk silicon.
- Adapt the existing code to use the new definitions. This has the
nice benefit of killing a magic (1 << 30) left behind be Jesse
Barnes.
No functional changes in this patch.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
0 files changed, 0 insertions, 0 deletions