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authorChris Wilson <chris@chris-wilson.co.uk>2010-08-07 11:01:28 +0100
committerEric Anholt <eric@anholt.net>2010-08-09 11:24:34 -0700
commit1d8e1c75ffa84400758aef9cc59298920b8801f9 (patch)
treec1faa4ad7c8754330edd959d0726b19376cf4f9c /drivers/gpu/drm/i915/intel_display.c
parent2e88e40bed136a7b7cb1c77d8dc6bd181d0d2732 (diff)
drm/i915: Enable aspect/centering panel fitting for Ironlake.
v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c16
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 24fbd0f24507..25e3866f9159 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2005,15 +2005,13 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
/* Enable panel fitting for LVDS */
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
|| HAS_eDP || intel_pch_has_edp(crtc)) {
- temp = I915_READ(pf_ctl_reg);
- I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
-
- /* currently full aspect */
- I915_WRITE(pf_win_pos, 0);
-
- I915_WRITE(pf_win_size,
- (dev_priv->panel_fixed_mode->hdisplay << 16) |
- (dev_priv->panel_fixed_mode->vdisplay));
+ if (dev_priv->pch_pf_size) {
+ temp = I915_READ(pf_ctl_reg);
+ I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
+ I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
+ I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
+ } else
+ I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
}
/* Enable CPU pipe */