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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-01-25 21:44:45 +0200 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-01-26 17:32:03 +0100 |
commit | 56a12a509296c87d6f149be86c6694d312b21d35 (patch) | |
tree | d50eb6be8db694c3ef35884b7d1c28991d83a6d4 /drivers/gpu/drm/i915/i915_sysfs.c | |
parent | 67cfc2032b516e44b972abe30209234343e1f145 (diff) |
drm/i915: Include display_mmio_offset in sequencer index/data registers
SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_sysfs.c')
0 files changed, 0 insertions, 0 deletions