diff options
author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-30 21:52:23 -0700 |
---|---|---|
committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-05 12:14:50 -0700 |
commit | 0a46ddd57c9ef9fb5376d4bff65d07e0aea30f35 (patch) | |
tree | 4c905aad892a322597dbf7041321637bedf15e9c /drivers/gpu/drm/i915/i915_reg.h | |
parent | 908a610557f4d8b46a0f82c01e31b30f5c998580 (diff) |
drm/i915/cnp: Wa 1181: Fix Backlight issue
This workaround fixes a CNL PCH bug when changing
backlight from a lower frequency to a higher frequency.
During random reboot cycles, display backlight seems to
be off/ dim for 2-3 mins.
The only functional change on this patch is to
set bit 13 of 0xC2020 for CNL PCH.
The rest of patch is organizing identation around
those bits definitions and re-organizing CFL workarounds.
v2: Only add the bit that matters without touching others
around (Jani).
Rebase on top of clock gating functions rename.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170831045223.3960-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c718c2f2eaeb..5651081ff789 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7483,6 +7483,7 @@ enum { #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) +#define CNP_PWM_CGE_GATING_DISABLE (1<<13) #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) /* CPU: FDI_TX */ |