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| author | Caz Yokoyama <caz.yokoyama@intel.com> | 2020-03-04 14:13:59 -0800 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2020-03-16 12:17:00 +0200 |
| commit | c09f6b4d0883dfb859c1ddcfb04c3260ef310ce0 (patch) | |
| tree | a0578fd5ef4a9eec8c2f1ee67edb22cd2c8d21e8 /drivers/gpu/drm/i915/gt/intel_workarounds.c | |
| parent | 9777d8b2d2a148bc5d46694ec4f2559282fec8cf (diff) | |
Revert "drm/i915/tgl: Add extra hdc flush workaround"
This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4.
The commit takes care Wa_1604544889 which was fixed on a0 stepping based on
a0 replan. So no SW workaround is required on any stepping now.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Fixes: 36a6b5d964d9 ("drm/i915/tgl: Add extra hdc flush workaround")
Link: https://patchwork.freedesktop.org/patch/msgid/1c751032ce79c80c5485cae315f1a9904ce07cac.1583359940.git.caz.yokoyama@intel.com
(cherry picked from commit 175c4d9b3b9a60b4ea0b8cd034011808c6a03b05)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_workarounds.c')
0 files changed, 0 insertions, 0 deletions