diff options
| author | Lucas Stach <l.stach@pengutronix.de> | 2017-09-28 15:41:21 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2017-10-10 11:45:06 +0200 |
| commit | 6eb3ecc33a6aaedda5ceb0824cafe34c47af2f55 (patch) | |
| tree | d37b4f6248078ec1a691c6c6b1ead5c956a0fa0a /drivers/gpu/drm/etnaviv | |
| parent | b670908384bda92c42076cf36614ee4f97763253 (diff) | |
drm/etnaviv: rework clock initialization
The reset path wants to initialize the clock control register regardless
of the DYNAMIC_FREQUENCY_SCALING feature, so don't call clock update, but
explicitly load the register.
Also disabling of the debug registers is moved into the reset function,
so we always get to the same state after a GPU reset. This means the
clock update function should not touch the bits already set in the clock
control register, but instead only update the scaling bits.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/etnaviv')
| -rw-r--r-- | drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index fc9a6a83dfc7..de34e221c2fe 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -420,9 +420,10 @@ static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) gpu->base_rate_shader >> gpu->freq_scale); } else { unsigned int fscale = 1 << (6 - gpu->freq_scale); - u32 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS | - VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); + u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); + clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; + clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); etnaviv_gpu_load_clock(gpu, clock); } } @@ -445,9 +446,9 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) while (time_is_after_jiffies(timeout)) { /* enable clock */ - etnaviv_gpu_update_clock(gpu); - - control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); + unsigned int fscale = 1 << (6 - gpu->freq_scale); + control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); + etnaviv_gpu_load_clock(gpu, control); /* Wait for stable clock. Vivante's code waited for 1ms */ usleep_range(1000, 10000); @@ -490,6 +491,10 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) continue; } + /* disable debug registers, as they are not normally needed */ + control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; + gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); + failed = false; break; } |