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| author | Uma Shankar <uma.shankar@intel.com> | 2019-06-12 12:14:58 +0530 |
|---|---|---|
| committer | Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | 2019-06-17 10:26:47 +0200 |
| commit | 377c70edd486754020ac4375ab2c403ed5108907 (patch) | |
| tree | 7e99f62c96f3282c1e97b2efdedc5bcb11db0ac9 /drivers/gpu/drm/bochs | |
| parent | 89a72304f2f3d4baf14e71c570ea4d99a00dae07 (diff) | |
drm/i915/icl: Add register definitions for Multi Segmented gamma
Add macros to define multi segmented gamma registers
V2: Addressed Ville's comments:
Add gen-lable before bit definition
Addressed Jani's comment
- Use REG_GENMASK() and REG_BIT()
V3: Addressed Ville's comments:
- Put comments at the end of line.
- Change the comment at start of ICL multisegmented gamma registers.
Added Ville's r-b
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1560321900-18318-3-git-send-email-uma.shankar@intel.com
Diffstat (limited to 'drivers/gpu/drm/bochs')
0 files changed, 0 insertions, 0 deletions