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author | Alex Deucher <alexander.deucher@amd.com> | 2018-11-06 11:19:00 -0500 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2018-11-06 16:25:51 -0500 |
commit | 3426d66d3e74ab0ab264a85e0795a17e3dde1e71 (patch) | |
tree | 0e466e112b606559ebc10255557b5a024caa016e /drivers/gpu/drm/amd | |
parent | 02680efbb10be0d2c867fe722ae23d588f6bebef (diff) |
drm/amdgpu/vega20: add CLK base offset
In case we need to access CLK registers.
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c index 2d4473557b0d..d13fc4fcb517 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c @@ -49,6 +49,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev) adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); } return 0; } |