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authorRex Zhu <Rex.Zhu@amd.com>2016-08-16 18:13:57 +0800
committerAlex Deucher <alexander.deucher@amd.com>2016-09-14 15:10:33 -0400
commit6429fb6685d72356cfacbbdb748c977d2e63a709 (patch)
treec2eec3db454c488f9af562cbf20a957f20395c55 /drivers/gpu/drm/amd/powerplay
parentc63e2d4c65e8e57b2c870ea46af9ac30d79d426b (diff)
drm/amd/powerplay: add feature flags in hwmgr to enable/disable special features.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay')
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 145656548efd..a4d490a8ffe6 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -70,6 +70,19 @@ enum PP_Result {
#define PCIE_PERF_REQ_GEN2 3
#define PCIE_PERF_REQ_GEN3 4
+enum PP_FEATURE_MASK {
+ PP_SCLK_DPM_MASK = 0x1,
+ PP_MCLK_DPM_MASK = 0x2,
+ PP_PCIE_DPM_MASK = 0x4,
+ PP_SCLK_DEEP_SLEEP_MASK = 0x8,
+ PP_POWER_CONTAINMENT_MASK = 0x10,
+ PP_UVD_HANDSHAKE_MASK = 0x20,
+ PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
+ PP_VBI_TIME_SUPPORT_MASK = 0x80,
+ PP_ULV_MASK = 0x100,
+ PP_ENABLE_GFX_CG_THRU_SMU = 0x200
+};
+
enum PHM_BackEnd_Magic {
PHM_Dummy_Magic = 0xAA5555AA,
PHM_RV770_Magic = 0xDCBAABCD,
@@ -635,6 +648,7 @@ struct pp_hwmgr {
struct pp_power_state *boot_ps;
struct pp_power_state *uvd_ps;
struct amd_pp_display_configuration display_config;
+ uint32_t feature_mask;
};